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DVD5500
DVD PLAYER SERVICE MANUAL
1. GENERAL DESCRIPTION
1.1 MT1379
The MT1379 Progressive Scan DVD-Player Combo Chip is a single-chip MPEG video decoding chip that integrates audio/video stream data processing, TV encoder, four video DACs with Macrovision. copy protection, DVD system navigation, system control and housekeeping functions. The features of this chip can be listed as follows: General Features: · · · · · · · Progressive scan DVD-player combo chip Integrated NTSC/PAL encoder. Built-in progressive video output DVD-Video, VCD 1.1, 2.0, and SVCD Unified track buffer and A/V decoding buffer. Direct interface of 32-bit SDRAM. Servo controller and data channel processing.
Video Related Features: · Macrovision 7.1 for NTSC/PAL interlaced video. · · · · Simultaneous composite video and S-video outputs, or composite and YUV outputs, or composite and RGB outputs. 8-bit CCIR 601 YUV 4:2:2 output. Decodes MPEG video and MPEG2 main profile at main level. Maximum input bit rate of 15Mbits/sec
Audio Related Features: · · · · · · · Dolby Digital (AC-3) and Dolby Pro Logic. Dolby Digital S/PDIF digital audio output. High-Definition Compatible Digital. (HDCD) decoding. Dolby Digital Class A and HDCD certified. SRS TrueSurround .. CD-DA. MP3.
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1.2 MEMORY
1.2.1 SDRAM Memory Interface The MT1379 provides a glueless 16-bit interface to DRAM memory devices used as OSD, MPEG stream and video buffer memory for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to support 128-Mb addressing. The memory interface controls access to both external SDRAM memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers.
1.3 DRIVE INTERFACES
The MT1379 supports the DV34 interface, and other RF and servo interfaces used by many types of DVD loaders. These interfaces meet the specifications of many DVD loader manufacturers.
1.4 FRONT PANEL
The front panel is based around an Futaba VFD and a common NEC front panel controller chip, (uPD16311). The MT1379 controls the uPD16311 using several control signals, (clock, data, chip select). The infrared remote control signal is passed directly to the MT1379 for decoding.
1.5 REAR PANEL
A typical rear panel is included in the reference design. This rear panel supports: - Six channel or two channel audio outputs - Optical and coax S/PDIF outputs. - Composite, S-Video, and SCART outputs The six-video signals used to provide CVBS, S-Video, and RGB are generated by the MT1379's internal video DAC. The video signals are buffered by external circuitry. Six channel audio output by the MT1379 in the form of three I S (or similar) data streams. The S/PDIF serial stream is also generated by the MT1379 output by the rear panel. The six channel audio DACs (AK4356,PCM1606) are used for six channel audio output with MT1379, and similarly AK4382A ,CS4392 Audio DACs are used for two channel audio output with MT1379.
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2. SYSTEM BLOCK DIAGRAM and MT1379 PIN DESCRIPTION
2.1 MT1379 PIN DESCRIPTION
SYMBOL
DVSS IREF PLLVSS LPIOP LPION LPFON LPFIP LPFIN LPFOP JITFO JITFN PLLVDD3 FOO TRO TROPENPWM PWMOUT1-2 DVDD2 DMO FMO FG HIGHA0-5 HIGHA6-7 AD7-4 DVDD3 AD3-0 IOA0-1 IOA2-7 A16-17 IOA18-20 APLLVSS APLLVDD3 ALE IOOE# IOWR# IOCS# UP1_2-6,7 UP3_0-1
TYPE
Ground Analog Input Ground Analog Output Analog Output Analog Output Analog Input Analog Input Analog Output Analog Output Analog Input Power Analog Output Analog Output Analog Output Analog Output Power Analog Output Analog Output Input Inout 2~16MA,SR PU Inout 2~16MA,SR PU Inout 2~16MA,SR Power Inout 2~16MA,SR Inout 2~16MA,SR PU Inout 2~16MA,SR PU Output 2~16MA,SR Inout 2~16MA,SR SMT Ground Power Inout 2~16MA,SR,PU,S MT Inout 2~16MA,SR SMT Inout 2~16MA,SR,SMT Inout 2~16MA,SR,PU,S MT Inout 4MA,SR,PU,SMT Inout
PIN NUMBERS
20,28,60,77,92,102 115,125,135,145 178,189 1
DEFINITION
Ground pin for internal digital circuitry
Current reference input. It generates reference Current for data PLL. Connect an external 100K Resistor to this pin and PLLVSS. 2 Ground pin for PLL and analog circuitry 3 Positive output for low pass filter(LFP) 4 Negative output for LFP 5 Negative output of loop filter amplifier(LFA) 6 Positive input of LFA 7 Negative input of LFA 8 Positive output of LFA 9 RF jitter meter output 10 Negative input of the operational amplifier for RF jigger meter 11 3.3V power pin for data PLL and related analog circuitry 12 Focus servo output. PDM output of focus servo compensator 13 Tracking servo output. PDM output of tracking servo compensator Tray open output,controlled by microcontroller. This is PWM output 14 for TRWMEN27hRW2=1 or is digital output for TRWMEN27hRW2=0 15-16 1st and 2nd general PWM output. 17,42,72,82,120,140,182 2.5V power pin for internally fully digital circuitry. 18 Disk motor control output. PWM output. 19 Feed motor control PWM output. 21 Motor Hall sensor input 22-27 Microcontroller address 8-13 29-30 31-34 35,66,97,111,130,150,185 ,192 36-39 40-41 43-48 49-50 51-52 54 55 56 57 58 59 61-65,67 68,69 Microcontroller address 14-15 Microcontroller address/data 7-4 3.3 power pin for internal digital circuitry Microcontroller address/data 3-0 Microcontroller adress 0-1/IO Microcontroller adress 2-7/IO Flash adress 16-17 Flash adress 18-19 Ground pin for audio clock circuitry 3.3V power pin for audio clock circuitry Microcontroller address latch enable Flash output enable, active low I/O Flash write enable, active low/IO Flash chip select,active low/IO Microcontroller port 1-2...1-7 Microcontroller port 3-0,3-1
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INT0# IR UP3_4,5 UWR# URD# RD7-4,3-0 RWE# CAS# RAS# RCS# BA0 RD15-12,11-8 CLK CLE RA11 RA9,8,7,64,10,0-3 DMVDD3 DMVSS DQM1,0-3,2 BA1 RD31-28,27-24 RD23-22,21-18 RD17-16 ABCK ALRCK ACLK MC_DATA SPDIF ASDATA0 ASDATA1 ASDATA2 ASDATA3 ASDATA4 DACVDDC VREF FS YUV0/CIN DACVSSC YUV1/C DACVDDB YUV2/Y DACVSSB YUV3/CVBS DACVDDA YUV4/G DACVSSA YUV5/B YUV6/R ICE
4MA,SR,PU,SMT Inout 2~16MA,SR,PU,S MT Input SMT Inout Inout 2~16MA,SR,PU,S MT Inout 2~16MA,SR,PU,S MT DRAM data 7-4,3-0 Output 2~16MA,SR Output 2~16MA,SR Output 2~16MA,SR Output 2~16MA,SR Output 2~16MA,SR Inout 2~16MA,SR,PU/PD ,SMT Output 2~16MA,SR Output 2~16MA,SR Output 2~16MA,SR Output 2~16MA,SR Power Ground Output 2~16MA,SR Output 2~16MA,SR Inout 2~16MA,SR PU/PD SMT Inout 2~16MA,SR PU/PD SMT Inout 2~16MA,SR PU/PD SMT Output 4MA Inout 4MA,PD,SMT Inout 4MA Input Output 2~16MA,SR :ON/OFF Inout 4MA PD SMT Inout 4MA PD SMT Inout 4MA PD SMT Inout 4MA PD SMT Inout 4MA PD SMT Power Analog input Analog Output Output 4MA,SR Ground Output 4MA,SR Power Output 4MA,SR Ground Output 4MA,SR Power Output 4MA,SR Ground Output 4MA,SR Output 4MA,SR Input PD,SMT
70 71 73-74 75 76 78-81,83-86 87 88 89 90 91 93-96,98-101 103 104 105 106,107,110,112114,119,121-124 108 109 116,117-136,137 118 126-129,131-134 138-139,141-144 146-147 148 149 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174
Microcontroller interrupt 0, active low IR control signal input Microcontroller port 3-4,3-5 Microcontroller write strobe,active low Microcontroller write strobe,active low DRAM data 7-4,3-0 DRAM write enable, active low. DRAM column adress strobe,active low DRAM row adress strobe,active low DRAM chip select, active low DRAM bank adress 0 DRAM data 15-12,11-8 DRAM clock DRAM clock enable DRAM adress bit 11 or serial data 3(channel 7/8) DRAM adresses 3.3V Power pin for DRAM clock circuitry Ground pin for DRAM clock circuitry Mask for DRAM input/output byte 1,0 DRAM bank address 0 DRAM corresponding data DRAM data 23-22,21-18/Videoin Data PortA 7-6,5-2 DRAM data 17-16/Videoin Data PortA 1-0 Audio bit clock Audio L/R channel clock,Trap value in power-on reset 1:ext. 0:int. Audio DAC master clock(384/256 audio sample frequency) Microphone serial input SPDIF output (1)Audio serial data 0(L/R)(2)Trap value in power on reset 1:factory test mode 0:normal mode Audio serial data 1(surround L/R),Trap value in power-on reset Audio serial data 2(center/left),Trap value in power-on reset Audio serial data 3(surround L/R),Trap value in power-on reset,videoin data portb 1 Audio serial data 4(center/left),Trap value in power-on reset,videoin data portb 2 3.3V power pin for VDEO DAC circuitry Bandgap refernce voltage Full scale adjustment Video data output bit 0/Compensation capacitor Ground pin for VIDEO DAC circuitry Video data output bit 1/Compensation capacitor 3.3V power pin for VDEO DAC circuitry Video data output bit 2/ Analog Y output Ground pin for VIDEO DAC circuitry Video data output bit 3/ Analog composite output 3.3V power pin for VDEO DAC circuitry Video data output bit 4/Green or Y Ground pin for VIDEO DAC circuitry Video data output bit 5/Blue or CB Video data output bit 5/Red or CR Microcontroller ICE mode enable
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BLANK# VSYN YUV7 HSYN SPMCLK SPDATA SPLRCK SPBCK XTALO XTALI PRST VFO13 IDGATE UDGATE WOBSI SDATA SDEN SLCK BDO ADCVSS ADIN RFSUBI TEZISLV TEI CSO FEI RFLEVEL RFRP_DC RFRP_AC HRFZC PWMVREF PWM2VREF ADCVDD3 RFDTSLVP RFDTSLVN RFIN RFIP
Inout 4MA,SR,SMT Inout,4MA,SR,SMT Inout 4MA,SR,SMT Inout 4MA,SR,SMT Input Input Input Input Output Input Input PD,SMT Output Output Output Input Output Output Output Input Ground Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input A Input Analog Input Analog Input A Input A Input Power Analog Output Analaog Output Analog Input Analog Input
175 176 177 179 180 181 183 184 186 187 188 190 191 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
Video blank area, active low/ Videoin field_601 Vertical Sync/Videoin Vsync_601 Video data output bit 7/Videoin Data PortB 3 Horizontal sync/ Vido in Hsync_601 Audio DAC master clock of SPDIF input/Videoin Data PortB 4 Audio data of SPDIF input/Vidoin Data PortB 5 Audio L/R channel clock of SPDIF input/Videoin Data PortB 6 Audio bit clock of SPDIF input/Videoin Data PortB 7 Crystal Output Crystal Input Power on reset input, active high The 1st,3rd header VFO pulse output Header detect signal output DVD_RAM recording data gate signal output Wobble signal input RF serial data output RF serial data latch enable RF serial clock output Flag of defect data input status Ground pin for ADC circuitry General A/D input RF subtraction signal input terminal Tracking error zero crossing low pass input Tracking error input Central servo input Focus error input Sub beam add input or RFRP low pass input RF ripple detect input RF ripple detect input(through AC coupling) High frequency RF ripple zero crossing A reference voltage input for PWM circuitry. Atypical value of 4.0 v A reference voltage input for PWM circuitry. Atypical value of 2.0 v 3.3 power pin for ADC circuitry Positive RF data slicer level output Negative RF data slicer level output Negative input of RF differential signal Positive input of RF differential signal
2.1 SYSTEM BLOCK DIAGRAM A sample system block diagram for the MT1379 DVD player board design is shown in the following figure:
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3. AUDIO OUTPUT
The MT1379 supports two-channel and six-channel analog audio output. In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround system. The MT1379 also provides digital output in S/PDIF format. The board supports both optical and coaxial SPDIF outputs.
4. AUDIO DACS
The MT1379 supports several variations of an I S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) is 2 possible using the MT1379 internal configuration registers. The I S format uses four stereo data 2 lines and three clock lines. The I S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is an AKM AK4382A. The DACs support up to 192kHz sampling rate. The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits use National LM833 op-amps to perform the low-pass filtering and the buffering.
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5 .VIDEO INTERFACE
5.1 Video Display Output The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the MT1379. The output section consists of a programmable CRT controller capable of operating either in Master or Slave mode. The video output section features internal line buffers which allow the outgoing luminance and chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation. Video Bus The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y) pixels; there are as many chrominance lines as luminance. Video Post-Processing The MT1379 video post-processing circuitry provides support for the color conversion, scaling, and filtering functions through a combination of special hardware and software. Horizontal upsampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the applicable scaling ratio. Video Timing The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The double clock typically is used for TV displays, the single for computer displays.
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6. FLASH MEMORY
The decoder board supports 70ns Flash memories. Currently 4 configurations are supported: FLASH_512K_8b FLASH_1024K_8b FLASH_512Kx2_8b FLASH_512Kx2_16b The MT1379 permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the host interface.
7. SERIAL EEPROM MEMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or equivalent.
8. AUDIO INTERFACE AUDIO SAMPLING RATE CONFIGURATION
AND
PLL COMPONENT
The MT1379 audio mode configuration is selectable, allowing it to interface directly with 2 low-cost audio DACs and ADCs. The audio port provides a standard I S interface input and 2 output and S/PDIF (IEC958) audio output. Stereo mode is in I S format while six channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The S/PDIF interface 2 consists of a bi-phase mark encoder, which has low skew. The transmit I S interface supports the 112, 128, 192, 256, 384, and 512 sampling frequency formats, where sampling frequency Fs is 2 usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I S transmit interface can be 16, 18, 20, 24, and 32-bit samples. For Linear PCM audio stream format, the MT1379 supports 48 kHz and 96 kHz. Dolby Digital audio only supports 48 kHz. The MT1379 incorporates a built-in programmable analog PLL in the device architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either be an output from or an input to the MT1379. Audio data out (TSD) and audio frame sync (TWS) are clocked out of the MT1379 based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is used to clock in audio data in (RSD) and audio receive frame sync (RWS).
9. FRONT PANEL
9.1 VFD CONTROLLER
The VFD controller is a NEC uPD16311. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes and when the button status is read. The MT1379 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD.
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10. CONNECTORS
10.1 SCART CONNECTORS
Pinout of the scart connector: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Audio Right Out Audio Right In Audio Left / Monu Out Audio Gnd Blue Gnd Audio Left / Mono In Blue Control Voltage Green Gnd Comms Data 2 Green Comms Data 1 Red Gnd Comms Data Gnd Red Fast Blanking Video Gnd Fast Blanking Gnd Composite Video In Composite Video Out Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For longer lengths, shielded co-ax cable become essential.
Scart Signals:
Audio signals 0.5V RMS, <1K output impedance, >10K input impedance. Red, Green, Blue 0.7Vpp ±2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-Video Chrominance signal, which is 0.3V. Composite Video / CSync 1Vpp including sync, ±2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances.
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0 to 0.4V: TV is driven by the Left unconnected, it is pulled
composite to 0V
video input signal (pin 19). by its 75R termination.
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Normal. 5 to 8V = TV wide screen 9.5 to 12V = AV mode
11. CIRCUIT DESCRIPTION
11.1 POWER SUPPLY:
· · · · · Socket PL1 is the 220VAC input. 2.5A fuse F1 is used to protect the device against short circuit. Line filters and capacitors L1, C1, L5 and L6 are used to block the parasitic coming from the mains. They also prevent the noise, produced in the circuit, from being injected to the line. Voltage is rectified by using diodes D1, D2, D3 and D4. Using capacitor C3 (470µf) a DC voltage is produced. (310- 320VDC). The current in the primary side of the transformer TR3 comes to the SMPS IC (IC3 TOP223Y). The SMPS IC has a three-pin TO-220 case and a cooler is mounted on it. It has a built-in oscillator, overcurrent and overvoltage protection circuitry and runs at 100kHz. It starts with the current from the primary side of the transformer and follows the current from the feedback winding. Voltages on the secondary side are as follows: -22V, -12V, 3.3V, 5V, 15V. D14 TL431 is a constant current regulator. TL431 watches the 5 volts and supplies the required current to IC2. There are a LED and a photo transistor in IC2. The LED inside the IC2 transmits the value of the current from D14 to phototransistor. Depending on the current gain of the phototransistor IC3 keeps the voltage on the 5-volt-winding constant. Adjustable voltage regulator IC5 (LM317) supplies 12 Volts. When the device enters stand-by mode, transistor Q2 starts to conduct and pulls the adjust pin of IC5 to ground, where this cuts 12Volts off. 22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel. Transistor Q4 and zener diode D14 are used to regulate +12 Volts. This voltage is used to feed op-amps on the back panel.
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11.2 FRONT PANEL:
· · · · · · · · · All the functions on the front panel are controlled by U7 (MT1379) on the mainboard. U7 sends the commands to IC2 uPD16311 via socket PL1 (pins 3,4 and 5). There are 16 keys scanning function, 2 LED outputs, 1 Stand-by output and VFD drivers on IC2. Pin 52 is the oscillator pin and is connected via R5 56K. LED D6 is red in stand-by mode and green when the device is on. When entering stand-by mode, pin 48 goes HIGH (+5V) and controls the transistor Q2 on the power board. Vacuum fluorescent display MD2 is specially designed for DVD. The scanned keys are transmitted via IC2 pin 5 and 6 to U1 on the mainboard. IR remote control receiver module IC3 (TSOP1836) sends the commands from the remote control directly to U1. Socket PL2 carries the VFD filament voltage and 22 Volts.
11.3 BACK PANEL:
· · · · · · · · · · · There are 1 SCART connector (PL4), 2 pieces RCA audio jacks, for audio output, 1 coaxial digital audio output JK3 and 1 laser digital audio output PL5 on the back panel. TOTX176 is used for laser output. For coaxial audio output SPDIF is used. Q22 .. Q27 transistors are to mute the audio outputs while switching the state of the unit(power on/off) There are two op-amps in U14, U16 and U18. They are used for left,right,rear left and right, subwoofer center audio channels. The feedback resistor is amplifying the gain. SCART pin 8 controls 16:9 and 4:3 mode using Q28,Q29 and Q30. When the pin8 output of the scart becomes 5 Volts, 4:3 mode is selected and 16:9 mode is selected when this output becomes 0. The circuit is adjusted to output 12 Volts for 4:3 mode and 6 Volts for 16:9 mode. Transistors Q28,Q29 and Q30 transmit these voltages when the device is turned on and cuts them off when it is turned off. FBL on pin 16 transmits 5 Volts via transistors Q12 and Q14 when the device is on. Socket PL2, which is coming from the mainboard, transmits RED, GREEN, BLUE and VIDEO signals to SCART over the buffer stage. LUMA and CHROMA signals of S-Video are transmitted to S-Video socket via transistors Q11 and Q13 respectively.
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12.SOFWARE UPTATE 12.1 Universal Service Password for Parental Level = 1369 12.2 Version Page (Hidden Menu)
To see Version Page; - Press DISPLAY button from remote - Press "1"-"3"-"5"-"7" at Setup Menu - Setup Menu screen refresh and "Version" selection can be seen under "Preferences Setup" - Select "Version" for Version Page - First 6 lines contains current VERSION information.1st and 5th line is for customers Other lines (Sub-Ver, 8032, Servo, Risc) for factory use only; 1st line contains build information example: 02.01.EF65 5th line contains hardware option example: A6AO.bin 7th line contains Region Code (Management ) - Press "DISPLAY" button on remote control to exit hidden menu. 5th line also shows CD update file name. It defines also Hardware options.
12.3 Build Names for Hardware Options
DVD5500 MTK Concept has 3 different hardware option: 1. 2 OPU Option 2. 2 VFD Option +TV DVD 3. 4 DAC Option This means there are 16 different software. There is a naming standard for software builds according to player's hardware options like; X X X X. bin VFD OPU DAC VFD Type: O = Old VFD / N = New small VFD / T = TV DVD OPU Type: A = ASA SANYO HD60 / F = FUSS HITACHI HOP 1200 DAC Type: A6 = AK4356 / A2 = AK4382 / P6 = PCM1606 / C2 = CS4392
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Example: A6AO.bin = AK4356, ASA, OLD VFD C2FN.bin = CS4392 ,ASA, NEW small VFD Service CD should contains following 16 files; A6AO.bin P6AO.bin A2AO.bin C2AO.bin A6AN.bin P6AN.bin A2AN.bin C2AN.bin A6FO.bin P6FO.bin A2FO.bin C2FO.bin A6FN.bin P6FN.bin A2FN.bin C2FN.bin A6AT.bin P6AT.bin A2AT.bin C2AT.bin A6FT.bin P6FT.bin A2FT.bin C2FT.bin
Note: Update CD should have no volume ID.
12.4 CD UPTADE PROCEDURE:
1) Any Player can be updated automatically with Update CD which contains proper files (see Service Cd.Jpg ) 2) Burn up CD within proper files 2) There should be no Volume Name for CD 3) Open Tray and place update CD 4) You can see "Upgrade File Detected. Press Play to start" OSD message 5) Press Play button to start upgrade 6) You can see "File copying" OSD message for a few second 7) Tray is open automatically 8) No need for CD in tray;Take it from tray. 9) During upgrade procedure "CD upgrade start, Please wait.." indicator at OSD, and "UPG" indicator at VFD 10) Upgrade procedure takes about a few minutes, please wait if tray is open. 11) When CD update is finished tray is closed, screen is refreshed, update is finished. 12) To see Version Page; - Press DISPLAY button from remote - Press "1"-"3"-"5"-"7" at Setup Menu - Setup Menu screen refresh and "Version" selection can be seen under "Preferences Setup" - Select "Version"or version Page - 1st line contains release number like EFXX - 5th line contains hardware options and build number - Press "DISPLAY" button on remote control to exit hidden menu.
12.5 Region Management
At version Page by using arrow keys you can change region.
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13.CIRCUIT SCHEMATICS : Appendix A
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