Text preview for : up8sa3.pdf part of Nokia 5110 Service Manual Gsm Telephone - File 17 - Part 1/3
Back to : gsm_NSE-1NX_©_.part1.rar | Home
System Module UP8S
NSE1
Block Diagram of System/RF Blocks
Original 03/98
3/A3S1
System Module UP8S
NSE1
Circuit Diagram of Baseband
(Version 9 Edit 64) for layout version 09
Original 03/98
3/A3S2
System Module UP8S
NSE1
Circuit Diagram of Power Supply (Version 9
Edit 216) for layout version 09
Original 03/98
3/A3S3
System Module UP8S
NSE1
Circuit Diagram of SIM Connectors (Version 9
Edit 54) for layout version 09
Original 03/98
3/A3S4
System Module UP8S
NSE1
Circuit Diagram of CPU Block (Version 9
Edit 155) for layout version 09
Original 03/98
3/A3S5
System Module UP8S
NSE1
Circuit Diagram of Audio
(Version 9 Edit 115) for layout version 09
Original 03/98
3/A3S6
System Module UP8S
NSE1
Circuit Diagram of IR Module (Version 9
Edit 93) for layout version 9
Original 03/98
3/A3S7
System Module UP8S
NSE1
Circuit Diagram of RF Block (Version
9 Edit 187) for layout version 09
Original 03/98
3/A3S8
System Module UP8S
NSE1
User Interface Connector (Version 9
Edit 75) for layout version 9
Original 03/98
3/A3S9
System Module UP8S
NSE1
Layout Diagram of UP8S Top (Version 09)
testpoint ref J102 J103 J107 J110 J111 J221 J222 J224 J229 J230 J231 J232 J233 J234 J236 J250 J252 J253 J254 J255 J502 J506 J510 J514
name FBUS_RX MBUS LGND VPP WDDISX 5V DSPXF VCOBBA MAD selftest MAD selftest VSIM VB (battery voltage in baseband) RFCLK VSRM RAMSELX GND COBBARSTX COBBAWRX COBBARDX COBBACLK Power control op.amp output voltage to N550 ( Vpd, pin ) RFC ( 13 MHz sinewave ) VRX ( regulated supply for RX ) VTX ( regulated supply for TX )
condition power on power on flash programming power on flash programming power on active state test mode set externally test mode set externally SIM power on battery connected active state power on active state power on active state active state active state power level depended
dclevel pulsed DC (0V/2.8V) pulsed DC (0V/2.8V) 0V nominal 5V (5V flash) or 3.0V (3V flash) reset state 0V, normal state 2.8V nominal 5.0V (5V flash) or 3.0V (3V flash) pulse active 0V, nonactive 2.8V nominal 2.8V (min 2.7V, max 2.85V)
aclevel
nominal 2.8V (3V SIM card) or 5.0V (5V SIM card) nominal 3.6V (min 3.0, max 4.2) typ. 1.0Vpp (min 0.5Vpp, max 2.0Vpp) nominal 5.5V (min 5V, max 6V) pulse active 0V, nonactive 2.8V 0V reset state 0V, normal state 2.8V pulse active 0V, nonactive 2.8V pulse active 0V, nonactive 2.8V pulsed DC (0V/2.8V) pulsed DC 0V 2.8 V min 2.7 / max 2.85 V, pulsed 2.8 V min 2.7 / max 2.85 V, pulsed typ. 1.0 Vpp min 0.5/max 2.0 Vpp CCONT switch mode regulator ripple voltage
Original 03/98
3/A3S10
System Module UP8S
testpoint ref J516 J518 J520 J522 J530&J532 J540 name VSYN_1 ( regulated supply for VCOs) VREF_2 ( ref. voltage for N500 ) AFC ( autom. freq. cntrl ) VXO ( regulated supply for VCTCXO ) 71 MHz IF input to N620 13 MHz output from N620 to Z620 95 dBm @ X540 (ext. RF connector ) 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain condition dclevel 2.8 V min 2.7 / max 2.85 V 1.5 V +/ 1.5% 0 2.3 V, typ. 1.15 V ( room temp. ) 2.8 V min 2.7 / max 2.85 V typ. ca. 1.2 V pulsed typ. ca. 1.5 V pulsed aclevel
NSE1
typ 100 140 uVpp balanced voltage at 71 MHz typ. ca. 700 uVrms
J550 & J552 J562
116 MHz TX IF to N500 RXC ( receive gain control voltage ) RX gain setting depended
typ. ca. 1.1 1.2 V pulsed control range is 0.5 1.45 V, ,pulsed. typ. 1.31.4 V for calibrated maximum gain
typ. ca. 100 mVrms each
Layout Diagram of UP8S Bottom (Version 9)
testpoint ref J101 J104 J108 J220 J223 J225 J226 J227 J228 J235
name FBUS_TX CCONTCSX (CCONT chip select) CHRG_CTRL V5V CCONTINT (charger, RTC interrupt) EXTSYSRESETX VCXOPWR PURX (power on reset) SLEEPCLK (32kHz clock) ROM1SELX
condition active state active state charger connected active state interrupt power on power on power up/down power on active state
dclevel pulsed DC (0V72.8V) pulse active 0V, nonactive 2.8V pulsed DC (0V/2.8V) nominal 5.0V (min 4.8V, max 5.2V) pulse active 2.8V, nonactive 0V reset state 0V, normal state 2.8V active state 2.8V, nonactive 0V reset state 0V, normal state 2.8V pulsed DC (0V/2.8V) pulse active 0V, nonactive 2.8V
aclevel
Original 03/98
3/A3S11
System Module UP8S
testpoint ref J251 J256 J500 name AGND COBBADAX Control voltage for UHF VCO module G600 condition pcb ground active state channel 60 channel 1 channel 124 dclevel 0V pulse active 0V, nonactive 2.8V 2.25 +/ 0.25 V > 0.8 V < 3.7 V typ. 2.0 2.2 V min 0.5 / max 4.0 V 2.8 V min 2.7 / max 2.85 V 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain typ ca. 1.0 1.1 V pulsed min. 0.7 / max. 1.4 V aclevel
NSE1
J504 J508 J534&J536
Control voltage for VHF VCO circuit VSYN_2 ( regulated supply for PLLS ) 13 MHz IF output to N250
typ. 50 mVpp balanced voltage at 13 MHz
J538
13 MHz output from Z620 to N620
typ. ca. 1.5 V pulsed
typ. ca 600 uVrms
J542 J554 J556 J558 J560
VHF VCO output ( 232 MHz ) TXC ( TX power control voltage ) TXP ( TX enable ) TXQP ( other half of balanced Qsignal ) TXIP ( other half of balanced Isignal )
@level 19 typ. ca. 0.6 V pulse @level 5 typ ca. 1.8 V pulse 2.8 V logic level pulse, ( max. 0.8 V "0" / min 2.0 V "1" ) 0.8 V pulsed 0.8 V pulsed
typ. 400 mVpp. > 100 mVpp required
400 mVpp 400 mVpp
Original 03/98
3/A3S12