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Semiconductor

ICM7226A, ICM7226B
8-Digit, Multi-Function, Frequency Counter/Timer
Description
The ICM7226 is a fully integrated Universal Counter and LED display driver. It combines a high frequency oscillator, a decade timebase counter, an 8-decade data counter and latches, a 7-segment decoder, digit multiplexer and segment and digit drivers which can directly drive large LED displays. The counter inputs accept a maximum frequency of 10MHz in frequency and unit counter modes and 2MHz in the other modes. Both inputs are digital inputs. In many applications, amplification and level shifting will be required to obtain proper digital signals for these inputs. The ICM7226 can function as a frequency counter, period counter, frequency ratio (fA/fB) counter, time interval counter or as a totalizing counter. The devices require either a 10MHz or 1MHz quartz crystal timebase, or if desired an external timebase can also be used. For period and time interval, the 10MHz timebase gives a 0.1µs resolution. In period average and time interval average, the resolution can be in the nanosecond range. In the frequency mode, the user can select accumulation times of 0.01s, 0.1s, 1s and 10s. With a 10s accumulation time, the frequency can be displayed to a resolution of 0.1Hz. There is 0.2s between measurements in all ranges. Control signals are provided to enable gating and storing of prescaler data. Leading zero blanking has been incorporated with frequency display in kHz and time in µs. The display is multiplexed at a 500Hz rate with a 12.2% duty cycle for each digit. The ICM7226A is designed for common anode displays with typical peak segment currents of 25mA, and the ICM7226B is designed for common cathode displays with typical segment currents of 12mA. In the display off mode, both digit drivers and segment drivers are turned off, allowing the display to be used for other functions.

August 1997

Features
· CMOS Design for Very Low Power · Output Drivers Directly Drive Both Digits and Segments of Large 8-Digit LED Displays · Measures Frequencies from DC to 10MHz; Periods from 0.5µs to 10s · Stable High Frequency Oscillator uses either 1MHz or 10MHz Crystal · Both Common Anode and Common Cathode Available · Control Signals Available for External Systems Interfacing · Multiplexed BCD Outputs

Applications
· Frequency Counter · Period Counter · Unit Counter · Frequency Ratio Counter · Time Interval Counter

Ordering Information
PART NUMBER ICM7226AlJL ICM7226BlPL TEMP. RANGE (oC) -25 to 85 -25 to 85 PACKAGE 40 Ld CERDIP 40 Ld PDIP PKG. NO. F40.6 E40.6

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

© Harris Corporation 1997

File Number

3169.1

9-15

ICM7226A, ICM7226B Pinouts
ICM7226A COMMON ANODE (CERDIP) TOP VIEW
CONTROL INPUT INPUT B MEASUREMENT IN PROGRESS FUNCTION STORE BCD 4 BCD 8 DP SEG e 1 2 3 4 5 6 7 8 9 40 INPUT A 39 HOLD 38 BUF OSC OUT 37 NC (NOTE 1) 36 OSC OUT 35 OSC IN 34 NC (NOTE 1) 33 EXT OSC IN 32 RST OUT 31 EXT RANGE 30 D1 29 D2 28 D3 27 D4 26 D5 25 VDD 24 D6 23 D7 22 D8 21 RANGE

SEG g 10 SEG a 11 VSS 12 SEG d 13 SEG b 14 SEG c 15 SEG f 16 BCD 2 17 BCD 1 18 RST INPUT 19 EXT DP IN 20

ICM7226B COMMON CATHODE (PDIP)

TOP VIEW
CONTROL INPUT INPUT B MEASUREMENT IN PROGRESS FUNCTION STORE BCD 4 BCD 8 D1 D3 1 2 3 4 5 6 7 8 9 40 INPUT A 39 HOLD 38 BUF OSC OUT 37 NC (NOTE 1) 36 OSC OUT 35 OSC IN 34 NC (NOTE 1) 33 EXT OSC IN 32 RST OUT 31 EXT RANGE 30 DP OUT 29 SEG g 28 SEG e 27 SEG a 26 SEG d 25 VDD 24 SEG b 23 SEG c 22 SEG f 21 RANGE

D2 10 D4 11 VSS 12 D5 13 D6 14 D7 15 D8 16 BCD 2 17 BCD 1 18 RST INPUT 19 EXT DP IN 20

NOTE: 1. For maximum frequency stability, connect to VDD or VSS .

9-16

ICM7226A, ICM7226B Functional Block Diagram
DIGIT OUTPUTS (8)

DECODER

8

DIGIT DRIVERS REFERENCE COUNTER +103

8

3

RANGE CONTROL LOGIC

EXT OSC INPUT OSC INPUT OSC OUTPUT BUF OSC OUTPUT 6 RESET INPUT MAIN EN COUNTER ÷103 CL 4 8 4 4 4 RESET OVERFLOW DP LOGIC 4 OSC SELECT 104 OR 105 100Hz STORE AND RESET LOGIC RANGE SELECT LOGIC 5

RANGE INPUT

EXT RANGE INPUT

CONTROL LOGIC

CONTROL INPUT

INPUT A INPUT B

INPUT CONTROL LOGIC

4

4

4

EXT DP INPUT

DATA LATCHES STORE OUTPUT MUX DECODER AND LZB LOGIC SEGMENT DRIVERS

D INPUT CONTROL LOGIC CL

Q MAIN FF R

4

7

8 SEGMENT OUTPUTS (8)

FUNCTION INPUT

FN CONTROL LOGIC

4

4

BCD OUTPUTS (4)

6 MEAS IN PROGRESS OUTPUT HOLD INPUT

RESET OUTPUT

STORE OUTPUT

9-17

ICM7226A, ICM7226B
Absolute Maximum Ratings
Maximum Supply Voltage (VDD - VSS). . . . . . . . . . . . . . . . . . . . 6.5V Maximum Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . 400mA Maximum Segment Output Current . . . . . . . . . . . . . . . . . . . . . 60mA Voltage On Any Input or Output Terminal (Note 1) . . . . . . . . . . . . . . VDD +0.3V to VSS -0.3V

Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 45 9 PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 1. Destructive latchup may occur if input signals are applied before the power supply is established or if inputs or outputs are forced to voltages exceeding VDD or VSS by 0.3V. 2. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VDD = 5.0V, TA = 25oC, Unless Otherwise Specified TEST CONDITIONS Display Off, Unused Inputs to VSS -25oC to 85oC, INPUT A, INPUT B Frequency at fMAX -25oC to 85oC 4.75V < VDD < 6.0V, Figure 9 Function = Frequency, Ratio, Unit Counter Function = Period, Time Interval MIN 4.75 10 TYP 2 14 MAX 5 6.0 UNITS mA V MHz

PARAMETER Operating Supply Current, IDD Supply Voltage Range (VDD -VSS), VSUPPLY Maximum Frequency INPUT A, Pin 40, fA(MAX)

2.5 2.5 250 0.1 2000 -

500 200 15

10 -

MHz MHz ns MHz µS Hz ms mV/µs

Maximum Frequency INPUT B, Pin 2, fB(MAX) Minimum Separation INPUT A to INPUT B, Time Interval Function

-25oC to 85oC 4.75V < VDD < 6.0V, Figure 10 -25oC to 85oC 4.75V < VDD < 6.0V, Figure 1

Oscillator Frequency and External Oscillator Frequency, -25oC to 85oC 4.75V < VDD < 6.0V fOSC Oscillator Transconductance, gM Multiplex Frequency, fMUX Time Between Measurements Input Rate of Charge, dVIN/dt Input Voltages: Pins 2, 19, 33, 39, 40, 35 Input Low Voltage, VIL Input High Voltage, VlH Pins 2, 39, 40, Input Leakage, A, B, IILK Input Resistance to VDD Pins 19, 33, RIN Input Resistance to VSS Pin 31, RIN Output Current Low Output Current, Pins 3, 5-7, 17, 18, 32, 38, IOL High Output Current, Pins 5-7, 17, 18, 32, HOL High Output Current, Pins 3, 38, HOL ICM7226A Segment Driver: Pins 8-11, 13-16 Low Output Current, IOL High Output Current, IOH VO = +1.5V VO = VDD -1.0V VOL = +0.4V VOH = +2.4V VOH = VDD -0.8V VIN = VDD -1.0V VIN = +1.0V -25oC to 85oC VDD -4.75V, TA = 85oC fOSC = 10MHz fOSC = 10MHz Inputs A, B

3.5 100 50

400 100

1.0 20 -

V V µA k k µA µA µA

400 100 265

-

-

25 -

35 100

-

mA µA

9-18

ICM7226A, ICM7226B
Electrical Specifications
VDD = 5.0V, TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS

PARAMETER Multiplex Inputs: Pins 1, 4, 20, 21 Input Low Voltage, VIL Input High Voltage, VIH Input Resistance to VSS, RIN Digit Driver: Pins 22-24, 26-30 Low Output Current, IOL High Output Current, IOH ICM7226B Segment Driver: Pins 22-24, 26-30 Leakage Current, IL High Output Current, IOH Multiplex Inputs: Pins 1, 4, 20, 21 Input Low Voltage, VIL Input High Voltage, VIH Input Resistance to VSS, RIN Digit Driver: Pins 8-11, 13-16 Low Output Current, IOL High Output Current, IOH NOTES:

2.0 VIN = +1.0V VO = +1.0V VO = VDD -2.0V 50

100

0.8 -

V V k

150

-0.3 180

-

mA mA

VO = VSS VO = VDD -2.0V

10

15

10 -

µA mA

VDD-0.8 VIN = VDD -1.0V VO = +1.0V VO = VDD -2.5V 100

360

VDD-2.0 -

V V k

50 -

75 100

-

mA µA

1. Assumes all leads soldered or welded to PC board and free air flow. 2. Typical values are not tested.

Timing Waveform
40ms STORE 30ms TO 40ms 60ms RESET 40ms UPDATE 190ms TO 200ms MEASUREMENT IN PROGRESS FUNCTION: TIME INTERVAL UPDATE PRIMING MEASUREMENT INTERVAL

INPUT A PRIMING EDGES INPUT B 250ns MIN MEASURED INTERVAL (FIRST)

NOTE: 1. If range is set to 1 event, first and last measured interval will coincide.

MEASURED INTERVAL (LAST)

FIGURE 1. WAVEFORMS FOR TIME INTERVAL MEASUREMENT (OTHERS ARE SIMILAR, BUT WITHOUT PRIMING PHASE)

9-19

ICM7226A, ICM7226B Typical Performance Curves
200 TA = 25oC 300 VDD = 5.5V 4.5 VDD 6.0V

50 VDD = 5.0V IDIGIT (mA) VDD = 4.5V IDIG (mA) 100 50 85oC 25oC -20oC 0 0 1 VOUT (V) 2 3 0 0 1 VDD-VOUT (V) 2 3 200

100

FIGURE 2. ICM7226B TYPICAL IDIGIT vs VOUT

FIGURE 3. ICM7226A TYPICAL IDIG vs VDD-VOUT

30

4.5 VDD 6.0V 25oC

80 -20oC

TA = 25oC VDD = 5.5V

60 20 ISEG (mA) ISEG (mA) 85oC 40 VDD = 5.0V VDD = 4.5V

10 20

0 0 1 VDD-VOUT (V) 2 3

0 0 1 VOUT (V) 2 3

FIGURE 4. ICM7226B TYPICAL ISEG vs VDD-VOUT

FIGURE 5. ICM7226A TYPICAL ISEG vs VOUT

200 VDD = 5.0V -20oC 25oC 150 IDIGIT (mA) ISEG (mA)

80 VDD = 5.0V -20oC 25oC 60 85oC 85oC 40

100

50

20

0

0 0 1 VOUT (V) 2 3 0 1 VOUT (V) 2 3

FIGURE 6. ICM7226B TYPICAL IDIGIT vs VOUT

FIGURE 7. ICM7226A TYPICAL ISEG vs VOUT

9-20

ICM7226A, ICM7226B Typical Performance Curves
20 fA (MAX) FREQUENCY UNIT COUNTER, FREQUENCY RATIO MODES 15 FREQUENCY (MHz)

(Continued)

10 fA (MAX) fB (MAX) PERIOD TIME INTERVAL MODES 5 TA = 25oC 0 3 4 VDD-VSS (V) 5 6

FIGURE 8. fA(MAX), fB(MAX) AS A FUNCTION OF SUPPLY

Description
INPUTS A and B The signal to be measured is applied to INPUT A in frequency period, unit counter, frequency ratio and time interval modes. The other input signal to be measured is applied to INPUT B in frequency ratio and time interval. fA should be higher than fB during frequency ratio.
COUNTED TRANSITIONS

Both inputs are digital inputs with a typical switching threshold of 2.0V at VDD = 5.0V and input impedance of 250k. For optimum performance, the peak-to-peak input signal should be at least 50% of the supply voltage and centered about the switching voltage. When these inputs are being driven from TTL logic, it is desirable to use a pullup resistor. The circuit counts high to low transitions at both inputs Note that the amplitude of the input should not exceed the device supply (above the VDD and below the VSS) by more than 0.3V, otherwise the device may be damaged. Multiplexed Inputs The FUNCTION, RANGE, CONTROL and EXTERNAL DECIMAL POINT inputs are time multiplexed to select the function desired. This is achieved by connecting the appropriate Digit driver output to the inputs. The function, range and control inputs must be stable during the last half of each digit output, (typically 125µs). The multiplexed inputs are active high for the common anode lCM7226A and active low for the common cathode lCM7226B. Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of operation is selected, since changes in voltage on the digit drivers can be capacitively coupled through the LED diodes to the multiplex inputs. For maximum noise immunity, a 10k resistor should be placed in series with the multiplexed inputs as shown in the application circuits.

50ns MIN INPUT A 4.5V 0.5V 50ns MIN tr = tf = 10ns

FIGURE 9. WAVEFORM FOR GUARANTEED MINIMUM fA(MAX) FUNCTION = FREQUENCY, FREQUENCY RATIO, UNIT COUNTER

MEASURED INTERVAL 250ns MIN INPUT A OR 4.5V INPUT B 0.5V

250ns MIN

tr = tf = 10s

FIGURE 10. WAVEFORM FOR GUARANTEED MINIMUM fB(MAX) AND fA(MAX) FOR FUNCTION = PERIOD AND TIME INTERVAL

9-21

ICM7226A, ICM7226B
Table 1 shows the functions selected by each digit for these inputs.
TABLE 1. MULTIPLEXED INPUT FUNCTIONS INPUT FUNCTION INPUT Pin 4 FUNCTION Frequency Period Frequency Ratio Time Interval Unit Counter Oscillator Frequency RANGE INPUT Pin 21 0.01s/1 Cycle 0.1s/10 Cycles 1s/100 Cycles 10s/1K Cycles Enable External Range Input CONTROL INPUT Pin 1 Display Off Display Test 1MHz Select External Oscillator Enable External Decimal Point Enable External DP INPUT Pin 20 DIGIT D1 D8 D2 D5 D4 D3 D1 D2 D3 D4 D5 D4 and Hold D8 D2 D1 D3 FUNCTION Frequency (fA) Period (tA) Ratio (fA /fB) Time Interval (AB) Unit Counter (Count A) Osc. Freq. (fOSC)

The implementation of different functions is done by routing the different signals to two counters, called "Main Counter" and "Reference Counter". A simplified block diagram of the device for functions realization is shown in Figure 11. Table 2 shows which signals will be routed to each counter in different cases. The output of the Main Counter is the information which goes to the display. The Reference Counter divides its input to 1, 10, 100 and 1000. One of these outputs will be selected through the range selector and drive the enable input of the Main Counter. This means that the Reference Counter, along with its' associated blocks, directs the Main Counter to begin counting and determines the length of the counting period. Note that Figure 11 does not show the complete functional diagram (See the Functional Block Diagram). After the end of each counting period, the output of the Main Counter will be latched and displayed, then the counter will be reset and a new measurement cycle will begin. Any change in the FUNCTION INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the FUNCTION INPUT is changed. In all cases, the 1-0 transitions are counted or timed.
TABLE 2. INPUT ROUTING MAIN COUNTER Input A Oscillator Input A Oscillator Input A Oscillator COUNTER 100Hz (Oscillator ÷105 or 104) Input A Input B Input A Input B Not Applicable 100Hz (Oscillator ÷105 or 104)

Decimal point is output for same digit that is connected to this input.

Function Input The six functions that can be selected are: Frequency, Period, Time Interval, Unit Counter, Frequency Ratio and Oscillator Frequency.

INTERNAL CONTROL

INTERNAL CONTROL

100Hz INPUT A INPUT B INPUT SELECTOR CLOCK REFERENCE COUNTER

÷ 1 ÷ 10 ÷ 100 ÷ 1000
INTERNAL CONTROL INTERNAL OR EXTERNAL OSCILLATOR INPUT A INTERNAL CONTROL RANGE SELECTOR

ENABLE INPUT SELECTOR CLOCK MAIN COUNTER

FIGURE 11. SIMPLIFIED BLOCK DIAGRAM OF FUNCTIONS IMPLEMENTATION

9-22

ICM7226A, ICM7226B
Frequency - In this mode input A is counted by the Main Counter for a precise period of time. This time is determined by the time base oscillator and the selected range. For the 10MHz (or 1MHz) time base, the resolutions are 100Hz, 10Hz, 1Hz and 0.1Hz. The decimal point on the display is set for kHz reading. Period - In this mode, the timebase oscillator is counted by the Main Counter for the duration of 1, 10, 100 or 1000 (range selected) periods of the signal at input A. A 10MHz timebase gives resolutions of 0.1µs to 0.0001µs for 1000 periods averaging. Note that the maximum input frequency for period measurement is 2.5MHz. Frequency Ratio - In this mode, the input A is counted by the Main Counter for the duration of 1, 10, 100 or 1000 (range selected) periods of the signal at input B. The frequency at input A should be higher than input B for meaningful result. The result in this case is unitless and its resolution can go up to 3 digits after decimal point. Time Interval - In this mode, the timebase oscillator is counted by the Main Counter for the duration of a 1-0 transition of input A until a 1-0 transition of input B. This means input A starts the counting and input B stops it. If other ranges, except 0.01s/1 cycle are selected the sequence of input A and B transitions must happen 10, 100 or 1000 times until the display becomes updated; note this when measuring long time intervals to give enough time for measurement completion. The resolution in this mode is the same as for period measurement. See the Time Interval Measurement section also. Unit Counter - In this mode, the Main Counter is always enabled. The input A is counted by the Main Counter and displayed continuously. Oscillator Frequency - In this mode, the device makes a frequency measurement on its timebase. This is a self test mode for device functionality check. For 10MHz timebase the display will show 10000.0, 10000.00, 10000.000 and Overflow in different ranges. Range Input The RANGE INPUT selects whether the measurement period is made for 1,10,100 or 1000 counts of the Reference Counter or it is controlled by EXT RANGE input. As it is shown in Table 1, this gives different counting windows for frequency measurement and various cycles for other modes of measurement. In all functional modes except Unit Counter, any change in the RANGE INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the RANGE INPUT is changed. Control Input Unlike the other multiplexed inputs, to which only one of the digit outputs can be connected at a time, this input can be tied to different digit lines to select combination of controls. In this case, isolation diodes must be used in digit lines to avoid crosstalk between them (see Figure 19). The direction of diodes depends on the device version, common anode or common cathode. For maximum noise immunity at this input, in addition to the 10K resistor which was mentioned before, a 39pF to 100pF capacitor should also be placed between this input and the VDD or VSS (See Figure 19). Display Off - To disable the display drivers, it is necessary to tie the D4 line to the CONTROL INPUT and have the HOLD input at VDD . While in Display Off mode, the segments and digit drivers are all off, leaving the display lines floating, so the display can be shared with other devices. In this mode, the oscillator continues to run with a typical supply current of 1.5mA with a 10MHz crystal, but no measurements are made and multiplexed inputs are inactive. A new measurement cycle will be initiated when the HOLD input is switched to VSS . Display Test - Display will turn on with all the digits showing 8s and all decimal points also on. The display will be blanked if Display Off is selected at the same time. 1MHz Select - The 1MHz select mode allows use of a 1MHz crystal with the same digit multiplex rate and time between measurement as with a 10MHz crystal. This is done by dividing the oscillator frequency by 104 rather than 105. The decimal point is also shifted one digit to the right in period and time interval, since the least significant digit will be in µs increment rather than 0.1µs increment. External Oscillator Enable - In this mode, the signal at EXT OSC INPUT is used as a timebase instead of the on-board crystal oscillator (built around the OSC INPUT, OSC OUTPUT inputs). This input can be used for an external stable temperature compensated crystal oscillator or for special measurements with any external source. The on-board crystal oscillator continues to work when the external oscillator is selected. This is necessary to avoid hang-up problems, and has no effect on the chip's functional operation. If the on-board oscillator frequency is less than 1MHz or only the external oscillator is used, THE OSC INPUT MUST BE CONNECTED TO THE EXT OSC INPUT providing the timebase has enough voltage swing for OSC INPUT (See Electrical Specifications). If the external timebase is TTL level a pullup resistor must be used for OSC INPUT. The other way is to put a 22M resistor between OSC INPUT and OSC OUTPUT and capacitively couple the EXT OSC INPUT to OSC INPUT. This will bias the OSC INPUT at its threshold and the drive voltage will need to be only 2VP-P . The external timebase frequency must be greater than 100kHz or the chip will reset itself to enable the on-board oscillator. External Decimal Point Enable - In this mode, the EX INPUT is enabled. A decimal point will be displayed for digit that its output line is connected to this input (EX INPUT). Digit 8 should not be used since it will override overflow output. Leading zero blanking is effective for digits to the left of selected decimal point. Hold Input Except in the unit counter mode, when the HOLD input is at VDD , any measurement in progress (before STORE goes low) is stopped, the main counter is reset and the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold the main counter data are not updated, so the last complete measurement is displayed. In unit counter mode when HOLD input is at VDD , the counter is not stopped or reset, but the display is frozen at that instantaneous value. When HOLD goes low the count continues from the new value in the new counter. DP the DP the the

9-23

ICM7226A, ICM7226B
RST IN Input The RST IN is provided to reset the Main Counter, stop any measurement in progress, and enable the display latches, resulting in the all zero display. It is suggested to have a capacitor at this input to VSS to prevent any hangup problem on power up. See application circuits. EXT RANGE Input This input is provided to select ranges other than those provided in the chip. In any mode of measurement the duration of measurement is determined by the EXT RANGE if this input is enabled. This input is sampled at 10ms intervals by the 100Hz reference derived from the timebase. Figure 12 shows the relationship between this input, 100Hz reference signal and MEAS IN PROGRESS. EXT RANGE can change state anywhere during the period of 100Hz reference by will be sampled at the trailing edge of the period to start or stop measurement.
REFERENCE COUNTER CLOCK MEAS IN PROGRESS EXT RANGE INPUT tr MEAS IN PROGRESS 40ms STORE 30ms TO 40ms RESET OUT 40ms 60ms 190ms TO 200ms

FIGURE 13. RESET OUT, STORE AND MEASUREMENT IN PROGRESS OUTPUTS BETWEEN MEASUREMENTS

BCD Outputs The BCD representation of each display digit is available at the BCD outputs in a multiplexed fashion. See Table 3 for digits truth table. The BCD output of each digit is available when its corresponding digit output is activated. Note that the digit outputs are multiplexed from D8 (MSD) to D1 (LSD). The positive going (ICM7226A, common anode) or the negative going (ICM7226B, common cathode) digit drive signals lag the BCD data by 2µs to 6µs. This starting edge of each digit drive signal should be used to externally latch the BCD data. Each BCD output drives one low power Schottky TTL load. Leading zero blanking has no effect on the BCD outputs.
TABLE 3. TRUTH TABLE BCD OUTPUTS NUMBER 0 1 2 3 4 5 6 7 8 9 BCD 8 PIN 7 0 0 0 0 0 0 0 0 1 1 BCD 4 PIN 6 0 0 0 0 1 1 1 1 0 0 BCD 2 PIN 17 0 0 1 1 0 0 1 1 0 0 BCD 1 PIN 18 0 1 0 1 0 1 0 1 0 1

FIGURE 12. EXTERNAL RANGE INPUT TO END OF MEASUREMENT IN PROGRESS

This input should not be used for short arbitrary ranges (because of its sampling period), it is provided for very long gating purposes. A way of using the ICM7226 for a short arbitrary range is to feed the gating signal into the INPUT B and run the device in the Frequency Ratio mode. Note that the gating period will be from one positive edge until the next positive edge of INPUT B (0.01s/1 cycle range). MEAS IN PROGRESS, STORE, RST OUT Outputs These outputs are provided for external system interfacing. MEAS IN PROGRESS stays low during measurements and goes high for intervals between measurements. Figure 13 shows the relationship between these outputs for intervals between measurements. All these outputs can drive a low power Schottky TTL. The MEAS IN PROGRESS can drive one ECL load if the ECL device is powered from the same power supply as the ICM7226.

BUF OSC OUT Output The BUFFered OSCillator OUTput is provided for use of the on-board oscillator signal, without loading the oscillator itself. This output can drive one low power Schottky TTL load. Care should be taken to minimize capacitive loading on this pin. Decimal Point Position Table 4 shows the decimal point position for different modes of lCM7226 operation. Note that the digit 1 is the least significant digit. Table is given for 10MHz timebase frequency.

TABLE 4. DECIMAL POINT POSITIONS RANGE 0.01s/1 Cycle 0.1s/10 Cycle 1s/100 Cycle 10s/1K Cycle External FREQUENCY D2 D3 D4 D5 N/A PERIOD D2 D3 D4 D5 N/A FREQUENCY RATIO D1 D2 D3 D4 N/A TIME INTERVAL D2 D3 D4 D5 N/A UNIT COUNTER D1 D1 D1 D1 N/A OSCILLATOR FREQUENCY D2 D3 D4 D5 N/A

9-24

ICM7226A, ICM7226B
Overflow Indication When overflow happens in any measurement it will be indicated on the decimal point of the digit 8. A separate LED indicator can be used. Figure 14 shows how to connect this indicator. When timing repetitive signals, it is not necessary to "prime" the lCM7226A and lCM7226B as the first alternating signal states automatically prime the device. See Figure 1. During any time interval measurement cycle, the ICM7226A and lCM7226B requires 200ms following B going low to update all internal logic. A new measurement cycle will not take place until completion of this internal update time. Oscillator Considerations
a f g e d c
DP

b

LED overflow indicator connections: Overflow will be indicated on the decimal point output of digit 8.
DEVICE ICM7226A ICM7226B CATHODE Decimal Point D8 ANODE D8 Decimal Point

The oscillator is a high gain complementary FET inverter. An external resistor of 10M or 22M should be connected between the oscillator input and output to provide biasing. The oscillator is designed to work with a parallel resonant 10MHz quartz crystal with a static capacitance of 22pF and a series resistance of less than 35. Among suitable crystals is the 10MHz CTS KNIGHTS ISI-002. For a specific crystal and load capacitance, the required gM can be calculated as follows:
CO 2 2 g M = C IN C OUT R S 1 + ------- CL C IN C OUT where C L = -------------------------------- C IN + C OUT

FIGURE 14. SEGMENT IDENTIFICATION AND DISPLAY FONT

Time Interval Measurement When in the time interval mode and measuring a single event, the lCM7226A and lCM7226B must first be "primed" prior to measuring the event of interest. This is done by first generating a negative going edge on Channel A followed by a negative going edge on Channel B to start the "measurement interval". The inputs are then primed ready for the measurement. Positive going edges on A and B, before or after the priming, will be needed to restore the original condition. Priming can be easily accomplished using the circuit in Figure 15.
SIGNAL A 2 SIGNAL B 2 VDD PRIME 1 VDD INPUT B INPUT A

CO = Crystal Static Capacitance RS = Crystal Series Resistance CIN = Input Capacitance COUT = Output Capacitance = 2f The required gM should not exceed 50% of the gM specified for the lCM7226 to insure reliable startup. The OSCillator INPUT and OUTPUT pins each contribute about 4pF to CIN and COUT . For maximum stability of frequency, CIN and COUT should be approximately twice the specified crystal static capacitance. In cases where non decade prescalers are used, it may be desirable to use a crystal which is neither 10MHz or 1MHz. In that case both the multiplex rate and time between measurements will be different. The multiplex rate is:
f OSC f OSC f MUX = ------------------ for 10MHz mode and f MUX = ------------------ for the 4 3 2 × 10 2 × 10 6 2 × 10 1MHz mode. The time between measurements is ------------------ in f OSC 2 × 10 the 10MHz mode and ------------------ in the 1MHz mode. f OSC
5

N.O.

150K 1 1 10K 1

100K VSS

1N914 0.1µF VSS VSS 10nF

DEVICE 1 2

TYPE CD4049B Inverting Buffer CD4070B Exclusive - OR

The buffered oscillator output should be used as an oscillator test point or to drive additional logic; this output will drive one low power Schottky TTL load. When the buffered oscillator output is used to drive CMOS or the external oscillator input, a 10k resistor should be added from the buffered oscillator output to VDD . The crystal and oscillator components should be located as close to the chip as practical to minimize pickup from other signals. Coupling from the EXTERNAL OSClLLATOR INPUT to the OSClLLATOR OUTPUT or INPUT can cause undesirable shifts in oscillator frequency.

FIGURE 15. PRIMING CIRCUIT, SIGNALS A AND B BOTH HIGH OR LOW

Following the priming procedure (when in single event or 1 cycle range) the device is ready to measure one (only) event.

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ICM7226A, ICM7226B
Display Considerations The display is multiplexed at a 500Hz rate with a digit time of 244µs. An interdigit blanking time of 6µs is used to prevent display ghosting (faint display of data from previous digit superimposed on the next digit). Leading zero blanking is provided, which blanks the left hand zeroes after decimal point or any non zero digits. Digits to the right of the decimal point are always displayed. The leading zero blanking will be disabled when the Main Counter overflows. The lCM7226A is designed to drive common anode LED displays at peak current of 25mA/segment, using displays with VF = 1.8V at 25mA. The average DC current will be greater than 3mA under these conditions. The lCM7226B is designed to drive common cathode displays at peak current of 15mA/segment using displays with VF = 1.8V at 15mA. Resistors can be added in series with the segment drivers to limit the display current, if required. The Typical Performance Curves show the digit and segment currents as a function of output voltage for common anode and common cathode drivers. To increase the light output from the displays, VDD may be increased to 6.0V. However, care should be taken to see that maximum power and current ratings are not exceeded. The SEGment and Digit outputs in both the ICM7226A and ICM7226B are not directly compatible with either TTL or
0 FREQUENCY MEASURE 0.01s 0.1s 1s 10s 1 CYCLE 10 CYCLES 102 CYCLES 103 CYCLES PERIOD MEASURE fOSC = 10MHz 1 10 103 FREQUENCY (Hz) 105 107 MAXIMUM NUMBER OF SIGNIFICANT DIGITS 1 2 3 4 5 6 7 8 1 10 102 103 104 105 TIME INTERVAL (µs) 106 107 108 MAXIMUM TIME INTERVAL FOR 10 INTERVALS MAXIMUM TIME INTERVAL FOR 103 INTERVALS MAXIMUM TIME INTERVAL FOR 102 INTERVALS

CMOS logic. Therefore, level shifting with discrete transistors may be required to use these outputs as logic signals. External latching should be down on the leading edge of the digit signal. Accuracy In a Universal Counter, crystal drift and quantization errors cause errors. In frequency, period and time interval modes, a signal derived from the oscillator is used in either the Reference Counter or Main Counter, and in these modes, an error in the oscillator frequency will cause an identical error in the measurement. For instance, an oscillator temperature coefficient of 20ppm/oC will cause a measurement error of 20ppm/oC. In addition, there is a quantization error inherent in any digital measurement of ±1 count. Clearly this error is reduced by displaying more digits. In the frequency mode maximum accuracy is obtained with high frequency inputs and in period mode maximum accuracy is obtained with low frequency inputs. As can be seen in Figure 16. In time interval measurements there can be an error of 1 count per interval. As a result there is the same inherent accuracy in all ranges as shown in Figure 17. In frequency ratio measurement can be more accurately obtained by averaging over more cycles of INPUT B as shown in Figure 18.
0

MAXIMUM NUMBER OF SIGNIFICANT DIGITS

2

4

6

8

FIGURE 16. MAXIMUM ACCURACY OF FREQUENCY AND PERIOD MEASUREMENTS DUE TO LIMITATIONS OF QUANTIZATION ERRORS
0 1 MAXIMUM NUMBER OF SIGNIFICANT DIGITS

FIGURE 17. MAXIMUM ACCURACY OF TIME INTERVAL MEASUREMENT DUE TO LIMITATIONS OF QUANTIZATION ERRORS

RANGE 2 3 4 5 6 7 8 1 10 102 103 104 fA /fB 105 106 107 108 1 CYCLE 10 CYCLES 102 CYCLES 103 CYCLES

FIGURE 18. MAXIMUM ACCURACY FOR FREQUENCY RATIO MEASUREMENT DUE TO LIMITATION OF QUANTIZATION ERRORS

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ICM7226A, ICM7226B Test Circuit
VDD = 5.0V DISPLAY DISPLAY OFF TEST 1MHz EXT OSC EXT DP TEST

EXT OSC IN FUNCTION GENERATOR 39pF FUNCTION GENERATOR 1 2 MEAS IN PROGRESS FUNCTION 10K D1 D8 D2 D5 D4 D3 STORE BCD C BCD D DP 3 4 5 6 7 8 9 10 11 12 ICM7226A 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D6 D7 D8 VDD VSS INPUT A CONTROL INPUT

FUNCTION GENERATOR D4 D8 D2 D1 1N914s D3 D5

10k INPUT B HOLD BUF OSC OUT VDD 10MHz CRYSTAL 22M RST OUT EXT RANGE D1 D2 D3 D4 D5 VDD D1 D2 D3 D4 100k D5 6 D1 D2 D3 100k D4 D5 8 6 D6 D7 8 DENOTES BU WITH 6 CONDUCTORS 5 CRYSTAL SPECS. = FO 10.00MHz CO 22pF RS 35 30pF VDD VDD 39pF 6 VDD

e g a d b c f
BCD B BCD A RESET

8

13 14 15 16 17 18 19 20

LED OVERFLOW INDICATOR

a b c d e f g
DP D8 D8 D7 D6 D5

D8

8

D4

D3

D2

D1

DEVICE ICM7226A ICM7226B

CATHODE DP D8

ANODE D8 DP

NOTE: Overflow will be indicated on the decimal point output of digit 7. FIGURE 19.

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ICM7226A, ICM7226B Typical Applications
The ICM7226 has been designed as a complete stand alone Universal Counter, or used with prescalers and other circuitry in a variety of applications. Since INPUT A and INPUT B are digital inputs, additional circuitry will be required in many applications, for input buffering, amplification, hysteresis, and level shifting to obtain the required digital voltages. For many applications a FET source follower can be used for input buffering, and an ECL 10116 line receiver can be used for amplification and hysteresis to obtain high impedance input, sensitivity and bandwidth. However, cost and complexity of this circuitry can vary widely, depending upon the sensitivity and bandwidth required. When TTL prescalers or input buffers are used, a pull up resistors to VDD should be used to obtain optimal voltage swing at INPUTS A and B. If prescalers aren't required, the ICM7226 can be used to implement a minimum component Universal Counter as shown in Figure 20. For input frequencies up to 40MHz, the circuit shown in Figure 21 can be used to implement a frequency and period counter. To obtain the correct value when measuring frequency and period, it is necessary to divide the 10MHz oscillator frequency down to 2.5MHz. In doing this the time between measurements is lengthened to 800ms and the display multiplex rate is decreased to 125Hz. If the input frequency is prescaled by ten, the oscillator frequency can remain at either 10MHz or 1MHz, but the decimal point must be moved. Figure 22 shows use of a ÷10 prescaler in frequency counter mode. Additional logic has been added to enable the ICM7226 to count the input directly in period mode for maximum accuracy.

10k 39pF VDD A IN 1 B IN 10k 2 3 4 5 D1 D8 D2 D5 D4 D3 D3 D2 D4 6 7 8 9 10 11 12 D5 D6 D7 D8 13 14 15 16 17 RESET 18 19 0.1µF 20 ICM7226B 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DP V+ EXT OSC IN 39pF V+ V+ VDD 100k

DISPLAY DISPLAY EXT OSC ENABLE BLANK TEST

HOLD

D4

D8 1N914s

D1

3 10MHz CRYSTAL 22M 39pF (TYP) V+ TYPICAL CRYSTAL PARAMETERS CL 22pF RS 35

g e a d
VDD 8

b c f
100k D1 D2 D3 D4 4

6

8

a b c d e f g
DP D8 D7 D6 D5 D4 D3 D2 D1 D8

FIGURE 20. 10MHz UNIVERSAL COUNTER

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ICM7226A, ICM7226B
VDD Q P D CK C EXT OSC ENABLE 39pF DISPLAY OFF DISPLAY TEST VDD 10k 1 2 1N914 10k D1 D4 V+ 3k D P D1 Q D3 D2 C Q V+ D5 V+ D B IN C Q V+ 74LS74 0.1 µF 8 P Q D6 D7 D8 D4 D8 3 V+ 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RESET ICM7226B 3k HOLD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DP 39pF VDD VDD 22M 39pF (TYP) VDD 3k VDD 10MHz CRYSTAL VDD VDD VDD VDD VDD VDD 100k D P Q D P VDD Q 74LS74 VDD Q P D CK A IN

÷2
Q

÷2
Q C

VDD

IC ÷2 CK1 C

IC ÷2 CK2 C

Q

Q VDD

g e a d
VDD

8

b c f
100k D1 D2 D3 D4 4

D1 D8 D2

F P R 3

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DP 8 D8 D7 D6 D5 D4 D3 D2 D1 D8 OVERFLOW

FIGURE 21. 40MHz FREQUENCY, PERIOD COUNTER

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ICM7226A, ICM7226B
VDD INPUT M1 CP ECL11C90 QTTL CE MS 74LS00 10k 39pF VDD D4 1 VDD M1 INPUT CP ECL11C90 QTTL CE MS 10k 2 3 4 5 6 V+ 10k V+ 10k D1 D8 D2 74LS00 V+ 10k D4 F P R UC DP 7 8 9 10 11 12 ICM7226A 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D6 D7 D8 RANGE D1 D2 D3 D4 D5 VDD D1 D2 D3 D4 D5 5 VDD EXT OSC IN 39pF 22M 39pF (TYP) VDD 10MHz CRYSTAL VDD 100k 8 HOLD D8 1N914s 10 k D1 D2 D3 EXT DISPLAY DISPLAY OSC EN OFF TEST

1MHz

e g a d b c f

VDD

13 14 15 16 17

8

4 S6

18 19 20

0.1µF

8

100k

2

8

a b c d e f g
DP D8 D8 D7 D6 D5 D4 D3 D2 D1 8

OVERFLOW

FIGURE 22. 100MHz MULTI-FUNCTION COUNTER

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ICM7226A, ICM7226B
VDD INPUT M1 CP ECL11C90 QTTL CE MS 39pF VDD VDD 3k D4 VDD FUNCTION SWITCH OPEN FREQ CLOSED PERIOD VDD 10k F D IN CONT 2 OUT 1 2 3 4 5 6 7 D1 D7 IN D3 CONT 2 OUT D2 D4 8 9 10 11 12 D5 D6 D7 D8 13 14 15 16 17 18 N.O. 0.1µF RESET INPUT 19 20 ICM7226B 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DP 39pF VDD VDD 22M 39pF (TYP) VDD 10MHz CRYSTAL VDD 3 100k HOLD D2 D1 10k 10k DISPLAY DISPLAY OFF TEST 10k 2N2222 VDD

1N914s VDD

CD4016

g e a d b c f
10k D1 D2 D3 D4 VDD 8 4

8 2

a b c d e f g
D8 D7 D6 D5 D4 D3 D2 D1 D8 OVERFLOW

FIGURE 23. 100MHz FREQUENCY, PERIOD COUNTER

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ICM7226A, ICM7226B
Figure 23 shows the use of a CD4016 analog multiplexer to multiplex the digital outputs back to the FUNCTION Input. Since the CD4016 is a digitally controlled analog transmission gate, no level shifting of the digit output is required. CD4051s or CD4052s could also be used to select the proper inputs for the multiplexed input on the ICM7226 from 2-bit or 3-bit digital inputs. These analog multiplexers may also be used in systems in which the mode of operation is controlled by a microprocessor rather than directly from front panel switches. TTL multiplexers such as the 74LS153 or 74LS251 may also be used, but some additional circuitry will be required to convert the digit output to TTL compatible logic levels. The circuit shown in Figure 24 can be used in any of the circuit applications shown to implement a single measurement mode of operation. This circuit uses the STORE output
STORE OUTPUT S1 100k S3 VDD 100k VDD STORE OUTPUT 100k 100pF N.O. HOLD SWITCH 100pF HOLD INPUT 100k VDD VDD 100k

to put the ICM7226 into a hold mode. The HOLD input can also be used to reduce the time between measurements. The circuit shown in Figure 25 puts a short pulse into the HOLD input a short time after STORE goes low. A new measurement will be initiated at the end of the pulse on the HOLD input. This circuit reduces the time between measurements to about 40ms from 200ms; use of the circuit shown in Figure 25 on the circuit shown in Figure 21 will reduce the time between measurements from 800ms to about 160ms. Using LCD Display Figure 26 shows the ICM7226 being interfaced to LCD displays, by using its BCD outputs and 8 digit lines to drive two ICM7211 display drivers.

HOLD INPUT

S2

SWITCH S1 S2 S3

FUNCTION Open-Single Meas Mode Enabled Closed-Initiate New Measurement Closed-Hold Input

FIGURE 24. SINGLE MEASUREMENT CIRCUIT FOR USE WITH ICM7226

FIGURE 25. CIRCUIT FOR REDUCING TIME BETWEEN MEASUREMENTS

a f g e d
+5V 1

a b c f g e d c e b f

a b g c d e f

a b g c d e f

a b g c d e f

a b g c d e f

a b g c d e f

a b g c d
+5V 1

28 SEGMENT LINES 5 ICM7211 5

28 SEGMENT LINES

ICM7211

35

31 32 33 34

30 29 28 27

27 28 29 30

31 32 33 34

36 35

22 23 24 26 D8 · · D5

7

6

17 18

27 28 29 30 D8 · · D1

ICM7226A

FIGURE 26. 10MHz UNIVERSAL COUNTER SYSTEM WITH LCD DISPLAY

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