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ICE1724 PCI Multi-Channel Audio Controller
Preliminary
CONFIDENTIAL
PCI Multi-Channel Audio Controller
November 2001
IC Ensemble, Inc. a VIA Technologies company Fremont, CA 94539
ICE1724 PCI Multi-Channel Audio Controller
Preliminary
How to contact VIA Technologies: [email protected] Tel: 1(510)6873460 for Sales/Mktg Fax: 1(510)6833301 http://www.icensemble.com
Ordering Information
· ICE1724 - 128PQFP
© 2000-2001 VIA Technologies, Inc. All Rights Reserved.
VIA Technologies PRODUCTS ARE NOT AUTHORIZED FOR, AND SHOULD NOT BE USED WITHIN, LIFE SUPPORT SYSTEMS OR NUCLEAR FACILTY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF VIA Technologies, Inc. Life support systems are those intended to support or sustain life, and show failure to perform when used as directed can reasonably expect to result in personal injury or death. Nuclear facilities are those involved in the production, handling, use, storage, disposal, or any other activity involving fissionable materials or their waste products. VIA Technologies believes the information contained herein to be correct at the time of the publication. VIA Technologies reserves the right to make changes at any time, without prior notice, to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. VIA Technologies provides no warranty for the use of our products and assumes no liability for errors contained in this document. VIA Technologies, the ICE logo are trademark of VIA Technologies, Inc. Other trademarks referenced in this document are owned by their respective companies. Printed in the U.S.A.
ICE1724 PCI Multi-Channel I/O Controller
Preliminary
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Envy24HT PCI Configuration Registers 3-2
PCI00: Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI02: Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI04: PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI06: PCI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI08: Revision ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI0A: Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI0C: Cache Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI0D: Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI0E: Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI0F: BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI10: Envy24HT I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI14: Multi-Channel I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2C: Sub-Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI34: Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI34: Interrupt Pin and Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI3E: Latency and Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI42: Subsystem ID Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI80: Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI81: Next Item Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI82: Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI84: Power Management Control and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI86: PMCSR_Base and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 3-2 3-3 3-3 3-3 3-4 3-4 3-4 3-4 3-4 3-5 3-5 3-5 3-5 3-5 3-6 3-6 3-6 3-6 3-7 3-7
4.1 Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
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CCS00: Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CCS01: Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CCS02: Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 CCS04: System Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 CCS05: AC-Link Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 CCS06: I2S Converters Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 CCS07: S/PDIF Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS0A: UART TX FIFO Queue Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS0B: UART RX FIFO Queue Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS0C: MIDI UART Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS0D: MIDI UART Command/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS0E: UART Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS10: I2C Port Device Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS11: I2C Port Byte Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS12: I2C Port Read/Write Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS13: I2C Port Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS14: GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS16: GPIO Write Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS18: GPIO Direction Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS1C: Power Down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS1E: GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 CCS1F: GPIO Write Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.2 Multi-Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.1 Multi-Channel Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
MT00: DMA Interrupt Status Register: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT01: Sampling Rate Select Register: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT02: I²S Data Format Register: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT03: DMA Interrupt Mask Register: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT04: Index Register for AC'97 Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT05: Command and Status Register for AC'97 Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MT06: Data Port Register for AC'97 codecs on Professional section . . . . . . . . . . . . . . . . . . . . MT10: Interleaved Playback DMA Current/Base Address Register . . . . . . . . . . . . . . . . . . . . . . MT14: Interleaved Playback DMA Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . MT18: Global Playback and Record DMA Start/Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . MT19: Interleaved Playback DMA Active Streams/PCI Burst Size Register . . . . . . . . . . . . . . . . MT1A: Global Playback and Record DMA FIFO Underrun/Overrun Register . . . . . . . . . . . . . MT1B: Global Playback and Record DMA Pause/Resume Register . . . . . . . . . . . . . . . . . . . . . . MT1C: Interleaved Playback DMACurrent/Base Terminal Count Register. . . . . . . . . . . . . . . . 4-12 4-12 4-13 4-14 4-14 4-17 4-17 4-19 4-19 4-20 4-20 4-21 4-21 4-22
4.2.2 Multi-Channel Interleaved DMA Playback Registers . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.2.3 Record DMA Stereo Pairs Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
MT20: Record DMA 0 Current/Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 MT24: Record DMA 0 Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 MT26: Record DMA 0 Current/Base Terminal Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
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Preliminary
MT30: Record DMA 1 Current/Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 MT34: Record DMA 1 Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 MT36: Record DMA1 Current/Base Terminal Count Register . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.2.4 Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
MT2C: Routing Control Register for Data to PSDOUT[0:3] and SPDOUT . . . . . . . . . . . . . . . 4-25
4.2.5 Integrated S/PDIF Transmitter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
MT3C: S/PDIF IEC958 Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
4.2.6 VU Peak Meter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
MT3E: Peak Meter Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 MT3F: Peak Meter Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.2.7 Concurrent Stereo Pairs Playback DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
MT40: SPDIFout/PDMA4 Playback DMA Current/Base Address Register . . . . . . . . . . . . . . . MT44: SPDIFout/PDMA4 Playback DMA Current/Base Count Register . . . . . . . . . . . . . . . . . MT46: SPDIFout/PDMA4 Playback DMACurrent/Base Terminal Count Register. . . . . . . . . . MT50: PDMA3 Playback DMA Current/Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . MT54: PDMA3 Playback DMA Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . MT56: PDMA3 Playback DMACurrent/Base Terminal Count Register . . . . . . . . . . . . . . . . . . MT60: PDMA2 Playback DMA Current/Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . MT64: PDMA2 Playback DMA Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . MT66: PDMA2 Playback DMACurrent/Base Terminal Count Register . . . . . . . . . . . . . . . . . . MT70: PDMA1 Playback DMA Current/Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . MT74: PDMA1 Playback DMA Current/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . MT76: PDMA1 Playback DMACurrent/Base Terminal Count Register . . . . . . . . . . . . . . . . . . 4-29 4-30 4-30 4-30 4-30 4-31 4-31 4-31 4-31 4-32 4-32 4-32
5.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 6.1 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
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Rev. 0.91, 11/05/01
ICE1724 PCI Multi-Channel I/O Controller
Preliminary
List of Figures
Figure 2-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7.
128-pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 I²S Format Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Crystals to Master Clocks clock generation tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Master Clocks to Bit Clocks, L/R Clocks and Sync generation . . . . . . . . . . . . . . . . . . . . . . 4-16 Multi-channel Interleaved DMA Playback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Data stream routing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Stereo Pairs DMA Playback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Cold Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Warm Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Master Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 xBCLK to xxSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Rise Time and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 AC-link Power Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
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List of Tables
Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 4-1. Table 4-2. Table 4-3. Table 5-2. Table 5-1. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 6-1.
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Alphabetical Pin Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Numerical Pin Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PCI Host Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 CCSxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 MTxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 DMA to I²S/AC-link time slots mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Cold Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Slave Mode Master clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 xBCLK / xxSYNC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 AC-link Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Mechanical Dimensions (millimeters, unless otherwise stated) . . . . . . . . . . . . . . . . . . . . . . . 6-2
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Section 1: Introduction
The Envy24HTTM is a versatile PCI 24bit multi-channel audio controller that brings your computer at par with the fidelity of state-of-the-art home audio electronics, such as 24bit/192kHz DVD-Audio. It allows up to 10 outbound streams and 4 simultaneous inbound channels. All paths pass 24bit audio, "as is", unaltered, bit per bit accurate. Some of the typical applications for this part are computer based high fidelity multi-channel audio, home theater and entertainment, cost effective multi-track audio, PC-based data acquisition, waveform generation. To maintain a full digital path for PCM or compressed audio formatc, the Envy24HT integrates a complete S/PDIF transmitter. All 5 output and 2 input pairs can be combined with professional grade I²S converters, S/PDIF receivers or multi-channel out AC-link codecs, such as the VT1616TM. The Envy24HT supplies a master I²C interface providing connection to an E²PROM to store and retrieve PCI Subsystem and Subsystem vendor IDs, specific board configurations and custom features identification. The Envy24HT integrates an independent MPU-401 MIDI UART. Direct access GPIOs brings flexibility for multi-purpose use. The Envy24HT is ACPI compliant making it suitable for platforms designed to be instantly on. Depending on the sampling rates that need to be supported by the target solution, one or two crystals are sufficient to operate the whole system. For more detail on the part, please refer to the system block diagram Figure 4-1 in Section 4.
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1.1 Features
· · · · · · · · · · · · · · · · · · PCI 2.2 I/F with bus mastering and burst modes 24-bit resolution audio format support Bit accurate transfers Sampling rates up to 192kHz 5 synchronous I²S/AC-link ouput data stream pairs 2 synchronous I²S/AC-link input data stream pairs Multi-channel AC-link supported alternatively Integrated S/PDIF transmitter with IEC958 line driver Digital loopback and stream routing mechanism Peak meters on all streams MPU-401 MIDI UART port ACPI and PCI PMI support I²C subset I/F for E²PROM (configuration and ID storage) and peripherals control 23-pin, direct access GPIO port Windows® WDM drivers 49.152/24.576 and 22.5792 MHz crystal operation 3.3V operating supply (5V tolerant I/O) 128-pin PQFP (14mm x 20mm body)
1.2 Applications
· · · · · · · · · "Pro-sumer" audio High Fidelity audio reproduction PC-based Home Theater PC-based multi-channel audio like DVD-Audio PC-based multi-track audio recording General purpose multi-channel I/O PC-based data acquisition PC-based waveform generation PC-based instrumentation
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Section 2: Pins
The following section includes the pinout diagram of the chip that is housed in a standard 128-PQFP. Also, three lists of pin assignments are provided for your convenience. They are logically sorted by functionality and description, alphabetically and numerically sorted in ascending order. These list are provided to assist hardware development, test, debugging and quality assurance. The mechanical data about the part can be found in Section 6.
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2.1 Pinout Diagram
GPIO21 GPIO22 PRST# SPDOUT SPDIN VSS SPSYNC SPSCLK SPMCLKIN SPMCLKOUT INTA# RST# VDD VSS PCICLK GNT# REQ# AD31 AD30 VDD AD29 AD28 AD27 AD26 AD25 VSS 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VDD AD24 CBE3# IDSEL AD23 AD22 VSS AD21 AD20 AD19 AD18 AD17 VDD VSS AD16 CBE2# FRAME# IRDY# TRDY# VSS DEVSEL# STOP# NC PAR CBE1# VSS VDD AD15 AD14 AD13 AD12 AD11 VSS AD10 AD9 AD8 CBE0# VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC GPIO20 VSS GPIO19 GPIO18 GPIO17 GPIO16 TX1 RX1 VDD SPDTX GPIO15 GPIO14 GPIO13 GPIO12 VSS GPIO11 PMCLK PSDOUT[3] PSDOUT[2] PSDOUT[1] VDD VSS PSDOUT[0] PBCLK GPIO10 GPIO9 GPIO8 VSS PSDIN[0] PSYNC SCLK SDA TESTEN# NC VDD_X1 XOUT1 XIN1
Figure 2-1. 128-pin PQFP Package
ICE1724
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VSS_X1 VDD_X2 XOUT2 XIN2 VSS_X2 GPIO7 GPIO6 GPIO5 GPIO4 VSS VDD GPIO3 GPIO2 GPIO1 GPIO0 AD0 AD1 AD2 VSS VDD AD3 AD4 AD5 AD6 AD7 VSS
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2.2 Pin Descriptions
The following table provides a brief description of each pin of the ICE1712. Pins with dual usage may be listed twice for consistency. Please note that all the PCI bus pins are 5V tolerant. The following abbreviations are used to identify the pin types. I - Input Signal O - Output Signal B - Bidirectional Signal OD - Open Drain A - Analog Signal PU - Pull-up. 50k nominal Table 2-1. Pin Descriptions
Symbol
PCI BUS INTERFACE AD[31:0] CBE#[3:0] PCICLK DEVSEL# I B B FRAME# GNT# IDSEL INTA# IRDY# PAR REQ# RST# STOP# TRDY# I²C PORT SDA SCLK B O Serial bidirectional dat. Serial bit shift clock I I OD B B O I B B B B Multiplexed PCI Address/Data Bus. Bus command/Byte Lane Enable. These signals are bus commands during the address phase and byte lane enable during the data phase. These signals are output during a bus master cycle. PCI Bus Clock. Device Select. The ICE1724 drives this signal active when it decodes its address as the current target of the current acces. PCI Cycle Frame. When asserted by the bus mster, this signal indicates the beginning of a bus transaction.During the final data phase of a bus transaction it is deasserted. When active it indicates bus master is granted to ICE1724. Initialization Device Select. This is the chip select during the PCI configuration register accesses PCI Interrupt Request. Initiator Ready. Parity Signal. Bus master control request System Reset. All ICE1724 registers and state machines are at default when this signal is asserted. Target disconnect signal. Target Ready.
Type
Description
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Table 2-1. Pin Descriptions (continued)
Symbol
MPU-401 UART TX1 RX1 O, PU I, PU MPU-401 Transmit data MPU-401 Receive data
Type
Description
PROFESSIONAL MULTI-TRACK AC-LINK / I²S INTERFACE PSYNC PBCLK PSDIN[1:0] PSDOUT[3:0] PMCLK PRST# CLOCKS XOUT1 XIN1 XOUT2 XIN2 A A A A Clock Out 1 49.152 (256*192kHz)/24.576MHz (512*48kHz). Runs the core blocks. Clock Out 2 22.5792MHz (512*44.1kHz) O I/O I O O O AC'97: 48kHz fixed rate sync pulse for up to 4 codecs, or 8 I²S type converters: Left/Right Clock Serial Bit Clock. It can be master or slave configured 2 separate incoming stereo stream pairs 4 separate outbound stereo stream pairs Master Clock for AC'97 codecs or I²S converters Cold reset for I²S/AC-link converters
S/PDIF (SONY/PHILIPS DIGITAL INTERFACE) SPMCLKIN SPMCLKOUT SPSCLK SPDIN SPDOUT SPDTX SPSYNC GENERAL PURPOSE I/O GPIO[22:4] GPIO3 / E²PROM GPIO[2:1] GPIO0 / I²S# TEST MODE TESTEN# I, PU Test mode enable. Do not connect for normal operation. B, PU B, PU B, PU B, PU General Purpose I/O. Capable of driving 8mA. General Purpose I/O. E²PROM presence indicator during power-up (default). The state is reflected on CCS13_7 bit. Capable of driving 8mA. General Purpose I/O. Capable of driving 8mA. General Purpose I/O. Sets AC-link interface for professional section during power-up (default). The state is reflected on PCI61_7 bit in reverse polarity. Capable of driving 8mA. O I O O I O A, PU S/PDIF Master Clock Input or other 256X clock for salve operation S/PDIF Master Clock Output is PMCLK/2 or /4, 128X PSYNC S/PDIF Serial Bit Clock Incoming S/PDIF Serial Data Copy of Outbound S/PDIF Serial Data present on SPDTX S/PDIF out IEC958 line driver output. The voltage divider implemented on the board will pull down signaling that the digital audio transmitter is implemented via bit CCS07_0. S/PDIF Frame Sync
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Table 2-1. Pin Descriptions (continued)
Symbol
POWER AND GROUND VDD VSS 3.3V digital supply Ground
Type
Description
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2.3 Pin Lists
Table 2-2 lists all the pins alphabetically. Table 2-3 lists all the pins in numerical order.
Table 2-2. Alphabetical Pin Listing
Symbol
AD[31:0] CBCLK CBE#[3:0] CMCLK CRST# CSDIN CSDOUT CSYNC DEVSEL# FRAME# GNT# GPIO[0]/I²S# GPIO[1] GPIO[2] GPIO[3]/E²PROM GPIO[22:4] IDSEL INTA# IRDY# NC PAR PBCLK PCICLK PMCLK PRST# PSDIN0 PSDOUT[3:0] PSYNC REQ# RST#
Pin(s)
2, 5-6, 8-12, 15, 28-32, 34-36, 40-44, 47-49, 120-121, 123-127, 90 3, 16, 25, 37 92 86 89 91 88 21 17 118 50 51 52 53 56-59, 75-77, 86, 88-91, 96-99, 101, 103-104 4 113 19 23, 68, 102 24 78 117 85 105 73 79, 82-84 72 119 114
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Table 2-2. Alphabetical Pin Listing (continued)
Symbol
RX1 SCLK SDA SPDIN SPDOUT SPDTX SPMCLKIN SPMCLKOUT SPSCLK SPSYNC STOP# TESTEN# TRDY# TX1 VDD VDD_X1 VDD_X2 VSS VSS_X1 VSS_X2 XIN[2:1] XOUT[2:1] 94 71 70 107 106 92 111 112 110 109 22 69 19 95 1, 13, 27, 38, 45, 54, 81, 93, 115, 122 67 63 7, 14, 20, 26, 33, 39, 46, 55, 74, 80, 87, 100, 108, 116, 128 64 60 61, 65 62, 66
Pin(s)
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Table 2-3. Numerical Pin Listing
Pin # 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Symbol
VDD AD24 CBE3# IDSEL AD23 AD22 VSS AD21 AD20 AD19 AD18 AD17 VDD VSS AD16 CBE2# FRAME# IRDY# TRDY# VSS DEVSEL# STOP# NC PAR CBE1# VSS VDD AD15 AD14 AD13 AD12 AD11 VSS
Pin # 65
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
Symbol
XOUT1 VDD_X1 VDD VSS TESTEN# SDA SCLK PSYNC PSDIN[0] VSS GPIO8 GPIO9 GPIO10 PBCLK PSDOUT[0] VSS VDD PSDOUT[1] PSDOUT[2] PSDOUT[3] PMCLK GPIO11 VSS GPIO12 GPIO13 GPIO14 GPIO15 SPDTX VDD RX1 TX1 GPIO16 GPIO17
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Table 2-3. Numerical Pin Listing (continued)
Pin # 34
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol
AD10 AD9 AD8 CBE0# VDD VSS AD7 AD6 AD5 AD4 AD3 VDD VSS AD2 AD1 AD0 GPIO[0] GPIO[1] GPIO[2] GPIO[3] VDD GPIO[4] GPIO[5] GPIO[6] GPIO[7] VSS_X2 XIN2 XOUT2 VDD_X2 VSS_X1 XIN1
Pin # 98
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Symbol
GPIO18 GPIO19 VSS GPIO20 NC GPIO21 GPIO22 TX2 SPDOUT SPDIN VDD SPSYNC SPSCLK SPMCLKIN SPMCLKOUT INTA# RST# VDD VSS PCICLK GNT# REQ# AD31 AD30 VDD AD29 AD28 AD27 AD26 AD25 VSS
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Section 3: PCI Interface and Configuration
Table 3-1. PCI Host Interface Register Map
Byte 3
Device Identification PCI Device Status Class Code BIST Header Type
Byte 2
Byte 1
Vendor Identification PCI Command Reserved. Read as 0 Latency Timer
Byte 0
Offset (Hex)
00 04
Revision ID Reserved. Read as 0
08 0C 10 14 18 1C
Controller I/O Base Address Multi-Channel I/O Base Address Subsystem ID Reserved. Read as 0 Capability Pointer Reserved. Read as 0 Minimum Latency and Maximum Grant SVID Mask Hardware Configuration Control Power Management Capability PMCSR Support Extensions and Data Next Item Pointer Capability ID Interrupt Pin and Line Subsystem Vendor ID
2C 30 34 38 3C 40 60 80 84
Power Management Control and Status
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3.1 Envy24HT PCI Configuration Registers
PCI00: Vendor Identification Register Address Offset: 00 - 01h Default Value: 1412h
Bit
15:0
Attribute
RO
Description
Vendor Identification Number. This is the 16-bit value assigned to IC Ensemble, Inc.
PCI02: Device Identification Register Address Offset: 02 - 03h Default Value: 1724h
Bit
15:0
Attribute
RO
Description
Device Identification Number. 1724 reflects the part number.
PCI04: PCI Command Register Address Offset: 04 - 05h Default Value: 0000h
Bit
15:10 9 8 7 6 5 4 3 2 1 0
Attribute
R0b R0b R/W R0b R0b R0b R0b R0b R/W R0b R/W
Description
Reserved. Read as 0s. Fast Back-to-Back Enable. This bit is hardwired to 0 (Not Implemented). SERR# enable. Hardwired to 0 (Not Implemented). A/D stepping enable. This bit is hardwired to 0 (Not Implemented). Parity error detect enable. Hardwired to 0 (Not Implemented). VGA palette snoop enable. Hardwired to 0 (Not Implemented). Memory write and invalidate enable. Hardwired to 0 (Not Implemented). Special Cycle Enable (SCE). Hardwired to 0 (Not Implemented). Bus master enable. 1=enable. 0=disable (default). Memory Access. Hardwired to 0 (Not Implemented). I/O Space accesses enable. 1=enable. 0=disable (default).
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PCI06: PCI Status Register Address Offset: 06 - 07h Default Value: 0210h
Bit
15 14 13 12 11 10:9 8 7 6 5 4 3:0
Attribute
R/W/C R/W/C R/W/C R/W/C R0b R10b R0b R0b R0b R0b R1b R0000b
Description
PAR status. Parity error detected (even when parity not enabled). SERR# status. Read as 0 (Not Implemented). Master abort status. This bit is set to 1 when master aborts and cleared by writing "1" to it. Received target abort status. This bit is set to 1 when target abort is received and cleared by writing a 1 to it. Signaled target abort status. This bit is set when target abort generated and cleared by writing a 1 to it. Hardwired to 0 (never abort). DEVSEL# timing status. Envy24 always asserts DEVSEL# with medium timing. PERR# response. Read as 0 (Not Implemented). Fast back to back. Read as 0 (Not implemented). User Define Function (UDF). Read as 0 (Not implemented). Reserved. Read as 0. 33MHz only. Hardwired to 1 to indicate the support for PCI power management capability. Reserved. Read as 0s.
PCI08: Revision ID Register Address Offset: 08h - 09h Default Value: 000Xh
Bit
15:0 7:0
Attribute
R00h RO
Description
Revision ID
PCI0A: Class Code Register Address Offset: 0Ah - 0Bh Default Value: 0401h
Bit
15:8 7:0
Attribute
RO RO
Description
Base Class. Reflects Multimedia Sub class. Reflects Audio.
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PCI0C: Cache Size Register Address Offset: 0Ch Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0. Not supported
PCI0D: Latency Timer Register Address Offset: 0Dh Default Value: 00h
Bit
7:3 2:0
Attribute
R/W RO
Description
Latency timer Read as 0
PCI0E: Header Type Register Address Offset: 0Eh Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0
PCI0F: BIST Register Address Offset: 0Fh Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0. Not supported
PCI10: Envy24HT I/O Base Address Offset: 10h - 13h Default Value: 00000001h
Bit
31:5 4:1 0
Attribute
RW R0h R1b
Description
Controller I/O Base Address for CCSxx registers described in chapter 4 Hardwired to 0 to have 32 bytes I/O space. This includes UARTs and game port. Hardwired to 1 to indicate registers map to I/O space
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PCI14: Multi-Channel I/O Base Address Offset: 14h -17h Default Value: 00000001h
Bit
31:7 6:1 0
Attribute
R/W R0 R1b
Description
Multi-Channel I/O Base Address for MTxx registers described in chapter 4 Hardwired to 0 to have 128 bytes I/O space Hardwired to 1 to indicate registers map to I/O space
PCI2C: Sub-Vendor ID Address Offset: 2Ch - 2Fh Default Value: 17241412h
Bit
31:0
Attribute
RO
Description
Sub-vendor ID: Read it from external E²PROM after reset if it exists, otherwise, same as vendor ID. It can also be written by disabling write protection bit defined in PCI42_7.
PCI34: Capability Pointer Address Offset: 34h Default Value: 80h
Bit
7:0
Attribute
RO
Description
CP7-CP0: Capability data structure pointer for PCI power management. Hardwired to 80h.
PCI34: Interrupt Pin and Line Address Offset: 3Ch - 3Dh Default Value: 01FFh
Bit
15:8 7:0
Attribute
RO R/W
Description
01h read from this register indicates the interrupt pin used is INTA# and cannot be modified. Interrupt line routing information set by POST during power-up initialization. Default FFh indicates no connection to the PIC yet.
PCI3E: Latency and Grant Address Offset: 3Eh - 3Fh Default Value: 0000h
Bit
15:8 7:0
Attribute
RO RO
Description
Maximum latency Minimum grant
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PCI42: Subsystem ID Mask Address Offset: 42h Default Value: 0000h
Bit Attribute Description
Reserved 7 R/W 0: SVID read only. (default) 1: SVID read/write enable.
PCI80: Capability ID Address Offset: 80h Default Value: 01h
Bit
7:0
Attribute
RO
Description
Capability ID
PCI81: Next Item Pointer
Address Offset: 81h Default Value: 00h
Bit
7:0
Attribute
RO
Description
Hardwired to 0 to indicate the end of list
PCI82: Power Management Capabilities Address Offset: 82h - 83h Default Value: 0401h
Bit
15:11 10 9 8:6 5 4 3 2:0
Attribute
RO R1 R0 R000 R0 R0 R0 R001b
Description
PME not supported. Hardwired to 0. D2 state support. Hardwire to 1. D1 state not support. Hardwired to 0. Reserved. DSI. Hardwired to 0. Aux. Power. Hardwired to 0 PMC clock for generation of PME#. Hardwired to 0. Hardwired to 001 to indicate PPMI 1.0 compliance
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PCI84: Power Management Control and Status Address Offset: 84h - 85h Default Value: 0000h
Bit
15 14:13 12:9 8 7:2
Attribute
R0b R00b R0h R0b RO
Description
PME status. Read as 0. Data scale. Not supported. Data select: Not supported. PME assertion. Hardwired to 0 Hardwired to 000000 Power state. To determine the current state of power state. 00 : D0 01 : D1 (not supported) 10 : D2 11 : D3_hot
1:0
R/W
There are four power states defined in the PCI bus power management spec.
States
D0 D1 D2 D3(hot)
Description
Normal operation state after system power up or internal reset not supported. Power down all the blocks defined in the power down registers. Same as D2 state, except a transition to D0 will generate an internal reset (incl. PCI config. space)
PCI86: PMCSR_Base and Data Address Offset: 86h - 87h Default Value: 0000h
Bit
15:0
Attribute
R0000h
Description
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Section 4: Hardware Interfaces
In the previous section PCI host interface and configuration registers were discussed. In this section description of the major blocks, their respective hardware interfaces and associated registers will be discussed. The first figure in this section, Figure 4-1, is a chip level block diagram with typical external interface usage. It is a very good overview of the whole chip, but should not be regarded as the most detailed diagram. As appropriate, the databook will resort to sub-block diagrams to further detail the functionality. These are the multi-track DMA transfer mechanism, data stream routing capabilities and the digital mixer block diagram. The following descriptive summary can be considered along with Figure 4-1. In its default state, the ICE1724 has an 8 interleaved DMA and an independent, concurrent stereo pair which is tied to the integrated SPDIF transmitter but the same data is simultaneously available at the corresponding I²S data output pin. The ganged channels can be disengaged to form independent stereo pairs while leaving the remainder tightly coupled in even quantity of channels, i.e. 8, 6, 4 or 2 ganged. This means that the part can output 5 simultaneous, independent stereo pairs that are not tightly time correlated as if it would be in the interleaved mode. See register MT19 for the various setting if you want to depart from the default mode. The incoming data stream, i.e. the Record DMA channels are always set as 2 independent and simultanous pairs. The above description about the flexiblity of the ICE1724 leads to effective use of bus bandwidth yet does not abandon the time correlation of multichannel streams or independent stereo operation without disturbing other stream that may start, stop or pause at random times, independent from one another. Since there is always a single master clock to run the system, regardless whether in master or slave mode, even in the independent stereo mode, all streams must be at the same sampling rate, including the S/PDIF output path and the record channels.
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4-2 S/PDIF Out Monitor copy ADC or S/PDIF In
I2S Out I2S Pair I2S or AC-Link Pair
4 DAC/Codec
S/PDIF Out
ADC/Codec or S/PDIF In
Four I2S or AC-Link Pairs
IEC958 Out
2x24b ch.
2x24b ch.
8x24b ch.
2x24b ch.
RX1 TX1
SD
GPIO
Rev. 0.91, 11/05/01
PDMA4 RDMA0 RDMA1 MPU-401 UART
PDMAx PDMAi
I²C/E²PROM PORT
23 pins GPIO
PCI 2.2 Bus Master BIU with Burst Mode
PCI BUS
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PCI Multi-Channel I/O Controller
Hardware Interfaces
Figure 4-1. Functional Block Diagram
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PCI Multi-Channel I/O Controller
4.1 Controller Registers
The following registers are offset from base address set by PCI10. The 32 bytes I/O space includes main control/status registers, I2C interface, MPU-401 MIDI UARTs and game port control as well. Each CCSxx register is physically located at the address determined by [PCI10]+xx and accessed directly. The registers can be accessed as a byte, word or dword register. Table 4-1. CCSxx Controller Register Map
Byte 3
S/PDIF Configuration RX UART queue -
Byte 2
Envy24HT Status I²S Configuration TX UART queue UART Setting
Byte 1
Interrupt Mask AC-link Configuration UART Comm./Status I²C Port Byte Address Global
Byte 0
System Configuration
Offset (Hex)
00 04 08
MIDI UART Data I²C Port Dev. Address
0C 10 14 18
I²C Port Control/Status I²C Port R/W Data GPIO[15:0] Write Mask Register GPIO[22:16] W. Mask
GPIO[15:0] Data Register
GPIO[22:0] Direction Register GPIO[22:16] Data Reg. Power Down
1C
CCS00: Control/Status Register Address Offset: 00h Default Value: 00h
Bit
7 6:0
Attribute
R/W R/W
Description
Entire Chip soft reset Reserved
CCS01: Interrupt Mask Register Address Offset: 01h Default Value: FEh
Bit
7 6 5 4 3:0
Attribute
R/W R/W R/W R/W R/W
Description
MPU-401 MIDI UART receive interrupt mask. See CCS0E for high watermark setting. Reserved MPU-401 MIDI UART transmit interrupt mask. See CCS0E for low watermark setting. Multi-channel playback and record. This is the macro interrupt mask for any P and RDMAx. Reserved
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CCS02: Interrupt Status Register Address Offset: 02h Default Value: 00h. These bits are sticky and only writing a 1 to that bit location will clear itself.
Bit
7 6 5 4
Attribute
R/W/C R/W R/W/C RO
Description
MPU-401 MIDI UART receiver FIFO Reserved MPU-401 MIDI UART transmit FIFO Multi-channel playback or record. This is the macro interrupt status for any PDMAx and RDMAx. To clear individual status bit, write a 1 to the associated bit location defined in section 4.2, MT00. Reserved
3:0
R/W
CCS04: System Configuration Register Address Offset: 04h Default Value: 0Fh The following four bytes (04h-07h) have to be read from E2PROM by driver and then written to setup the codec configuration, unless otherwise noted.
Bit Attribute Description
XIN1 Clock Source Configuration. Refer to register MT01. 00: XIN1: 24.576MHz crystal (96kHz*256) 01: XIN1: 49.152MHz crystal (192kHz*256) 1x: - Reserved 1: MPU-401 UART implemented 0: MPU-401 UART not implemented. -Reserved 00: one stereo ADC connected 01: two stereo ADCs connected 10: one stereo ADC and a S/PDIF receiver connected 11: No physical inputs Must have at least one stereo pair DAC. 00: one stereo DAC connected 01: two stereo DACs connected 10: three stereo DACs connected 11: four stereo DACs connected
7:6
R/W
5 4
R/W R/W
3:2
R/W
1:0
R/W
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CCS05: AC-Link Configuration Register Address Offset: 05h Default Value: 00h Except for bit 7, the four bytes at CCS04 should be read from E2PROM by driver and then written to setup the codec configuration.
Bit
7 6:2
Attribute
R/W R/W
Description
Multi-channel converter type: 0: AC'97 1: I²S. Reflects power-up status of pin 50 during reset cycle in reverse polarity. Can be overwritten. Reserved. If bit 7 is 0, i.e. AC'97 mode, it may affect the DMA to pin mappings where the audio streams are transferred to. See description in MT05[1:0] and Table 4-3. 0: split mode: AC'97 codec SDATA_OUT split to different pin outputs, PSDOUT[3:0]. The individual stereo AC'97 codecs like VT1611A should be properly IDed. 1: AC-link packed mode: AC'97 codec SDATA_OUT packed in slots per AC'97 2.2 spec only on PSDOUT0 (pin79). See VT1616 spec as the codec to be used in this mode. Reserved.
1
R/W
0
R/W
CCS06: I2S Converters Features Register Address Offset: 06h Default Value: 01h This byte is valid only when CCS05_7 is 1. The four bytes at CCS04 should be read from E2PROM by driver and then written to setup the codec configuration.
Bit Attribute Description
For I²S codec Volume and mute 0: I²S codec has no volume/mute control feature. 1: I²S codec has volume/mute control capability and need to be program through GPIO (e.g., CS4222) I²S converter 96kHz sampling rate support. 0: does not; 1 : supports Converter resolution: 00: 16-bit 01: 18-bit 10: 20-bit 11: 24-bit I²S converter 192kHz sampling rate support. 0: does not; 1 : supports Other I²S IDs
7
R/W
6
R/W
5:4
R/W
3 2:0
R/W R/W
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CCS07: S/PDIF Configuration Register Address Offset: 07h Default Value: 01h The four bytes at CCS04 should be read from E2PROM by driver and then written to setup the codec configuration.
Bit
7
Attribute
R/W
Description
1: Enable integrated S/PDIF transmitter. Valid only when bit 6 of this register is `1'. Must be disabled to change mode via MT3C. 1: Internal S/PDIF Out implemented. Reflects the state of pin 92, SPDTX during reset. If `0', the transmitter is not implemented on the board. Note that it is reverse polarity of pin 92 reset state. S/PDIF chip IDs 1: S/PDIF Stereo In is present. 1: External S/PDIF Out implemented.
6 5:2 1 0
R/O R/W R/W R/W
CCS0A: UART TX FIFO Queue Status Register Address Offset: 0Ah Default Value: 00h Description: This read-only register reflects the number of valid bytes in hex form, ready to be transmitted on TX1 (pin95) from the TX FIFO. The UART FIFO is 32bytes deep in each direction.
Bit
7:5 4:0
Attribute
RO RO
Description
Reserved. Valid MPU-401 data bytes in TX FIFO.
CCS0B: UART RX FIFO Queue Status Register Address Offset: 0Bh Default Value: 00h Description: This read-only register reflects the number of valid bytes hex form, to be read by the host from the RX FIFO. The UART FIFO is 32bytes deep in each direction.
Bit
7:5 4:0
Attribute
RO RO
Description
Reserved. Valid MPU-401 data bytes in RX FIFO.
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CCS0C: MIDI UART Data Register Address Offset: 0Ch Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART data register
CCS0D: MIDI UART Command/Status Register Address Offset: 0Dh Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART command and status register
CCS0E: UART Setting Register Address Offset: 0Eh Default Value: 00h Description: This register allows setting high/low watermarks for RX/TX FIFO interrupts to avoid polling or constant interruption during heavy system activity. The UART FIFO is 32bytes deep in each direction.
Bit
7:6 5 4:0
Attribute
R/W R/W R/W
Description
Reserved. 1: Receive FIFO high watermark setting. 0: Transmit FIFO low watermark setting. Enter the watermark value, between 0 and 31 (00h to 1Fh). Both RX and TX FIFO are 32bytes. The default watermark level is 0 for both TX and RX.
CCS10: I2C Port Device Address Register Address Offset: 10h Default Value: 00h Each write to this register will trigger to start the read/write cycle. So, before write to this I/O address, driver needs to check to make sure that the status bit is idle as defined in the I²C status register CCS13. The controller is always the only master and does not support multi-byte data burst mode.
Bit
7:1
Attribute
R/W
Description
I2C device address. Device address "1010000" is reserved for the external I²C E2PROM such as 24C02 for subvendor ID and configuration data. 0: read 1: write
0
R/W
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CCS11: I2C Port Byte Address Register Address Offset: 11h Default Value: 00h
Bit
7:0
Attribute
R/W
Description
Byte address to read or write
CCS12: I2C Port Read/Write Data Register Address Offset: 12h Default Value: 00h
Bit
7:0
Attribute
RW
Description
Read or write data
CCS13: I2C Port Control and Status Register Address Offset: 13h Default Value: 00h When bit 0 is 0 (meaning the I2C port is idle), SCLK (pin 71) will be tri-stated. Envy24HT is providing the serial clock only when it reads/writes through I2C bus at a nominal rate of 31.25kHz.
Bit
7 6:2 1 0
Attribute
RO 0 R/W RO
Description
Reflects the power strapping on GPIO3 (pin 53). A 1 (default) indicates external E2PROM exists. A 0 (pull down by a resistor) means, no external E2PROM connected. Reserved. Keep at 0 state. I²C port read/write status. 0: idle 1: busy
CCS14: GPIO Data Register Index: 14 -15h Default Value: 0000h The direction is set up in CCS18, the GPIO direction control register (see CCS1E for MSB GPIO Data Register). These register bits can be writable only when the corresponding mask bit is zero in the mask register, CCS16. If the direction is output, it reads back the last data written. The use of these will depend upon board configuration as defined by the E²PROM settings content. See CCS04 register description for more details.
Bit
15:0
Attribute
R/W
Description
GPIO data (Warning: few GPIO pins may be shared with other functions)
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CCS16: GPIO Write Mask Register Index: 16 - 17h Default Value: FFFFh
Bit
15:0
Attribute
R/W
Description
GPIO15 through GIO0 write mask 0: Corresponding CCS14 register bit can be written. 1: Can NOT be written.
CCS18: GPIO Direction Control Register Index: 18h - 1Ah Default Value: 000000h
Bit
22:4 3 2 1:0
Attribute
R/W R/W R/W R/W
Description
GPIO22 through GPIO4 direction. GPIO3 direction. During reset, this pin is used for E²PROM power-on strapping. GPIO2 direction. If TESTEN# pin is active, this pin is always input. GPIO1 and GPIO0 direction.
For all bits 0: input; 1: output. CCS1C: Power Down Register Index: 1Ch Default Value: 00h
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R/W R/W R/W R/W R/W R/W
Description
1: Crystal clock generation power down for XTAL_1 Reserved 1: Crystal clock generation power down for XTAL_2 1: Stop I²C port clock 1: Stop MIDI clock 1: Stop S/PDIF clock Reserved. 1: Stop Multi-channel I²S serial interface clock
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CCS1E: GPIO Data Register Index: 1Eh Default Value: 00h The direction is set up in CCS18, the GPIO direction control register (see CCS14 for LSW GPIO Data Register). These register bits can be writable only when the corresponding mask bit is zero in the mask register CCS1F. Also, if the direction is output, it reads back the last data written.
Bit
6:0
Attribute
R/W
Description
GPIO22 through GPIO16 data
CCS1F: GPIO Write Mask Register Index: 1Fh Default Value: FFh
Bit
6:0
Attribute
R/W
Description
GPIO22 through GIO16 write mask 0: Corresponding CCS1E register bit can be written. 1: Can NOT be written.
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PCI Multi-Channel I/O Controller
4.2 Multi-Channel Control Registers
The following registers are offset from base address set by PCI14. The MTxx registers are located at [PCI14]+xx. The 128 bytes I/O space controls the multi-channel record and playback, audio stream routing, digital mixer and related output capability. The Playback DMA default organization is 8 interleaved and a concurrent, independent stereo pair tied to the SPDIF out linedriver and a copy to the respective I²S data out pin. Refer to the introduction of this chapter for a concise description of the DMA channels involved. Table 4-2. MTxx Controller Register Map
Byte 3
DMA Interrupt Mask AC `97 Data Port Interleaved Playback DMA (PDMAi) Current/Base Address Global DMA Pause/R. PDMAi Current/Base Count Underrun/Overrun PDMAi Burst Size Global DMA Start/Stop
Byte 2
I²S data format
Byte 1
AC `97 Comm./Stat.
Byte 0
AC `97 Index
Offset (Hex)
00 04 08 0C 10 14 18 1C 20
Sampling Rate Select. DMA Interrupt Status
PDMAi Current/Base Terminal Count
Record DMA 0 (RDMA0) Current/Base Address Record DMA 0 Current/Base Terminal Count
-
Record DMA 0 Current/Base Count
24 28 2C 30
Routing control to PSDOUT[3:0] and SPDOUT Record DMA 1 Current/Base Address Record DMA 1 Current/Base Terminal Count
-
Record DMA 1 Current/Base Count S/PDIF IEC958 Control Register
34 38 3C 40 44 50 54 60 64 70 74
Peak meter data
Peak meter index
Playback DMA 4 (PDMA4)/ S/PDIF output Current/Base Address PDMA4 Current/Base Terminal Count PDMA4 Current/Base Count
Playback DMA 3 (PDMA3) output Current/Base Address PDMA3 Current/Base Terminal Count PDMA3 Current/Base Count
Playback DMA 2 (PDMA2) output Current/Base Address PDMA2 Current/Base Terminal Count PDMA2 Current/Base Count
Playback DMA 1 (PDMA1) output Current/Base Address PDMA1 Current/Base Terminal Count PDMA1 Current/Base Count
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4.2.1 Multi-Channel Mode Registers
MT00: DMA Interrupt Status Register: Address Offset: 00h Default Value: 00h This register relates to both all DMA operation modes. When DMAs are stopped, the last latched value is retained. This "DC" value may affect the converters state.
Bit
7 6 5 4 3 2 1 0
Attribute
R/W/C R/W/C R/W/C R/W/C R/W/C R/W/C R/W/C R/W/C
Description
SPDIF Out/PDMA4 pair playback interrupt status. Write a 1 to clear. PDMA3 pair playback interrupt status. Write a 1 to clear. PDMA2 pair playback interrupt status. Write a 1 to clear. PDMA1 pair playback interrupt status. Write a 1 to clear. DMA FIFO underrun/overrun condition. See MT1A for status. RDMA1 (typically S/PDIF input) pair record interrupt status. Write a 1 to clear. RDMA0 pair (typically ADC) record interrupt status. Write a 1 to clear. Multi-channel interleaved/PDMA0 pair playback interrupt status. Write a 1 to clear.
MT01: Sampling Rate Select Register: Address Offset: 01h Default Value: 00h. This register applies to . When in slave mode, e.g. S/PDIF input, 256X master clock alone selects the sampling rate. See Figure 4-3 and Figure 4-4 on page 15 and page 16 respectively, in this chapter
Bit
7:5 4
Attribute
R000b R/W
Description
S/PDIF input clock as the master. 0: disabled 1: enabled (Envy24HT slave mode) S/PDIF receiver chip or other source provides the master clock through SPMCLKIN (pin 111) Note that in this mode, 256X is the highest master clock available while the AC'97 MCLK requires 512X. AC'97 codecs, such as the VT1611A are designed based on BCLK which uses MCLK/2, i.e. 256X. When S/PDIF provides the master clock, if VIA AC'97 codecs are used, before setting S/PDIF as the master clock, proceed to switching the primary codec into slave mode (refer to the VT1611A datasheet). In this mode PBCLK will be output from Envy24HT.
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Bit
3:0
Attribute
R/W
Description
Codec and S/PDIF sampling rate select. The entire system runs synchronously, based on the same master clock and sampling rate. All channels are set to the same rate. These bits are ignored if S/PDIF input is master. See bit 4 of this register. 0000: 48kHz (default) 0001: 24kHz 0010: 12kHz 0011: 9.6kHz 0100: 32kHz 0101: 16kHz 0110: 8kHz 0111: 96kHz 1110: 192kHz only for CCS04_6=1 (X1=49.152MHz) or MT02_3=1 (128X) & CCS04_6=0 1111: 64kHz 1000: 44.1kHz 1001: 22.05kHz 1010: 11.025kHz 1011: 88.2kHz 1100: 176.4kHz (forces to 128X mode only) others: reserved
MT02: I²S Data Format Register: Address Offset: 02h Default Value: 00h
Bit
7:4 3
Attribute
R0 R/W
Description
MCLK/LRCLK ratio, except for 176.4kHz where 128X is the only choice 0: 256x (default) 1: 128x
2 1:0
R/W R/W Data format: 00: I²S (timing diagram provided below) others: Reserved
See Figure 4-2 below for a timing diagram for bits [1:0]. See Figure 4-3 and Figure 4-4 on page 15 and page 16 respectively for the visual description of other bits.
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PSYNC/ SPSYNC PBCLK/ SPSCLK PSDIN[0:3] PSDOUT[0:3] SPDIN SPDOUT
Left
Right
MSB
LSB
MSB
LSB
MSB
Figure 4-2. I²S Format Timing Diagram MT03: DMA Interrupt Mask Register: Address Offset: 03h Default Value: FFh This register relates to all DMA channels. By default all interrupts are off (`1'), i.e. masked. When enabled (set to `0'), MT00 interrupt status reflects each DMA channels interrupt state.
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R/W R/W R/W R/W R/W R/W
Description
SPDIF Out/PDMA4 pair playback interrupt mask. Always valid. PDMA3 pair playback interrupt mask. Valid only when MT19>00b PDMA2 pair playback interrupt mask. Valid only when MT19>01b PDMA1 pair playback interrupt mask. Valid only when MT19=11b DMA FIFO underrun/overrun condition interrupt mask. MT1A reports the offending channel. RDMA1 (typically S/PDIF input) pair record interrupt mask. Always valid. RDMA0 pair (typically ADC) record interrupt mask. Always valid. Multi-channel interleaved/PDMA0 pair playback interrupt mask. Always valid.
MT04: Index Register for AC'97 Codecs Address Offset: 04h Default Value: 00h This register is valid when AC-link interface (CCS05_7 = 0) is used. It has no validity when the converter interface is set to I²S mode (CCS05_7 = 1).
Bit
7 6:0
Attribute
R0 R/W
Description
AC'97 registers Index. Refer to the AC'97 specification for register descriptions.
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SP* = S/PDIF I²S port fs = Sampling Rate SCLK (pin 71) 1 2 1 49 1 8 1 2 MPU-401 Timer
CCS4_6 = 1
MIDI TX/RX rate
XIN1 (pin 64)
CCS4_6 = 0 CCS4_6=0 or (CCS4_6=1 & MT01_[3:0]=08h)
(for 24.576MHz and 49.152MHz when fs=192kHz)
Rev. 0.91, 11/05/01
MT01_[3:0]<08h or >0Bh
(only for 49.152MHz when fs!=192kHz)
CCS4_6=1 & MT01_[3:0] != 08h 1, 2, 3, 4, 6, 8, 10, 12
divide by
Master 256X PMCLK (pin 85)
Figure 4-3. Crystals to Master Clocks clock generation tree
CONFIDENTIAL
divide by 1, 2, 4, 8
MT01_[3:0]=08h,09h,0Ah,0Bh MT01_4=1
Slave
XIN2 (pin 60)
MT01_4=0
1 2
MT02_3=0 MT02_3=1
128X
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SPMCLKIN (pin 111)
256fs
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4 - 16
256 or 64fs
CCS5_7 = 0
default (256X or 128X)
PBCLK (pin 78)
MT02_2 = 0 MT02_3 = 1 & CCS5_7 = 1
1 4 1 2 1 256 1 64
PSYNC (pin 72) fs
Rev. 0.91, 11/05/01
MT02_3 = 0 & CCS5_7 = 1 CCS5_7 = 0 MT02_3 = 1
128X MCLK 1 2 default 256X MCLK 1 64 1 2 fs
PMCLK (pin 85) 256 or 128 fs
for AC'97 mode only
Figure 4-4. Master Clocks to Bit Clocks, L/R Clocks and Sync generation
SPSYNC (pin 109)
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MT02_3 = 0
SPMCLKOUT (pin 112) 128fs SPSCLK (pin 110) 64fs
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SP* = S/PDIF I²S port fs = Sampling Rate
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MT05: Command and Status Register for AC'97 Codecs Address Offset: 05h Default Value: 00h This register is valid when AC-link interface (CCS05_7 = 0) is used. It has no meaning when the converter interface is set to I²S mode (CCS05_7 = 1)..
Bit
7 6
Attribute
R/W R/W
Description
Cold reset. Write 1 to assert PRST# (pin105) active. Write back 0 to remove reset condition from all professional section codecs. Warm reset. Write 1 to have warm reset by asserting PSYNC (pin 72). This bit together with PRST# (pin 105) active (MT05_7=1) can be used to set the external VIA primary AC'97 codec to slave mode (such as the VT1611A). This must be done when S/PDIF input is the master. Apply Cold reset to restore codec master mode. Write 1 to write to AC'97 codec register Reading a 1 indicates the write cycle is still in progress, cleared when write cycle complete. Write 1 to read AC'97 CODEC register Reading a 1 indicates the read cycle is still in progress, cleared when there is valid data. AC'97 codec ready status bit. After power-on, check that this bit is 1 before accessing codec registers. ID for external AC'97 registers read/write when split mode (CCS05_1 = 0) is used. When a 6channel AC'97 like the VT1616 is used (CCS05_1 = 1), the multichannel PCM data is transmitted on the default slots but on the same data out pin, PSDOUT0, pin 79. 00: select primary AC'97 codec. PCM transmitted on time slots 3,4. 01: select second slave AC'97 codec.PCM transmitted on time slots 3,4. 10: select third slave AC'97 codec. PCM transmitted on time slots 7,8. 11: select fourth slave AC'97 codec. PCM transmitted on time slots 6,9.
5 4 3 2 1:0
R/W R/W RO R0b R/W
MT06: Data Port Register for AC'97 codecs on Professional section Address Offset: 06h - 07h Default Value: 00h This register is valid when AC-link interface (CCS05_7 = 0) is used. It has no meaning when the converter interface is set to I²S mode (CCS05_7 = 1).
Bit
15:8 7:0
Attribute
R/W R/W
Description
AC'97 codec register data high byte (index 07h) Refer to the AC'97 specification for register descriptions.. AC'97 codec register data low byte (index 06h). Refer to the AC'97 specification for register descriptions.
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4.2.2 Multi-Channel Interleaved DMA Playback Registers The following Figure 4-5 represents the manner the data is sequenced and interleaved for efficient transfer of multi-channel data over PCI bus. A total of 12 layers (or sample times t0 through t11) deep buffer structure is implemented for a seamless flow of each stream, i.e. a maximum of 12*8chs*24bit data can be buffered before the physical output pins. Each burst cycle fills 4 layers (or sample time tx to tx+4) for each channel. If empty time slots (or layers) remain, a new bus request is issued until all layers are full. An initial buffer fill therefore, generates 3 consecutive bus requests. 32-bit unpacked data transfers are used across the PCI bus regardless of the audio data resolution. All transfer data are left (MSB) justified. Each transfer request results into a PCI bus master burst cycle. The maximum and default burst size is 4*8chs.=32 PCI data cycles. The burst size can be reduced to 6, 4 or 2 channels (see MT19), i.e. shrink to 24, 16 or 8 PCI data cycles transferred. This improves PCI bus efficiency when only a limited amount of channels are used and frees up the DMA FIFO for independent stereo pair operation where each channel has independent control over the data flow.
to physical outputs
Stream/Track 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Burst 2 channels Burst 4 channels Burst 6 channels Burst all 8 channels Burst 2 channels Burst 4 channels Burst 6 channels Burst all 8 channels Burst 2 channels Burst 4 channels Burst 6 channels Burst all 8 channels Burst 2 channels Burst 4 channels Burst 6 channels Burst all 8 channels (default, see MT19 ) skipping unused channels
time slot tx
time slot tx+1
time slot tx+2
time slot tx+3
Byte Lanes
3
2
1
0
PDMAi (Interleaved PCI
Playback)
Figure 4-5. Multi-channel Interleaved DMA Playback diagram
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The usa