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050-200332 TOSHIBA

SERVICE MANUAL

COLOUR TELEVISION
29VH27E
AK52 Chassis

PRINTED IN UK.

2003 C

SM52-DRX_IF

TABLE OF CONTENTS
1.INTRODUCTION.......................................................................................................................... 1 2.TUNER........................................................................................................................................ 1 3.IF PART (DRX 3960A) ................................................................................................................. 1 4.VIDEO SWITCH TEA6415............................................................................................................ 2 5.MULTI STANDARD SOUND PROCESSOR .................................................................................. 2 6.SOUND OUTPUT STAGE WITH TDA7480L ................................................................................. 2 7.VERTICAL OUTPUT STAGE WITH TDA8177F............................................................................. 2 8.VIDEO OUTPUT AMPLIFIER TDA6109........................................................................................ 2 9.POWER SUPPLY (SMPS)............................................................................................................ 3 10.MICROCONTROLLER SDA5550................................................................................................ 3 10.1.General Features................................................................................................................ 3 10.2.External Crystal and Programmable Clock Speed.............................................................. 3 10.3.Microcontroller Features.................................................................................................... 3 10.4.Memory .............................................................................................................................. 3 10.5.Display Features................................................................................................................. 3 10.6.ROM Characters................................................................................................................. 3 10.7.Acquisition Features.......................................................................................................... 4 10.8.Ports................................................................................................................................... 4 11.SERIAL ACCESS 32K EEPROM ................................................................................................ 4 12.CLASS AB STEREO HEADPHONE DRIVER TDA1308............................................................... 4 13.SAW FILTERS ........................................................................................................................... 4 14.IC DESCRIPTIONS .................................................................................................................... 4 14.1.TDA6109 ............................................................................................................................. 5 14.1.1.General Description ..................................................................................................... 5 14.1.2.Features....................................................................................................................... 5 14.1.3.Pinning......................................................................................................................... 5 14.2.27W401 ............................................................................................................................... 5 14.2.1.Description................................................................................................................... 5 14.2.2.Features....................................................................................................................... 5 14.2.3.Connections................................................................................................................. 6 14.3.24LC32A............................................................................................................................. 6 14.3.1.Description................................................................................................................... 6 14.3.2.Features....................................................................................................................... 6 14.3.3.Pin Descriptions........................................................................................................... 7 14.4.SDA5275............................................................................................................................. 7 14.4.1.Features....................................................................................................................... 7 14.4.2.Pin Definition and functions......................................................................................... 8 14.5.DRAM 4MX4........................................................................................................................ 9 14.5.1.General Description ..................................................................................................... 9 14.5.2.Features....................................................................................................................... 9 14.5.3.Pin Assignment............................................................................................................ 9 14.6.SDA9400............................................................................................................................10 14.6.1.General Description ....................................................................................................10 14.6.2.Features......................................................................................................................10 14.6.3.Pin Definition ..............................................................................................................11 14.7.LM317T ..............................................................................................................................11 14.7.1.Description..................................................................................................................11 14.7.2.Features......................................................................................................................11 14.8.DDP3310............................................................................................................................12 14.8.1.Description..................................................................................................................12 14.8.2.Features......................................................................................................................12 14.8.3.Pin connection and short descriptions .......................................................................12 14.9.SDA5550............................................................................................................................14 14.9.1.General definition........................................................................................................14 14.9.2.Features......................................................................................................................14 14.10.TEA6415C........................................................................................................................15 14.10.1.General Description ..................................................................................................15 14.10.2.Features....................................................................................................................15 14.10.3.Pinning......................................................................................................................16 i

14.11.VPC3230D........................................................................................................................16 14.11.1.General Description ..................................................................................................16 14.11.2.Pin Connections and Short Descriptions ..................................................................16 14.12.TDA1308T ........................................................................................................................18 14.12.1.General Description ..................................................................................................18 14.12.2.Features....................................................................................................................18 14.12.3.Pinning......................................................................................................................18 14.13.MSP34X1G (MSP3411G) ..................................................................................................18 14.13.1.Description................................................................................................................18 14.13.2.Features....................................................................................................................19 14.13.3.Pin connections ........................................................................................................20 14.14.TL431...............................................................................................................................21 14.14.1.Description................................................................................................................21 14.14.2.Features....................................................................................................................21 14.14.3.Pin Configurations ....................................................................................................21 14.15.DRX3960A .......................................................................................................................22 14.15.1.Introduction...............................................................................................................22 14.15.2.Features....................................................................................................................22 14.15.3.Pin connection and short descriptions .....................................................................22 14.16.LM7808 ............................................................................................................................23 14.16.1.Description................................................................................................................23 14.16.2.Features....................................................................................................................23 14.17.BDX53BFI ........................................................................................................................23 14.17.1.Description................................................................................................................23 14.17.2.Applications..............................................................................................................23 14.18.TDA8177F ........................................................................................................................24 14.18.1.Description................................................................................................................24 14.18.2.Features....................................................................................................................24 14.18.3.Pin connections ........................................................................................................24 14.18.4.Block Diagram...........................................................................................................24 14.19.LM1086 ............................................................................................................................24 14.19.1.Description................................................................................................................24 14.19.2.Features....................................................................................................................24 14.19.3.Applications..............................................................................................................25 14.19.4.Connection Diagrams................................................................................................25 14.20.MC44608 ..........................................................................................................................25 14.20.1.Description................................................................................................................25 14.20.2.General Features.......................................................................................................25 14.20.3.Pin Connections........................................................................................................26 14.21.TCET1102G......................................................................................................................26 14.21.1.Description................................................................................................................26 14.21.2.Applications..............................................................................................................26 14.21.3.Features....................................................................................................................26 14.22.TDA7480L ........................................................................................................................27 14.22.1.Description................................................................................................................27 14.22.2.Features....................................................................................................................27 14.22.3.Pin Functions............................................................................................................27 14.23.SAA3010T ........................................................................................................................27 14.23.1.Description................................................................................................................27 14.23.2.Features....................................................................................................................28 14.23.3.Pinning......................................................................................................................28 15.AK52 CHASSIS MANUAL ADJUSTMENTS PROCEDURE ........................................................28 15.1.PRELIMINARY ...................................................................................................................28 15.2.SYSTEM VOLTAGE ADJUSTMENTS..................................................................................28 15.3.AFC ADJUSTMENTS .........................................................................................................28 15.4.FOCUS ADJUSTMENTS.....................................................................................................29 15.5.SCREEN ADJUSTMENTS ..................................................................................................29 15.6.IF ADJUSTMENT FOR L' MODE.........................................................................................29 16.AK52 CHASSIS PRODUCTION SERVICE MODE ADJUSTMENTS ............................................30 16.1.PRELIMINARY ...................................................................................................................30 16.2.H/V (HORIZONTAL AND VERTICAL GEOMETRY ALIGNMENTS).......................................30 ii

16.3.VIDEO ALIGNMENTS .........................................................................................................33 16.4.SERVICE ALIGNMENTS.....................................................................................................34 17.BLOCK DIAGRAM ....................................................................................................................36 18.CIRCUIT DIAGRAMS................................................................................................................37

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1.INTRODUCTION
11AK52 is a 100Hz flicker free colour television capable of driving 28"4:3/16:9, 32" 16:9, 33"4:3 and 29"4:3 real flat picture tubes. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I', and L/L´. Sound system output is supplying 2x10W (10%THD) for left and right outputs of 8ohm speakers. TV supports the level 1.5 teletext standard. It is possible to decode transmissions including high graphical data. The chassis is equipped with two full EuroScarts, one SCART for AV input/output, one front-AV input, one back-AV input, one headphone output, one SVHS input (via SCART and SVHS connector), two external speaker outputs (left and right).

2.TUNER
The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR 2 systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I C bus (PLL). Below you will find info on one of the Tuners in use. General description of UV1316: The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L', I and I'. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of UV1316: 1. Member of the UV1300 family small sized UHF/VHF tuners 2. Systems CCIR: B/G, H, L, L', I and I'; OIRT: D/K 2 3. Digitally controlled (PLL) tuning via I C-bus 4. Off-air channels, S-cable channels and Hyperband 5. World standardized mechanical dimensions and world standard pinning 6. Compact size 7. Complies to "CENELEC EN55020" and "EN55013" Pinning: 1. Gain control voltage (AGC) 2. Tuning voltage 3. I²C-bus address select 4. I²C-bus serial clock 5. I²C-bus serial data 6. Not connected 7. PLL supply voltage 8. ADC input 9. Tuner supply voltage 10. Symmetrical IF output 1 11. Symmetrical IF output 2 : : : : : : 4.0V, Max: 4.5V Max: 5.5V Min:-0.3V, Max: 5.5V Min:-0.3V, Max: 5.5V 5.0V, Min: 4.75V, Max: 5.5V 33V, Min: 30V, Max: 35V

3.IF PART (DRX 3960A)
Tuner output IF signal is pre-filtered with only one 8-MHz channel SAW filter. The entire multistandard processing is performed. The Digital Receiver Front-end DRX 3960A performs the entire multi-standard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and generation of the second sound IF (SIF). Video and tuner AGC is controlled and adjusted by take over voltage. The alignmentfree DRX 3960A needs no special external components. All control functions and status registers are 2 accessible via I C bus interface.

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4.VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is to switch 8 video-input sources on the 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.

5.MULTI STANDARD SOUND PROCESSOR
The MSP34x1G family of single-chip Multi-standard Sound Processors covers the sound processing of all analog TV -Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Signal conforming to the standard by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA -J) and the FM Stereo Radio standard.

6.SOUND OUTPUT STAGE WITH TDA7480L
The TDA7480L is an audio class-D amplifier assembled in Power DIP package specially designed for high efficiency applications mainly for TV and Home Stereo sets. Mute stand-by function of the audio amplifier can be described as the following; the pin 12 (MUTE/STAND-BY) controls the amplifier status by two different thresholds, referred to ground. When Vpin 12 voltage is lower than 0.7V the amplifier is in Stand-by mode and the final stage generators are off. When Vpin 12 is higher than 4V, the amplifier is in play mode. The TDA7480L is a 10W+10W stereo sound amplifier with mute/stand-by facility. MUTE control signal coming from microcontroller (when it is at high level) activates the mute function. IC is muted when mute pin is at low level (pin12). MUTE pin can also be activated via an external pop-noise circuitry in order to eliminate pop noise when TV is turned off. Just after the TV is turned off, this circuit switches the IC to stand-by mode by pulling the mute pin voltage to ground.

7.VERTICAL OUTPUT STAGE WITH TDA8177F
The IC TDA8177F is the vertical deflection booster circuit. Two supply voltages, +12V and -12V are needed to scan the inputs VERT+ and VERT-, respectively. And a third supply voltage, +60V for the flyback limiting are needed. The vertical deflection coil is connected in series between the output and feedback to the input.

8.VIDEO OUTPUT AMPLIFIER TDA6109
The TDA6109 includes three video output amplifiers in order to drive the three cathodes of a colour picture tube directly. To obtain maximum performance, the amplifier is used with black-current control.

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9.POWER SUPPLY (SMPS)
The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer generates 135V for FBT input, +/-14V for audio amplifier, 8V stand by voltage and 8V, 12V and 5V supplies for other different parts of the chassis. An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. This circuit produces a control voltage according to the changes in 135V DC voltage, via an optocoupler (TCET 1102G) to pin3 of the IC. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.

10.MICROCONTROLLER SDA5550
10.1.General Features · Feature selection via special function register · Simultaneous reception of TTX, VPS, PDC, and WSS (line 23) · Supply Voltage 2.5 and 3.3 V · ROM version is used. 10.2.External Crystal and Programmable Clock Speed · Single external 6MHz crystal, all necessary clocks are generated internally · CPU clock speed selectable via special function registers. · Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz 10.3.Microcontroller Features · 8bit 8051 instruction set compatible CPU. · 33.33-MHz internal clock (max.) · 0.360 ms (min.) instruction cycle · Two 16-bit timers · Watchdog timer · Capture compare timer for infrared remote control decoding · Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) · ADC (4 channels, 8 bit) · UART (rxd, txd) 10.4.Memory · Up to 128 Kilobyte on Chip Program ROM · Eight 16-bit data pointer registers (DPTR) · 256-bytes on-chip Processor Internal RAM (IRAM) · 128bytes extended stack memory. · Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX · UP to 16KByte on Chip Extended RAM (XRAM) consisting of; - 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX) - 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software - 3 Kilobyte Display Memory 10.5.Display Features · ROM Character set supports all East and West European Languages in single device · Mosaic Graphic Character Set · Parallel Display Attributes · Single/Double Width/Height of Characters · Variable Flash Rate · Programmable Screen Size (25 Rows x 33...64 Columns) · Flexible Character Matrixes (HxV) 12 x 9...16 · Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters in Enhanced Mode · CLUT with up to 4096 colour combinations · Up to 16 Colours per DRCS Character · One out of 8 Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters 10.6.ROM Characters · Shadowing · Contrast Reduction · Pixel by Pixel Shiftable Cursor With up to 4 Different Colours · Support of Progressive Scan and 100 Hz. 3

· 3 X 4Bits RGB-DACs On-Chip · Free Programmable Pixel Clock from 10 MHz to 32MHz · Pixel Clock Independent from CPU Clock · Multinorm H/V-Display Synchronization in Master or Slave Mode 10.7.Acquisition Features · Multi-standard Digital Data Slicer · Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+) · Four Different Framing Codes Available · Data Caption only limited by available Memory · Programmable VBI-buffer · Full Channel Data Slicing Supported · Fully Digital Signal Processing · Noise Measurement and Controlled Noise Compensation · Attenuation Measurement and Compensation · Group Delay Measurement and Compensation · Exact Decoding of Echo Disturbed Signals 10.8.Ports 2 · One 8-bit I/O-port with open drain output and optional I C Bus emulation support (Port0) · Two 8-bit multifunction I/O-ports (Port1, Port3) · One 4-bit port working as digital or analogue inputs for the ADC (Port2) · One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7) · One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)

11.SERIAL ACCESS 32K EEPROM
24LC32 is the 32Kbit electrically erasable programmable memory. The memory is compatible with the 2 I C standard, two wire serial interface, which uses a bi-directional data bus and serial clock.

12.CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

13.SAW FILTERS
X6966M is an 8-MHz SAW Filter which is used for pre-filtering the IF input signal of DRX 3960A. The entire multistandard processing is performed within this filter which limits the signal bandwidth to 8 MHz and suppresses major parts of the adjacent channels.

14.IC DESCRIPTIONS
TDA6109 27W401 24LC32 SDA5275 DRAM 4MX4 SDA9400 LM317T DDP3310 SDA5550 TEA6415 VPC3230D TDA1308T MSP3411G TL431 DRX3960A LM7808 BDX53BFI TDA8177F LM1086 MC44608 TCET1102G TDA7480L SAA3010T 4

14.1.TDA6109
14.1.1.General Description The TDA6109JF includes three video output amplifiers in one plastic DIL-bent-SIL 9-pin medium power (DBS9MPF) package (SOT111-1), using high-voltage DMOS technology, and is intended to drive the three cathodes of a colour CRT directly. To obtain maximum performance, the amplifier should be used with blackcurrent control. 14.1.2.Features · Typical bandwidth of 9.0 MHz for an output signal of 60 V (p-p) · High slew rate of 1850 V/ms · No external components required · Very simple application · Single supply voltage of 200 V · Internal reference voltage of 2.5 V · Fixed gain of 51 · Black-Current Stabilization (BCS) circuit · Thermal protection. 14.1.3.Pinning
SYMBOL Vi(1) Vi(2) Vi(3) GND Iom VDD Voc(3) Voc(2) Voc(1) PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION inverting input 1 inverting input 2 inverting input 3 ground (fin) black current measurement output supply voltage cathode output 3 cathode output 2 cathode output 1

14.2.27W401
14.2.1.Description The M27W401 is a low voltage 4 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organized as 524,288 by 8 bits. The M27W401 operates in the read mode with a supply voltage as low as 2.7V at ­40 to 8??C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP32W (window ceramic frit-seal package) has a transparent lid, which allows the user to expose the chip to ultraviolet light to erase the bit pat-tern. A new pattern can then be written to the device by following the programming procedure. For application where the content is programmed only one time and erasure is not required, the M27W401 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. 14.2.2.Features 2.7V to 3.6v Low voltage in Read Operation Access time: ­70ns at VCC = 3.0V to 3.6V ­80ns at VCC = 2.7V to 3.6V Pin Compatible with M27C4001 Low Power Consumption: ­1?mA max Standby Current ­ 15mA max Active Current at 5MHz Programming Time 10? s/byte m High Reliability CMOS Technology ­ 2,000V ESD Protection ­ 200mA Latchup Protection Immunity 5

Electronic Signature ­ Manufacturer Code: 20h ­ Device Code: 41h 14.2.3.Connections

DIP connections

LCC Connections

TSOP Connections

Signal Names
A0-A18 Q0-Q7 E G Vpp Vcc Vss Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground

14.3.24LC32A
14.3.1.Description The Microchip Technology Inc. 24LC32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (2.5V to 6.0V). It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24LC32A also has a page-write capability of up to 32 bytes of data. The 24LC32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24LC32A devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/ low-voltage, nonvolatile code and data applications. The 24LC32A is available in the standard 8-pin plastic DIP and both 150 mil and 200 mil SOIC packaging. 14.3.2.Features · Single supply with operation down to 2.5V · Maximum write current 3 mA at 6.0V · Standby current 1 mA max at 2.5V · 2-wire serial interface bus, I 2 CÔ compatible · 100 kHz (2.5V) and 400 kHz (5V) compatibility · Self-timed ERASE and WRITE cycles · Power on/off data protection circuitry · Hardware write protect · 1,000,000 Erase/Write cycles guaranteed · 32 byte page or byte write modes available 6

· · · · · · · · · ·

Schmitt trigger filtered inputs for noise suppression Output slope control to eliminate ground bounce 2 ms typical write cycle time, byte or page Up to eight devices may be connected to the same bus for up to 256K bits total memory Electrostatic discharge protection > 4000V Data retention > 200 years 8-pin PDIP and SOIC packages Temperature ranges Commercial (C): 0°C to +75°C Industrial (I): -40°C to +85°C

14.3.3.Pin Descriptions A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24LC32A for multiple device operation and conform to the 2-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte. SDA Serial Address/Data Input/Output This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull up resistor to VCC (typical 10 kO for 100 kHz, 2 kO for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL HIGH are reserved for indicating the START and STOP conditions. SCL Serial Clock This input is used to synchronize the data transfer from and to the device. WP This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 000-FFF). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. W CC +2.5V to 6V Power Supply W SS Ground

14.4.SDA5275
14.4.1.Features

· Single chip teletext IC · Analog CVBS-input with onchip clamping circuitry · Slicer · Supports level 1, 2.5 and 3.5 ETSI teletext standard · Stores up to 14 teletext pages on chip · Stores up to 2048 teletext pages with external 16 M memory · SDA 5275: full level 2.5 processing · Analog RGB-output · 41 Latin script languages · 12 ´ 10 character size · Parallel display attributes · 64 from 4096 colors selectable · Enhanced flash modes · Dynamically redefinable character set (DRCS, PCS) · Pixel graphics · Full screen display (64 ´ 32 or 80 ´ 24 character positions) · Horizontal and vertical scrolling · Graphic cursors · 4:3 and 16:9 display · Multinorm display (50/60/100/120 Hz) · RISC-processor · Firmware downloadable 2 · I C / 3 wire UART-interface (1 Mbit/s) · Independent clocks for acquisition and display 7

· Tools for greatly simplified software development · 24-Kbyte on-chip reconfigurable DRAM · 44160-bit character ROM · One external crystal for all standards 14.4.2.Pin Definition and functions
Pin No. P-LCC-68-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Symbol INTQ CLK-IO TCSQ/FLD VS/VCS HS XOUT XIN GPO TM CVBS VDD1 VDDA VSSA1 N.C. N.C. VDD2 RES N.C. N.C. N.C. VDD3 N.C. VREF N.C. VDD4 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3 VSS4 CASQ N.C. N.C. N.C. VSS3 N.C. N.C. N.C. N.C. N.C. VSS2 VBB N.C. Function Interrupt request output to ext. controller System clock input/output Composite sync output/ field output Vertical sync input/output Horizontal sync input/output 20.5-MHz crystal oscillator output 20.5-MHz crystal oscillator input General purpose output Test pin, leave open or connect VSS CVBS-video signal input + 5 V digital supply + 5 V analog supply Analog ground Not connected Not connected + 5 V digital supply Chip reset Not connected Not connected Not connected + 5 V digital supply Not connected + 3 V reference voltage input Not connected + 5 V digital supply External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address Row address strobe (DRAM) Write enable (DRAM) External DRAM-data External DRAM-data External DRAM-data External DRAM-data 0 V digital supply Column address strobe Not connected Not connected Not connected 0 V digital supply Not connected Not connected Not connected Not connected Not connected 0 V digital supply Substrate bias voltage N.C.* (depends on version) Not connected

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58 59 60 61 62 63 64 65 66 67 68

VSSA2 RGB-GND VSS1 R G B BLAN CORQ SCL SDA I2CEN

Analog ground RGB-ground 0 V digital supply Analog red display output Analog green display output Analog blue display output Blanking signal open drain output Contrast reduction open drain output Bi-directional I2C Bus clock port Bi-directional I2C Bus data port I2C Bus enable

14.5.DRAM 4MX4
14.5.1.General Description The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 con-figuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are "don't care"). READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#. 14.5.2.Features · Industry-standard x4 pin out, timing, functions and packages · State-of-the-art, high-performance, low-power CMOS silicon-gate process · Single power supply (+3.3V ±0.3V or +5V ±10%) · All inputs, outputs and clocks are TTL-compatible · Refresh modes: RAS#-ONLY, HIDDEN and CAS#-BEFORE - RAS# (CBR) · Optional Self Refresh (S) for low-power data retention · 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) · Extended Data-Out (EDO) PAGE MODE access cycle · 5V-tolerant inputs and I/Os on 3.3V devices 14.5.3.Pin Assignment

Top View *NC on 2K refresh and A11 on 4K refresh options. Note: The "#" symbol indicates signal is active LOW. 9

14.6.SDA9400 14.6.1.General Description The SDA9400 is a new component of the Micronas MEGAVISION ® IC set in a 0.35µm embedded DRAM technology (frame memory embedded). The SDA9400 is pin compatible to the SDA9401 (field memory embedded). The SDA9400 comprises all main functionalities of a digital feature box in one monolithic IC. The scan rate conversion to 100/120 Hz interlaced (50/60 Hz progressive) is based on a motion adaptive algorithm. The scan rate converted picture can be vertically expanded. The SDA9400 has a free running mode, therefore features like scan rate conversion to e.g. 70, 75 Hz with joint lines or multiple picture display (e.g. tuner scan) are possible. Due to the frame based signal processing, the noise reduction has been greatly improved. Furthermore separate motion detectors for luminance and chrominance have been implemented. For automatic controlling of the noise reduction parameters a noise measurement algorithm is included, which measures the noise level in the picture or in the blanking period. In addition a spatial noise reduction is implemented, which reduces the noise even in the case of motion. The input signal can be compressed horizontally and vertically with a certain number of factors. Therefore split screen is supported. Beside these additional functions like coloured background, windowing and flashing are implemented. 14.6.2.Features · Two input data formats - 4:2:2 luminance and chrominance parallel (2 x 8 wires) - ITU-R 656 data format (8 wires) · Two different representations of input chrominance data - 2`s complement code - Positive dual code · Flexible input sync controller · Flexible compression of the input signal - Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - Digital horizontal compression of the input signal (1.0, 2.0, 4.0) · Noise reduction - Motion adaptive spatial and temporal noise reduction (3D-NR) - Temporal noise reduction for luminance frame based or field based - Temporal noise reduction for chrominance field based - Separate motion detectors for luminance and chrominance - Flexible programming of the temporal noise reduction parameters - Automatic measurement of the noise level (5-bit value, readable by I²C bus) · 3-D motion detection - High performance motion detector for scan rate conversion - Global motion detection flag (readable by I²C bus) - Movie mode and phase detector (readable by I²C bus) · TV mode detection by counting line numbers (PAL, NTSC, readable by I²C bus) · Embedded memory - 5 Mbit embedded DRAM core for field memories - 192 kbit embedded DRAM core for line memories · Flexible clock and synchronization concept - Decoupling of the input and output clock system possible · Scan rate conversion - Motion adaptive 100/120 Hz interlaced scan conversion - Motion adaptive 50/60 Hz progressive scan conversion - Simple static interlaced and progressive conversion modes for 100/120 Hz interlaced or 50/60 Hz progressive scan conversion: e.g. ABAB, AABB, AA*B*B, AAAA, BBBB, AB, AA* - Simple progressive scan conversion with joint lines: 50 Hz -> 60, 70, 75 Hz progressive 60 Hz -> 70, 75 Hz progressive - Large area and line flicker reduction · Flexible digital vertical expansion of the output signal (1.0, ... [1/32] ..., 2.0) · Flexible output sync controller - Flexible positioning of the output signal - Flexible programming of the output sync raster - External synchronization by backend IC possible (e.g. split screen for one TV channel with joint lines and one PC VGA channel) 10

· Signal manipulations - Insertion of coloured background - Vertical and/or horizontal windowing with four different speed factors - Flash generation (for supervising applications, motion flag readable by I²C bus) - Still frame or field - Support of split screen applications - Multiple picture display - Tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes) - Support of multi picture display with PIP or front -end processor with integrated scaler (e.g. 9 times display of PIP pictures, picture tracking, random pictures, still-in-moving picture, movingin-still picture) · I²C-bus control (400 kHz) · P-MQFP-64 package · 3.3 V ± 5% supply voltage 14.6.3.Pin Definition
Pin No. 2,8,24,42,55 9,25,41,56 36,52,58 35,51,53,57,59 43,..,50 31,..,34;37,...,40 30 Name VSS1 VDD1 VSS2 VDD2 YIN0...7 UVIN0...7 RESET Type S S S S I/TTL I/TTL PD I/TTL Description Supply voltage ( V SS = 0 V ) Supply voltage ( V DD = 3.3 V ) Supply voltage ( V SS = 0 V ) Supply voltage ( V DD = 3.3 V ) Data input Y (see input data format) Data input UV (for 4:2:2 parallel, see input data format) (for CCIR 656, see input data format) System reset. The RESET input is low active. In order to ensure correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the system clock CLK1. H-Sync input (only for full CCIR 656) V-Sync input (only for full CCIR 656) Synchronization enable input I2C-Bus data line (5V ability) I2C-Bus clock line (5V ability) System clock 1 Data output UV (see output data format) Data output Y (see output data format) Horizontal active video output EXSYN=0 (I²C-bus parameter): V-Sync output EXSYN=1: External V-Sync input for output part EXSYN=0 (I²C-bus parameter): H-Sync output EXSYN=1: External H-Sync input for output part Interlace signal for AC coupled vertical deflection Crystal connection / System clock 2 Crystal connection Clock output (depends on I²C parameters CLK11EN, CLK21EN, FREQR) Test input, connect to V SS for normal operation

23 22 29 21 20 54 17,..,10 7,..,3;1;64;63 62 61 60 18 28 27 26 19

HIN VIN SYNCEN SDA SCL I CLK1 UVOUT0...7 YOUT0...7 HREF VOUT/ VEXT HOUT/ HEXT INTERLACED X1 / CLK2 X2 CLKOUT TEST

I/TTL PD I/TTL PD I/TTL I/O I I/TTL O/TTL O/TTL O/TTL I/O/ TTL I/O/ TTL O/TTL I/TTL O/AN O/TTL I/TTL

14.7.LM317T
14.7.1.Description The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1.5 amps over an output range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow­out proof. The LM317 serves a wide variety of applications including local, on card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317 can be used as a precision current regulator. 14.7.2.Features · Output Current in Excess of 1.5 A 11

· · · · · · ·

Output Adjustable between 1.2 V and 37 V Internal Thermal Overload Protection Internal Short Circuit Current Limiting Constant with Temperature Output Transistor Safe­Area Compensation Floating Operation for High Voltage Applications 2 Available in Surface Mount D PAK, and Standard 3­Lead Transistor Package Eliminates Stocking many Fixed Voltages

14.8.DDP3310
14.8.1.Description The DDP 3310B is a single-chip digital Display and Deflection Processor designed for high-quality back-end applications in 100/120-Hz TV sets with 4:3 or 16:9 picture tubes. The IC can be combined with members of the DIGIT 3000 IC family (VPC 32xx, TPU 3040), or it can be used with third-party products. The IC contains the entire digital video component and deflection processing and all analog interface components. 14.8.2.Features Video processing ­ linear horizontal scaling (0.25 ... 4) ­ non-linear horizontal scaling "panorama-vision" ­ dynamic peaking ­ soft limiter (gamma correction) ­ color transient improvement ­ programmable RGB matrix ­ picture frame generator ­ two analog RGB/Fast-Blank inputs. The DDP 3310B is a single-chip digital Display and Deflection Processor designed for high-quality backDeflection processing ­ scan velocity modulation output ­ high-performance H/V deflection ­ EHT compensation for vertical / East/West ­ soft start/stop of H-Drive ­ vertical angle and bow ­ differential vertical output ­ vertical zoom via deflection ­ horizontal and vertical protection circuit ­ adjustable horizontal frequency for VGA/SVGA display Miscellaneous ­ selectable 4:1:1/ 4:2:2 YC r C b input ­ selectable 27/ 32-MHz line-locked clock input ­ crystal oscillator for horizontal protection ­ automatic picture tube adjustment (cutoff, white-drive) ­ single 5-V power supply ­ hardware for simple 50/60-Hz to 100/ 120-Hz conversion (display frequency doubling) ­ two I2 C-controlled PWM outputs ­ beam current limiter 14.8.3.Pin connection and short descriptions NC = not connected X = obligatory; connect as described in circuit diagram OUT = Output
Pin no PLCCK 68 pin 1 2 3 4 Pin name VSUPP GNDP VS2 FIFORRD Type SUPPLY SUPPLY IN OUT Connection (if not used) X X GNDD LV

LV = if not used, leave vacant IN = Input SUPPLY = Supply Pin
Short description Supply voltage, Output pin driver Ground, Output pin driver Additional VSYNC input FIFO Read counter reset

12

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

FIFORD FIFOWR FIFORWR HOUT HFLB SAFETY VPROT FREQSEL CM1 CMO RSW2 RSW1 SENSE GNDM VERT+ VERTEW XREF SVM ROUT GOUT BOUT GNDO VSUPO VRD/BCS FBLIN1 RIN1 GIN1 BIN1 FBLIN2 RIN2 GIN2 BIN2 TEST RESQ PWM1 PWM2 HCS C0 C1 C2 C3 C4 C5 C6 C7 VSUPD GNDD LLC2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LLC1 HS VS XTALK2 XTALK1 SDA SCL

OUT OUT OUT OUT IN IN IN IN IN IN OUT IN/OUT IN SUPPLY OUT OUT OUT IN OUT OUT OUT OUT SUPPLY SUPPLY IN IN IN IN IN IN IN IN IN IN IN OUT OUT IN IN IN IN IN IN IN IN IN SUPPLY SUPPLY IN IN IN IN IN IN IN IN IN IN IN IN OUT IN IN/OUT IN/OUT

LV LV LV X Hout GNDO GNDO X X X LV LV GNDO X GNDO GNDO GNDO X VSUPO VSUPO VSUPO VSUPO X X X GNDO GNDO GNDO GNDO GNDO GNDO GNDO GNDO GNDD X LV LV GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD X X X GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VSUPD X GNDD X X X X

FIFO Read Enable FIFO Write Enable FIFO Write counter reset Horizontal Drive Output Horizontal Flyback Input Safety Input Vertical protection Input Selection of H-Drive Frequency Range Clock select 40.5 or 27/32 MHz Clock select 27/32 MHz Range Switch2, Measurement ADC Range Switch1, Measurement ADC Sense ADC Input Ground, MADC Input Differantial Vertical Sawtooth Output Differantial Vertical Sawtooth Output Vertical Parabola Output Reference Input for RGB DACs Scan Velocity Modulation Analog Output Red Analog Output Green Analog Output Blue Ground, Analog Back-end Supply Voltage, Analog Back-end DAC Reference, Beam Current Safety Fast-Blank1 Input Analog Red1 Input Analog Green1 Input Analog Blue1 Input Fast-Blank2 Input Analog Red2 Input Analog Green2 Input Analog Blue2 Input Test Pin Reset Input, active low I2C-controlled DAC I2C-controlled DAC Half-contrast Picture Bas Chroma (LSB) Picture Bas Chroma Picture Bas Chroma Picture Bas Chroma Picture Bas Chroma Picture Bas Chroma Picture Bas Chroma Picture Bas Chroma (MSB) Supply Voltage, Digital Circuitry Ground, Digital Circuitry System Clock Input (27/32/40.5 MHz) Picture Bas Luma (LSB) Picture Bas Luma Picture Bas Luma Picture Bas Luma Picture Bas Luma Picture Bas Luma Picture Bas Luma Picture Bas Luma (MSB) Single Line-Locked Clock Input (13.5/16 MHz) Horizontal Sync Input Vertical Sync Input Analog Crystal Output (5-MHz Security Clock) Analog Crystal Input (5-MHz Security Clock) I2C-Bus Data I2C-Bus Clock

13

14.9.SDA5550
14.9.1.General definition The SDA5550M is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). The device provides an integrated generalpurpose, fully 8051-compatible Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists of up to 17 Kbytes. This device can support external memory up to 1Mbyte ROM and RAM.TVTEXT Controller contains a data slicer for VPS, WSS, PDC and TXT, an acceleration acquisition hardware module, a display generator for Level 1.5 TXT and powerful On screen Display capabilities based on parallel attributes, and pixel oriented characters (DRCS). The 8 bit Microcontroller operates at 360nsec cycle time (min). Controller with dedicated hardware does most of the internal TXT acquisition processing, transfer data to/from 2 external memory interface and receives/transmits data via I C-firmware user interface. SDA5550M is realized in 0.25 micron technology with 2.5V supply voltage and 3.3V I/O compatible. The IC produces the following input or output control signals; AGC_CON, MODE_SW, L / L', PIP_MODS, PIP_SEL, ON/OFF (stand-by), SC1..3_IN_AV (pin 8 information from 3 SCARTs), AFC, MUTE (to mute audio 2 output IC), I CEN. 14.9.2.Features General · Feature selection via special function register · Simultaneous reception of TTX, VPS, PDC, and WSS (line 23) · Supply Voltage 2.5 and 3.3 V External Crystal and Programmable clock speed Single external 6MHz crystal, all necessary clocks are generated internally CPU clock speed selectable via special function registers. Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz Microcontroller Features · 8bit 8051 instruction set compatible CPU. · 33.33-MHz internal clock (max.) · 0.360ms (min.) instruction cycle · Two 16-bit timers · Watchdog timer · Capture compare timer for infrared remote control decoding · Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) · ADC (4 channels, 8 bit) · UART Memory · Non-multiplexed 8-bit data and 16 ... 20-bit address bus (ROMless Version) · Memory banking up to 1Mbyte (Romless version) · Up to 128 Kilobyte on Chip Program ROM · Eight 16-bit data pointer registers (DPTR) · 256-bytes on-chip Processor Internal RAM (IRAM) · 128bytes extended stack memory. · Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX · UP to 16KByte on Chip Extended RAM (XRAM) consisting of; - 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX) - 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software - 3 Kilobyte Display Memory Display Features · ROM Character Set Supports all East and West European Languages in single device · Mosaic Graphic Character Set · Parallel Display Attributes · Single/Double Width/Height of Characters 14

· Variable Flash Rate · Programmable Screen Size (25 Rows x 33...64 Columns) · Flexible Character Matrixes (HxV) 12 x 9...16 · Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters in Enhanced Mode · CLUT with up to 4096 color combinations · Up to 16 Colors per DRCS Character · One out of Eight Colors for Foreground and Background Colors for 1-bit DRCS and ROM Characters · Shadowing · Contrast Reduction · Pixel by Pixel Shiftable Cursor With up to 4 Different Colors · Support of Progressive Scan and 100 Hz. · 3 X 4Bits RGB-DACs On-Chip · Free Programmable Pixel Clock from 10 MHz to 32MHz · Pixel Clock Independent from CPU Clock · Multinorm H/V-Display Synchronization in Master or Slave Mode Acquisition Features · Multistandard Digital Data Slicer · Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+) · Four Different Framing Codes Available · Data Caption only Limited by available Memory · Programmable VBI-buffer · Full Channel Data Slicing Supported · Fully Digital Signal Processing · Noise Measurement and Controlled Noise Compensation · Attenuation Measurement and Compensation · Group Delay Measurement and Compensation · Exact Decoding of Echo Disturbed Signals Ports · One 8-bit · Two 8-bit · One 4-bit · One 2-bit · One 4-bit
2

I/O-port with open drain output and optional I C Bus emulation support (Port 0) multifunction I/O-ports (Port 1, Port 3) port working as digital or analog inputs for the ADC (Port 2) I/O port with secondary functions (P4.2, 4.3, 4.7) I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)

14.10.TEA6415C
14.10.1.General Description The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75? load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration. 14.10.2.Features · 20MHz Bandwidth · Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage) · 8 Inputs (CVBS, RGB, MAC, CHROMA,...) · 6 Outputs · Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge · Bus controlled · 6.5dB gain between any input and output · 55dB crosstalk at 5mHz 15

· Fully ESD protected 14.10.3.Pinning 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Input Data Input Clock Input Input Prog Input Vcc Input Input Ground Output Output Output Output Output Output Ground Input : : : : : : : : : : : : : : : : : Max : 2Vpp, Input Current: 1mA, Max : 3mA Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V Max : 2Vpp, Input Current: 1mA, Max : 3mA Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V Max : 2Vpp, Input Current: 1mA, Max : 3mA Max : 2Vpp, Input Current: 1mA, Max : 3mA Max 12V Max Max : 2Vpp, Input Current: 1mA, Max: 3mA : 2Vpp, Input Current: 1mA, Max : 3mA : 2Vpp, Input Current: 1mA, Max : 3mA Min Min Min Min Min Min : : : : : : 4.5Vpp 4.5Vpp 4.5Vpp 4.5Vpp 4.5Vpp 4.5Vpp

5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp,

Max : 2Vpp, Input Current : 1mA, Max : 3mA

14.11.VPC3230D
14.11.1.General Description The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products. The main features of the VPC 323xD are; ­ high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking ­ multi-standard color decoder PAL/NTSC/SECAM including all substandards ­ four CVBS, one S-VHS input, one CVBS output ­ two RGB/YC r C b component inputs, one Fast Blank (FB) input ­ integrated high-quality A/D converters and associated clamp and AGC circuits ­ multi-standard sync processing ­ linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling `Panorama-vision' ­ PAL+ preprocessing ­ line-locked clock, data and sync, or 656-output interface ­ peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS ­ high-quality soft mixer controlled by Fast Blank ­ PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution ­ 15 predefined PIP display configurations and expert mode (fully programmable) ­ control interface for external field memory ­ I2C-bus interface ­ one 20.25-MHz crystal, few external components ­ 80-pin PQFP package 14.11.2.Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
Pin No. PQFP 80-pin 1 2 Pin Name Type Connection (if not used) VREF VREF Short Description

B1/CB1IN G1/Y1IN

IN IN

Blue1/Cb1 Analog Component Input Green1/Y1 Analog Component Input

16

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD GNDD GNDCAP SCL SDA RESQ TEST VGAV YCOEQ FFIE FFWE FFRSTW FFRE FFOE CLK20 GNDPA VSUPPA LLC2 LLC1 VSUPLLC GNDLLC Y7 Y6 Y5 Y4 GNDY VSUPY Y3 Y2 Y1 Y0 C7 C6 C5 C4 VSUPC GNDC C3 C2 C1 C0 GNDSY VSUPSY INTLC AVO FSY/HC/HSYA MSY/HS VS FPDAT/VSYA VSTBYY CLK5 NC XTAL1 XTAL2 ASGF GNDF VRT

IN IN IN IN IN OUT SUPPLYD SUPPLYD OUT IN/OUT IN/OUT IN IN IN IN OUT OUT OUT OUT OUT IN/OUT OUT OUT OUT IN/OUT SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT OUT OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT IN/OUT OUT IN/OUT SUPPLYA OUT IN OUT SUPPLYA OUTPUT

VREF VREF VREF VREF X LV or GNDD X X X X X X X GNDD GNDD GNDD LV LV LV LV LV LV X X LV LV X X GNDY GNDY GNDY GNDY X X GNDY GNDY GNDY GNDY GNDC GNDC GNDC GNDC X X GNDC GNDC GNDC GNDC X X LV LV LV LV LV LV X LV LV or GNDD X X X X X

Read1/Cr1 Analog Component Input Blue2/Cb2 Analog Component Input Green2/Y2 Analog Component Input Read2/Cr2 Analog Component Input Analog Shield GNDF FIFO Reset Write Input Digital Decoupling Circuitry Supply Voltage Supply Voltage, Digital Circuitry Ground, Digital Circuitry Digital Decoupling Circuitry GND I2C Bus Clock I2C Bus Data Reset Input, Active Low Test Pin, connect to GNDD VGAV Input Y/C Output Enable Input, Active Low FIFO Input Enable FIFO Write Enable FIFO Reset Write/Read FIFO Read Enable FIFO Output Enable Main Clock output 20.25 MHz Pad Decoupling Circuitry GND Pad Decoupling Circuitry Supply Voltage Double Clock Output Clock Output Supply Voltage, LLC Circuitry Ground, LLC Circuitry Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Ground, Luma Output Circuitry Supply Voltage, Luma Output Circuitry Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma (LSB) Picture Bus Chroma (MSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Supply Voltage, Chroma Output Circuitry Ground, Chroma Output Circuitry Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (LSB) Ground Sync Pad Circuitry Supply Voltage, Sync Pad Circuitry Interlace Output Active Video Output Front Sync/ Horizontal Clamp Pulse/Front-End Horizontal Sync Output Main Sync/Horizontal Sync Pulse Vertical Sync Pulse Front End/Back-End Data/Front-End Vertical Sync Output Standby Supply Voltage CCU 5 MHz Clock Output Not Connected Analog Crystal Input Analog Crystal Output Analog Shield GNDF Ground, Analog Front-End Reference Voltage Top, Analog

17

67 68 69 70 71 72 73 74 75 76 77 78 79 80

I2CSEL ISGND VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 VSUPAI GNDAI VREF FB1IN AISGND

IN SUPPLYA SUPPLYA OUT IN IN IN IN IN SUPPLYA SUPPLYA OUTPUT IN SUPPLYA

X X X LV LV VRT VRT VRT VRT X X X VREF X

I2C Bus Address Select Signal Ground for Analog Input, connect to GNDF Supply Voltage, Analog Front-End Analog Video Output Chroma/Analog Video 5 Input Video 1 Analog Input Video 2 Analog Input Video 3 Analog Input Video 4 Analog Input Supply Voltage, Analog Component Inputs Front-End Ground, Analog Component Inputs Front-End Reference Voltage Top, Analog Component Inputs FrontEnd Fast Blank Input Signal Ground for A nalog Component Inputs, connect to GNDAI

14.12.TDA1308T
14.12.1.General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. It gets its input from two analog audio outputs (DACA_L and DACA_R) of MSP3411G. The gain of the output is adjustable by the feedback resistor between the inputs and outputs.

14.12.2.Features · Wide temperature range · No switch ON/OFF clicks · Excellent power supply ripple rejection · Low power consumption · Short-circuit resistant · High performance · high signal-to-noise ratio · High slew rate · Low distortion · Large output voltage swing. 14.12.3.Pinning
SYMBOL OUTA INA(neg) INA(pos) V SS INB(pos) INB(neg) OUTB V DD PIN 1 2 3 4 5 6 7 8 DESCRIPTION Output A Inverting input A Non-inverting input A Negative supply Non-inverting input B Inverting input B Output B Positive supply

14.13.MSP34X1G (MSP3411G)
14.13.1.Description The MSP 34x1G family of single-chip Mullet-standard Sound Processors covers the sound processing of all analog TV -Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure shows a simplified functional block diagram of the MSP34x1G. The MSP34x1G has all functions of the MSP34x0G with the addition of a virtual surround sound feature. Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP34x1G includes our virtualizer algorithm "3D-PANORAMA" which has been approved by the Dolby 1) Laboratories for compliance with the "Virtual Dolby Surround" technology. In addition, the MSP34x1G includes the 18

"PANORAMA" algorithm. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA -J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments. All MSP 34xxG versions are pin and software downward compatible to the MSP 34xxD. MSP34x1G further simplifies controlling software. Standard selection requires a singleI2 C transmission only. The MSP34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I2 C interaction is necessary (Automatic Sound Selection).

14.13.2.Features 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator PANORAMA virtualizer algorithm Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs Interrupt output programmable (indicating status change) Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness Loudspeaker channel with MDB (Micronas Dynamic Bass) AVC: Automatic Volume Correction Subwoofer output with programmable low-pass and complementary high-pass filter 5-