Text preview for : 4.pdf part of Motorola A6188 Schematic Diagram Phone Gsm - (Tot File 11) - Part 1/3
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A1
GSM_LNA275
RX LOCAL OSCILLATOR
A9
GSM LNA
GSM_LNA275 DCS_LNA275 C FL460 925-960MHz B Q461 FL470 925-960MHz B Q1254 5 6 EXT ANT SW_RF from J600 U101 3 2 9 1 1805-1880MHz B FL450 Q101 / Q102 U401 SWITCH CONTROL CIRCUIT DCS_LNA275 MIX_275 PAC_275 B+ Q451 C FL465 RF_V2 B+ 1805-1880MHz B Q1254 E MIX_275 E FL457 C 400 MHz C B
Osc. discrete circuty
Q1255 MIX_275 CR259
800MHz E9
PLL
C8 RF_V1
U913 MAGIC
F7 ( SCLK_OUT ) BCLKR ( SDFS ) BFSR ( SDRX ) BDR to WhiteCap
4 10
7
Q490 C
C
A7 STEP ATT. SWITCH C7 F2
TAI CHI - ORGANISER P5.0
PHASE DETECTOR
A/D
RX SPI
G9 G8
SW_VCC
C Q242 E E Q240 C
B
F1 REG. H1 PHASE DET PLL SWITCH
G1 J7 J9 13MHz
VRef
DCS_LNA
RF_V1
B
H2
H7, C8; J1
CR230 J6 G6 MAGIC_13MHz CLK_SELCT
SUPER FILTER
EGSM: 880-915Mhz DCS: 1710-1785MHz
1-3 Q330 5
4
MUX Prog. Divider
to WhiteCap from WhiteCap
DM_CS EGSM: 1325-1360MHz DCS: 1405-1480MHz RVCO_250 DCS_VCO
SF_OUT
C1 A1
1 /2
PA_B+
5 FL300 2 3
10-15
RX VCO
CR251 CR250 C257 V1 Inductive layer DCS_SEL
1 4
U300 DCS PA U400 GSM PA
CR300 2 1, 7 CR301 7 2, 8 C Q400 B G_TX_VCO PAC_275 D_TX_VCO 2 1, 3 NPA_MUTE 12 EGSM: 880-915Mhz DCS: 1710-1785MHz C Q300 B Q262 C Q455 B Q253 Q255
B1 A3
PHASE DET PLL
Startup Reference E1 26MHz Y230
REFERENCE OSCILLATOR
J8 C4 F9 SPI LOGIC CONTROL FACE G5 INTER H4 J3
( CE ) MQSPI_CS1 ( SPI_CLK ) MOSPI_CLK1 ( SPI_DATA ) DX1
CR306,307
GSM_PINDIODE
-5V_SW
10-15
SHIFT LEVEL CIRCUIT 7
DM_CS V1_FILT
TX_EN from WhiteCap GP04
U340 PAC
RF_IN 2 PAC_275
DET SAT.
U250 TX VCO
10 G_TX_VCO D_TX_VCO 6
6 4 SF_OUT
TX LOOP FILTER
( SDTX ) BDX TX Q344 MODULATION SPI TX_EN J2 ( TX_CLK ) BCLKX G7
4, 14 10 12 8 11 U341 DET_SW AOC_DRIVE SAT_DETECT
PA_B+
PAC_275
TVCO_250
( GSM / DCS SELECT )
Q343
RVCO_250
( RX VCO, GSM/DCS SELECT )
DETECT_SW AOC_DRIVE SAT_DETECT TX_KEY_OUT
A5 H8 B6 B4 C5 PA CONTROL LOGIC J4 CONTROL H5
RX_ACQ DM_CS TX_KEY from WhiteCap
TX_KEY_OUT NPA_MUTE TVCO_250 PAC_275 DCS_VCO MIX_275 GSM_LNA275 DCS_LNA275 G_TX_VCO D_TX_VCO GSM_PINDIODE
EUROPE MIDDLE EAST & AFRICA
25.10.99
RX SIGNAL PATH TX SIGNAL PATH
REFERENCE CLOCK Orderable Part Non - Orderable Part
GSM / DCS SELECT CIRCUIT
CUSTOMER SERVICES LEVEL 3 RF Block Diagram TAI CHI ORGANISER Ralf Lorenzen, Michael Hansen, Ray Collins Page1 Rev. 1.1
MAIN VCO SIGNAL PATH TUNING VOLTAGES
HEAD_INT KBR0, KBR1, KBR2 ( Keyboard ) KBC0, KBC1, KBC2, KBC3 BKLT_EN DP_EN HS_INT VIB_EN LED_RED LED_GRN LS1_IN LS2_IN LS3_TX LS3_RX CLK_SELCT TX_EN DM_CS TX_KEY RX_EN RX_ACQ RESET ( SDTX ) BDX ( TX_CLK ) BCLKX from / to MAGIC ( SCLK_OUT ) BCLKR ( SDFS ) BFSR ( SDRX ) BDR
N3 H2, H3, H1 K1, J4, J3, J2 K2 E10 KEYPAD P4 DISPLAY K4 INTERFACE M3 M2 E8 SIM D6 INTER E1 FACE E6 A1 C3 D2 C1 F5 E2 CTM E1 E4 E2 MODULE E3 E3 E4 M4 P2 C6 A2 A3 B4 C4 J5 SERIAL INTER FACE DSP
A4 C14, D4, E12, H4, J10, K6, N12 B5, B9, B10, G12, K14, L11, N8 U700 L8 WHITE_CAP SPI M8 INTERFACE M7 M E M O R Y CPU I N T E R F A C E
( CE ) MQSPI_CS1 ( SPI_CLK ) MOSPI_CLK1 ( SPI_DATA ) DX1
V2 V3 PRESENCE DETECT ( MAGIC SPI )
BATT CONNECTOR
DATA BUS ADDRESS BUS
( Flip Con. ) R_W V2 C9 E9 D11 D9 A9 CE2 CE3 R_W D6, E1 B2 U702 A1 G6 CE0 CE1 D7 F8 V2 RESET A4, A6, F6 B4
J611 J614 BATT + N/C J613 BATT_SER_DATA
J610 BATT_THERM J612 GND
( WhiteCap ) VIB_EN B+
1 5
J810
U801
4
SRAM
U701 EPROM EEPROM
KBC0 KBR0 KBR1
HOME PAGE UP PAGE DOWN POWER ON / OFF VA CW Jog Switch
Baseband to Digital Speech
CTM F3 A/D CHARGE N6
-5V_EN
LS_V1 2 U901
STDBY 1 LS_V1 -5V
J 600 DSC_EN_B+ 13 PC_RXD 6 PC_TXD 7
BATT FDBK EXT_B+ SW_RF
DEEP SLEEP CIRCUIT
V1
ON / OFF KBR0
DSC UART INTERF. SPI INTERFACE TIMER D7 K5 G14 MAGIC_13MHz RTC_BATT
5
From PDA ( for RS232 ) To PDA
D5 A6
EXT B+ BATT + BATT + CHRG_EN
CCW
4
AUDIO SPI
GCAP_CLK 13 MHz
GCLK 32.768 KHz
14 2 8 9 1 3 10 15 5 15 PIN EXT CONN.
Ext Charger_En
EXT_B+
UTXD URXD To / From PDA ON / OFF (From Switch)
GCAP SPI
KBC1 U970 Q970 RTC BATT BT2 B+ Q634 ( GCAP2 ) V2 CR940 Q942
KBR2
TAI CHI - Organiser
URTS_PA6 On/Off GND GND GND GND MAN_TEST_AD
Y633
CR920
F5 C7 G5 SPI INTERFACE
A7 B7 D6 REAL TIME CLOCK SELECT SENSE CNTL D9 E8 F7 D10 F6 LEVEL J7 SHIFTJ8 K7 G6 K10 H8 C8 Logic Control G4
VREF REG. V3 REG. V2 REG. V1 REG.
R932 I SENSE CHRGC BATT+ EXT_B+ CLK RST SIM_I/O 6 4 5 LS1_IN LS2_IN LS3_TX LS3_RX PWR_SW STDBY G9 B5 J5 A6 C6 A10, C10 VREF 2.775V,for MAGIC V3 1,8V, for WhiteCap J900 SIM Con. 1 2 VSIM1
Q932
CR932 Q635 BATT FDBK
LED_RED ( WhiteCap ) LED_GRN
5 2 6 Q805 1
3 Q805 4
( Ext Accessory Sense) A1 VS944 DSC_EN_AD DOWNLINL_AD BATT_THERM ISENSE B2 SENSE A2 B3 CNTL. D9
U900 G_CAP2
RX SIGNAL PATH TX SIGNAL PATH MAIN VCO SIGNAL PATH TUNING VOLTAGES REFERENCE CLOCK Orderable Part Non - Orderable Part EUROPE MIDDLE EAST & AFRICA
BKLT_EN
RESET
C4 D2 C3
UPLINK DOWNLINK
11 12
MIC J910
V2 2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM LS_V1 5.0V, for DSC Bus, Negative Voltage Regulator
J2 PA_DRV Interface Audio Codec H6 H7 SPRSPR+
HEADSET J504
VSIM REG. VBOOST1 REG.
VSIM1 3.0 or 5.0V, for SIM Card Circuit
U980
H3 H2
H9
K5 E10
B10 LX
U980
18.10.99
SPKR J9833 ALRT_VCC TO PDA
Q938 L901
CR901
CUSTOMER SERVICES LEVEL 3 AL Block Diagram Dualband Tai Chi Organiser
BKLT+ ( Flip Con. )
V_BOOST1 Internal GCap use only (VSIM1, LS_V1)
Rev. 1.1 Page1
B+
Q938
Ralf Lorenzen, Michael Hansen, Ray Collins