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Data Sheet
gmZ1
DAT-0001-D
August 1998
200 Town Centre Blvd. · Suite 400 · Markham · · ON Canada · L3R 8G5 · Tel: (905) 470-2742 · Fax: (905) 470-9022 1871 Landings Drive · Mountain View · · CA USA · 94043 · Tel: (650) 428-4277 · Fax: (650) 428-4288 www.genesis-microchip.com / [email protected]
Genesis Microchip
Genesis Microchip
gmZ1 Data Sheet DAT-0001-D
(supersedes gmZ1 Data Sheet DAT-0001-C)
Document Preliminary 1.0 DAT-0002-A
(CD-ROM)
Revision Details
Date May 1997 Aug 1997
DAT-0001-B DAT-0001-C
Figs. 2, 10, 17, 18, 21, 26, 27, Tables 6, 30, Soft Reset description, No Zoom Mode, Z_HORZ_SV, Z_VERT_SV Ref. timing diagrams (p91, 92, 96), Ordering Info (p101), 1.5V switching level threshold (p90), fig. 32, fig. 41, fig. 42, DH_BKGND_END (p81). Changed reference to " multiscan" on page 3. Added Table 3 D_BYPASS Mode signals. Added note to Section 5.7
Oct 1997 April 1998
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Table of Contents
TABLE OF CONTENTS
1. 2. 3. 4. 5. OVERVIEW...................................................................................................................................1 FEATURES & APPLICATIONS ..................................................................................................2 GENERAL OPERATION .............................................................................................................4 PINOUT .........................................................................................................................................6 FUNCTIONAL DESCRIPTION .................................................................................................13 5.1. POWER- ON RESET .......................................................................................................................13 5.2. SYSTEM CLOCKS ........................................................................................................................14 5.2.1. Input Port Clock..............................................................................................................14 5.2.2. Display Port Clock...........................................................................................................14 5.2.3. Overlay Port Clock ..........................................................................................................15 5.2.4. Host Interface Port Clock................................................................................................15 5.3. INPUT PORT................................................................................................................................16 5.3.1. VGB Input Port ...............................................................................................................16 5.3.2. VGA Input Port ...............................................................................................................22 5.3.3. Operating Modes .............................................................................................................27 5.3.4. Input Active Window Control ..........................................................................................30 5.4. RGB OUTPUT PORT ....................................................................................................................33 5.4.1. Data Transfer Modes.......................................................................................................33 5.4.2. Programmable Input Lock Event ....................................................................................34 5.4.3. D_BYPASS Mode ............................................................................................................35 5.4.4. Display Timing Generation .............................................................................................36 5.4.5. Output Display Timing Exception Handling ...................................................................41 5.4.6. Display Active Window Control.......................................................................................41 5.5. OVERLAY PORT ..........................................................................................................................45 5.5.1. Input Signals ...................................................................................................................45 5.5.2. Output Control Signals....................................................................................................49 5.6. HOST INTERFACE PORT ...............................................................................................................50 5.6.1. Host Interface Protocol ...................................................................................................50 5.6.2. Host Interface State Description .....................................................................................57 5.6.3. Typical Usage Scenarios..................................................................................................58 5.6.4. Interrupts.........................................................................................................................61 5.6.5. Updating Register Contents.............................................................................................61 5.6.6. Host I/F Address Map/Control Bit Map. .........................................................................62 5.7. HOST INTERFACE REGISTERS.......................................................................................................64 5.7.1. Host Interface and Main Control Register ......................................................................64 5.7.2. Input Control Register.....................................................................................................66 5.7.3. Display Control Register..................................................................................................68 5.7.4. Display Output Port Control Register..............................................................................70
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Table of Contents
5.7.5. 5.7.6. 5.7.7. 5.7.8. 5.7.9. 5.7.10. 5.7.11. 5.7.12. 5.7.13. 5.7.14. 6. 7. 8.
Display Clock Control Register .......................................................................................71 Status Register.................................................................................................................72 Interrupt Control Register 1 ............................................................................................73 Interrupt Control Register 2 ............................................................................................74 Input Video Register........................................................................................................75 Display Register...............................................................................................................77 Zoom Register .................................................................................................................78 Filter Horizontal Control Register...................................................................................80 Display Horizontal Control Register................................................................................80 Overlay Register ..............................................................................................................84
ELECTRICAL SPECIFICATIONS ............................................................................................86 ORDERING INFORMATION ..................................................................................................104 MECHANICAL SPECIFICATIONS ........................................................................................105
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TABLE OF FIGURES
FIGURE 1: FUNCTIONAL BLOCK DIAGRAM ................................................................................................1 FIGURE 2: GMZ1 SYSTEM BLOCK DIAGRAM .............................................................................................5 FIGURE 3: GMZ1 PINOUT .........................................................................................................................6 FIGURE 4: VIDEO COLOR DECODER CONNECTION TO GMZ1 ......................................................................17 FIGURE 5: VCLREQ, VCBLNK - START OF FRAME .......................................................................................19 FIGURE 6: VCLREQ OPERATION ................................................................................................................19 FIGURE 7: VCLREQ OPERATION DURING END OF FRAME/FIELD ................................................................20 FIGURE 8: SINGLE PIXEL MODE - VGB PORT INTERFACING ..................................................................21 FIGURE 9: CCIR 601 SIGNAL RANGE ....................................................................................................21 FIGURE 10: DATA RANGE ......................................................................................................................23 FIGURE 11: PIXEL WIDTH MODE ............................................................................................................24 FIGURE 12: SINGLE PIXEL - RGB " VGA"PORT INTERFACING ...............................................................24 FIGURE 13: RGB SINGLE PIXEL TIMING.................................................................................................25 FIGURE 14: DOUBLE PIXEL - VGA AND VGB PORTS INTERFACING .......................................................25 FIGURE 15: RGB DOUBLE PIXEL TIMING ...............................................................................................26 FIGURE 16: RGB DOUBLE PIXEL OFFSET TIMING #1.............................................................................27 FIGURE 17: RGB PORT DOUBLE PIXEL OFFSET TIMING #2 ...................................................................27 FIGURE 18: NTSC DE-INTERLACING ZOOM ...........................................................................................29 FIGURE 19: PAL DE-INTERLACING ZOOM ..............................................................................................29 FIGURE 20: YUV DATA START OF ACTIVE WINDOW ..............................................................................30 FIGURE 21: YUV DATA END OF ACTIVE WINDOW .................................................................................31 FIGURE 22: INPUT ACTIVE WINDOW ......................................................................................................32 FIGURE 23: DISPLAY DATA TIMING SINGLE PIXEL MODE ........................................................................33 FIGURE 24: DISPLAY DATA TIMING DOUBLE PIXEL MODE .......................................................................34 FIGURE 25: D_BYPASS MODE DISPLAY TIMING ..................................................................................36 FIGURE 26: DISPLAY TIMING DIAGRAM ...................................................................................................44 FIGURE 27: EXAMPLE OF OVERLAY IMPLEMENTATION ............................................................................45 FIGURE 28: OVERLAY PORT - START OF ACTIVE OVERLAY LINE ............................................................47 FIGURE 29: OVERLAY PORT - END OF ACTIVE OVERLAY LINE ................................................................47 FIGURE 30: OVERLAY ACTIVE REGION PROGRAMMING ..........................................................................48 FIGURE 31: HOST INTERFACE PORT ......................................................................................................50 FIGURE 32: HOST I/F START CONDITION (FOLLOWED BY ADDRESS CYCLE).........................................54 FIGURE 33: HOST I/F ADDRESS TRANSFER ...........................................................................................54 FIGURE 34: HOST I/F ADDRESS READ BACK (ARB) TRANSFER ............................................................55 FIGURE 35: HOST I/F WRITE DATA TRANSFER ......................................................................................56 FIGURE 36: HOST I/F READ DATA TRANSFER ........................................................................................56 FIGURE 37: HOST I/F STOP CONDITION (AFTER A READ DATA TRANSFER)............................................57 FIGURE 38: HOST INTERFACE OPERATING STATES AND TRANSFERS .....................................................57 FIGURE 39: IDD @ 16PF OUTPUT LOAD .....................................................................................................88 FIGURE 40: IDD @ 10PF OUTPUT LOAD .....................................................................................................90 FIGURE 41: CLOCK REFERENCE LEVELS .................................................................................................94 FIGURE 42: SETUP AND HOLD REFERENCE LEVELS ................................................................................94 FIGURE 43: VGA & VGB PORT TIMING ................................................................................................95
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FIGURE 44: VGA & VGB PORT TIMING ................................................................................................95 FIGURE 45: 4-WIRE MODE HOST I/F TIMING .........................................................................................97 FIGURE 46: OVERLAY PORT TIMING .......................................................................................................98 FIGURE 47: PROPAGATION DELAY REFERENCE LEVELS ..........................................................................99 FIGURE 48: SINGLE PIXEL DISPLAY PORT TIMING ................................................................................100 FIGURE 49: DISPLAY PORT TIMING ......................................................................................................100 FIGURE 50: DISPLAY PORT TIMING - DCLK_PHASE[1:0]...................................................................101 FIGURE 51: DOUBLE PIXEL - DISPLAY PORT TIMING.............................................................................102 FIGURE 52: BY-PASS MODE - DISPLAY PORT TIMING ..........................................................................103 FIGURE 53: Q4 PACKAGE (208-PIN PQFP) ........................................................................................105 FIGURE 54: H2 PACKAGE (208-PIN PQFP WITH HEAT SLUG) ............................................................106
LIST OF TABLES
TABLE 1: GMZ1 PINOUT ...........................................................................................................................7 TABLE 2: SUMMARY - I/O INTERFACING TO GMZ1 ..................................................................................16 TABLE 3: CORRESPONDING INPUT/OUTPUT SIGNALS IN D_BYPASS .....................................................35 TABLE 4: DISPLAY TIMING GENERATION: SYNCHRONIZATION MODES ...................................................36 TABLE 5: OVERLAY COLOR CONTROLS ..................................................................................................46 TABLE 6: HOST I/F SDO MODE.............................................................................................................51 TABLE 7: SUMMARY OF THE 3-WIRE HOST I/F TRANSFER MODES .........................................................52 TABLE 8: SUMMARY OF THE 4-WIRE HOST I/F TRANSFER MODES .........................................................53 TABLE 9: MON_SEL[2:0] .....................................................................................................................63 TABLE 10: HOSTCTRL ........................................................................................................................64 TABLE 11: IPCTRL ...............................................................................................................................66 TABLE 12: DCONTROL........................................................................................................................68 TABLE 13: DOUTCNTRL......................................................................................................................70 TABLE 14: DCLK_CTRL.......................................................................................................................71 TABLE 15: STATUS..............................................................................................................................72 TABLE 16: IRQ1CNTRL .......................................................................................................................73 TABLE 17: IRQ2CNTRL .......................................................................................................................74 TABLE 18: INPUT VIDEO .........................................................................................................................75 TABLE 19: DISPLAY LINE RATE...............................................................................................................77 TABLE 20: ZOOM ...................................................................................................................................78 TABLE 21: FHC - FILTER HORIZONTAL CONTROL ..................................................................................80 TABLE 22: DISPLAY HORIZONTAL ...........................................................................................................80 TABLE 23: OVERLAY ..............................................................................................................................84 TABLE 24 RECOMMENDED OPERATING CONDITIONS ..............................................................................86 TABLE 25: ABSOLUTE MAXIMUM RATINGS ..............................................................................................86 TABLE 26 DC CHARACTERISTICS ..........................................................................................................87 TABLE 27 : IDD FOR DIFFERENT CONDITIONS, 16PF OUTPUT LOADING .....................................................88
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TABLE 28 : POWER DISSIPATION = 2.92W @ 3.6V, 84MHZ, 100% DATA SWITCHING ...............................89 TABLE 29 : POWER DISSIPATION = 2.26W @ 3.6V, 65MHZ, 100% DATA SWITCHING ..............................89 TABLE 30 : POWER DISSIPATION = 2.21W @ 3.3V, 84MHZ, 75% DATA SWITCHING .................................89 TABLE 31 : POWER DISSIPATION = 1.68W @ 3.3V, 65MHZ, 75% DATA SWITCHING ................................90 TABLE 32 : IDD FOR DIFFERENT CONDITIONS WITH 10PF OUTPUT LOADING ..............................................91 TABLE 33 : POWER DISSIPATION = 2.84W @ 3.6V, 84MHZ, 100% DATA SWITCHING ...............................91 TABLE 34 : POWER DISSIPATION = 2.20W @ 3.6V, 65MHZ, 100% DATA SWITCHING ...............................91 TABLE 35 : POWER DISSIPATION = 2.14W @ 3.3V, 84MHZ, 75% DATA SWITCHING .................................92 TABLE 36 : POWER DISSIPATION = 1.65W @ 3.3V, 65MHZ, 75% DATA SWITCHING ................................92 TABLE 37: VGA & VGB PORT TIMING ..................................................................................................93 TABLE 38: HOST I/F PORT TIMING .........................................................................................................96 TABLE 39: OVERLAY PORT TIMING.........................................................................................................97 TABLE 40: MISCELLANEOUS INPUTS TIMING ...........................................................................................98 TABLE 41: SINGLE PIXEL MODE DISPLAY PORT TIMING..........................................................................98 TABLE 42: DISPLAY PORT TIMING - DCLK_PHASE[1:0].....................................................................101 TABLE 43: DOUBLE PIXEL MODE DISPLAY PORT TIMING ......................................................................102 TABLE 44: DISPLAY PORT TIMING - D_BYPASS MODE .........................................................................103
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gmZ1 Data Sheet
1. Overview
The gmZ1 is a highly-integrated IC producing real-time, high-quality, scaled digital video or computer graphics images. Three separate data channels have been integrated into the gmZ1, allowing complete images to be resized using a single device. The gmZ1 performs image magnification (zoom) on 24-bit RGB or 16-bit YUV input data streams. The RGB video ports support single width (24-bit) or double width (48-bit) pixel transfers. The gmZ1 performs advanced interpolation and finite impulse response (FIR) filtering independently in both the vertical and horizontal directions. The output image' spatial frequency s response is automatically adjusted to preserve image bandwidth and to minimize imaging artifacts, resulting in the highest image quality. Both graphics and status overlay information can be displayed on top of the scaled video data by means of an overlay port. A "transparent" capability exists for viewing zoomed video within and around any alpha-numeric or graphics overlay.
Figure 1: Functional Block Diagram
External Ovly Generation 16-bit YUV VGBCLK 48-bit (2 Pixels) RGB VGACLK YUV Input RGB Input YUV to RGB Overlay Mux & Output Data Path
Zoom Buffer
Vertical Zoom Filter
Horz Zoom Filter
48-bit RGB (2 Pixels)
VGBHS, VGAHS
Cropping Control
Write Control
Memory Control
Read Control
Display Control
DHS DVS DEN DCLK
VGBVS, VGAVS VGACREF,VGBCREF DREFCLK1 DREFCLK2 SCS, SDO SDI SCLK Host I/F Control
IRQ1 IRQ2
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gmZ1 Data Sheet
2. Features & Applications
High quality advanced zoom-only engine: Fully programmable zoom ratios Independent Horizontal/Vertical zoom An advanced zoom algorithm provides pristine image quality Spatial de-interlacing of video inputs Corrected spatial positioning of odd and even input lines Built-in display timing generator Can be used to drive AMLCD panels Special support for DMD engines Fully programmable timing parameters YUV inputs: 16-bit YUV input video Clock rates up to 45MHz NTSC/PAL square pixels/CCIR601 Glue-less connection to many color decoders, ex. Philips SAA7110/7111 Built-in YUV to RGB color space converter RGB inputs: Single 24-bit RGB pixels @ 84MHz 48-bit RGB pixel @ 42MHz Programmable input port Output Pixel Modes supported: 1 and 2 pixel/clock panel support Single 24 bit RGB pixel/clock @ 84MHz Dual 48 bit RGB pixels/clock @ 42 MHz Dithering logic to enhance pixel color depth for 18-bit panels Compliant with proposed VESA FPDI-2 standard via direct connect to NSC, C&T, SII LVDS transceivers Operating Modes Bypass mode with no filtering 1:1 scaling Non-interlaced zoom De-interlacing zoom Display Synchronization Modes Frame Sync - input & output frame periods are forced to synchronize Line Sync - display line rate synthesized from the input line rate Free Run - input and output rates are not synchronized - ideal for frame-rate conversions
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gmZ1 Data Sheet
Simplicity of design speeds time to market
Single-chip zoom-only solution No external memory required Programmable horizontal and vertical front and back porches on input data Input active window region decoded Active window framing signal requests pixels 2 clocks before sampling time Using line request and pixel request signals, pipelined video data I/F can be easily designed Overlay menus supported via dedicated port, control, and data lines 4-wire or 3-wire serial host interface for easy connection to Intel/Motorola MCUs
Applications Projection Systems based on AMLCDs, DMDs Fixed-resolution Pixelated Display devices Multiscan LCD Panels for CRT replacement Standards conversion Scan doublers/quadruplers/converters Home theater Video Walls
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gmZ1 Data Sheet
3. General Operation
The gmZ1 has been designed to simplify connection to both digital video and graphics data streams. Once the gmZ1 is programmed, high quality zoom processing is performed using independently adjustable ADVANCED ZOOM filtering in the vertical and horizontal directions. All filter coefficients are generated internally without additional programming. The gmZ1 scales the selected input video by a 1X or larger zoom ratio to create an output image of equal or greater size. The gmZ1 requires no external frame buffer when the input and output formats have equal frame rates and the vertical active periods are synchronized. Magnification plus frame-rate conversion may be performed using the Genesis gmFC1 Frame Rate Converter chip along with the gmZ1 (see Application Note MSD-0016). The video input data is transferred to the gmZ1 at the selected video input pixel clock rate and stored in an internal zoom buffer. Data is read from the zoom buffer for processing by the onchip scaler and subsequent display at the display pixel clock rate. The selected input and output display clocks can run at different frequencies. An overlay port outputs programmable overlay timing information to external overlay circuitry that generates 8-bit overlay color select data (See Application Note MSD-0008). Two independent overlay display regions may be displayed on top of the scaled output. Pixel-by-pixel enabling control provides "transparent" capability for viewing zoomed video within and around any alpha numeric or graphics overlay. The gmZ1 can be initialized by an external micro-controller to program the control, status, filter parameter, and timing parameter registers via a serial interface port. All registers can be accessed using read, write, burst-read, and burst-write I/O cycles. The gmZ1 provides status and video timing information to the system through a status register and programmable interrupts. A gmZ1 Programming Cable and software is available from Genesis Microchip to help speed up gmZ1 designs. This Cable Module allows a PC to access and program gmZ1 registers directly (See Application Note MSD-0004). What' sOn Software is also available to help in calculating gmZ1 register parameters (See The What' sOn User Guide SED-0015).
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gmZ1 Data Sheet
Figure 2: gmZ1 System Block Diagram
18/36 or 24/48
16/24
/
VGB PORT
Video Decoder
HS CREF LLC
DISPLAY PORT
NTSC/PAL/ SECAM
VS
/
DCLK DVS DHS DEN
VSYNC VGACLK HSYNC I/P PLL
VGA PORT
VGA / SVGA / XGA
24/48 RGB Capture 3x ADC
/
gmZ1
HSYNC
HOST I/F PORT SDI / SDO/ SCS 3
OVERLAY PORT
DREFCLK2
DREFCLK1
4 Overlay Control EPLD 8
8 ROM Overlay Buffer
*
Microcontroller
SCLK
/
O/P PLL CLK
XTAL OSC
* Overlay control may be simplified using a single chip OSD device such as the Motorola 141544DW. See Genesis Application Note MSD-0008.
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gmZ1 Data Sheet
4. Pinout
Figure 3: gmZ1 Pinout
GND GND GND GND VDD OVACTIV2 VGBVS VGBHS VGBCLK VGBCREF VCODD VGAHS VGACREF GND VGACLK VGAVS VGAGRN0 VGAGRN1 VGAGRN2 VGAGRN3 VGAGRN4 VGAGRN5 VGAGRN6 VGAGRN7 VGARED0 VDD IPCLK0 VCBLNK VGARED1 GND VGARED2 VCLREQ VGARED3 VGARED4 VGARED5 VGARED6 VGARED7 VGBRED0 (VGBYIN0) VGBRED1 (VGBYIN1) VGBRED2 (VGBYIN2) VGBRED3 (VGBYIN3) VGBRED4 (VGBYIN4) VGBRED5 (VGBYIN5) VGBRED6 (VGBYIN6) VGBRED7 (VGBYIN7) VGABLU0 VGABLU1 GND GND GND GND GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
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GND GND GND GND GND DAGRN6 DAGRN7 DARED0 DARED1 VDD DARED2 DARED3 GND OVCOLA2 OVCOLA1 VDD OVCOLA0 OVENA OVCOLB2 OVCOLB1 OVCOLB0 OVENB GND DCLK DEN DHCLK VDD DVS DHS DOE MSBFIRST GND IRQ2 SCLKPOL VDD GND DARED4 DARED5 GND DARED6 DARED7 VDD DABLU0 DABLU1 GND DABLU2 DABLU3 VDD GND GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
GND GND GND GND GND OVACTIV1 OVCLK OVSYNC VGBGRN7 VGBGRN6 VGBGRN5 VGBGRN4 VGBGRN3 VGBGRN2 VGBGRN1 VDD DREFCLK2 GND DREFCLK1 VDD VGBGRN0 DBGRN0 GND DBGRN1 DBGRN2 DBGRN3 VDD DBGRN4 DBGRN5 DBGRN6 DBGRN7 GND DBRED0 DBRED1 DBRED2 DBRED3 DFSYNC RESET VDD DAGRN0 DLOCK DAGRN1 GND DAGRN2 DAGRN3 DAGRN4 DAGRN5 VDD GND GND GND GND
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
gmZ1
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
GND GND GND GND VDD VGABLU2 VGABLU3 VGABLU4 VGABLU5 VGABLU6 VGABLU7 VGBBLU0 (VGBUVIN0) VGBBLU1 (VGBUVIN1) VDD VGBBLU2 (VGBUVIN2) VGBBLU3 (VGBUVIN3) VGBBLU4 (VGBUVIN4) VGBBLU5 (VGBUVIN5) VGBBLU6 (VGBUVIN6) VGBBLU7 (VGBUVIN7) GND DBBLU7 DBBLU6 DBBLU5 DBBLU4 VDD DBBLU3 DBBLU2 DBBLU1 GND DBBLU0 DBRED7 VDD DBRED6 DBRED5 DBRED4 GND IRQ1 SDO SDI SCLK SCS VDD DABLU7 DABLU6 DABLU5 DABLU4 GND GND GND GND GND
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gmZ1 Data Sheet
Table 1: gmZ1 Pinout
"VGB" Input Port (YUV or RGB Data) - Input Signals PIN #
148 147 150 149 119 118 117 116 115 114 113 112 177 171 170 169 168 167 166 165 93 92 90 89 88 87 86 85
Symbol
VGBCLK VGBCREF VGBVS VGBHS VGBRED0/VGBYIN0 VGBRED1/VGBYIN1 VGBRED2/VGBYIN2 VGBRED3/VGBYIN3 VGBRED4/VGBYIN4 VGBRED5/VGBYIN5 VGBRED6/VGBYIN6 VGBRED7/VGBYIN7 VGBGRN0 VGBGRN1 VGBGRN2 VGBGRN3 VGBGRN4 VGBGRN5 VGBGRN6 VGBGRN7 VGBBLU0/VGBUVIN0 VGBBLU1/VGBUVIN1 VGBBLU2/VGBUVIN2 VGBBLU3/VGBUVIN3 VGBBLU4/VGBUVIN4 VGBBLU5/VGBUVIN5 VGBBLU6/VGBUVIN6 VGBBLU7/VGBUVIN7
I/O Description
I I I I I I I I I I I I I I I I I I I I I I I I I I I I Video input system clock Input pixel clock qualifier - programmable active high or low Vertical sync - programmable active high or low Horizontal sync - programmable active high or low Red input data /Input data for Y - LSBit Red input data /Input data for Y Red input data /Input data for Y Red input data /Input data for Y Red input data /Input data for Y Red input data /Input data for Y Red input data /Input data for Y Red input data /Input data for Y - MSBit Green input data - LSBit Green input data Green input data Green input data Green input data Green input data Green input data Green input data - MSBit Blue input data /Input data for UV - LSBit Blue input data /Input data for UV Blue input data /Input data for UV Blue input data /Input data for UV Blue input data /Input data for UV Blue input data /Input data for UV Blue input data /Input data for UV Blue input data /Input data for UV - MSBit
Note: VGB port input data represents the Right pixel of a pixel pair in double wide mode
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gmZ1 Data Sheet
"VGA" Input Port (RGB Data) - Input Signals PIN #
142 144 141 145 132 128 126 124 123 122 121 120 140 139 138 137 136 135 134 133 111 110 99 98 97 96 95 94
Symbol
VGACLK VGACREF VGAVS VGAHS VGARED0 VGARED1 VGARED2 VGARED3 VGARED4 VGARED5 VGARED6 VGARED7 VGAGRN0 VGAGRN1 VGAGRN2 VGAGRN3 VGAGRN4 VGAGRN5 VGAGRN6 VGAGRN7 VGABLU0 VGABLU1 VGABLU2 VGABLU3 VGABLU4 VGABLU5 VGABLU6 VGABLU7
I/O Description
I I I I I I I I I I I I I I I I I I I I I I I I I I I I Video graphics input system clock Video graphics input system clock enable - programmable active high or low Vertical sync - programmable active high or low Horizontal sync - programmable active high or low Red input data - LSBit Red input data Red input data Red input data Red input data Red input data Red input data Red input data - MSBit Green input data - LSBit Green input data Green input data Green input data Green input data Green input data Green input data Green input data - MSBit Blue input data - LSBit Blue input data Blue input data Blue input data Blue input data Blue input data Blue input data Blue input data - MSBit
Note: VGA port input data represents the Left pixel of a pixel pair in double wide mode
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gmZ1 Data Sheet
Input Port Control Signals - Common Control signals for "VGB" and "VGA" ports. PIN #
146 125 129
Symbol
VCODD VCLREQ
VCBLNK
I/O Description
I O O Interlace Mode Field status, programmable active high or low. Default 1=odd field, 0=even field Line request signal indicates the gmZ1 is ready to accept input lines When de-asserted, blanking output indicates active capture window for the selected (VGA or VGB) video input
Overlay Port PIN #
163 164 162 151 18 17 15 14 22 21 20 19
Symbol
OVCLK
OVSYNC OVACTIV1 OVACTIV2
I/O Description
O O O O I I I I I I I I Clock for external overlay circuit (operates at half the display pixel rate). Overlay vertical synchronization pulse indicates start of new frame of display overlay data. Overlay status indicates active overlay window region #1 Overlay status indicates active overlay window region #2 Enables overlay "A" color. Overlay "A" color select - Blue Overlay "A" color select - Green Overlay "A" color select - Red Enables overlay "B" color. Overlay "B" color select - Blue Overlay "B" color select - Green Overlay "B" color select - Red
OVENA OVCOLA0 OVCOLA1 OVCOLA2 OVENB OVCOLB0 OVCOLB1 OVCOLB2
Display Port PIN #
30
Symbol
DOE
I/O Description
I Display Port Output Enable. A logic "1" tri-states all Display Output Port clock, control and data output signals. Display timing reference clock #1 Display timing reference clock #2 Display output clock. Programmable phase. Half rate display output clock. Programmable phase. Display vertical sync. Programmable active high or low. Display horizontal sync. Programmable active high or low.
175 173 24 26 28 29
DREFCLK1 DREFCLK2 DCLK DHCLK DVS DHS
I I O O O O
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gmZ1 Data Sheet
PIN #
25 8 9 11 12 37 38 40 41 196 198 200 201 202 203 6 7 43 44 46 47 58 59 60 61 189 190 191 192 69 70 71 73 178 180 181 182 184 185 186
Symbol
DEN DARED0 DARED1 DARED2 DARED3 DARED4 DARED5 DARED6 DARED7 DAGRN0 DAGRN1 DAGRN2 DAGRN3 DAGRN4 DAGRN5 DAGRN6 DAGRN7 DABLU0 DABLU1 DABLU2 DABLU3 DABLU4 DABLU5 DABLU6 DABLU7 DBRED0 DBRED1 DBRED2 DBRED3 DBRED4 DBRED5 DBRED6 DBRED7 DBGRN0 DBGRN1 DBGRN2 DBGRN3 DBGRN4 DBGRN5 DBGRN6
I/O Description
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Display enable (specifies active area of display). Programmable active high or low. Red output data - LSBit Red output data Red output data Red output data Red output data Red output data Red output data Red output data - MSBit Green output data - LSBit Green output data Green output data Green output data Green output data Green output data Green output data Green output data - MSBit Blue output data - LSBit Blue output data Blue output data Blue output data Blue output data Blue output data Blue output data Blue output data - MSBit Red output data - LSBit Red output data Red output data Red output data Red output data Red output data Red output data Red output data - MSBit Green output data - LSBit Green output data Green output data Green output data Green output data Green output data Green output data
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gmZ1 Data Sheet
PIN #
187 74 76 77 78 80 81 82 83
Symbol
DBGRN7 DBBLU0 DBBLU1 DBBLU2 DBBLU3 DBBLU4 DBBLU5 DBBLU6 DBBLU7
I/O Description
O O O O O O O O O Green output data - MSBit Blue output data - LSBit Blue output data Blue output data Blue output data Blue output data Blue output data Blue output data Blue output data - MSBit
Note: DA output data represents the Left pixel of a pixel pair in double wide mode. DB output data represents the Right pixel of a pixel pair in double wide mode. Host Interface Control Signals PIN # Symbol I/O Description
194 31 34 63 64 65 66
RESET MSBFIRST
I I I I I I O
SCLKPOL
SCS SCLK SDI SDO
Reset input for initializing the device Selects data bit order MSB or LSB first operation, 0=LSBit First; 1=MSBit First. 0=SDI sampled on SCLK rising edge, SDO clock out on SCLK falling edge. Serial Control I/F Chip select Serial Control I/F Clock Serial Control I/F Input Data Serial Control I/F Output Data
Miscellaneous Interface Signals PIN # Symbol I/O Description
67 IRQ1 O Interrupt or status output to host controller. Programmable to indicate IPVsync, OPVsync, Zoom buffer Error (over/under flow). Interrupt or status output to host controller. Programmable to indicate IPVsync, OPVsync, Zoom buffer Error (over/under flow). Display REFCLK lock status Display Timing Forced Synchronization - forces the Display Timing Generation to a programmable location within the blanking interval when a falling edge is detected. Selected input pixel port clock (VGBCLK or VGACLK). For use as reference to external display clock synthesis PLL which generates DREFCLK1 or DREFCLK2.
33
IRQ2
O
197 193
DLOCK DFSYNC
I I
130
IPCLKO
O
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gmZ1 Data Sheet
Power and Ground Power Supply, +3.3V [18 pins] 10, 16, 27, 35, 42,48, 62, 72,79, 91, 100, 131,152, 172, 176, 183, 195, 204
Ground [51 pins]
1, 2, 3, 4, 5, 13, 23, 32, 36, 39, 45, 49, 50, 51, 52, 53,54, 55, 56, 57, 68, 75, 84, 101, 102, 103, 104 105, 106, 107, 108, 109, 127, 143, 153, 154, 155 156, 157, 158, 159, 160, 161, 174, 179, 188, 199 205, 206, 207, 208
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gmZ1 Data Sheet
5. FUNCTIONAL DESCRIPTION
5.1. Power-on Reset
A Power-on Reset cycle is required to place the gmZ1 into a defined state, and should be initiated after any power supply excursion outside of the range specified in Table 26. If a Power-on Reset cycle is not performed, the operation of the gmZ1 cannot be guaranteed and the output image data may be corrupted. A Power-on Reset cycle is performed by asserting RESET for at least 100 nsec. This forces all internal programmable registers to be set to zero. SCLK must be asserted (logic high) for a minimum of 50 nsec during the RESET pulse. After the RESET pulse, the selected input and display clocks (VGBCLK and DREFCLK1 by default) must receive a minimum of 8 rising clock edges before normal operation will commence.
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gmZ1 Data Sheet
5.2. System Clocks
There are master clocks for each of the gmZ1' four ports: the Input Port, the Display Port, the s Overlay Port, and the Host Interface Port. 5.2.1. Input Port Clock The Input Port is divided into the VGA Port and the VGB Port.
5.2.1.1. VGACLK & VGACREF - VGA Input Port (RGB Data)
The VGACLK signal provides the master clock for the VGA Input Port. This clock supports operating speeds up to 84 MHz. VGACLK synchronizes data on the input buses and the writing of data to the gmZ1. The active edge of VGACLK is programmable through the host interface. The VGACREF (VGA Port Clock Reference) signal provides a clock by clock enable (or stall) capability when transferring data and control information into the VGA Input Port. VGACREF must be asserted during the selected edge of VGACLK for control and data information to be sampled.
5.2.1.2. VGBCLK & VGBCREF - VGB Input Port (YUV or RGB Data)
VGBCLK is the master clock for the VGB Input Port, which accepts YUV or RGB data. This clock is connected to a 1X or 2X pixel clock in the external system with operating frequencies up to a maximum of 45 MHz when in YUV mode, or 84 MHz when in RGB mode. The active edge of VGBCLK is programmable through the Host Interface. The VGBCREF (VGB Port Clock Reference) signal provides a clock-by-clock enable (or stall) capability when transferring data and control information into the VGB Input Port. VGBCREF must be asserted during the selected edge of VGBCLK to enable the sampling of control and data information. 5.2.2. Display Port Clock
5.2.2.1. DREFCLK1 DREFCLK2, DCLK and DHCLK
Two separate display reference clocks (DREFCLK1 and DREFCLK2) are supported to allow systems to easily integrate both a free-running crystal oscillator and an external Phase Lock Loop (PLL) generated clock for display timing. The PLL display clock can be synchronized to the external video input to achieve frame lock through clock synchronization.
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gmZ1 Data Sheet
DREFCLK1: This clock input is driven by an external free running crystal oscillator source and is the default clock source during power-up-reset. It must always be driven by a free-running clock for the gmZ1 device to reset properly. DREFCLK2: This clock input is driven from an external crystal oscillator source or PLL. The gmZ1 can be programmed to use DREFCLK2 as the display timing master clock by setting the HOSTCTRL: DREFCLK2_EN control bit. DREFCLK1 and DREFCLK2 control all display timing. A buffered version of the enabled clock is output on the DCLK pin. A separate DHCLK signal operating at half the DCLK rate is output and available to systems using Double Pixel Mode. The Display Port data and control outputs are sampled by any external device using the DCLK and DHCLK outputs. These clocks provide controlled set-up and hold times for sampling the data outputs. The DCLK and DHCLK active edge (rising/falling) is programmable and the clock phase relative to the data and control outputs is also software controlled. By default, DCLK and DHCLK are rising-edge aligned to the data and control outputs. (DCLK leads DHCLK which in turn leads the state changes on the control and data outputs to provide finite hold times for external devices.) 5.2.3. Overlay Port Clock The overlay clock output, OVCLK, operates at the same frequency as DHCLK (one half of the display pixel clock rate) and must be used as the clock for any off-chip overlay generation circuitry. This clock is used by external overlay generation circuitry to latch the gmZ1 overlay output control signals and to clock the overlay color select and enable control signals into the gmZ1. 5.2.4. Host Interface Port Clock The Serial Clock (SCLK) must be provided by the external system to clock input and output serial data. The active edge is determined by the Serial Clock Polarity (SCLKPOL) pin. Address and data transfers are composed of sixteen pulses of SCLK framed by an asserted SCS (Serial Chip Select). Each transfer cycle must consist of 16 SCLK cycles - valid control, address, or data bits must be provided with each SCLK.
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gmZ1 Data Sheet
5.3. Input Port
Table 2 summarizes the basic signal connections required for specific input data formats. The Reference Page gives the location of a detailed explanation for each item in this data sheet.
Table 2: Summary - I/O Interfacing to gmZ1
Input Data Format YUV Single Pixel RGB "VGB" Single Pixel RGB "VGA" Single Pixel RGB Double Pixel Pixel Width 16-bit Required Signals
"VGB" Input Port:
VGBCLK, VGBCREF, VGBHS, VGBVS,
Reference Page 16
VGBYIN[7:0] and VGBUVIN[7:0].
24-bit 24-bit 48-bit
Input Port Control Signals: Use all signals. "VGB" Input Port: Use all signals. Input Port Control Signals: Use all signals "VGA" Input Port: Use all signals. Input Port Control Signals: Use all signals "VGA" Input Port:
of each 48-bit pixel pair. Use all signals. This port supports the 24-bits (Left pixel)
16, 20 22, 24 22, 25
"VGB" Input Port:
Use VGBRED[7:0], VGBGRN[7:0], VGBBLU[7:0].
This port supports the 24-bits (Right pixel) of each 48-bit pixel pair. This port is clocked and controlled by the VGA clock/control signals.
RGB Double Pixel Offset
48-bit
Input Port Control Signals: Use all signals. "VGA" Input Port: Use all signals. This port supports the 24-bits of each 48bit pixel pair. Pixels are latched when VGACREF = ` . 1'
22, 26
"VGB" Input Port:
Use VGBRED[7:0], VGBGRN[7:0], VGBBLU[7:0].
This port supports the 24-bits (Right pixel) of each 48-bit pixel pair. This port is clocked and controlled by the VGA clock/control signals. Pixels are latched when VGACREF = ` . 0'
Input Port Control Signals:
Use all signals.
5.3.1. VGB Input Port The VGB Input Port supports interlaced and non-interlaced data streams and provides an easy direct connection to most common color decoder chips. As an example, a glueless connection from the Philips SAA7110 color decoder to the gmZ1 VGB Input Port is shown in Figure 4. The VGB Input Port supports video timing for square pixel and CCIR601 formatted NTSC/PAL/SECAM, as well as non-standard data streams. The VGB port supports YUV and RGB data formats.
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gmZ1 Data Sheet
Figure 4: Video Color Decoder Connection to gmZ1
LL27 OR LLC VGBCLK VGBCREF VGBVS VGBHS VGBYIN(7:0), VGBUVIN(7:0)
Video Color Decoder (SAA7110)
CREF VS HS Y7-Y0, UV7-UV0
gmZ1 VGB Port
16
The gmZ1 always uses an even number of active Y and UV samples per line. Odd numbers of active samples are not supported, however the total number of pixel clocks (blanking and active) per line can be an odd value.
5.3.1.1. VGB Port I/O Signals (YUV Data)
VGBVS The VGB Input Port samples VGBVS (VGB Port Vertical Sync) during qualified VGBCLK cycles, i.e. when VGBCREF is asserted during an active VGBCLK edge. When VGBVS assertion is detected, the gmZ1 begins processing a new input field. The VGBVS active state is programmable via the HOSTCTRL register. VGBHS The VGB Input Port samples VGBHS (VGB Port Horizontal Sync) during qualified VGBCLK cycles. Upon VGBHS assertion, the VGB Input Port prepares for the next incoming line of video data. The VGBHS active state is programmable via the HOSTCTRL register. Note: VGBHS can be used to stall the gmZ1 on a "line-by-line" basis. VCODD The VCODD signal (Input ODD Field Indicator) determines the vertical start location of the active window. For interlaced video sources, VCODD selects one of two programmable vertical start locations. For non-interlaced video sources, this signal is ignored and all input frames are treated as "ODD" fields. VCODD is common to the VGB and VGA Input Ports. VCODD must be valid during each field/frame' first active VGBHS pulse as defined by the s IPV_STARTODD or IPV_STARTEVN programmable registers. Since VCODD determines the field polarity, it must assume its correct state before the lesser of the start odd or start even values. VCODD must remain valid for the entire vertical active region, i.e. during all active lines. The VCODD active state is programmable via the register set. (By default, VCODD = ` 1' indicates odd fields.)
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gmZ1 Data Sheet
VCBLNK VCBLNK (Input Port Composite Blanking Indicator) indicates that the gmZ1 device is sampling pixels in the Active Display Window region. This signal frames the active region when the gmZ1 accepts pixel data for zoom processing. This signal is common to the VGB/VGA Input Ports.
When required, the external system should sample VCBLNK during qualified clock edges (i.e. during a valid combination of VGBCLK edge and VGBCREF state). VCBLNK is de-asserted two qualified pixel clocks before the first input data is sampled, and can be used as a pixel request signal. For applications where the external system is providing VGB Input Port data from a memory storage buffer (i.e. frame buffer, FIFO) , the predictive blanking signal allows the system one qualified clock edge to sample VCBLNK , and the next qualified clock edge to output data to the VGB Port. This data is then sampled on the subsequent qualified clock edge by the gmZ1. For applications where the external system is providing free-running video and control signals to the Input Port, the VCBLNK signal does not provide any controlling function, but can be used to monitor the active samples accepted by the VGB Input Port.
VCLREQ The Line Request, VCLREQ output signal that indicates the gmZ1 is ready for input video lines. This signal is common to the VGA/VGB Input Port.
If the external system is providing a free-running video source to the VGB Port, the VCLREQ signal is not typically utilized, since the flow of video data and control information cannot be stalled. However, VCLREQ can be monitored to determine the input lines accepted by the VGB Input Port. If the external system is providing source data and control information from a memory device without periodic video line timing, the gmZ1 de-asserts VCLREQ at the end of each active video line until the VGB Port is ready for the next line. VCLREQ is always de-asserted between input video lines to stall the flow of input data while the gmZ1 is flushing internal pipelines. When VCLREQ is asserted to request the next input line, the system should always provide a VGBHS to initialize the gmZ1 for the next line. VGBHS should be followed by the programmed amount of blanking and valid data. Once asserted to request data, VCLREQ will remain asserted until the programmed number of pixels have been transferred into the VGB Port. VCLREQ and VCBLNK are intended to be utilized by system frame buffer controllers to provide high-speed pipelined image/video data interfaces with minimal external glue logic.
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gmZ1 Data Sheet
Figure 5: VCLREQ, VCBLNK - Start of Frame
VGACLK VGAVS
VCLREQ
VGAHS
VCBLNK
VGA (data)
XXX A0
event --
A
B
C
D
E
F
A - VSYNC occurs B - VGA Port samples VGAVS to detect start of first line of a new field or frame. GmZ1 internal line # set to 1. C - VCLREQ is asserted nine clocks after VGAVS assertion. D - gmZ1 reaches vertical active region start value (IPV_ACTIV_STARTODD, IPV_ACTIV_STARTEVN) E - VGA Port indicates pending start of active region, 2 pixels before IPH_ACTIV_START. F - VGA Port samples first pixel of first line of frame. There are IPH_ACTIV_WIDTH active pixel samples per active line.
Note: VGAVS is programmed active low, VGAHS is programmed active high.
Figure 6: VCLREQ Operation
VGBVS/VGAVS (input) VGBHS/VGAHS (input) VCLREQ (output) VCBLNK (output)
System indicates start of next line with Hsync. When VGB/VGA Input Port is ready for next line, VCLREQ goes active again to request next line. After programmed # of active pixels, VCBLNK and VCLREQ indicate end of horizontal active region. VCBLNK indicates horizontal active region.
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gmZ1 Data Sheet
Figure 7: VCLREQ Operation During End of Frame/Field
VGBVS/VGAVS VGBHS/VGAHS VCLREQ (output) VCBLNK (output)
System indicates start of last active line with Hsync. After programmed # of valid pixel clocks, VCBLNK indicates start of horz. active region. After programmed # of active pixels, VCBLNK indicates end of horz. active region. VCLREQ goes inactive - end of image.
VGACLK VCLREQ VCBLNK
After VS leading edge is detected , VCLREQ requests lines of data for next frame or field.
5.3.1.2. VGB Port I/O Signals (RGB Data)
The VGB port supports RGB single pixel data on its own (up to 84MHz data rates), or doublepixel data streams in combination with the VGA port. The VGA port is described beginning with section 5.3.2. A connection to an RGB single-pixel source is shown below in Figure 8.
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gmZ1 Data Sheet
Figure 8: Single Pixel Mode - VGB Port Interfacing
CLK CREF VGBCLK VGBCREF VGBVS VGBHS
ADC
VS HS
gmZ1 RGB "VGB" Input Port
RA[7:0], GA[7:0], BA[7:0]
VGBRED[7:0], VGBGRN[7:0], VGBBLU[7:0]
24
The functionality of the control signals is identical whether the VGB port is processing YUV or RGB data.
5.3.1.3. Data Format
YUV input data is accepted through an 8-bit Y channel, and an 8-bit multiplexed UV (or Cb, Cr) channel. UV data is sub-sampled using standard 4:2:2 sampling. Y data values can be full range 0 - 255; however, they will be clamped by internal circuitry to be in the CCIR601 range (16 to 235). UV data values can be full range 0 - 255; however, they will be clamped by internal circuitry to be in the range 16 to 240. See Figure 9. The VGB port also accepts full scale RGB data on the VGBRED, VGBGRN, and VGBLU buses. The gmZ1 contains a color space converter that always transforms 4:2:2 YUV data to 24-bit RGB. R = 1/256 [298Y + 409V - 57014]
G = 1/256 [298Y - 100U - 208V + 34692] B = 1/256 [298Y + 517U + Cb = U, Cr = V 1V - 70964]
Figure 9: CCIR 601 Signal Range
+255 +235
White (100%)
+255 +240
U-component range
blue 100%
+255 +240
V-component range
red 100%
luminance range
+128
+128
+128
+16 0
Black
+16 0
yellow 100%
+16 0
cyan 100%
Y Signal Range
U Signal Range
V Signal Range
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gmZ1 Data Sheet
5.3.2. VGA Input Port The VGA Input Port accepts real-time video graphics data and control signals (HSYNC, VSYNC, Pixel clock, Clock Qualifier). The VGA Input Port supports interlaced and noninterlaced video data streams with three different input modes: Single-Pixel, Double-Pixel and Double-Pixel-Offset.
5.3.2.1. VGA Port I/O Signals
VCODD The VCODD signal (Input ODD Field Indicator) determines the vertical start location of the active window. For interlaced video sources, VCODD selects one of two programmable vertical start locations. For non-interlaced video sources, this signal is ignored and all input frames are treated as "ODD" fields. VCODD is common to the VGB and VGA Input Ports. VCODD must be valid during each field/frame' first active VGAHS pulse as defined by the s IPV_STARTODD or IPV_STARTEVN programmable registers. Since VCODD determines the field polarity, it must assume its correct state before the lesser of the start odd or start even values. VCODD must remain valid for the entire vertical active region i.e. during all active lines. The VCODD active state is programmable via the register set. (By default, VCODD = ` 1' indicates odd fields.)
VCBLNK VCBLNK (Input Port Composite Blanking Indicator) indicates that the gmZ1 device is sampling pixels in the Active Display Window region. This signal frames the active region when the gmZ1 accepts pixel data for zoom processing. This signal is common to the VGB/VGA Input Ports.
When required, the external system should sample VCBLNK during qualified clock edges (i.e. during a valid combination of VGBCLK edge and VGBCREF state). VCBLNK is de-asserted two qualified pixel clocks before the first input data is sampled, and can be used as a pixel request signal. For applications where the external system is providing VGA Input Port data from a memory storage buffer (i.e. frame buffer, FIFO) , the predictive blanking signal allows the system one qualified clock edge to sample VCBLNK , and the next qualified clock edge to output data to the VGA Port. This data is then sampled on the subsequent qualified clock edge by the gmZ1. For applications where the external system is providing free-running video and control signals to the Input Port, the VCBLNK signal does not provide any controlling function, but can be used to monitor the active samples accepted by the VGB Input Port.
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gmZ1 Data Sheet
VCLREQ
The Line Request, VCLREQ output signal indicates the gmZ1 is ready for input video lines. This signal is common to the VGA/VGB Input Port. For applications where the external system is providing a free-running video source to the VGA Port, the VCLREQ signal is not typically utilized, since the flow of video data and control information cannot be stalled. However, VCLREQ can be monitored to determine the input lines accepted by the VGA Input Port. If the external system is providing source data and control information from a memory device without periodic video line timing, the gmZ1 de-asserts VCLREQ at the end of each active video line until the VGA Port is ready for the next line. VCLREQ is always de-asserted between input video lines to stall the flow of input data while the gmZ1 is flushing internal pipelines. When VCLREQ is asserted to request the next input line, the system should always provide a VGAHS to initialize the gmZ1 for the next line. VGAHS should be followed by the desired number of blanking and valid data. Once asserted to request data, VCLREQ will remain asserted until the programmed number of pixels have been transferred into the VGA Port. VCLREQ and VCBLNK are intended to be utilized by system frame buffer controllers to provide high-speed pipelined image/video data interfaces with minimal external glue logic. See Figure 6 and Figure 7.
5.3.2.2. Data Format
The VGB port supports single pixel width (24 bit) and double pixel width (48 bit transfers). Each pixel consists of 8 bits for each color component: R (Red), G (Green), and B (Blue). Individual Red, Green, and Blue data values are full range 0 - 255.
Figure 10: Data Range
a) Unsigned Integer
255
1111 1111
0
0000 0000
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gmZ1 Data Sheet
5.3.2.3. Pixel Width Control
The three available pixel modes are selected by the IPCTRL register and IP2PIXWIDE_EN and IP2PIXOFFSET_EN bits.
Figure 11: Pixel Width Mode
Mode Single Pixel VGA Port Single Pixel VGB Port Double Pixel Double Pixel Offset YUV Single Pixel
IP2PIXWIDE_EN IP2PIXOFFSET_EN RGB_B_SEL IP_RGB_EN
0 0 1 0 0
0 0 0 1 0
0 1 0 0 0
1 1 1 1 0
5.3.2.3.1. Single Pixel Mode
Figure 12: Single Pixel - RGB "VGA" Port Interfacing
CLK CREF VGACLK VGACREF VGAVS VGAHS
ADC
VS HS
gmZ1 RGB "VGA" Input Port
RA[7:0], GA[7:0], BA[7:0]
VGARED[7:0], VGAGRN[7:0], VGABLU[7:0]
24
In this mode, the Horizontal Active Window is programmable in single pixel increments. The sync and control signals are sampled by the gmZ1 every pixel clock when the pixel clock qualifier (VGACREF) is active. 24-bit RGB data is transferred into the gmZ1 only when VGACREF is asserted during the "active" region as indicated by VCBLNK . There is a two clock latency between VCBLNK being de-asserted and data being accepted by the gmZ1. VGAVS (VGA Port Vertical Sync) is sampled during the selected edge of VGACLK when VGACREF is active. VGAHS is sampled during the selected edge of VGACLK when VGACREF is active.
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gmZ1 Data Sheet
Figure 13: RGB Single Pixel Timing
VGACLK (input) VGACREF (input) VGA (data input) VGB (data input) VCBLNK (output) xxx rgb0 xxx rgb1 rgb2 xxx rgb3 rgb4
Note: There is a two clock latency between the de-assertion of VCBLNK and the gmZ1 accepting data. There is also a two clock latency at the end of a line between assertion of VCBLNK and the last data sample accepted by the gmZ1.
5.3.2.3.2. Double Pixel Mode
Figure 14: Double Pixel - VGA and VGB Ports Interfacing
CLKA ACREF VGACLK VGACREF VGAVS VGAHS VGARED[7:0], VGAGRN[7:0], VGABLU[7:0] 24 RB[7:0], GB[7:0], BB[7:0] 24 VGBRED[7:0], VGBGRN[7:0], VGBBLU[7:0]
ADC
AVS AHS
gmZ1 RGB Input Port
RA[7:0], GA[7:0], BA[7:0]
In this mode, the Horizontal Active Window is programmable in double pixel increments. The gmZ1 samples the sync and control signals every pixel clock when the pixel clock qualifier (VGACREF) is active. Note that only pixel clocks where VGACREF is active are counted. Both the VGA and VGB buses are sampled on every qualified pixel clock during the active region indicated by the VCBLNK signal. Note that the maximum transfer rate is one pixel pair every two pixel clocks. VGACREF must be inactive for at least 1 clock period every other pixel clock. Data is not sampled when the pixel
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gmZ1 Data Sheet
clock qualifier is in-active. Therefore in Double Pixel Mode the sync inputs always correspond to 2 pixels. VGAVS (VGA Port Vertical Sync) is sampled during the selected edge of VGACLK when VGACREF is active. VGAHS is sampled during the selected edge of VGACLK when VGACREF is active
Figure 15: RGB Double Pixel Timing
VGACLK (input) VGACREF (input) VGA (data input) VGB (data input) VCBLNK (output) xxx xxx rgb0 rgb1 rgb2 rgb3 rgb4 rgb5 xxx xxx rgb6 rgb7 rgb8 rgb9
Note: There is a two clock latency between the de-assertion of VCBLNK and the gmZ1 accepting data. There is also a two clock latency at the end of a line between the assertion of VCBLNK and the last data sample accepted by the gmZ1.
5.3.2.3.3. Double Pixel Offset Mode.
In this mode, the Horizontal Active Window is programmable in single pixel increments. The sync and control signals are sampled by the gmZ1 every pixel clock, independently of the pixel clock qualifier (VGACREF) state. All pixel clocks are counted. Pixel data on the VGA bus (24 bit RGB) is transferred into the gmZ1 on each rising edge of pixel clock while VGACREF is active. Pixel data on the VGB (24-bit RGB) is transferred into the gmZ1 on rising edge of the pixel clock while VGACREF is NOT active. The VGACREF active state is programmable to allow the interchanging of A and B Port transfers. The pixel clock qualifier acts as a pixel A/B select for systems providing double width pixel data in a "ping-pong" fashion. Note that the pixel transfer rate is one pixel pair every two pixel clocks and the pixel clock qualifier must be half the pixel clock frequency.
VGAVS (VGA Port Vertical Sync) and VGAHS are sampled during the selected edge of VGACLK. (Not dependent on the state of VGACREF).
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gmZ1 Data Sheet
Figure 16: RGB Double Pixel Offset Timing #1
VGACLK (input) VGACREF (input) VGA (data input) VGB (data input) VCBLNK (output) xxx xxx rgb0 rgb2 rgb4 rgb6 rgb8 rgb10 rgb9 rgb11
rgb1
rgb3
rgb5
rgb7
Figure 17: RGB Port Double Pixel Offset Timing #2
VGACLK (input) VGACREF (input) VGA (input) VGB (input) VCBLNK (output) xxx xxx rgb1 rgb0 rgb3 rgb5 rgb7 rgb9
rgb2
rgb4
rgb6
rgb8 rgb10
Note: In Figure 16 and Figure 17 there is a two clock latency between the de-assertion of VCBLNK and the gmZ1 accepting data. This latency also holds true at the end of a line, between the assertion of VCBLNK and the last data sampled.
5.3.3. Operating Modes The gmZ1 operates in several modes: No Zoom, Standard Zoom and De-Interlacing Zoom. These modes will either allow the data to "pass-through" (i.e. the output data will be identical to
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gmZ1 Data Sheet
the input or the de-interlaced input), data will be zoomed (magnified), or the interlaced data will be de-interlaced and possibly zoomed.
5.3.3.1. No Zoom Mode
In No Zoom mode, the input image data passes through the gmZ1 unchanged. The number of active pixels per line and the number of active lines per frame remains unchanged. However, the data crosses clock boundaries from the input video pixel clock to the display pixel clock. No Zoom mode is enabled when the input and output active windows are the same size, i.e. register values for the Input Video Register are equal: IPH_ACTIV_WIDTH = DH_ACTIV_WIDTH IPV_ACTIV_LNGTH = DV_ACTIV_LNGTH No Zoom mode also requires the horizontal and vertical scaling values to be set to zero, i.e. Z_HORZ_SV = 0 and Z_VERT_SV = 0.
5.3.3.2. Standard Zoom Mode
This mode is used to magnify non-interlaced data, i.e. graphics. Input image data may be magnified both vertically and horizontally - the vertical and horizontal zoom ratios are independently adjustable. The zoom ratio is set by programming the input active window parameters to the source image size, and by programming the display active window parameters to the required output image size. The Z_HORZ_SV and Z_VERT_SV registers must be programmed for zoom operation. DH_ACTIV_WIDTH > IPH_ACTIV_WIDTH DV_ACTIV_LNGTH > IPV_ACTIV_LNGTH
5.3.3.3. De-Interlacing Zoom Mode
This mode is used to spatially de-interlace input data, i.e. video. Every input field is magnified to the output frame resolution, however, the even and odd fields have different fractional vertical offsets applied to properly map the two input fields into the non-interlaced output frame. This ensures the fields are correctly aligned in the output frame and eliminates interlacing artifacts.
5.3.3.3.1. NTSC Video
The spatial de-interlacing process assumes the ODD field is always mapped spatially higher than the EVEN field, which is true for NTSC video sources. No special operations are required by the user to handle NTSC video.
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DAT-0001-D
Genesis Microchip
gmZ1 Data Sheet
Figure 18: NTSC De-Interlacing Zoom
Y1
(Y1)
F1 Y2
(Y2)
F2 F3
Y3
(Y3)
Y4
(Y4)
where IPV_ACTIV_STARTODD = Y1 IPV_ACTIV_STARTEVN = Y2
F4 F5
Y5
(Y5)
Y6
(Y6)
F6 F7
Y7
(Y7)
Y8
(Y8)
EVEN Output Frame
F8
ODD Output Frame
NTSC ODD Field (gmZ1 ODD Field)
NTSC EVEN Field (gmZ1 EVEN Field)
5.3.3.3.2. PAL
For PAL sources, the ODD field is mapped spatially lower than the EVEN field. Since the gmZ1 always maps input fields spatially higher when VCODD is active, the PAL definition of ODD can be accommodated by inverting the VCODD "active" state through the IPCTRL register IPODD_INV control bit. IPODD_INV should be programmed so that the VCODD active state corresponds with input fi