Text preview for : 8575A.pdf part of Mitac 8575A Service Manual
Back to : 8575A.part1.rar | Home
SERVICE MANUAL FOR
8575A
8 5 7 5 A
BY: Sissel Diao
TESTING TECHNOLOGY DEPARTMENT // TSSC TESTING TECHNOLOGY DEPARTMENT TSSC Aug . 2002
8575A N/B Maintenance
Contents
1. Hardware Engineering Specification ...........................................................................
4
1.1 Introduction ......................................................................................................................... 4 1.2 System Hardware Parts .......................................................................................................... 6 1.3 Other Functions .................................................................................................................... 42 1.4 Peripheral Components ........................................................................................................... 47 1.5 Power Management ............................................................................................................... 50 1.6 Appendix 1: SiS961 GPIO Definitions ......................................................................................... 52 1.7 Appendix 2: H8 Pins Definitions ................................................................................................ 53
2. System View and Disassembly ....................................................................................
59
2.1 System View ......................................................................................................................... 59 2.2 System Disassembly ............................................................................................................... 62
3. Definition & Location of Connectors / Switches ..............................................................
81
3.1 Mother Board ....................................................................................................................... 81 3.2 DC Power Board ................................................................................................................... 84 3.3 ESB Board ........................................................................................................................... 85 3.4 Touch-pad ........................................................................................................................... 86 3.5 Daughter Board .................................................................................................................... 86
1
8575A N/B Maintenance
Contents
4. Definition & Location of Major Component ..................................................................
87
4.1 Mother Board ....................................................................................................................... 87
5. Pin Description of Major Component ...........................................................................
89
5.1 Intel Pentium 4 Processor mPGA478 Socket ................................................................................. 89 5.2 SiS650 IGUI Host / Memory Controller ....................................................................................... 95 5.3 SiS691 MuTIOL Media I/O Controller ....................................................................................... 100 5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder .......................................................................... 106 5.5 PCI1410GGU PCMCIA Controller ............................................................................................ 109 5.6 uPD72872 IEEE1394 Controller ................................................................................................ 114
6. System Block Diagram ............................................................................................. 7. Maintenance Diagnostics ..........................................................................................
116 117
7.1 Introduction ......................................................................................................................... 117 7.2 Error Codes ......................................................................................................................... 118 7.3 Maintenance Diagnostics ......................................................................................................... 120
8. Trouble Shooting ....................................................................................................
121
8.1 No Power ............................................................................................................................. 122
2
8575A N/B Maintenance
Contents
8.2 No Display ........................................................................................................................... 8.3 VGA Controller Failure LCD No Display .................................................................................... 8.4 External Monitor No Display ................................................................................................... 8.5 Memory Test Error ............................................................................................................... 8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ............................................................................... 8.7 Hard Disk Drive Test Error ..................................................................................................... 8.8 CD-ROM Driver Test Error ..................................................................................................... 8.9 USB Test Error ..................................................................................................................... 8.10 PIO Port Test Error ............................................................................................................. 8.11 Audio Failure ..................................................................................................................... 8.12 LAN Test Error .................................................................................................................. 8.13 PC Card Socket Failure ......................................................................................................... 8.14 IEEE 1394 Failure ...............................................................................................................
129 133 135 137 139 141 143 145 148 150 153 155 157 159 182 184 217
9. Spare Parts List ..................................................................................................... 10. System Exploded Views .......................................................................................... 11. Circuit Diagram ................................................................................................... 12. Reference Material ................................................................................................
3
8575A N/B Maintenance
1. Hardware Engineering Specification
1.1 Introduction
The 8575A motherboard would support the Intel® Pentium® 4 processor with FC-PGA2 packaged, using 478-Pin micro PGA (mPGA478) socket, which will supports different speeds up to Willamette P4 1.7GHz (Throttling)/Northwood above 2.0GHz (Throttling). This system is based on PCI architecture, which have standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as power indicator, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery charging status. It also equipped 2 USB ports. The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM), support PC2100 & PC2700. SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.
4
8575A N/B Maintenance
The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like P4. The SiS301LV is a Display device which has two data operation paths. Channel B path is selected when SiS301LV performs TV or LCD only display function. There's scaling hardware in this path. In LCD display mode, this hardware can make lower VGA resolution display to fit up to 1280x1024 LCD panel. In TV display mode, this scaler can provide overscan and underscan option for TV. At TV and LCD simultaneous display mode, TV data stream run through Channel B and LCD data stream run through Channel A. To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto the motherboard. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows 95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI). Following chapters will have more detail description for each individual sub-systems and functions.
5
8575A N/B Maintenance
1.2 System Hardware Parts
CPU Mobile Intel® Pentium® 4 Processor M Built on 0.13-micron process Available speeds 1.80GHz, 1.70GHz, 1.60GHz, 1.50GHz, 1.40GHz Intel® Pentium® 4 processor; Willamette/Northwood with mFCPGA2 Package, mPGA 478 Socket Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling) FSB 400MHz /PC 2100/1600 SiS 650+SiS961: Host & Memory & AGP Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance memory controller, a AGP interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO. SiS301LV 256KB Flash EPROM Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI 0MB on board memory -Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) -Support PC2100 & PC2700 8/16/32/64 UMA ICS 952001 ICS 93722 Hitachi H8 3437S Card Bus Controller: TI PCI1410 One type II slot/ Card Bus support/ No ZV port support Power Switch : TI TPS2211 AC97 CODEC: Advance Logic, Inc, ALC201 Power Amplifier: TI TPA0202 NS PC87393 56Kbps (V.90, worldwide) MDC Modem ICS1893Y-10 10/100 base T PHY IEEE1394 OHCI Controller : NEC uPD72872
6
Core logic
VGA Control System BIOS Memory
Video Memory Clock Generator DDR Clock Buffer Embedded controller PCMCIA
Audio System Super I/O Modem PHY of LAN IEEE1394
8575A N/B Maintenance
1.2.1 CPU_Intel Pentium 4 Processor
Built on 0.13-micron process technology and Intel® NetBurstTM micro-architecture, the Mobile Intel® Pentium® 4 Processor - M represents a new generation of mobile computing. It provides superior capabilities for graphics-intensive multimedia applications, and processor-intensive background computing tasks such as compression, encryption, and virus scanning. Enhanced Intel® SpeedStep® technology helps to optimize application performance and power consumption, and Deeper Sleep Alert State, a dynamic power management mode, adjusts voltage during brief periods of inactivity - even between keystrokes - for longer battery life. Innovative Micro FCPGA packaging technology enables the processor to fit into small form factors, such as thin-and-light notebooks. The Intel® Pentium® 4 processor, Intel's most advanced, most powerful processor, is based on the new Intel® NetBurstTM micro-architecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multi-tasking user environments. The Intel Pentium 4 processor delivers this world-class performance for consumer enthusiast and business professional desktop users as well as for entry-level workstation users. Highlights of the Pentium 4 Processor : Available at speeds ranging from 1.50 to 2 GHz Featuring the new Intel NetBurst micro-architecture
7
8575A N/B Maintenance
Supported by the SiS650 chipset Fully compatible with existing Intel Architecture-based software Internet Streaming SIMD Extensions 2 Intel® MMXTM media enhancement technology Memory cache ability up to 4 GB of addressable memory space and system memory scalability up to 64GB of physical memory Support for uni-processor designs Based upon Intel's 0.18 micron manufacturing process Intel Pentium 4 Processor Product Feature Highlights The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as a number of enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floatingpoint and Multi-media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances were made possible with improvements in processor technology, process technology, and circuit design that could not previously be implemented in high-volume, manufacturable solutions. The features and resulting benefits of the new micro-architecture are defined below.
8
8575A N/B Maintenance
Hyper Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared to the P6 micro-architecture used on today's Pentium III processors. One of the key pipelines, the branch prediction/ recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to 10 stages in the P6 micro-architecture. This technology significantly increases the performance, frequency, and scalability of the processor. 400 MHZ System Bus: The Pentium4 processor supports Intel's highest performance desktop system bus by delivering 3.2 GB of data per second into and out of the processor. This is accomplished through a physical signaling scheme of quad pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium III processor's 133-MHz system bus. Level 1 Execution Trace Cache: In addition to the 8KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processor's execution units and a reduction in the overall time required to recover from branches that have been mis-predicted.
9
8575A N/B Maintenance
Rapid Execution Engine: Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in half a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processor runs at 3 GHz. 256KB, Level 2 Advanced Transfer Cache: The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughput channel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium III processor at 1 GHz. Features of the ATC include: Non-Blocking, full speed, on-die Level 2 cache 8-way set associativity 256-bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about 33% over the P6 generation processor's branch prediction capability. It does this by implementing a 4KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction algorithm.
10
8575A N/B Maintenance
Enhanced Floating-Point and Multimedia Unit: The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register for data movement which improves performance on both floating-point and multimedia applications. Internet Streaming SIMD Extensions 2 (SSE2): With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications. Features Used for Test and Performance / Thermal Monitoring: Built-in Self Test (BIST) provides single stuck-at fault coverage of the micro-code and large logic arrays, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs), and ROMs. IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Pentium 4 processor and system connections through a standard interface. Internal performance counters can be used for performance monitoring and event counting. Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to expected application power usages rather than theoretical maximums.
11
8575A N/B Maintenance
1.2.2 System Frequency
1.2.2.1 System frequency synthesizer_ICS952001
Programmable Timing Control HubTM for P4TM processor General Description : The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
12
8575A N/B Maintenance
Recommended Application: SiS645/650 style chipsets Output features: 2 - Pairs of differential CPUCLKs @ 3.3V 1 - SDRAM @ 3.3V 8 - PCI @3.3V 2 - AGP @ 3.3V 2 - ZCLKs @ 3.3V 1 - 48MHz, @3.3V fixed 1 - 24/48MHz, @3.3V selectable by I2 C 3 - REF @3.3V, 14.318MHz Key Specifications: PCI - PCI output skew: < 500ps CPU - SDRAM output skew: < 1ns AGP - AGP output skew: <150ps
13
8575A N/B Maintenance
Features/Benefits: Programmable output frequency, divider ratios, output rise/fall time, output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions Programmable watch dog safe frequency. Support I2 C Index read/write and block read/write operations For PC133 SDRAM system use the ICS9179-06 as the memory buffer. For DDR SDRAM system use the ICS93705 as the memory buffer. Uses external 14.318MHz crystal.
14
8575A N/B Maintenance
1.2.2.2 DDR buffer frequency synthesizer_ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: SiS645/650 style chipsets Product description/features: Low skew, low jitter PLL clock driver I2 C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3.3V tolerant CLK_INT input Switching Characteristics PEAK - PEAK jitter (66MHz): <120ps PEAK - PEAK jitter (>100MHz): <75ps CYCLE - CYCLE jitter (66MHz): <120ps CYCLE - CYCLE jitter (>100MHz): <65ps OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time: 650ps - 950ps DUTY CYCLE: 49.5% - 50.5%
15
8575A N/B Maintenance
1.2.3 Core Logic_SiS650 + SiS961
1.2.3.1 SiS650 IGUI Host/Memory Controller
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO. SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated ondie termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is incorporated to connect SiS650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multithreaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
16
8575A N/B Maintenance
An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB. The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to support the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.
17
8575A N/B Maintenance
Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/MCommand Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.
18
8575A N/B Maintenance
1.2.3.2 SiS961 MuTIOL® Media I/O overview
The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like PIII, K7 and P4. The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1channel Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation. Besides, 4 separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codec maximally, effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both traditional consumer digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are supported. VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital audio channel. The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supporting full duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames, Magic Packet and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated MAC provides a scheme to store the MAC address without the need of an external EEPROM. The 25 MHz oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking system.
19
8575A N/B Maintenance
The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment. The MuTIOL® Connect to PCI bridge supporting 6 PCI master is compliant to PCI 2.2 specification. The SiS961 also incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired keyboard controller and PS2 mouse interface, Real Time clock with 256B CMOS SRAM and two 8259A compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported. The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep power state for Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.
20
8575A N/B Maintenance
1.2.4 SiS301LV TV Encoder / LVDS Transmitter
General Description SiS301LV, which is an accompany chip of SiS VGA chip, integrates : A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display. A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display. All the above functions can support dual-display features. It means that the second display device driven by SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the primary VGA chip then transforms them into composite, S-Video or component video output for TV display, LVDS signals for LCD display. The output display combination can be one of the three : (1) Primary CRT+SiS301LV TV (2) Primary CRT+SiS301LV LCD (3) SiS301LV TV + SiS301LV LCD.
V ide o D e co de r
The package type of SiS301LV is 128-pin LQFP.
Fra m e B u ffe r
F ea ture C on n ector CRT M o n itor
P rim a ry VG A (S iS 65 0/ S iS 33 0 )
1st cha nne l 2 nd c hannel S iS 30 1 LV N TS C /P A L TV LC D M on ito r
21
8575A N/B Maintenance
1.2.4.1 TV-Out :
Supports PAL and NTSC Systems. Supports Composite, S-Video, and Component RGB( SCART) Output Signals Supports Macrovision Copy Protection Process Rev. 7.1.L1 Support Progressive TV 525P YPbPr Output Signals. Support Macrovision Conpy Protection Waveforms for 525p Progressive Scan Output Supports TV/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode Provides Adaptive 6-Line Anti-Flicker Filtering. Provides Hardware Interpolation for Programmable Under-Scan/Over-Scan Adjustment. Provides Programmable Display Position Adjustment. Provides Programmable Notch Filter for Cross Color Elimination. Provides Chrominance Filter for Cross Luminance Elimination. Provides Color Saturation Adjustment for Vivid TV Output. Provides Gamma Correction Independent of That of Primary VGA. Auto-Sense of TV Connection
22
8575A N/B Maintenance
1.2.4.2 LVDS
Supports LVDS Transmitter Function. Single LVDS supports pixel rate up to 110M pixel/sec. Compatible with TIA/EIA-644 LVDS standard. Provides Bi-linear Scaling to Scale VGA Low Resolution Mode up for LCD Display up to 1280x1024 Supports LCD/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode. Support 2D dither for 18-bit panels. Provides Programmable Display Centering. Compliant with VESA DDC2B Compliant with VESA Plug & Display, Hot Plugging Function. Provides Correction Independent of That of Primary VGA
23
8575A N/B Maintenance
1.2.5 PC Card Interface Controller: TI PCI1410
The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required. . The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is register compatible with the IntelE 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization.
24
8575A N/B Maintenance
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1410, such as socket activity lightemitting diode (LED) outputs, are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Features Ability to wake from D3hot and D3cold Fully compatible with the Intel 430TX (Mobile Triton II) chipset A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGAE ball grid array (GGU) package, or 209-terminal MicroStar BGAE (GHK) package 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards Single PC Card or CardBus slot with hot insertion and removal Burst transfers to maximize data throughput on the PCI bus and the CardBus bus Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts
25
8575A N/B Maintenance
1.2.5.1 Single-Slot PC Card Power Interface Switch: TPS2211A
The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOSTM process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available. End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners.
26
8575A N/B Maintenance
Features Fully Integrated VCC and Vpp Switching for Single-Slot PC CardTM Interface Low rDS(on) (70-m 5-V VCC Switch and 3.3-V VCC Switch) Compatible With Industry-Standard Controllers 3.3-V Low-Voltage Mode Meets PC Card Standards 12-V Supply Can Be Disabled Except During 12-V Flash Programming Short-Circuit and Thermal Protection Space-Saving 16-Pin SSOP (DB) Compatible With 3.3-V, 5-V, and 12-V PC Cards Break-Before-Make Switching PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association) LinBiCMO is a trademark of Texas Instruments
27
8575A N/B Maintenance
1.2.6 IEEE1394 : NEC µPD72872 OHCI-Link Layer Controller
The µPD72872 is NEC's 1-chip solution of an OHCI-LINK layer controller and a two port, physical layer implementation compliant to P1394a specification draft 2.0. It supports the connection with transmission speeds up to 400Mbps. The two-port shrink version of the µPD72870 chip with PCI/CardBus Interface offers a compact and low-cost solution for implementing applications in PC, PC-Cards as µPD72872 supports the 1394 Open Host Controller Interface 1.0 Features Link Layer compliant with 1394 Open Host Controller Interface specification release 1.0 Physical layer compliant with definition in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) Selectable active port number (1, 2 ports) Modular 32-bit host interface compliant with PCI specification release 2.1 Supports PCI Bus Power Management Interface specification release 1.1 Modular 32-bit host interface compliant with CardBus specification Cycle Master and Isochronous Resource Manager support 32-bit CRC generation and checking for receive/transmit packets Supports 4 isochronous transmit DMAs and 4 isochronous receive DMAs 2-wire Serial EEPROMTM interface supported
28
8575A N/B Maintenance
Separate power supply Link and PHY Programmable latency timer from serial EEPROMTM in CardBus mode (CARD_ON = 1) Temperature range: 0 to 70°C Operating voltage: 3.3 V ± 10%, single power supply
1.2.7 AC'97 Audio System: Advance Logic, Inc, ALC201
SiS961 is an AC'97 2.1 compliant controller that communicates with companion Codecs SiS a digital serial link called the AC-link. The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The ALC201 provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where high-quality audio is required. The ALC201 AC'97 CODEC provides a complete high quality audio solution. Features Single chip audio CODEC with high S/N ratio (>90 dB) 18-bit ADC and DAC resolution Compliant with AC'97 2.2 specification Meet performance requirements for audio on PC2001 systems
29
8575A N/B Maintenance
18-bit stereo full-duplex CODEC with independent and variable sampling rate 4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX 2 analog line-level mono input: PC_BEEP, PHONE_IN Mono output with 5-bit volume control Stereo output with 5-bit volume control 2 MIC inputs: Software selectable Power management 3D Stereo Enhancement Headphone output with 50mW/20ohm driving capability (ALC201) Line output with 50mW/20ohm driving capability (ALC201A) Headphone jack-detect function to mute LINE output Multiple CODEC extension MC'97 chained in allowed for multi-channel application External Amplifier power down capability Support S/PDIF out is fully compliant with AC'97 specification rev2.2 DC offset cancellation Power support: Digital: 3.3V Analog: 5V Standard 48-Pin LQFP Package
30
8575A N/B Maintenance
1.2.8 MDC: PCTel Modem Daughter Card PCT2303W
The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The combination of PC-TEL's well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance. PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computer's system software. It requires less power to operate and less physical space than standard modem solutions. PC-TEL's HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future. The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC'97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC'97 Interface specification Rev. 2.1.
31
8575A N/B Maintenance
The chip set is fully programmable to meet worldwide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent worldwide requirements for out-ofband energy, billing-tone immunity, lightning surges, and safety requirements. Operating System Compatibility Windows 98 /NT4.0 /Win 2K /Win XP Compatibility ITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000, 46667, 45333, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000bps 56000, 54000, 52000, 50000, 48000, 46000, 44000, 42000, 40000, 38000, 36000, 32000bps 33600,31200 bps 28800 bps 14400 bps 9600,4800 bps 2400 bps 1200 bps 300 bps 1200/75 bps
32
K56Flex ITU-T V.34Annex ITU-T V.34 ITU-T V.32bis ITU-T V.32 ITU-T V.22bis ITU-T V.22 ITU-T V.21 ITU-T V.23
8575A N/B Maintenance
ITU-T V.17 ITU-T V.29 ITU-T V.27ter Bell 212A Bell 103 Modulation 56000bps(V90&K56Flex) 33600 bps (V.34Annex) 28800 bps (V.34) 14400 bps (V.32bis) 12000 bps (V.32bis) 9600 bps (V.32bis) 7200 bps (V.32bis) 9600 bps (V.32) 4800 bps (V.32) 14400 bps (V.17) 12000 bps (V.17) 9600 bps (V.29) 7200 bps (V.29) 4800 bps (V.27ter) PCM TCM TCM TCM TCM TCM QAM TCM, QAM QAM TCM TCM QAM QAM DPSK
33
14400,12000,9600,7200 bps 9600,7200 bps 4800,2400 bps 1200 bps 300 bps
8575A N/B Maintenance
2400 bps (V.27ter) 2400 bps (V.22bis) 1200/75bps (V.23) 1200bps(V.22/Bell 212A) 300bps(V.21/Bell 103) Data Compression V.42bis, MNP5 Error Correction V.42 LAPM, MNP 2-4 DTE interface DTMF Tone Frequency
Low Group Frequency (Hz) High Group Frequency (Hz) 1209 1336 1477 1633 697 1 2 3 A 770 4 5 6 B 852 7 8 9 C 941 * 0 # D
DPS QAM FSK DPSK FSK
DTMF signal level
34
8575A N/B Maintenance
1.2.8.1 High Group 1.2.8.2 Low Group
Dialing Type Telephone Line interface Return Loss Flow Control Receive Level Transmit Level
-10+/-2dBm -12+/-2dBm
Tone or pulse dialing RJ-11 300HZ - 3400HZ >= 10db XOFF/XON or RTS/CTS -35 +/- 2dBm >-15 dBm
Specification and features subject to change without notice!
35
8575A N/B Maintenance
1.2.9 Keyboard System: H8 (3437S) Universal Keyboard Controller
CPU Two-way general register configuration Eight 16-bit registers or sixteen 8-bit registers High-speed operation Maximum clock rate: 16Mhz at 5V Available in temperature range: 0°C~70°C Include 60KB ROM and 2KB RAM 16-bit free-running timer One 16-bit free-running counter Two output-compare lines Four input capture lines 8-bit timer (2 channels) PWM timer (2 channels) I2C bus interface (one channel) Host interface (HIF) Each channel has one 8-bit up counter, two time constant registers Resolution: 1/250 Duty cycle can be set from 0 to 100% Include single master mode and slave mode 8-bit host interface port Three hosts interrupt requests (HIRQ1, 11,12) Regular and fast A20 gate output Controls a matrix-scan keyboard by providing a keyboard scan function with wake-up Interrupts and sense ports 10-bit resolution 8 channels: single or scan mode (selectable)
36
Memory
Keyboard controller A/D converter
8575A N/B Maintenance
D/A converter Interrupts Power-down modes Hardware standby mode A single chip microcomputer On-chip flash memory Maximum 64kbyte-address space Support three PS/2 port for external keyboard, mouse and internal track pad. Support SMI, SCI trigger input: Cover switch Battery charging control Smart Battery monitoring Control D/D system on/off Fan control and LED indicator serial interface 100pin TQFP 8-bit resolution 2 channels Nine external interrupt lines: NMI#, IRQ0 to 7# 26 on-chip interrupt sources Sleep mode Software standby mode
37
8575A N/B Maintenance
1.2.10 System Flash Memory (BIOS)
2 M bit Flash memory Flashed by 5V only User can upgrade the system BIOS in the future just running flash program
1.2.11 Memory System
64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg x 64 [HD]) VDD= VDDQ= +2.5V ±0.2V VDDSPD = +2.2V to +5.5V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bi-directional data strobe (DQS) transmitted/received with data--i.e.,source-synchronous data capture Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.) Four internal device banks for concurrent operation
38
8575A N/B Maintenance
Selectable burst lengths: 2, 4 or 8 Auto precharge option KBC and PS2 mouse can be individually disabled Auto Refresh and Self Refresh Modes 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Serial Presence Detect (SPD) with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold-plated edge contacts
1.2.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver The ICS1893
General Description The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100BaseTXCarrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications.
39
8575A N/B Maintenance
The ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity. The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common. Features Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5 to +85 C DSP-based baseline wander correction to virtually eliminate killer packets across temperature range from -5 to +85 C Low-power, 0.35-micron CMOS (typically 400 mW) Single 3.3-V power supply
40
8575A N/B Maintenance
Single-chip, fully integrated PHY provides PCS, PMA, PMD and AUTONEG sublayers of IEEE standard 10Base-T and 100Base-TX IEEE 802.3 compliant Fully integrated, DSP-based PMD includes: Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder Highly configurable design supports: Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface (bypasses the PCS) 10M 7-wire Serial Interface Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
41
8575A N/B Maintenance
1.3 Other Functions
1.3.1 Hot Key Functions
Keys Combination Fn + F1 Fn + F2 Fn + F3 Fn + F4 Fn + F5 Fn + F6 Fn + F7 Fn + F8 Fn + F9 Fn + F10 Fn + F11 Fn + F12 Feature Reserve Reserve Volume Down Volume Up LCD/external CRT switching Brightness down Brightness up Brightness MAX Pause Break Panel Off/On Suspend to DRAM / HDD Meaning
Rotate display mode in LCD only, CRT only, and simultaneously display. Decreases the LCD brightness Increases the LCD brightness Toggle Max Brightness
Toggle Panel on/off Force the computer into either Suspend to HDD or Suspend to DRAM mode depending on BIOS Setup.
1.3.2 Power on/off/suspend/resume button
APM mode At APM mode, Power button is on/off system power.
42
8575A N/B Maintenance
APM mode At ACPI mode. Windows power management control panel set power button behavior. You could set "standby", "power off" or "hibernate"(must enable hibernate function in power Management) to power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.3.3 Cover Switch
System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover. At ACPI mode there are four functions to be chosen at windows power management control panel. 1. 2. 3. 4. None Standby Off Hibernate (must enable hibernate function in power management)
1.3.4 Reset Switch
There is a reset switch at bottom side of notebook. It will reset embedded controller H8 and turn off system totally. When system hands up and Power button has no function, this switch is the only way to turn off system without remove power source.
43
8575A N/B Maintenance
1.3.5 LED Indicators
System has eight status LED indicators to display system activity, which include three at front side and five above keyboard. 1) Three LED indicators at front side: From left to right that indicates: AC Power, Battery Power and Battery Status AC Power: This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by batteries. Battery Power: This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the notebook is off or powered by batteries, or when Suspend to Disk. Battery Status: During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged. 2) Five LED indicators above keyboard: From left to right that indicates LAN, CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK and SCROLL LOCK.
44
8575A N/B Maintenance
1.3.6 Battery Status
Battery Warning System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead. Also, this function protects system from mal-function while battery capacity is low. Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds. System will suspend to HDD after 2 Minutes to protect users data. Battery Low State After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second. Battery Dead State When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life.
1.3.7 Fan power on/off management
FAN is controlled by H8 embedded controller-using AD2201 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.
45
8575A N/B Maintenance
1.3.8 CMOS Battery
CR2032 3V 220mAh lithium battery When AC in or system main battery inside, CMOS battery will consume no power. AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years. Battery was put in battery holder, can be replaced.
1.3.9 I/O Port
One Power Supply Jack. One External CRT Connector For CRT Display Supports two USB port for all USB devices. One MODEM RJ-11 phone jack for PSTN line One RJ-45 for LAN. Headphone Out Jack. Microphone Input Jack. Line in Jack One Card Bus Sockets for one type II PC card extension
1.3.10 Battery current limit and learning
Implanted H/W current limit and battery learning circuit to enhance protection of battery.
46
8575A N/B Maintenance
1.4 Peripheral Components
1.4.1 LCD Panel
LCD 14.1 Hyundai HT14X12-100A
1.4.2 Ext.Floppy Disk Drive
Mitsumi D353GU External USB 3.5" 1.44MB /1.2 MB/720KB FDD (Option)
1.4.3 HDD
Hitachi 30GB Height: 9.5 mm, 2.5"
1.4.4 24X CD-ROM Drive
TEAC
47
8575A N/B Maintenance
1.4.5 8W/4R CD-RW
KEM Height: 12.7 mm IDE I/F
1.4.6 Keyboard
Windows 98 Keyboard, 1 color, multi languages support JP, US and Europe Keyboard with " Volume UP " and " Volume Down " word.
1.4.7 Track Pad Synaptics
Accurate positioning Low fatigue pointing action Low profile No moving part, high reliability Low power consumption Environmentally sealed Compact size. Software configurable Low weight Operating temperature: 0 to 60 degree C
48
8575A N/B Maintenance
Operating humidity: 5%-95% relative humidity, non condensing Storage temperature: -40 to +65 degree C ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01 Power supply voltage: 5.0Voltage ± 10% Power supply current: 4.0mA max operating
1.4.8 Fan
HY45J05-001
1.4.9 Memory
DDR-RAM/ATP//128M/256M DDR-RAM/Apacer//128M/256M DDR-RAM/Unidorsa//128M/256M
1.4.10 Modem MDC
Askey
49
8575A N/B Maintenance
1.5 System Management
The 8575A system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.
1.5.1 System Management Mode
Full on mode In this mode, each device is running with the maximal speed. CPU clock is up to its maximum. Doze Mode In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode. Standby mode For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device: CPU: Stop grant LCD: backlight off HDD: spin down
50
8575A N/B Maintenance
Suspend to DRAM The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device: Suspend to DRAM: CPU: off Twister K: Partial off VGA: Suspend PCMCIA: Suspend Audio: off SDRAM: self refresh Suspend to HDD: All devices are stopped clock and power-down System status is saved in HDD All system status will be restored when powered on again
1.5.2 Other Power Management Functions
HDD & Video access System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.
51
8575A N/B Maintenance
1.6 Appendix 1: SiS961 GPIO Definitions
SB_SiS961 GPIO
Signal Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 RING# AC_SDIN2 LDRQ1# THERM# EXTSMI# CLKRUN# PREQ5# PGNT5# MUX Function Mitac Definition MB_ID0 CD_IN# SB_THRM# EXTSMI# CLKRUN# LCD_ID0 LCD_ID1 LCD_ID2 WAKEUP# SCI# CRT_IN# SPK_OFF CPU_STP# MPCIACT# /DPRSLPVR CD_PWRON# VR_HILO# LO_HI# VGATEM# CD_RST SMBCLK SMBDATA Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OD I/O O O O Power Plane Main Main Main Main Main Main Main AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX During Tolerant PCISRT# After PCISRT# S1 S3 Off Off Off Off Off Off Off S4/S5 Off Off Off Off Off Off Off
Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
GPIO10 AC_SDIN3 GPIO11 GPIO12 CPUSTP# GPIO13 DPRSLPVR GPIO14 GPIO15 VR_HILO# GPIO16 LO_HI# GPIO17 VGATEM# GPIO18 PMCLK GPIO19 SMBCLK GPIO20 SMBDATA
Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
52
8575A N/B Maintenance
1.7 Appendix 2: H8 Pins Definitions
The shadowed block is the selected function
Name Pin H8 Pin Definitions H8_MODE0 H8_MODE1 STBY# POWER BTN# RESET# Crystal Crystal RESET OUT During RESET I I I I I I I O After RESET/OFF I I I I I I I O H H H H LH ON STANDBY Function
MD0 MD1 STBY# NMI# RESET# XTAL EXTAL RESET OUT#
6 5 8 7 1 2 3 100
I I I I I I I O
H H H HL H H
I I I I I I I O
H H H H H
H H mode3 single chip mode H8 Hardware Standby input pull high Power button H8 chip reset Crystal input
Port A COMOS input level (input high min=3.5V, input low max=1.0V) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 48 47 31 30 21 20 11 10 LID# H8 ADEN# RI# BATT DEAD# H8 SUSC H8 SUSC# BAT_CLK H8_SUSB I I I I I I I I I I I I I I I I H H/L H H H L L H I I I I I I I I L I I I I I I I I H H/L H H L H H H Invert from SUSA# to wake up H8 when system resumed by MDC modem and internal LAN. Inform system power management status AC adaptor in detect Ring detect Battery low detect System resume from S4 soft off through RTC Alarm System to S4 soft off
53
8575A N/B Maintenance
PCI reset gate
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function
Port B TTL input voltage (input high min=2V, input low max=0.8V) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB6 PB7 91 10 81 80 69 68 58 57 58 57 H8 SB PWRBTN# H8 WAKE# Force Discharge CHARGING1 VDD5 SW H8 RCIN# CHARGING2 SMbus SW VADJ1 VADJ2 T T T T T T T T T T O O O O O O O O O O LLH L O O O O O O O H LH L H IHL O O O O O O O O O O O Keep H Keep H Keep H Keep Keep H Keep H Keep Keep Keep Keep Lithium ion battery charging CV mode voltage level adjust Power button trigger VIA8231 on/off Duplicate Power BTN# 53V Wake up SB at ACPI mode 53V
Power button trigger VIA8231 on 53V Battery charge control H8 VDD5 power source switch Reset CPU Battery charge control
Port 1 TTL input voltage (input high min=2V, input low max=0.8V) P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 79 78 77 76 75 74 73 72 KB OUT0 KB OUT1 KB OUT2 KB OUT3 KB OUT4 KB OUT5 KB OUT6 KB OUT7 L L L L L L L L O O O O O O O O L L L L L L L L O O O O O O O O LH LH LH LH LH LH LH LH O O O O O O O O Keep L Keep L Keep L Keep L Keep L Keep L Keep L Keep L Key matrix scan output 0 Key matrix scan output 1 Key matrix scan output 2 Key matrix scan output 3 Key matrix scan output 4 Key matrix scan output 5 Key matrix scan output 6 Key matrix scan output 7
54
8575A N/B Maintenance
Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function
Port 2 TTL input voltage (input high min=2V, input low max=0.8V) P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 67 66 65 64 63 62 61 60 KB OUT8 KB OUT9 KB OUT10 KB OUT11 KB OUT12 KB OUT13 KB OUT14 KB OUT15 L L L L L L L L O O O O O O O O L L L 0 0 0 0 0 O O O O O O O O LH LH LH LH LH LH LH LH O O O O O O O O Keep L Keep L Keep L Keep L Keep L Keep L Keep L Keep L Key matrix scan output 8 Key matrix scan output 9 Key matrix scan output 10 Key matrix scan output 11 Key matrix scan output 12 Key matrix scan output 13 Key matrix scan output 14 Key matrix scan output 15
Port 3 TTL input voltage (input high min=2V, input low max=0.8V) P30/HDB0/D0 P31/HDB1/D1 P32/HDB2/D2 P33/HDB3/D3 P34/HDB4/D4 P35/HDB5/D5 P36/HDB6/D6 P37/HDB7/D7 82 83 84 85 86 87 88 89 ISA SD0 ISA SD1 ISA SD2 ISA SD3 ISA SD4 ISA SD5 ISA SD6 ISA SD7 T T T T T T T T I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Keep Keep Keep Keep Keep Keep Keep Keep ISA DATA bit 0 ISA DATA bit 1 ISA DATA bit 2 ISA DATA bit 3 ISA DATA bit 4 ISA DATA bit 5 ISA DATA bit 6 ISA DATA bit 7
55
8575A N/B Maintenance
Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function
Port 4 TTL input voltage (input high min=2V, input low max=0.8V) P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ1 P44/TMCO1/HIRQ1 P45/TMRI1/HIRQ1 P46/PWM0 P46/PWM0 P47/PWM1 49 50 51 52 53 54 55 55 56 H8 PWR ON H8 THRM# SCI#/ FAN SPD SW H8 SCI/ FAN SPEED ISA IRQ1 ISA IRQ12 Beep sound FAN ON#0 FAN ON#1 T T T T T T T T T O O O O O O O O O 1 1 0 0 L L H O O O O O O O O LH H O O O O O O O O O Keep Keep H Keep Keep Keep Keep Keep Keep Keep System power on, need pull down to define initial state during reset Thermal throttling control to Southbridge SCI output and Fan Speed Tachometer Switch Need invert to SCI# sending to SB 53V/ Fan speed tachometer Keyboard IRQ1 PS2 mouse IRQ12 Hot key and battery dead beep sound Fan power PWM control Fan power PWM control
Port 5 TTL input voltage (input high min=2V, input low max=0.8V) P50/TXD0 P51/RXD0 P52/SCK0 14 13 12 LED DATA H8 SMI# LED CLK T T T O O O O O O O O O Keep Keep Keep LED indicator shift data External SMI# 53V
LED indicator shift clock
56
8575A N/B Maintenance
Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function
Port 6 Schmitt trigger input voltage (min=1.0V max=3.5V) P60/KEYIN0/FTCI P61/KEYIN1/FTOA P62/KEYIN2/FTIA P63/KEYIN3/FTIB P64/KEYIN4/FTIC P65/KEYIN5/FTID P66/KEYIN6/IRQ6 P67/KEYIN7/IRQ7 26 27 28 29 32 33 34 35 KEY IN0 KEY IN1 KEY IN2 KEY IN3 KEY IN4 KEY IN5 KEY IN6 KEY IN7 T T T T T T T T I I I I I I I I I I I I I I I I I I I I I I I I Keep Keep H Keep Keep Keep Keep Keep Keep Key matrix input 0 need pull high Key matrix input 1 need pull high Key matrix input 2 need pull high Key matrix input 3 need pull high Key matrix input 4 need pull high Key matrix input 5 need pull high Key matrix input 6 need pull high Key matrix input 7 need pull high
Port 7 TTL input voltage (input high min=2V, input low max=0.8V) P70/AN0 P71/AN1 P71/AN1 P72/AN2 P73/AN3 P73/AN3 P74/AN4 P75/AN5 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 38 39 39 40 41 41 42 43 43 44 45 BAT VOLT1 BAT VOLT2 I_LIMIT 3V/PWR ok 2.5V LI/NIMH# BAT TEMP1 BAT TEMP2 VCC CORE Charge-I_CTR BL ADJ T T T T T T T T T T T I I I I I I I I I O O I I I I I I I I I O O I I I I I I I I I O O T T T T T Keep T T T T T Charging current adjust Backlight inverter brightness adjust To differential 3S3P lithium ion battery and 9S NiMH battery Battery thermister temperature Battery thermister temperature Monitor system on/off state Battery voltage measure Battery voltage