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MDX-65
SERVICE MANUAL
US Model Canadian Model AEP Model UK Model E Model
Dolby noise reduction extension manufactured under license from Dolby Laboratories Licensing Corporation. "DOLBY" and the double-D symbol a are trademarks of Dolby Laboratories Licensing Corporation.
Model Name Using Similar Mechanism Mini Disc Mechanism Type Optical Pick-up Name
MDX-62 MG-798K-133 KMS-241A/J2N
SPECIFICATIONS
System Mini disc digital audio system Laser Diode Properties Material: GaAlAs Wavelength: 780 nm Emission Duration: Continuous Laser output Power: Less than 44.6 µW* * This output is the value measured at a distance of 200 mm from the objective lens surface on the Optical Pick-up Block. Frequency response 10 20,000 Hz Wow and flutter Below measurable limit Signal-to-noise ratio 95 dB Outputs Bus control output (8 PIN) Analog audio output (RCA PIN) Current drain 300 mA (MD playback) 600 mA (during loading or ejecting a disc) Dimensions Approx. 176 × 83.5 × 142 mm (7 × 3 3/8 × 5 18/32 in.) (w/h/d) not incl. projecting parts and controls Mass Approx. 1.1 kg (2 lb. 7 oz.) Power requirement 12 V DC car battery (negative ground) Supplied accessories Mounting hardware (1 set) Bus cable 5.5 m (1) RCA pin cord 5.5 m (1) · U.S. and foreign patents licensed from Dolby Laboratories Licensing Corporation. · Design and specifications subject to change without notice.
FEATURES
· Sony BUS system compatible with mobile MD changers. · Direct-in system for inserting and removing MDs easily. · No waiting time to change discs in continuous play. · The MD changer compartment has a built in light for easy use even in the dark. · 1 bit Digital/Analog converter for high quality sound reproduction.
MINIDISC CHANGER
MICROFILM
1
SECTION 4 DIAGRAMS
4-1. IC PIN DESCRIPTIONS
· IC100 CXA2523AR (RF AMP) Pin No. Pin Name 1 I 2 3 49 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 J VC AF PD APC APCREF GND TEMPI TEMPR SWDT SCLK XLAT XSTBY FOCNT VREF EQADJ 3TADJ VCC WBLADJ TE CSLED SE ADFM ADIN ADAGC ADFG AUX FE ABCD BOTM PEAK RF RFAGC AGCI COMPO COMPP ADDC OPO OPN RFO MORFI MORFO I/O I I O I I O I -- I O I I I I I O I I -- I O I O O I I O O O O O O O I I O I I O I O I O Pin Description I-V converted RF signal input (I) from detector of optical pick-up. I-V converted RF signal input (J) from detector of optical pick-up. Center voltage (+1.65 V) generation output Signal input (A to F) from detector of optical pick-up. Quantity monitor input of light from laser diode of optical pick-up. Laser amplifier output to automatic power control circuit. Reference voltage input for laser power setting. GND Temperature sensor connecting pin (Not used in this set.) Reference voltage output for temperature sensor. (Not used in this set.) Write data signal input from System controller (IC600). Serial clock signal input from System controller (IC600). Serial latch signal input from System controller (IC600). Standby signal input ("L" : Standby) (Fixed at "H" in this set.) Center frequency control voltage input of internal circuit filter (BPF22, BPF3T and EQ). Reference voltage output (Not used in this set.) Center frequency setting input of internal circuit filter (EQ). Center frequency setting input of internal circuit filter (BPF3T). Power supply pin (+3.3 V) Center frequency setting input of internal circuit filter (BPF22). Tracking error signal output to CXD2652AR (IC200). Connecting pin for low pass filter condenser of sled error signal. Sled error signal output to CXD2652AR (IC200). FM signal output of ADIP. FM signal input of ADIP by AC combination. External condenser connecting pin for AGC of ADIP. ADIP double FM signal output (22.05 kHz ± 1 kHz) to CXD2652AR (IC200). Support signal (I3 signal/temperature signal) output (Not used in this set.) Focus error signal output to CXD2652AR (IC200). Quantity signal output of light to CXD2652AR (IC200). Bottom hold signal output of quantity signal (RF/ABCD) of light to CXD2652AR (IC200). Peak hold signal output of quantity signal (RF/ABCD) of light to CXD2652AR (IC200). Playback EFM RF signal output to CXD2652AR (IC200). External condenser connecting pin of AGC circuit for RF. RF signal input by AC combination. User comparator output pin (Not used in this set.) User comparator input pin (Fixed at "L" in this set.) External condenser connecting pin for low frequency interception of ADIP amplifier. External condenser connect pin for lower cut of ADIP amplifier. User operational amplifier inversion input pin (Fixed at "L" in this set.) RF signal output RF signal input of MO by AC combination. RF signal output of MO.
11
· IC600 µPD784216GC-027-8EU (SYSTEM CONTROLLER) Pin No. Pin Name I/O Pin Description 1 M1 O Elevator motor (M904) drive signal output 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28, 29 30 32 33 34 35 36 37, 38 39 40 41 42 43 44 45 46 47 48 49 50 51, 52 53 55 56 59 60 61 62 M1 M2 M2 MDMON LES SES HOME VDD X2 X1 VSS XT2 XT1 RESET BU IN BUS ON SQ SY STR SW -- CC XINT -- AVDD AVREF0 INIT TEMP EHS -- -- AVSS ERR PWM -- AVREF1 -- -- MD SI MD SO MD CKO -- -- UNISI UNISO UNI CKI LINKOFF -- -- D-BASS1, 2 -- MNT0 3 AGING AGCHK TFTON O O O O I I I -- -- -- -- -- -- -- I I I I O I O -- -- I I I I O -- O O -- O -- I O O O -- I O I O O I O O O O O O Elevator motor (M904) drive signal output Loading motor (M903) drive signal output Loading motor (M903) drive signal output Mechanism deck system power control output ("H" : Power ON) Loading end sensor detection switch (S902) input Store end sensor detection switch (S903) input Home position detection switch (S901) input ("L" : Home position) Power supply pin (+5 V) Main system clock connecting pin (14 MHz) Main system clock connecting pin (14 MHz) GND Sub system clock connecting pin (32.768 kHz) Sub system clock connecting pin (32.768 kHz) System reset input Backup OFF detection input ("L" : Backup OFF) BUS OFF detection of SONY BUS. ("H" : BUS OFF) Sub code Q sync input from CXD2652AR (IC200). STOP switch (S600) input Not used. Interruption status input from CXD2652AR (IC200). Not used. Power supply for A/D converter. (+5 V) Reference voltage for A/D converter. Initial input pin at reset. Thermistor connecting pin for temperature detection. Elevator height position detection input Connect to GND. Connect to GND. Analog GND Error data output (Not used in this set.) Not used. Reference voltage for D/A converter. Not used. Not used. Read data signal input from CXD2652AR (IC200). Write data signal output to CXA2523AR (IC100) and CXD2652AR (IC200). Serial clock signal output to CXA2523AR (IC100) and CXD2652AR (IC200). Not used. Not used. Serial data input for SONY BUS. Serial data output for SONY BUS. Serial clock input for SONY BUS. Link control signal output for SONY BUS. ("H" : Link OFF) Not used. Not used. Digital D-BASS select output 1, 2 (Not used in this set.) Not used. Monitor 0 3 signal input from CXD2652AR (IC200). Not used. Not used. Not used.
12
Pin No. 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 85 86 93 94 95 96 97 98 99 100
Pin Name -- EE CS EE CKO EE SIO SENS LIMIT SW DOORSW MD LAT MD RST VSS MD ON EMPH O A ATT ILLON TSTSMD TSTCKO TSTSO TSTMOD VDD TSTOUT0 3 TSTIN0 7 TEST/VPP DCS1 DCS2 DCS3 DCS4 DCS5 DCS6
I/O O O O I/O I I I O O -- O O I O I O O I -- O I -- I I I I I I
Pin Description Not used. Chip select output to EEPROM. (Not used in this set.) Serial clock output to EEPROM. (Not used in this set.) Data input from/output to EEPROM. (Not used in this set.) Internal status input from CXD2652AR (IC200). Optical pick-up innermost track limit position detection switch (S400) input Front door open detection switch (S620) input ("L" : Open complete) Serial latch signal output to CXA2523AR (IC100) and CXD2652AR (IC200). Reset signal output to CXD2652AR (IC200). GND Servo system power control output ("H" : Power ON) De-emphasis circuit control output ("H" : De-emphasis ON) Analog mute control input ("H" : Mute ON) Illumination lamp (PL620) light-up control output ("H" : Lamp light-up) Single mode setting pin ("L" : Single mode) Serial clock output to LED for TEST mode display. (Not used in this set.) Serial data output to LED for TEST mode display. (Not used in this set.) TEST mode setting pin ("L" : TEST mode) Power supply pin (+5 V) TEST key output pin of 4 × 8 matrix. (Not used in this set.) TEST key input pin of 4 × 8 matrix. (Not used in this set.) Fixed at "L" in this set. Disc with/without detection 1 switch (S611) input ("H" : with disc) Disc with/without detection 2 switch (S612) input ("H" : with disc) Disc with/without detection 3 switch (S613) input ("H" : with disc) Disc with/without detection 4 switch (S614) input ("H" : with disc) Disc with/without detection 5 switch (S615) input ("H" : with disc) Disc with/without detection 6 switch (S616) input ("H" : with disc)
13
MDX-65
4-5. SCHEMATIC DIAGRAM -- SERVO SECTION -- · Refer to page 33 for Waveforms and page 35 for IC Block Diagrams.
21
22
(Page 23)
MDX-65
4-6. SCHEMATIC DIAGRAM -- MAIN SECTION -- · Refer to page 34 for Waveforms and page 37 for IC Block Diagrams.
(Page 22)
23
24
(Page 32)
MDX-65
4-9. SCHEMATIC DIAGRAM -- POWER SECTION -- · Refer to page 37 for IC Block Diagrams.
(Page 24)
31
32
· Waveforms
Servo Section 1 IC100 4 (A) PLAY MODE 200 mV/DIV, 10 µsec/DIV 5 IC100 #· (RF) PLAY MODE 500 mV/DIV, 1 µsec/DIV 9 IC200 @§ (XBCK) Main Section 1 IC600 !º (X2) 5 IC500 1 (XT1)
Approx. 150 mVp-p
Approx. 1.1 Vp-p
3.2 Vp-p
2.7 Vp-p
3.2 Vp-p
354 ns
2 IC100 8 (E) PLAY MODE 100 mV/DIV, 10 µsec/DIV 6 IC100 #¢, IC200 ^ (FE) PLAY MODE 200 mV/DIV, 0.5 msec/DIV !º IC200 !§ (OSCI)
71 ns 2 IC600 !¢ (XT1)
89 ns
Approx. 150 mVp-p
400 mVp-p
2.8 Vp-p
2.6 Vp-p
44.3 ns 3 IC100 9 (F) PLAY MODE 100 mV/DIV, 10 µsec/DIV 7 IC100 @§, IC200 &¢ (TE) PLAY MODE 500 mV/DIV, 0.5 msec/DIV
30.4 µs
3 IC500 4 (LRCK)
Approx. 150 mVp-p
2.8 Vp-p
2.0 Vp-p
22.7 µs
4 IC100 1, 2 (I, J) PLAY MODE 100 mV/DIV, 10 µsec/DIV 8 IC200 @ (LRCK) 4 IC500 6 (BCK)
3.2 Vp-p
150 mVp-p
2.8 Vp-p
22.7 µs
354 ns
33
34
· IC Block Diagrams Servo Section
IC100 CXA2523AR
COMPO
COMPP
MORFO
RF AGC
MORFI
ADDC
48
47
46
45 + USROP
44
43 42 + BPF3T
41
40 RF AGC
39
38 EQ
37
+
RFA1
USRC DET EQ AUX SW
RFA2 I J 1 2 1 2 OFST 1 2 GRV GRVA 2 1 HLPT 1 2
RFA3 3T
PEAK3T P-P WBL PEAK BOTTOM WBL PBH
PTGR
3T
TEMP 36 BOTM
VC
3
A
4 IVR
B
5 IVR
C
6 IVR
D
7 IVR
E
8 IVR
F
9 IVR
GSW PD 10 + + APC 11 APCREF 12 13
GND
TEMPI
SWDT
F0CNT
VREF
EQADJ
TEMPR
XSTBY
3TADJ
SCLK
35
XLAT
VCC
+
CVB
PBSW
PEAK
AGCI
OPN
OPO
RFO
RF
35 ABCD 34 FE 33 AUX BPFC 32 ADFG
+
AA
ABCDA
+
31 ADAGC BB + + 30 ADIN FEA
+
CC BPF22 + + DD WBL WBL ATA ADIP AGC
DET
29 ADFM
+
1 PTGR 2 SEA
TG
28 SE 27 CSLED
+
EE
+ EBAL
EE' EFB ESW
+ + TESW
1 2 TEA
TG
26 TE
+ IV
FF
+ FBAL
FF'
WBL 3T EQ VI CONV 25 WBLADJ
AUXSW COMMAND
BGR VREF
SCRI - PARA DECODE
14
15
16
17
18
19
20
21
22 23
24
IC200 CXD2652AR
APCREF F0CNT TEST3 TEST2 TEST1 SRDR DVDD DCHG SPRD EFMO TRDR LDDR DVSS FRDR SFDR ADFG CKRF SPFD DTRF TFDR XLRF FFDR FGIN APC FS4
100 99 98 97 96 95
94 93
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
AUTO SEQUENCER
MNT0 1 MNT1 2 MNT2 3 MNT3 4 MONITOR CONTROL EACH BLOCK
SPINDLE SERVO
PWM GENERATOR
75 AUX2 74 TE 73 SE 72 AVSS 71 ADRB
ADIP DECODER SWDT 5 SCLK 6 XLAT 7 SRDT 8 SENS 9 XRST 10 SQSY 11 DQSY 12 RECP 13 SUBCODE PROCESSOR CPU I/F EACH BLOCK SERVO DSP A/D CONVERTER ANALOG MUX
70 ADRT 69 AVDD 68 ADIO 67 VC 66 AUX1 65 FE 64 ABCD 63 BOTM 62 PEAK 61 CLTV
PLL
60 FILO 59 FILI 58 PCO 57 PDO 56 AVSS
XINT 14 TX 15 OSCI 16 OSCO 17 XTSL 18 NC 19 DVSS 20 DIN 21 DOUT 22 CLOCK GENERATOR EACH BLOCK
SHOCK RESISTANT MEMORY CONTROLLER
EFM/ACIRC ENCODER/ DECODER
DIGITAL AUDIO I/F
SAMPLING RATE CONVERTER
COMP
55 RFI 54 BIAS 53 AVDD 52 ASYI 51 ASYO
ADDT 23 DADT 24 LRCK 25
ATRAC ENCODER/DECODER
ADDRESS/DATA BUS A00 - A11, D0 - D3
26 27 28
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
50
DVDD
XBCK
DVSS
XCAS
FS256
XRAS
IC300 MPC17A38ZVMEL
PGND PGND PGND GND PS OE F/R4 PI4 RO3 VD RO4 RI3 FI3 VD FO3 FO4 VD VG
36
35 34 33
32 31 30 29
28 27
26 25 24
MVCI
XWE
XOE
D1
D0
D2
A03
A02
A01 A00
A10
A04
A05
A06
A07
A08
A11
A09
D3
23
22 21
20 19
DC/DC CONVERTER VC CLOCK VC CLK DETECTOR VC
DRIVER
DRIVER
DRIVER
DRIVER
PRE-DRIVER VC
PRE-DRIVER VC
PRE-DRIVER VC
PRE-DRIVER
CONTROL VC
CONTROL VC
CONTROL VC
CONTROL
VC 1
LG
2 3 4
VC CLK GND
5 6 7 8 9 10
RI1 FI1 VD FO1 PGND PGND
11
RO1
12 13 14
VD RO2 PGND
15 16 17 18
FO2 VD FI2 RI2
36
Main Section IC500 PCM1718E-T1 IC700, 701 LB1638MTP-T1
GND 1 10 N.C.
XTI 1 DGND 2 VDD 3 LRCIN 4 DIN 5 BCKIN 6 ZERO 7
CLK CONTROL INPUT INTERFACE MODE CONTROL DIGITAL FILTER
20 XTO 19 CLKO 18 17 16 15 14 MUTE DM1 DM0 RSTB FORMAT
IN1 2
CONTROL LOGIC
9 OUT1 8 VS 7 OUT2
VCC 3 IN2 4 GND 5
NOISE SHAPER 5 LEVEL DAC LOWPASS FILTER 5 LEVEL DAC LOWPASS FILTER CMOS AMP 13 D/C L 12 VOUTL 11 VCC
6 N.C.
D/C R 8 VOUTR 9 AGND 10
CMOS AMP
Power Section IC900 BA8272F-E2
DATA OUT LINK OFF CLK OUT DATA IN BUS ON
IC970 TL5001CPS-E20
FEED BACK
RESET
VCC
INPUT
14
13
12
11
10
9
8
4
3
2
RESET SWITCH
U.V.L.O REFERENCE VOLTAGE + OSC + S.C.P. COMPARATOR 1 SWITCH 'ON' AT 'H' DEAD-TIME COMPARATOR +
1
2
3
4
5
6
7
BUS CLK
BUS ON OUT
VREF
BUS DATA
BUS RESET
BUS ON IN
GND
ERROR AMP
+ PWM COMPARATOR + S.C.P. LATCH
S.C.P. COMPARATOR 2 5 6 7 8
DEAD-TIME CONTROL
SCP
RT
37
GND
OUT
1
VCC