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UOCIII-N1D series
Rev. 2.7 -- 14 July 2004
Versatile signal processor for low- and mid-range TV applications
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Preliminary data sheet
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1. General description
Digital video processing circuit
The UOCIII series consists of the following 3 basic concepts:
· Stereo versions. These versions contain the TV processor with a stereo audio
· AV stereo versions. These versions contain the TV processor with stereo audio
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1. 2.
The QIP90 package is developed to cope with low-cost 1 layer printed circuit boards with through-hole application. Both standard and "face down" versions of the QIP90 and QFP128 0.8mm pitch package are available.
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selector and the TCG µ-Controller. Options are the digital sound processing circuit, the digital video processing circuit, the adaptive digital PAL/NTSC comb filter and a teletext decoder with a 10 page text memory. mono audio signals and the TCG µ-Controller. Options are the adaptive digital PAL/NTSC combfilter and a teletext decoder with 10 page text memory.
· Mono sound versions. These versions contain the TV processor with a selector for
The most important features of the complete IC series are given in the following feature lists. The exact feature content of the various ICs is given in the Tables 2, 3 and 4. The ICs are mounted in a QFP-128 and a QIP901 package2 and can be used in economy television receivers with 90° and 110° picture tubes. Both packages are according to the ROHS legislation, which also means that these packages are lead-free. The ICs have supply voltages of 5V, 3.3V. Also an 1.8V supply is needed, but this can be simply derived by adding an emitter follower at a reference voltage from the device. UOCIII is supported by a comprehensive Global TV Software Development kit to enable easy programming and fast time-to-market (see also Section 21 "Licenses").
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selector, the TCG µ-Controller, the multi-standard stereo or BTSC decoder, the digital sound processing circuit and the digital video processing circuit. Options are the adaptive digital PAL/NTSC comb filter and a teletext decoder with 10 page text memory.
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Adaptive digital (4H/2H) PAL/NTSC combfilter Teletext decoder with 10 page text memory Multi-standard stereo decoder BTSC stereo decoder Digital sound processing circuit
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The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed Caption decoder. In addition the following functions can be added:
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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2. Features
2.1 Analogue Video Processing (all versions)
s Multi-standard vision IF circuit with alignment-free PLL demodulator s Internal (switchable) time-constant for the IF-AGC circuit s Switchable group delay correction and sound trap (with switchable centre frequency) for the demodulated CVBS signal s DVB/VSB IF circuit for preprocessing of digital TV signals. s Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as Y-input for Y/C signals. However, only 2 Y/C sources can be selected because the circuit has 2 chroma inputs. It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the YUV interface and the RGB/YPBPR input are not needed. The QIP90 versions have only 2 CVBS inputs, one chroma input and no YUV interface. s Automatic Y/C signal detector s Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the chrominance signal. s Integrated luminance delay line with adjustable delay time s Picture improvement features with peaking (with switchable centre frequency, depeaking, variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone control, gamma control and blue- and black stretching. All features are available for CVBS, Y/C and RGB/YPBPR signals. s Switchable DC transfer ratio for the luminance signal s Only one reference (24.576 MHz) crystal required for the TCG µ-Controller, digital sound processor, Teletext- and the colour decoder s Multi-standard colour decoder with automatic search system and various "forced mode" possibilities s Internal base-band delay line s Indication of the Signal-to-Noise ratio of the incoming CVBS signal s Linear RGB/YPBPR input with fast insertion. s YUV interface. When this feature is not required some pins can be used as additional RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input (CVBS/YX and CX). The QIP90 version has no YUV interface. s Tint control for external RGB/YPBPR signals s Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages. s RGB control circuit with `Continuous Cathode Calibration', white point and black level off-set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. s Contrast reduction possibility during mixed-mode of OSD and Text signals s Adjustable `wide blanking' of the RGB outputs s Horizontal synchronization with two control loops and alignment-free horizontal oscillator s Vertical count-down circuit s Vertical driver optimized for DC-coupled vertical output stages
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Preliminary data sheet
Rev. 2.7-- 14 July 2004
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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s Horizontal and vertical geometry processing with horizontal parallelogram and bow correction and horizontal and vertical zoom s Low-power start-up of the horizontal drive circuit
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2.2 Analogue video processing
2.2.1 Stereo versions
2.2.2 Mono versions
s The low-pass filtered `mixed down' I signal is available via a single ended output stage
2.3 Digital Video Processing (some versions)
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s Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation. s AM demodulator without extra reference circuit s The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this demodulator is optional for special applications. Normally the FM demodulators of the stereo demodulator/decoder part are used (see below). s The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second sound channel can be demodulated. In such an application it is necessary that an external bandpass filter is inserted. s The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be demodulated. For the QIP90 versions this is valid only for the "stereo" versions s Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF). For the QIP90 versions this is valid only for the "stereo" versions
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2.5 Audio Interfaces and switching
2.5.1 Stereo versions with audio DSP
s Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R channel. Finally 1 stereo SPEAKER output with digital controls. The QIP90 versions have 3 stereo inputs. s AVL (Automatic Volume Levelling) circuit for the headphone channel. s Digital input crossbar switch for all digital signal sources and destinations
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Preliminary data sheet
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2.4 Sound Demodulation (all versions)
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s Double Window mode applications. It is possible to display a video and a text window or 2 text windows in parallel. s Linear and non-linear horizontal scaling of the video signal to be displayed.
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s The low-pass filtered `mixed down' I signal is available via a single ended or balanced output stage. The QIP90 versions have only a single ended output.
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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s Digital output crossbar for exchange of channel processing functionality s Digital audio input interface (stereo I2S input interface), not for QIP90 versions s Digital audio output interface (stereo I2S output interface), not for QIP90 versions
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2.5.2 AV stereo versions without audio DSP
s Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo SPEAKER output with independent L&R analogue volume control. s Analogue mono AVL circuit at left audio channel
s Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output s AVL circuit
2.6 Stereo Demodulator and Decoder (full stereo versions)
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2.7 Audio Multi Channel Decoder (versions with Audio DSP)
s Dolby® Pro Logic® (DPL) 3 s Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit this feature an external DAC is required.
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Dolby is a trademark of Dolby Laboratories
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Preliminary data sheet
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Demodulator and Decoder Easy Programming (DDEP) Auto standard detection (ASD) Static Standard Selection (SSS) DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation NICAM decoding (B/G, I, D/K and L standard) Two-carrier multistandard FM demodulation (B/G, D/K and M standard) Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound Adaptive de-emphasis for satellite FM Optional AM demodulation for system L, simultaneously with NICAM Identification A2 systems (B/G, D/K and M standard) with different identification time constants FM pilot carrier present detector Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option BTSC MPX decoder SAP decoder digital dbx® noise reduction 6 Japan (EIAJ) decoder FM radio decoder Soft-mute for DEMDEC outputs DEC, MONO and SAP FM overmodulation adaptation option to avoid clipping and distortion
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2.5.3 Mono versions
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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2.8 Volume and tone control for loudspeakers (versions with Audio DSP)
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2.9 Reflection and delay for loudspeaker channels (versions with Audio DSP)
2.11 RDS/RBDS (For QIP90 versions only possible with external FM demodulator)
s Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data System (RBDS) signal s RDS and RBDS block detection s Error detection and correction s Fast block synchronisation s Synchronisation control (flywheel) s Mode control for RDS/RBDS processing s Different RDS/RBDS block information output modes
4. 5. 6. 7. 8.
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Also referred to as "Dynamic Bass Enhancement" Also referred to as "Dynamic Ultra Bass-II" For the use of these products a licence is required. More details are given in Section 21 "Licenses", Section 22 "Patents" and Section 23 "Trademarks" Also referred to as "I-Mono" or "Incredible Mono" Also referred to as "I-Stereo" or "Incredible Stereo"
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
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Extended Pseudo Stereo (EPS) 7 Extended Spatial Stereo (ESS) 8 Virtual Dolby® Surround (VDS 422,423) 3 SRS 3D and SRS TruSurround® 6
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2.10 Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (versions with Audio DSP)
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s Dolby® Pro Logic® Delay 3 s Pseudo hall/matrix function
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Automatic Volume Level (AVL) control Smooth volume control Master volume control Soft-mute Loudness Bass, Treble Five band graphic equaliser Dynamic Bass Boost (DBB) 4 Dynamic Virtual Bass (DVB) 5 BBE® Sound processing 6 Graphic equaliser Processed or non processed subwoofer output Programmable beeper
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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2.12 µ-Controller
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2.13 Data Capture
s Text memory up to 10 pages s Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) s Data Capture for US Closed Caption s Data Capture for 525/625 line WST, VPS (PDC system A) and 625 line Wide Screen Signalling (WSS) bit decoding s Automatic selection between 525 WST/625 WST s Automatic selection between 625 WST/VPS on line 16 of VBI s Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput s Automatic detection of FASTEXT transmission s Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters s Signal quality detector for video and WST/VPS data types s Comprehensive teletext language coverage s Vertical Blanking Interval (VBI) data capture of WST data
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80C51 µ-controller core standard instruction set and timing 0.4883 µs machine cycle maximum of 256k x 8-bit flash programmable ROM maximum of 8k x 8-bit Auxiliary RAM 12-level Interrupt controller for individual enable/disable with two level priority Two 16-bit Timer/Counter registers One 24-bit Timer (16-bit timer with 8-bit Pre-scaler) WatchDog timer Auxiliary RAM page pointer 16-bit Data pointer Stand-by, Idle and Power Down modes 24 general-purpose I/O pins (12 for QIP90 versions) 14 bits PWM for Voltage Synthesis Tuning 8-bit A/D converter with 4 multiplexed inputs 5 PWM (6-bits) outputs for analogue control functions (1PWM for QIP90 versions) I2C byte level bus interface. Remote Control Pre-processor (RCP) Universal Asynchronous Receiver Transmitter (UART)
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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2.14 Display
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Teletext and Enhanced OSD modes Features of level 1.5 WST and US Close Caption 50Hz/60Hz display timing modes Two page operation for 16:9 screens Serial and Parallel Display Attributes Single/Double/Quadruple Width and Height for characters Smoothing capability of both Double Size, Double Width & Double Height characters Scrolling of display region Variable flash rate controlled by software Soft colours using CLUT with 4096 colour palette Globally selectable scan lines per row (9/10/13/16/) and character matrix [12x9, 12x13, 12x16, 16x18, (VxH)] Fringing (Shadow) selectable from N-S-E-W direction Fringe colour selectable Contrast reduction of defined area Cursor Special Graphics Characters with two planes, allowing four colours per character 64 software redefinable On-Screen display characters 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) G1 Mosaic graphics, Limited G3 Line drawing characters WST Character sets and Closed Caption Character set in single device SVM for Text Curtaining effect via software
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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3. Quick reference data
Table 1: SYMBOL Supply VP IP VDDA IDDA VDDC/P IDDC/P VPAudio [1] IPAudio [1] Ptot Input voltages ViVIFrms) ViSIF(rms) ViSSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) ViY(p-p) ViU(p-p) / ViPB(p-p) ViV(p-p) / ViPR(p-p) Output signals Vo(IFVO)(p-p) Vo(QSSO)(rms) video IF amplifier sensitivity (RMS value) sound IF amplifier sensitivity (RMS value) external audio input (RMS value) analogue supply voltage TV processor supply current (5.0 V) digital supply TV processor / analogue supply periphery supply current (3.3 V) digital supply to core/periphery supply current (1.8 V) audio supply voltage supply current (5.0/8.0 V) total power dissipation 4.7 - 3.0 - - - - - - - - - - - - - - 1.65 4.7 5.0 190 3.3 36 1.8 5.3 - 3.6 - - - - Quick reference data PARAMETER MIN. TYP. MAX.
UNIT V mA V mA V mA V mA W µV dBµV mV V V V V V V V
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- - - 1.0 - 0 - 10 - -
QSS sound IF amplifier sensitivity (RMS value)
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value) [2]
external CVBS/Y input (peak-to-peak value)
RGB inputs (peak-to-peak value)
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external chroma input voltage (burst amplitude) (peak-to-peak value) luminance input signal (peak-to-peak value) U / PB input signal (peak-to-peak
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V / PR input signal (peak-to-peak value) [2]
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demodulated CVBS output (peak-to-peak value) sound IF intercarrier output (RMS value) demodulated AM sound output (RMS value) non-controlled audio output signals (RMS value) selected CVBS output (peak-to-peak value) tuner AGC output current range RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current
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440 8.0 0.5 8.4 1.87 75 45 1.0 1.0 1.0 0.3 0.7 -1.33 / +0.7 -1.05 / +0.7 2.0 100 250 - 2.0 - 1.2 - 1 - 150 tbf - 1.3 1.4 1.0 0.8 - - 1.4 / 1.0 - - - - - - 1 - - - 1.2
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V mV mV V V mA V mA mA mA
Vo(AMOUT)(rms) Vo(AUDIO)(rms)
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Io(AGCOUT) VoRGB(p-p) IoHOUT IoVERT IoEWD
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Vo(CVBSO)(p-p)
The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is 2 Vrms. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
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Preliminary data sheet
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4. Ordering information
4.1 Ordering options
Preliminary data sheet Rev. 2.7 -- 14 July 2004 9 of 352
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Philips Semiconductors
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001 [2] BTSC - NTSC 128/ 256 8 1.25 2.25
Table 2:
Overview of types of Mono versions (for notes see Table 4) 001 - NTSC 128 8 1.25 2.25 010 - MULTI 128 8 1.25 2.25 011 - MULTI 128 8 1.25 2.25 020 10 MULTI 128 8 1.25 2.25 021 10 MULTI 128 8 1.25 2.25
TDA11xxxH/H1 [1] 000 Audio DSP Number of teletext pages - Comb filter Colour decoder NTSC Mono FM radio ROM size (k) 128 Aux RAM size (k) 8 Display RAM (k) 1.25 DRCS RAM (k) 2.25 Table 3:
Overview of types of Stereo versions (for notes see Table 4) 004PQ [2] 005PQ [2] 010 [2] BTSC BTSC MULTI - - - NTSC NTSC MULTI
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011 [2] MULTI - MULTI 128/ 256 8 1.25 2.25
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TDA12xxxH/H1/PQ [1] 000 [2] Stereo decoder [3] BTSC Number of teletext pages - Comb filter Colour decoder NTSC Stereo FM radio RDS/RBDS ® digital dbx Dolby® ProLogic® Virtual Dolby® (VDS) SRS® 3D Stereo SRS® TruSurround BBETM Double Window / Panorama mode ROM size (k) 128/ 256 Aux RAM size (k) 8 Display RAM (k) 1.25 DRCS RAM (k) 2.25
014PQ [2] 015PQ [2] 020 [2] MULTI MULTI MULTI - - 10 MULTI MULTI MULTI
021 [2] MULTI 10 MULTI
024PQ [2] 025PQ [2] MULTI MULTI 10 10 MULTI MULTI
The audio features is indicated in the type number, see Table 5
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UOC -N1D series
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128/ 256 128/ 256 128/ 256 8 8 8 1.25 1.25 1.25 2.25 2.25 2.25
128/ 256 128/ 256 128/ 256 8 8 8 1.25 1.25 10 2.25 2.25 2.25
128/ 256 8 10 2.25
128/ 256 128/ 256 8 10 2.25 8 10 2.25
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Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Table 4: Audio DSP
Overview of types of AV-Stereo versions
[1]
TDA12xxxH/H1/PQ
050PQ 051PQ 060
061 - MULTI
062 [2] - MULTI
063 [2] - MULTI
064PQ [2] 065PQ [2] 070 - MULTI - MULTI MULTI 10
071 10 MULTI
072 [2] 10 MULTI
073 [2] 10 MULTI
074PQ [2] 075PQ [2] 10 MULTI 10 MULTI
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- MULTI 128 8 1.25 2.25
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Number of teletext pages - Comb filter Colour decoder Mono FM radio RDS/RBDS digital dbx® Dolby® ProLogic® Virtual Dolby® (VDS) SRS® 3D Stereo SRS® TruSurround BBETM Double Window / Panorama mode ROM size (k) Aux RAM size (k) Display RAM (k) DRCS RAM (k) 128 8 1.25 2.25
- MULTI
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128 8 1.25 2.25 128 8
MULTI
1.25 2.25
The "standard" QFP version is indicated with "H" and the "facedown" version with "H1". The versions in the columns without "PQ" indication are available in the "H", "H1" and the normal QIP package. The versions in the columns with the addition "PQ" are available only in the "face-down" QIP package. For these versions the feature indication can be found on Table 5, and details on types number are given in section 4.1.1. When the BTSC demodulation is active the EIAJ demodulation is also activated.
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128/ 256 8 1.25 2.25
The audio features is indicated in the type number, see Table 5
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8 1.25 2.25 128/ 256 8 1.25 2.25 128/ 256 128/ 256 128 128 8 10 2.25 128/ 256 8 10 2.25 128/ 256 8 10 2.25 128/ 256 128/ 256 8 10 2.25 8 10
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UOC -N1D series
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Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
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4.1.1 Type Number and Feature Indication
The complete type number of these versions is given below. TDA12000H1/N1VXY0AA The explanation of the various parts of the type number is given below:
· The first 8 characters indicate the type number, the last 2 characters vary depending
on the version.
· The first 3 characters after the slash (/) indicate the IC version. · The characters "X" and "Y" give an indication of the Feature Content. More
information is given in Table 5.
· The last 3 characters give an indication of the ROM code.
Table 5: First Indication (X) 0 1 2 3 4 5 6 7 8 9 A B C D E F Feature Indication, characters "X" and "Y" ROM size 0 = 128k 1 = 256k 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 digital dbx® 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Dolby® Virtual ProLogic Dolby® (VDS) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Second SRS® 3D SRS® BBETM Indication Stereo TruSurround (Y) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
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indicated with "H" and the "face-down version" with "H1". The QIP version is indicated with PQ.
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· The next 1 or 2 characters indicate the package. The normal QFP128 version is
DW / PANORAMA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
U N C N O
U N
O E C LL N PY O U O C TR ED N O
C LL O TR
9397 750 XXXXX
C
om
pa ny
C
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 2.7-- 14 July 2004
11 of 352
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
5. Block diagram
Philips Semiconductors
QSSO/AMOUT REFO
SSIF SCART/CINCH IN/OUT I2S LS-OUT L R HP-OUT L R
C om
SOUND PLL DEEMPHASIS PAL/SECAM/NTSC DECODER REF C DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. Y A/D CONVERTER ALL-STANDARD STEREO DECODER AM
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO AGCOUT VIFIN
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
AUDIO SELECT ADC/DAC
AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs RDS
I/Os
pa
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
BASE-BAND
µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES SCAVEM ON TEXT PEAKING SCAN VELOCITY MODULATION U/V DELAY YUV CON.
DELAY LINE
ny
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
YUV IN/OUT
BL R
G
B
CR RO GO BO BCLIN BLKIN SVM
VIDEO SWITCH VIDEO IDENT. VIDEO FILTERS
BRI
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
C
on
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V VERTICAL & EAST-WEST GEOMETRY RGB/YPBPR INSERT YUV INTERFACE
SKIN TONE U/V TINT
RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
SATURATION
fid
SAT
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL L Signal processor for lowEand mid-range TV LE E E D D D D C C C C O O O O
UOC -N1D series
en
Vo Uo Yo
Yi
Ui Vi
V-DRIVE HOUT
EHTO BL
G/Y
EWD
R/PR B/PB B/PB SWO1 BL R/PR G/Y (CVBSx/Yx) (Cx)
tia l
PY
Fig 1. Block diagram of the "Stereo" TV processor
U N C O
12 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
SSIF QSSO/AMOUT REFO SCART/CINCH IN/OUT I2S LS-OUT L R HP-OUT L R
C om
SOUND PLL DEEMPHASIS PAL/SECAM/NTSC DECODER REF C DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. Y AM VERTICAL & EAST-WEST GEOMETRY V-DRIVE EHTO BL EWD
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO AGCOUT VIFIN
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
AUDIO SELECT ADC/DAC
AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs RDS
I/Os
pa
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
BASE-BAND
µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
DELAY LINE
ny
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
SCAVEM ON TEXT PEAKING CON.
YUV IN/OUT
BL R
G
B
CR RO GO BO BCLIN BLKIN SVM
VIDEO SWITCH VIDEO IDENT. VIDEO FILTERS
SCAN VELOCITY MODULATION U/V DELAY
BRI
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
C
on
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V
RGB/YPBPR INSERT YUV INTERFACE
SKIN TONE U/V TINT
SATURATION
RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
fid
SAT
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
Vo Uo Yo Yi Vi Ui
G/Y B/PB R/PR G/Y (CVBSx/Yx) (Cx)
HOUT
R/PR B/PB
SWO1 BL
tia l
O
Fig 2. Block diagram of the "AV-stereo" TV processor with audio DSP
PY U N C O
O
13 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
O
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
SSIF QSSO/AMOUT REFO SCART/CINCH IN/OUT LS-OUT L R
C om
SOUND PLL DEEMPHASIS PAL/SECAM/NTSC DECODER REF C DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. Y AM VERTICAL & EAST-WEST GEOMETRY V-DRIVE EHTO BL EWD
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO AGCOUT VIFIN
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
AUDIO SELECT
VOLUME CONTROL
I/Os
RDS
pa
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
BASE-BAND
µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
DELAY LINE
ny
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
SCAVEM ON TEXT PEAKING CON.
YUV IN/OUT
BL R
G
B
CR RO GO BO BCLIN BLKIN SVM
VIDEO SWITCH VIDEO IDENT. VIDEO FILTERS
SCAN VELOCITY MODULATION U/V DELAY
BRI
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
C
on
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V
RGB/YPBPR INSERT YUV INTERFACE
SKIN TONE U/V TINT
SATURATION
RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
fid
SAT
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
Vo Uo Yo Yi Vi Ui
G/Y B/PB R/PR G/Y (CVBSx/Yx) (Cx)
HOUT
R/PR B/PB
SWO1 BL
tia l
O
Fig 3. Block diagram of the "AV-stereo" TV processor without audio DSP
PY U N C O
O
14 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
O
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
AUDOUT/AMOUT
(SSIF)
SWITCH SIFIN/DVBIN DVBO/IFVO FMRO AGCOUT
QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
VIFIN
VISION IF/AGC/AFC REF PLL DEMOD. DVB MIXER GROUP DELAY SOUND TRAP
QSSO/AMOUT AUDEEM
AUDIO5 AUDIO4
AUDIO3 AUDIO2
C
IFVO/SVO/ CVBSI CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4 YSYNC CVBSO/PIP H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE VIDEO SWITCH VIDEO IDENT. VIDEO FILTERS
SOUND PLL DEEMPHASIS AUDIO SWITCH AVL VOLUME CONTROL
PAL/SECAM/NTSC REF DECODER
(AVL) V (REFO) HOUT
I/Os
Fig 4. Block diagram of the "Mono" TV processor
om
µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
pa
DIGITAL 4H/2H COMB FILTER Y DELAY ADJ. Y VERTICAL + EW GEOMETRY AND DRIVE U/V V-DRIVE (EWD) EHTO
RDS YUV IN/OUT
SCAVEM ON TEXT
ny
BL
SVM COR R G B BL RO GO BO BCLIN BLKIN SKIN TONE U/V TINT SATURATION BLACK STRETCH GAMMA CONTROL
BASE-BAND
DELAY LINE
C
YUV INTERFACE VO UO YO G/Y SWO1 BL
PEAKING SCAN VELOCITY MODULATION U/V DELAY YUV
CONTR/BRIGHTN OSD/TEXT INSERT BLUE STRETCH CCC WHITE-P. ADJ.
RGB/YUV/YPBPR INSERT
R/PR B/PB
G/Y (CVBS/Yx)
on
YI
fid
UI VI B/PB R/PR (Cx)
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en tia l
U N C O
O O
PY
15 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
O
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
6. Pinning information
Table 6: SYMBOL Pinning information
Preliminary data sheet Rev. 2.7 -- 14 July 2004 16 of 352
9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp VSSP2 VSSC4 VDDC4 VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+HPL VREF_POS_LSR+HPR VREF_NEG_HPL+HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG EWD/AVL VDRB VDRA VIFIN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
C
QFP "Face down" version
"Standard" version
QIP DESCRIPTION "Standard" & "Face-down" version All versions
om
AV Stereo No audio dsp
Mono
pa
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114
1 1 3 16 16 17 16 17 16 18 19 20 78 21 22
ground ground digital supply to SDACs (1.8V) supply (3.3 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) crystal oscillator input crystal oscillator output ground V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs) decoupling digital supply 1st supply voltage TV-processor (+5 V)
ny
113 112 111 110 109 108 107 106 105 113 112 111 110 109 108 107 106 105
C on
23 24 25 26 27 75 77 76 28
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
[1]
phase-2 filter phase-1 filter ground 1 for TV-processor SECAM PLL decoupling bandgap decoupling East-West drive output or AVL capacitor vertical drive B output vertical drive A output IF input 1
en
tia
l
O O
PY U N C O N TR O L LE D C O O N TR O U U N C PY PY
O
PY
N
LL E
C O
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6: SYMBOL "Standard" version Pinning information QFP "Face down" version QIP DESCRIPTION "Standard" & "Face-down" version All versions
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp
C
25 26 27 28 29 30 31 32 33 - 34 35 36 37 38 39 40 41 42 43 44 45 - 47
AV Stereo No audio dsp 104 103 102 101 100 99 98 97 96
Mono
om
25 26 27 28 29 30 31 32 33 34 - - - - 38 39 40 41 42 43 - 45 - 47
VIFIN2 VSC IREF GNDIF SIFIN1/DVBIN1 [2] SIFIN2/DVBIN2 [2] AGCOUT EHTO AVL/SWO/SSIF/ REFO/REFIN [2] [3] AUDIOIN5 AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM QSSO/AMOUT/ AUDEEM
[2]
25 26 27 28 29 30 31 32 33
104 103 102 101 100 99 98 97 96
104 103 102 101 100 99 98 97 96
29 30 31 32 33 34 35 74 44
IF input 2 vertical sawtooth capacitor reference current input ground connection for IF amplifier SIF input 1 / DVB input 1 SIF input 2 / DVB input 2 tuner AGC output EHT/overvoltage protection input Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation audio 5 input audio-5 input (left signal) audio-5 input (right signal) audio output for SCART/CINCH (left signal) audio output for SCART/CINCH (right signal) decoupling sound demodulator
pa
- 95 94 93 92 91 90 89 88 87 86 85 84 83 82 - 95 94 93 92 91 90 89 88 87 86 85 84 - 82
ny
95 - - - - 91 90 89 88 87 86 - 84 - 82
C on
- 34 35 36 37 38 39 40 41
37 38 64
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
36 39 40 41 42 43 44 45
GND2 PLLIF SIFAGC/DVBAGC
QSS intercarrier output / AM output / deemphasis (front-end audio out) ground 2 for TV processor IF-PLL loop filter
tia
[2] [2]
DVBO/IFVO/FMRO DVBO/FMRO VCC8V AGC2SIF VP2
[2]
42 43 44 45 46 47
AGC sound IF / internal-external AGC for DVB applications Digital Video Broadcast output / IF video output / FM radio output Digital Video Broadcast output / FM radio output 8 Volt supply for audio switches AGC capacitor second sound IF 2nd supply voltage TV processor (+5 V)
l
O O
PY
U N C O
17 of 352
PY
N TR O O N TR O U N C
L LE D C O PY LL E O
O
PY U N
C
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6: SYMBOL "Standard" version Pinning information QFP "Face down" version QIP DESCRIPTION "Standard" & "Face-down" version All versions
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp
C
48 - 49 50 51 52 - 53 54 55 - 56 57 58 59 62 63 - - - 64 65 66 67 68 69 70
AV Stereo No audio dsp 81 - 80 79 78 77 -
Mono
om
48 49 - - 51 52 53 - - 55 56 - - 58 59 - - 62 - - 64 65 66 67 68 69 70
IFVO/SVO/CVBSI [2] AUDIOIN4 AUDIOIN4L AUDIOIN4R CVBS4/Y4 C4 AUDIOIN2 AUDIOIN2L/SSIF [3]
48 - 49 50 51 52 -
81 - 80 79 78 77 -
81 80 - - 78 77 76
46 47 48 49 50 51
IF video output / selected CVBS output / CVBS input audio 4 input audio-4 input (left signal) audio-4 input (right signal) CVBS4/Y4 input chroma-4 input audio 2 input audio 2 input (left signal) / sound IF input audio 2 input (right signal) CVBS2/Y2 input audio 3 input audio 3 input (left signal) audio 3 input (right signal) CVBS3/Y3 input chroma-2/3 input audio output for audio power amplifier (left signal) audio output for audio power amplifier (right signal) audio output / AM output / FM output, volume controlled audio output for headphone channel (left signal) audio output for headphone channel (right signal) CVBS / PIP output scan velocity modulation output flyback input/sandcastle output or composite H/V timing output horizontal output ground connection for comb filter supply voltage for comb filter (5 V) V-input for YUV interface (2nd R input / PR input or CX input)
pa
76 75 74 - 73 72 71 70 69 68 - 67 66 65 64 63 62 61 60 59 76 75 74 - 73 72 71 70 67 66 - - - 65 64 63 62 61 60 59
ny
- - 74 73 - - 71 70 - - 67 - - 65 64 63 62 61 60 59
53 AUDIOIN2R 54 CVBS2/Y2 55 AUDIOIN3 - AUDIOIN3L 56 AUDIOIN3R 57 CVBS3/Y3 58 C2/C3 59 AUDOUTLSL 60 AUDOUTLSR 61 AUDOUT/AMOUT/FMOUT - AUDOUTHPL 62 AUDOUTHPR 63 CVBSO/PIP 64 SVM 65 FBISO/CSY 66 HOUT 67 VSScomb 68 VDDcomb 69 70 VIN (R/PRIN2/CX)
C
52 53 54 55 56 57 58 59 60 61 71 72 73 62 63
on
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
tia
l
O O
PY
U
N
C
O
18 of 352
PY
N
TR O
-
U
N
L LE D C O PY LL E O N TR O O
C U N C
O
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6: SYMBOL "Standard" version Pinning information QFP "Face down" version QIP DESCRIPTION "Standard" & "Face-down" version All versions
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp
C
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96
AV Stereo No audio dsp 58 57
Mono
om
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96
UIN (B/PBIN2) YIN (G/YIN2/CVBS-YX) YSYNC YOUT UOUT (INSSW2) VOUT (SWO1) INSSW3 R/PRIN3 G/YIN3 B/PBIN3 GND3 VP3 BCLIN BLKIN RO GO BO VDDA1 VREFAD_NEG VREFAD_POS VREFAD GNDA VDDA(1.8V) VDDA2(3.3) VSSadc VDDadc(1.8)
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
58 57
58 57 56 55 54 53 52
65 66 67 68
56 55 54 53 52
56 55 54 53 52
U-input for YUV interface (2nd B input / PB input) Y-input for YUV interface (2nd G input / Y input or CVBS/YX input)) Y-input for sync separator Y-output (for YUV interface) U-output for YUV interface (2nd RGB / YPBPR insertion input) V-output for YUV interface (general purpose switch output) 3rd RGB / YPBPR insertion input 3rd R input / PR input 3rd G input / Y input 3rd B input / PB input ground 3 for TV-processor 3rd supply for TV processor beam current limiter input black current input Red output Green output Blue output analog supply for TCG µ-Controller and digital supply for TV-processor (+3.3 V) negative reference voltage (0 V) positive reference voltage (3.3 V) reference voltage for audio ADCs (3.3/2 V) ground analogue supply for audio ADCs (1.8 V) supply voltage SDAC (3.3 V) ground for video ADC and PLL supply voltage video ADC and PLL
pa
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33
ny
51 50 49 48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33
C
69 70 79 80 81 82 83 84 85 86
on
87 88 89 87 90 88 1 90
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
tia
l
O O
PY U
N
C
O
19 of 352
PY
N N
TR O TR O
U
N
L
LE D C O PY LL E
C O U N C O
O
PY
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6: SYMBOL "Standard" version Pinning information QFP "Face down" version QIP DESCRIPTION "Standard" & "Face-down" version All versions
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp
C
97 98 99 100 101 - 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
AV Stereo No audio dsp 32
Mono
om
97 98 99 100 101 - 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
INT0/P0.5 P1.0/INT1 P1.1/T0 VDDC2 VSSC2 P0.4/I2SWS P0.4 P0.3/I2SCLK P0.3 P0.2/I2SDO2 P0.2 P0.1/I2SDO1 P0.1 P0.0/I2SDI1/O P0.0 P1.3/T1 P1.6/SCL P1.7/SDA VDDP(3.3V) P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P3.0/ADC0 P3.1/ADC1 VDDC1 DECV1V8
97 98 99 100 101 102 - 103 - 104 - 105 - 106 - 107 108 109 110 111 112 113 114 115 116 117 118
32
32 31 30 29 28 -
2 4 5 3 1 10 -
31 30 29 28 27
31 30 29 28 -
external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs) port 1.0 or external interrupt 1 port 1.1 or Counter/Timer 0 input digital supply to core (1.8 V) ground port 0.4 or I2S word select port 0.4 port 0.3 or I2S clock port 0.3 port 0.2 or I2S digital output 2 port 0.2 port 0.1 or I2S digital output 1 port 0.1 port 0.0 or I2S digital input 1 or I2S digital output port 0.0 port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line supply to periphery and on-chip voltage regulator (3.3 V) port 2.0 or Tuning PWM output port 2.1 or PWM0 output port 2.2 or PWM1 output port 2.3 or PWM2 output port 3.0 or ADC0 input port 3.1 or ADC1 input digital supply to core (+1.8 V) decoupling 1.8 V supply
pa
- 26 - 25 - 24 - 23 - 22 21 20 19 18 17 16 15 14 13 12 11 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
ny
27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
C on
50 11 51 6 7 8 9 10 11 47 48 12 13 3 3
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en
tia
l
O O
PY U
N
C
O
20 of 352
PY
N N
TR O TR O
U
N
L
LE D
C
O
O
PY
C O PY
U N
LL E
C O
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Table 6: SYMBOL "Standard" version Pinning information QFP "Face down" version QIP DESCRIPTION "Standard" & "Face-down" version All versions
Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Stereo + AV Mono Stereo + AV Stereo AV stereo No stereo audio dsp
C
119 120 121 122 123 124 125 126 127 128
[1] [2] [3]
AV Stereo No audio dsp 10 9 8 7 6 5 4 3 2 1
Mono
om
119 120 121 122 123 124 125 126 127 128
P3.2/ADC2 P3.3/ADC3 VSSC/P P2.4/PWM3 P2.5/PWM4 VDDC3 VSSC3 P1.2/INT2 P1.4/RX P1.5/TX
119 120 121 122 123 124 125 126 127 128
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
14 15 1 53 54 3 1 2 53 54
port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 2.4 or PWM3 output port 2.5 or PWM4 output digital supply to core (1.8V) ground port 1.2 or external interrupt 2 port 1.4 or UART bus port 1.5 or UART bus
The function of this pin can be chosen by means of the AVLE bit.
The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in Table 7 "Pin functions for various modes of operation". The function of pin 33 (face down: 96 and QIP: 44) is controlled by the CMB2-CMB0 bits in subaddress 4AH. When one of the SIF or SSIF functions are selected this selection is overruled by the SSIFS or SSIFM bits (subaddress 35H) when these bits are set to "1". In that case pin 53 (face down: 76 and QIP: 50) is activated as second sound IF input.
pa
ny
C on
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
UOC -N1D series
en tia l
U N C O
O O
PY
21 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
O
PY
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Preliminary data sheet Rev. 2.7 -- 14 July 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 XXXXX
Philips Semiconductors
Table 7: IC MODE
Pin functions for various modes of operation DVB MODE ANALOGUE TV MODE FM-PLL MODE (QSS = 0) FM DEMODULATION 0 - 1 0 QSS MODE (QSS = 1) QSS/AM DEMODULATION QSS-FM DEMODULATION 101/111 1 1 0 1 0 - 1 0 FM RADIO MODE
C om
0 100 EWD REFIN 101/111 0 - 1 010/011 - pin 108 pin 100 pin 99 pin 75 pin 33 pin 34
[1]
FUNCTION IFA/IFB/IFC bits FMR bit FMI bit AVLE bit CMB2/CMB1/CMB0 bits AM bit
000/001/010/011/100/110 0 0 1
pa
-
000/001/010/011/101/110
ny
0
1
0
1
-
-
Standard Face-down Standard QFP QFP QIP pin 21 pin 29 pin 30 pin 33
[1]
AVL DVBIN1 DVBIN2
[1]
AVL - - SWO/ SSIF/ REFO AUDEEM - IFVO -
EWD
AVL
EWD
AVL
EWD
AVL SIFIN1 SIFIN2
EWD
C
SIFIN1 SIFIN2 SWO/SSIF/REFO
on
pin 96
pin 44
SWO
AVL/ SWO/ SSIF/ REFO
AVL/SWO/SSIF/ REFO
SWO/ SSIF/ REFO AUDEEM
AVL/ SWO/ SSIF/ REFO
SWO/ SSIF/ REFO
AVL/ SWO/ SSIF/ REFO
fid
U U U U U N N N N N C C C C C O N IIIT ONT ONT ONT ONT RO RO RO RO R LL LL LL Signal processor for lowEand mid-range TV LLE E E D D D D C C C C O
pin 39 pin 42 pin 43 pin 44 pin 48 pin 62
[2] [2] [3] [4]
pin 90 pin 87 pin 86 pin 85 pin 81 pin 67
[2] [2] [3] [4]
pin 36/pin 41 pin 42 n.a. pin 46 pin 59
[3] [4] [2]
- DVBAGC DVBO DVBO SVO/CVBSI AUDOUT
[1] [2] [3] [4]
QSSO SIFAGC IFVO -
AMOUT
QSSO
AMOUT
AUDEEM SIFAGC FMRO FMRO IFVO/SVO/CVBSI AUDOUT
UOC -N1D series
en tia
IFVO/SVO/CVBSI AUDOUT
IFVO/SVO/CVBSI AUDOUT AMOUT
AUDOUT AMOUT
AUDOUT
The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH.
The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H.
l
O
The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H.
PY U N C O
This functionality is only valid for the mono versions. In the "stereo" and "AV-stereo" versions this pin has the function of audio output for the headphone channel (left signal).
O
22 of 352
PY
N TR O L LE D C O PY LL E O N TR O O U N C U N C
O
PY
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C
U N C
U N C N O TR ED C PY O O LL O TR C
6.1 Pinning
U N C N O
U N
O E C LL N PY O U O C TR ED N O
C LL O TR
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
P1.7/SDA P1.6/SCL P1.3/T1 P0.0/I2SDI1 P0.1/I2SDO1 P0.2/I2SDO2
P0.3/I2SCLK
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P0.4/I2SWS
99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
113 112 111 110 109 108
107 106
105 104 103 102 101 100
C
XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF 21 22 23 24 25 26 27 28 29 30 31 32
fid on
QFP-128 0.8mm pitch "standard version"
39 40 47 48 52 AUDIOIN2L 53 AUDIOIN2R/SSIF 54 CVBS2/Y2 55 AUDIOIN3L 56 AUDIOIN3R 57 CVBS3/Y3 58 SIFAGC/DVBAGC DVBO//IFVO/FMRO DVBO/FMRO VCC8V AGC2SIF VP2 SVO/IFOUT/CVBSI C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR AUDIOIN4R CVBS4/Y4 C4 AUDIOIN4L 60 61 62 63 CVBSO/PIP 64 41 42 49 50 35 36 37 38 43 44 45 46 GND2 PLLIF 51 59 33 34
VSSP2 1 VSSC4 2 VDDC4 3 VDDA3(3.3V) 4 VREF_POS_LSL 5 VREF_NEG_LSL+LSR 6 VREF_POS_LSR+HPL 7 VREF_NEG_HPL+HPR 8 VREF_POS_HPR 9
pa ny
GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO
om
9397 750 XXXXX
C
Fig 5. Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Preliminary data sheet
Rev. 2.7-- 14 July 2004
en tia
96 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 91 VREFAD 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 B/PBIN3 G/YIN3 R/PRIN3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
97 INT0/P0.5
VSSC2 VDDC2
23 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C U N
U N C U N N O C
U N C N O TR ED C PY O C N O O O E C LL N PY O U O C TR ED LL O TR C
LL O TR
VSSC1/P P3.3/ADC3 119 P3.2/ADC2 118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
VDDC3 P2.5/PWM4 P2.4/PWM3
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
127 P1.4/RX 126 P1.2/INT2 125 VSSC3
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
124
123 122 121 120
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96
P1.7/SDA P1.6/SCL
VREF_POS_LSL VREF_NEG_LSL+LSR VREF_POS_LSR+HPL VREF_NEG_HPL+HPR VREF_POS_HPR
on C
QFP-128 0.8mm pitch "standard version"
39 40 47 48 41 SIFAGC/DVBAGC 42 DVBO//IFVO/FMRO 43 - 44 VCC8V 45 - 46 VP2 SVO/IFOUT/CVBSI AUDIOIN2L/SSIF
9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
fid
Rev. 2.7-- 14 July 2004
CVBS3/Y3 C2/C3 59 - 60 - 61 AUDOUTLSL 62 AUDOUTLSR 63 CVBSO/PIP 64
33 34 AUDIOIN3L AUDIOIN4R CVBS4/Y4 C4 AUDIOIN4L AUDIOIN2R CVBS2/Y2 AUDIOIN3R GND2 PLLIF 52 53 54 55 56 57 58 35 36 37 38 49 50 51
pa ny
9397 750 XXXXX
C
Fig 6. Pin configuration of "AV stereo" versions without Audio DSP
om
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Preliminary data sheet
en tia
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDDA3(3.3V)
3 4 5 6 7 8
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 B/PBIN3 G/YIN3 R/PRIN3
VSSP2 VSSC4 VDDC4
1 2
P0.2
91 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO
INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
24 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C U N
U N C U N N O C
U N C N O TR ED C PY O C N O O O E C LL N PY O U O C TR ED LL O TR C
LL O TR
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 91 90 VREFAD_POS 89 VREFAD_NEG 96 88 VDDA1(3.3V.) 87 BO 86 GO
P1.7/SDA P1.6/SCL
VREF_POS_LSL VREF_NEG_LSL+LSR VREF_POS_LSR+HPL VREF_NEG_HPL+HPR VREF_POS_HPR
on C
QFP-128 0.8mm pitch "standard version"
39 40 47 48 SIFAGC/DVBAGC DVBO//IFVO/FMRO VCC8V VP2 SVO/IFOUT/CVBSI DECSDEM AMOUT/QSSO/AUDEEM 60 61 AUDOUT/AMOUT 62 - 63 CVBSO/PIP 64 52 53 54 CVBS2/Y2 55 AUDIOIN3 56 - 57 CVBS3/Y3 58 C2/C3 59 41 42 49 50 35 36 37 38 43 44 45 46 AUDIOIN4 CVBS4/Y4 C4 51 AUDIOIN2 GND2 PLLIF 33 34
9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
fid
Rev. 2.7-- 14 July 2004
pa ny
9397 750 XXXXX
C
Fig 7. Pin configuration "mono" versions
om
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5 -
Preliminary data sheet
en tia
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDDA3(3.3V)
3 4 5 6 7 8
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 B/PBIN3 G/YIN3 R/PRIN3 VDDcomb VSScomb HOUT FBISO/CSY SVM
VSSP2 VSSC4 VDDC4
1 2
P0.2
INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X)
25 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C U N
U N C U N N O C
U N C N O TR ED C PY O C N O O O E C LL N PY O U O C TR ED LL O TR C
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR
122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR
LL O TR
119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
115 114 113 112 111 110 109 108
105 104 103 102 101 100
97 EHTO 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 DVBO/FMRO 84 VCC8V 83 AGC2SIF 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 CVBS2/Y2 73 AUDIOIN3L 72 AUDIOIN3R 71 CVBS3/Y3 70 69 68 67 66 65 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR CVBSO/PIP
P0.4/I2SWS VSSC2 VDDC2 P1.1/T0 P1.O/INT1 INT0/P0.5
GNDA 37 VREFAD 38 VREFAD_POS 39 VREFAD_NEG 40
pa ny
P0.2/I2SDO2 P0.3/I2SCLK
QFP-128 0.8 mm pitch "face down version"
VP3 47 GND3 48 B/PBIN3 49 G/YIN3 50 R/PRIN3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46
9397 750 XXXXX
C
Fig 8. Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
om
VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36
C
P1.6/SCL P1.3/T1 P0.0/I2SDI1 P0.1/I2SDO1
21 22 23 24 25 26 27 28 29 30 31 32
on
Rev. 2.7-- 14 July 2004
9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20
P3.3/ADC3
fid
Preliminary data sheet
en tia
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
AVL/SWO/SSIF/ 96 REFIN/REFOUT
26 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C U N
U N C U N N O C
U N C N O TR ED C PY O C N O O O E C LL N PY O U O C TR ED LL O TR C
LL O TR
VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR
122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR
119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
VSSP2
115 114 113 112 111 110 109 108
105 104 103 102 101 100
128
127
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL P1.3/T1 P0.0 P0.1 P0.2 P0.3 P0.4 VSSC2 VDDC2 P1.1/T0 P1.O/INT1 INT0/P0.5 21 22 23 24 25 26 27 28 29 30 31 32 P3.3/ADC3
C
on
QFP-128 0.8mm pitch "face down version"
VREFAD_POS 39 VREFAD_NEG 40 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46 VP3 47 GND3 48 B/PBIN3 49 G/YIN3 50 R/PRIN3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDA2(3.3V) 35 VDDA(1.8V) 36 GNDA 37 - 38 VDDadc(1.8) 33 VSSadc 34
fid
Rev. 2.7-- 14 July 2004
pa ny
9397 750 XXXXX
C
Fig 9. Pin configuration of "AV stereo" versions without Audio DSP
om
Preliminary data sheet
en tia
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
CVBS2/Y2 AUDIOIN3L
AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR CVBSO/PIP
27 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
U N C
U N C
U N C U N
U N C U N N O C
U N C N O TR ED C PY O C N O O O E C LL N PY O U O C TR ED LL O TR C
LL O TR
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR 122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR
119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
115 114 113 112 111 110 109 108
105 104 103 102 101 100
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5 94 93 92 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4 79 78 CVBS4/Y4 77 C4 76 AUDIOIN2 75 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL P1.3/T1 P0.0 P0.1 P0.2 P0.3 P0.4 VSSC2 VDDC2 P1.1/T0 P1.O/INT1 INT0/P0.5 21 22 23 24 25 26 27 28 29 30 31 32 P3.3/ADC3
C
on
QFP-128 0.8mm pitch "face down version"
39 40 47 48 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36
fid
GNDA VREFAD_POS VREFAD_NEG
VP3 GND3 B/PBIN3 G/YIN3 R/PRIN3 49 50 37 38
pa ny
9397 750 XXXXX
C
Fig 10. Pin configuration "mono" versions
om
Preliminary data sheet
Rev. 2.7-- 14 July 2004
en tia
C2/C3 -
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
l
CVBS2/Y2 AUDIOIN3 CVBS3/Y3
CVBSO/PIP
AUDOUT/AMOUT -
28 of 352
Philips Semiconductors
UOCIII-N1D series
Signal processor for low and mid-range TV
ED ED ED C C PY O PY O N O N O N O N O LL O TR LL O TR LL O TR
C
P3.2/ADC2 14 P3.3/ADC3 15 VDDA3(3.3V) 16 GNDA3 17 XTALIN 18 XTALOUT 19 VSSA1 20 DECDIG 21 VP1 22 PH2LF 23 PH1LF 24 GND1 25 SECPLL 26 DECBG 27 VIFIN1 28 VIFIN2 29 VSC 30 IREF 31
QIP Standard version
fid
on
pa ny
GNDIF 32 DVBIN1/SIFIN1 33 DVBIN2/SIFIN2 34
om
AGCOUT 35 AMOUT/QSSO/AUDEEM 36 AUDOUTSL 37 AUDOUTSR 38 GND2 39 PLLIF 40 SIFAGC/DVBAGC 41 DVBO//IFVO/FMRO 42 VCC8V 43 AGC2SIF/SWO/AVL/ 44 SSIF/REFIN/REFO VP2 45
C
Fig 11. Pin configuration of "standard" QIP versions
9397 750 XXXXX © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 2.7-- 14 Jul