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4

3

2
REVISIONS REV A DESCRIPTION ORIGINATION

1

DATE

APPROVED

D

D

C

C

B
1118 6652CE02C PIN SOCKETS PRINTED CIRCUIT BOARD

B
U502_Y201 PCB REF DES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

COMPONENTS U502, Y201 (12 PINS) NOTES

PART NO

DESCRIPTION
HIGHEST REF DES USED

NOTES

TOLERANCES DECIMALS .XX +-.010 .XXX +-.005 FRACTIONS +-1/32 ANGLES +-2

SCHEMATIC
APPROVAL DATE
06-08-03

ANALOG DEVICES
TITLE

804 WOBURN ST WILMINGTON, MA 01887

MATERIAL

DRAWN BY:

DML/JDB

DESIGNED BY:

REF DES NOT USED
CHECKED:

CASCADE CUSTOMER EVALUATION BOARD

A

FINISH

APPROVED BY:

SIZE

FSCM NO

DRAWING NUMBER

REV

A

MFG ENGINEER:

B
SCALE NONE 1-8-2004_9:53

6652CE02D
SHEET 1 OF 7

D

DO NOT SCALE

4

3

2

1

6
J101
1 3 2

5
CR101

4
E101 E102 E103 LM317 (Alternate) R102=267, R103=453 C104=10uF

3
LM317 (Alternate) R107=120, R108=267 C110=10uF

2

1

E107

E108

C101
1

C102 0.1U

C103 0.01U

D
AC Adaptor 6VDC_2A

10U

1

VR101 ADP3338AKC-3.3 3
VI

4
VO

VR103 ADP3338AKC-1.8 2
VO

4
VO

E109

VIN_D

1 R102 SEL
2

F101 2

+3.3V

3
VI VO

2

1 R108 SEL
1

F103 2

J102 1 2 VCCINT (+1.8V)

D

1 E104 E105 E106

10U R103 200

1

2

VR102 ADP3338AKC-2.5 3 VIN_D
VI VO

C142 4
VO

1

2

R101 0
1

10U 2 F102 1 R105 SEL
1

1

10U

C105 10U

CR107 AMBER VDDIO

C144 10U

C110 10U

2

2

2

ADJ

ADJ

HEADER2 R109 25.5

C106

C112 10U

C104

R107 0

C111 10U

CR103 VCCINT Red

1

1 2

2

2

VDD (+2.5V) C109 10U

ADJ

LM317 (Alternate) R104,R105=267 C107=10uF

1

2

R106 200

J104 1

J103 1 AVDDIN +2.5VOUT_EXT VDDIO DRVDD 2 1

F107

2 C123 10U
1 2

VDDIO (+3.3V) R116 200

C143

C107 10U
1

C

10U

R104 0

C108 10U

AMBER CR102
1 2

2 3 4
5 6

2

C

VDD Amber

CR106 AMBER

1

E110

E111

4
VO

J105
1 3 2

CR108

VIN_A

1

3

VI

VO

2

AVDDIN

1

E112

VR104 LM317EMP

NOTES: +3.3V: Support components of Eval. Bd. VR101 AVDD - Analog support components of Eval Bd. +3.0V VR104 VDDIO: Digital I/O supply on 6652 +3.3V VR101 VDD - Digital Core supply on 6652 +2.5V VR102 DUTAVDD - Analog ADC Core Supply on 6652 +3.0V VR104 XTAL - Onboard XTAL Encode +3.3V VR201

2

1

TP101 3.0V
1

VCCINT

DUTDRVDD

VDD

AVDD

C148 0.1U

C149 0.01U

1

10U
AC Adaptor 6VDC_2A

1

1

----

C147
2

ADJ

R111 267
1

1

F104 2 C115 C116 0.1U

2

AVDD C124 10U
1 1 1 1 1

0.1U

0.1U

0.1U

0.1U

10U

C132 0.1U 10U

1

1

C125

C126

C127

C128

C129

E113

E114

R110 374

B

C114 10U

E115

2

1

1

1

----

E116

E117

E118

2

1

1

1

1

1

100 10U CR104 AVDDIN Green
1

0.1U

10U

C140 0.1U 10U

0.1U

0.1U

0.1U

2

2 2 2 2 2 2

C130 10U

C131

C133 0.1U

2

2

C145 10U

C113 10U

10U

B
TP102 3.0V
1

1

VDDIO DUTAVDD

+3.3V

F106 1 R112 2 C117 C118

C134
2

C135

C136

C137

C138 10U

C139

C141 0.1U

2

2

2

2

1

VR105 LM317EMP

1

1

4
1

VO

1

2

VIN_D

3

VI

VO

2
2

ADJ

1
1

R114 267

R115 100
1

DRVDD

E119

1

E120
CR105 DRVDD Green VDDIO

1

2.5V/3.0V F105 1 2

TP103 2.5V/3.0V/3,3V
1

2

DUTDRVDD C122 0.1U

C120
1

E121
1

3.3V C121 10U
1 2

A

C146 10U

C119 10U

R113 267

10U

TP104
GND
1

A
7910 Triad Center Dr. Greensboro, NC 27409 Title:

2

2.5V=> R113=267. 3.0V=> R113=374.

Drawing Number: Date:
06-08-03

AD6652BGA2 CUSTOMER EVAL BD 6652CE02D
Filename:

Rev:

D
1

Drawn By: Design By: PLL TRM Sheet
2 of 7

W:\PROJECTS\6652\CUST_EVAL\6652CE01\6652CE01D

6

5

4

3

2

2-10-2004_16:05

6

5

4

3

2
R205
1 2

1
ACLK AVDD

R201

33
J215
1 2

Clock: Signal Generator Input
J201

AVDD

1 2

J207

2

499

NC7WZ16P6X
J209
1 2

2

1

J210
1

C201

J218
1 2

1 A1 2 GND

Y1 6 5 VCC Y2 4 AVDD
1 2

D
2

1

J211

2

1 2

0.1U
J220
1
2

R203 10K

C217 0.1U

D

3 A2 R204 499 J208
1

U201

1

R202 49.9
2

R210
1 2

2

1

CLK +3.3V

1

2

J205

J216
1 2

NC7WZ16P6X
J212
1 2

33

J213
1

2

J214
1

1 A1 2 GND

Y1 6 5 VCC Y2 4 +3.3V
1 2

VR201
ADP3338AKC-3.3 VIN_A

J217

J206
1 2 2

2

4
VO VI VO

1

2

3 A2 U202

C218
1 2

C219 0.1U
1 2

C220 0.1U

3

2
2

F201 1 R220 SEL 2

J204
1 2

J219
1

0.1U

ADJ

2

1

R209 332
1 1

C215
1

C216
1 2

D-Clock delay circuit.

2

0.1U

0.01U

NC7WZ16P6X
1 A1 2 GND Y1 6 5 VCC Y2 4 +3.3V

C
C212 10U C213
1

C
R224
1 2

R219 0

C214 10U

CR201 1 AMBER 3 5 7

Y201

1 2

XTAL

OE

VCC

14 12 10 8

FPGA_CLK

2

33

OE' VCC' GND'OUT' GND OUT CRYSTAL_3

10U

3 A2 U204

1

C207

2

NOTE: If through hole crystal is used, insulate SMD crstyal pads with kapton or other insulating tape. XFMR INPUT B R218 49.9
2

R215
1 2

10P
VIN-B C208

T202

49.9
1 2

6
5

1
1

2

1

R214 SEL

J203

2 3 ADT-KK81

4
1

R216
1 2

SEL
VIN+B C209

C202

49.9
TP204
1 2

2

R206
1 2

10P

B
2

VIN+A
1

1

49.9
R208 SEL
1

C210 10U

10P

B

C203

2

R213
1 2

SEL

VIN-A
1 2 1

C211 0.1U
R217 AVDD
1 2 1 2

XFMR INPUT A J202

49.9
T201 6 5
1

C204

1 2 3

TP203
1

2

10P
C205 10U

R221

R207 49.9
2

4

1K

1K

ADT-KK81 C206
1 2

NC7WZ16P6X
0.1U
R211 R212
1 2 2

+3.3V R222
2 1

TP205
1

OTRA

1 A1 2 GND

Y1 6 5 VCC Y2 4

CR202
1 2

200 R223
2 1

RED

AVDD

1

OTRB

3 A2 U203

CR203
1 2

1K

1K

200 TP206
1

RED

A

A
7910 Triad Center Dr. Greensboro, NC 27409 Title: Drawing Number: Date:
06-08-03

FPGA_OTRA FPGA_OTRB

AD6652BGA2 CUSTOMER EVAL BOARD AD6652CE02D
Filename: Rev:

D
1

Drawn By: Design By: PLL TRM Sheet
3 of 7

6

5

4

3

2

2-10-2004_16:05

6
C323 AVDD AVDD J301
1 1 2

5
VREF

4
J302 DUTAVDD
1 2

3

2

1

1

2

R301 5.49K 1 OUT1 R302 10K 2 -IN1 1
2

MICRO PORT J309

R305
SHARED_REF PCLK_SRC
1

2 4 6 8 10 12 14 16 18 20 22 A1 CS DTACK PA7_LA7 A2 PA6_LA6 D1 D3 CS RESET MODE D6 D4 D2

VIN+A

PB13

PB11

PB15

PB12

ACLK

3 2 AD1580
2

-

OUT2 7 -IN2 6

D5 D3 D1

5 7 9 11

R12

R11

R10

P16

P12

P11

T14

T12

T11

T10

R9

R8

R7

R6

R5

R4

R3

R2

R1

T9

T8

T7

T6

T5

T4

T3

PDWNB

PB5_LB5

VIN+A

PB13

PB11

PB15

PB12

PB9

PB1_LB1

PBCH0_LBCLKOUT

SHRDREF

PBREQ

OTRB

DCLK

ACLK

PCLK

PBIQ

4 V-

N/C

N/C

N/C

N/C

N/C

N/C

N/C

N/C

N/C

N/C

0.1U
U302

AD822AR DS TP301
1

13 15 17 19 21

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

N/C

N/C

+ +IN2 5

T2

D0

P9

C301

P10

3 +IN1 +

CLK

AVDD

PB9

1

V+ 8

OTRB

PBIQ

U303

D7

3

PBREQ

PDWNA

D

PB5_LB5

PBCH0_LBCLKOUT

0.1U
2

PB1_LB1

D

PA7_LA7 A2 PA6_LA6 D1 D3 CS RESET MODE SYNCD OTRA PDWNA TD0 PA4_LA4

LIB-B

P8 P7 P6 P5 P4 P3 P2 P1 N16 N3 N2 N1 M3 M2 M1 L16 L3 L2 L1 K16 K15 K3 K2 K1 J16 J3 J2 J1 SCLK PB7_LB7 PB6_LB6 REFTA REFBA CHIP_ID0 PAACK CHIP_ID3 VREF TMS TDI CHIP_ID1 PBACK VDDIO PB14 PB10 PB8 PB0_LB0 SDIN VIN-A PB2_LB2 PBCH1_LBCLKIN PAIQ PB4_LB4 PB3_LB3 CHIP_ID2

3

1

PBACK RES_VDDIO PB14 PB10 PB8 PB0_LB0 SDIN VIN-A PB2_LB2

R/W A2

Int 1V R303 10K
2 1 2

A0 C325

C324 0.1U

Int 2V

C326
HEADER22
1 2

1

J305

J304 Ext 2X
1 1

2

AVDD

10U

0.1U

J303
Int Prog
1

SYNCD SENSE OTRA PDWNB TDO PA4_LA4

C

VDDIO
1

R304 10K

REFTB

AD6652
256 PIN BGA CASCADE II
INTERNALLY CONNECTED PINS:

C

PBCH1_LBCLKIN PAIQ PB4_LB4 PB3_LB3 CHIP_ID2

C332 J306A J306B
1 1 1 2

1

1

1

1

1

2

0.01U
REFTA

C331
2

R308 5K
2

R309 4.99K
2

R310 4.99K
2

R311 4.99K
2

PACH0_LACLKOUT A0 TRST

PACH0_LACLKOUT A0 TRST R/W D4 D6 SYNCC SYNCA LIA-A DUTYEN PA9 PA3_LA3

1

1

1

1

0.01U C302
1 2 1 1

REFBB REFBA

R/W CHIP_ID0 CHIP_ID1 CHIP_ID2

VDD;D4,E4,D5,E5,D6,E6,D7,E7,M8,N8,M9,N9,M10,N10,M11,N11 VDDIO;D8,E8,D9,E9,D10,E10,D11,E11,M4,N4,M5,N5,M6,N6,M7,N7 DUTAVDD;J13,K13,L13,M13,M14,N13,N14,P13,P14,R13,R14,T13 DUTAVDD;A13,A14,B13,B14,C13,C14,D13,D14,E13,E14,F13,G13,H13 DUTDRVDD;D12,E12,F12,G12,H12,J12,K12,L12,M12,N12

AGND SCLK PB7_LB7 PB6_LB6 REFTA REFBA CHIP_ID0 PAACK CHIP_ID3 VREF

0.1U
C303 10U

J307A J307B
1 2

C306 0.1U
C307

J312 1 3 5

2 4 6

D4 D6 SYNCC SYNCA

C304
2 2

C305
2

C308 0.1U

10U
2

C309 0.1U

CHIP_ID3

8 7 HEADER8

0.1U

0.1U

DUTYEN PA9 PA3_LA3

B12 C1 C2 C3 C4 C5

B
J310 PCLK_SRC +3.3V U304 3 4 5 6 1 3 5 U304 2 4 6 TRST TCLK TDI TMS TDO PCLK JTAG J308

B

PACH1_LACLKIN

A1 DS

A1 DS PA1_LA1 PA2_LA2 SYNCB DTACK VIN+B
LIA-B LIB-A

TMS TDI PA5_LA5 PA0_LA0 PAREQ REFBB REFTB SENSE
SENSE H16

PA10

PA12

PA11

PA13

PA15

PA8

D2

G1

G2

G3

G15

G16

1
2

F1

F2

C6

C7

C8

C9

D1

D2

D3

F3

H1

H2

C10

C11

C12

C16

D16

J311

2

2 4 U301

5 7 9

6 8

IDT74LVC86A
1

LIB-A 3

IDT74LVC86A

PACH1_LACLKIN

PA1_LA1

PA2_LA2

PA5_LA5

DTACK

VIN+B

PAREQ

SYNCB

REFBB

REFTB

10
D2 D5 D7

PA0_LA0

VIN-B

TCLK

PA10

F16

PA12

PA11

PA13

PA15

9 10

U304 8

VDDIO

VDD

+3.3V

DUTAVDD

DUTDRVDD

PA14

PA8

H3

E1

E2

E3

HEADER6

3

4

J313 LIA-A 1

D5

N/C

D7

1

PA14

2

AGND

VIN-B

TCLK

D0

D0

CHIP_ID1

3

A

IDT74LVC86A
1

C310
1 2 2

C311
1 2

C312
1 2

C313 0.1U

C321
1 2

C314
1 2

C315
1 2

C316
1 2

C317
1 2

C322
1 2

C318
1 2

C319
1 2

C320
1 2

C327
1 2

C333
1 2

C334
1 2

C328
1 2

C329 0.1U
1 2

C330

A
7910 Triad Center Dr. Greensboro, NC 27409 Title:

12 13

U304 11

0.1U

0.1U

0.1U

0.1U 10U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

IDT74LVC86A

AD6652BGA2 CUSTOMER EVAL BOARD
Drawing Number: Date:
06-08-03

6652CE02D
Filename:

Rev:

D
1

Drawn By: Design By: PLL TRM Sheet 4 of 7

6

5

4

3

2

2-10-2004_16:04

6
FPGA_TDO

5

4
+3.3V G13 J11

3

2
CONF_DONE FPGA_TMS FPGA_TCK

1

NSTATUS

PBREQ

PBIQ

VCCIO3

A18 FPGA_DB7 FULL_FLAG I/O I/O I/O I/O I/O I/O B8 C6 C7 C8 D6 D7 D8 D9 E7 B17 B18 C16 C17 C18 D16 D17 D18 E16 E17

VCCIO3

+3.3V C10 G8 C9 E6

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EP20K100_324BGA BANK #3 PINS CONNECTED INTERNALLY:

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

N18 M18 L18 L17 L16 K18 J18 J15 J14 H18 H17 H14

PAREQ

PAIQ

FD8 FD10

+3.3V M11 P13

D10

U10

U11

B10

FD12 FD11 M10 N10 FD13 FD14 N11 P10 P11 P12 FD16 FD15 Q6 Q4 R11 R12 R13 R14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

TRST

VCCIO1

VCCIO1

TMS

TDO

TCK

T9

T10

U8

U9

B9

D
PB13 PB15 PBACK FPGA_OTRB FPGA_OTRA PDWNA A2 A3 A4 A5 A6 A7 A8 B3 B4 B5 B7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, INITDONE

D
I/O I/O I/O I/O V16 V15 V14 V13 V12 V11 V10 V9 U16 U15 Q11 Q13 Q10 Q12 Q14 Q16 PDWNB DUTYEN

VCCIO5

CONF_DONE

VCCINT;F7,G6,G11,H9,H12,J8,K11,L7,L10,M8,M13,N5,N12 GND;K9,K10,L8,L11,M7,M12,N6,N13,P5,P14,R4,R15 GND;D4,D15,E5,E14,F6,F13,G7,G9,G12,H8,H11,J9,J10

nSTATUS

EP20K100_324BGA BANK #5

VCCIO5

FAST2

FAST1

FAST4

FAST3

NCEO

I/O I/O

EP20K100_324BGA BANK #1

I/O I/O I/O

VCCINT;F7,G6,G11,H9,H12,J8,K11,L7,L10,M8,M13,N5,N12 GND;K9,K10,L8,L11,M7,M12,N6,N13,P5,P14,R4,R15 GND;D4,D15,E5,E14,F6,F13,G7,G9,G12,H8,H11,J9,J10

I/O I/O I/O I/O

I/O, RDYnBSY

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O G18

I/O, CLKUSR

I/O I/O

I/O DATA5 DATA4 DATA3 DATA2 DATA1 I/O

E18

G14

G15

G16

F15

F16

F17

F18

H13

I/O

I/O

I/O

I/O

I/O

I/O

I/O U13

T11

T12

T13

T14

T15

R16

T16

U12

U14

U401
ASTROBE FD17

I/O

F8

U401

G17

I/O

E9

E11

F10

C5

B2

B6

C

E8

F9

U401

E10

C
Q5 Q3 Q2 Q1 Q0 Q17 Q15 V8 V7 V6 V5 V4 V3 U7 U6 U5 U4 MODE RESET CS D3

INIT_DONE

BBUSY

P5

P4

P3

P2

P1

+3.3V +3.3V J401
1

+3.3V N7 VCCIO6 P6 L9 VCCIO6 R401 1K M5 VCCINT M9 N8 +3.3V N14 L12 N9 D0 I/O I/O I/O I/O EP20K100_324BGA BANK #4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V18 V17 U18 U17 T18 T17 R18 R17 P18 Q7 Q8 FD0 Q9 FD2 FD1 FD4 FD3 FD6 DTACK D2 D5 D7 SYNCB P4 P7 P8 P9 R5 R6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EP20K100_324BGA BANK #6
2

2

3

J402
2
1

VCCIO6

+3.3V H10 F12

3

1

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

SYNCD SYNCA SYNCC D6 D4

NCONFIG

R/W H15

VCCIO2

VCCIO2

MSEL1

A9 A10 FPGA_DB2 FPGA_DB4 A11 A12 A13 A14 A15 FPGA_DB6 FPGA_DB8 FPGA_DB1 A16 A17 B11

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O

D11 D12

P0 H16 K15

MSEL0

K17

K16 CLK1p

DS

D13 D14 E12 E13 E15 F11 F14 G10 J12 J13 K13 K14 L13 L14 L15 M14 M15 I/O I/O I/O I/O I/O I/O I/O I/O I/O

MSEL1

MSEL0

I/O,CLK3n

I/O,CLK1n

nCONFIG

CLK3p

K12

J16

J17

VCCIO4

B

CLKLK_ENA

VCCIO4

B

EP20K100_324BGA
BANK #2

I/O I/O I/O I/O I/O I/O I/O

T3

T4

T5

T6

T7

R7

R8

R9

B16

B15

B14

B13

C15

C14

C13

C12

U401

C11

B12

VCCINT;F7,G6,G11,H9,H12,J8,K11,L7,L10,M8,M13,N5,N12 GND;K9,K10,L8,L11,M7,M12,N6,N13,P5,P14,R4,R15 GND;D4,D15,E5,E14,F6,F13,G7,G9,G12,H8,H11,J9,J10

P15

P16

FPGA_DB5

FPGA_DB3

N15

N16

M16

M17

FD9

MR

FD7

N17

U401

WCLK

RCLK

+3.3V

VCCINT

EMPTY

FULL

FD5

P17

R10

T8

U401

A
1 2

A
C401
1 2

C402
1 2

C403
1 2

C404
1 2

C405
1 2

C406
1 2

C407
1 2

C408
1 2

C409
1 2

C410
1 2

C411
1 2

C412
1 2

C413
1 2

C414
1 2

C415 0.1U
1 2

C416 0.1U

7910 Triad Center Dr. Greensboro, NC 27409 Title:

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

AD6652BGA2 CUSTOMER EVAL. BD
Drawing Number: Date:

6652CE02D
Filename:

Rev:

D
1

Drawn By: Design By: PLL TRM Sheet 5 of 7

6

5

4

3

2

1-8-2004_16:56

6
PA5_LA5 PA10

5

4
TP501
1

3

2

1

A1

+3.3V +3.3V M6 J504 1 2

R510 SEL C511

R3

N3

N2

K8

I/O CLKLK_OUT2n

I/O, LOCK4

I/O, LOCK2

I/O, DEV_OE

VCCIO7

VCCIO7

P0

PB7_LB7 SCLK

G1 G3 G5

I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O

V2 V1 U3 U2 U1 T2 T1

PA6_LA6 A0

DCLK

PCLK

D

R511 1K

FPGA_CLK

L4

FPGA_TDI

HEADER2

1 2

SEL
M3 N4 +3.3V H7 P2 +3.3V I/O I/O I/O I/O I/O I/O E1 E2 E3 E4 F1 F2 F3 F4 G2 J1 PB6_LB6 PA12 FPGA_DB1 FPGA_DB2 FPGA_DB3 FPGA_DB4 FPGA_DB5 PACH1_LACLKIN PA13 R/W PB3_LB3 PBCH1_LBCLKIN PB4_LB4 FPGA Debug Port PB0_LB0 SDIN PB2_LB2 P3
CLKLK_OUT2p VCC_CKLK2 CLKLK_FB2p GND_CKLK2 GND_CKOUT2 VCC_CKLK4 VCC_CKOUT2 GND_CKLK4

1 2

J7 K7 K6 L6

VCCINT

D

VCCINT

K3

K2

D1 PACH0_LACLKOUT A2 PA4_LA4 PA7_LA7 PB12 PB11 PB5_LB5 PB9 PB10 PB14 A1 B1 C1 C2 C3 C4 D1 D2 D3 D5 I/O I/O I/O I/O I/O I/O I/O I/O I/O, DATA6

CLK4p

CLK2p

PA15 PAACK

H1 H2 H3 H4

F5

L2

J4

J3

J2

EP20K100_324BGA BANK #7

VCCIO8

VCCIO8

TDI

DCLK

DATA0

nCE

EP20K100_324BGA

U401

I/O

I/O

I/O

I/O

I/O R1

M1

N1

R2

K1

K4

L1

P1

U401

I/O

PA8

PA0_LA0

PA1_LA1

PA2_LA2

PA3_LA3

PA11

PA14

PA9

PBCH0_LBCLKOUT PB1_LB1 PB8

EP20K100_324BGA BANK #8 I/O, CLKLK_FB2n I/O, DEV_CLRn

I/O I/O I/O I/O

J503 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16

I/O, DATA7

I/O, CLK2n

I/O,CLK4n

I/O I/O

I/O, nWS

I/O, nCS

I/O, nRS

C
FULL GND +3.3V MR +3.3V WCLK GND +3.3V +3.3V

U501 58 60 61 62 63 64 1 2 3 FF/IR FWFT/SI LD MRS PRS WCLK WEN SEN DC PAF HF PAE EF/OR RCLK REN RT OE 57 56
U401

G4

J5

H5

H6

J6

M2

I/O, CS

C

M4

K5

L3

L5

P6

54 53 52 51 50 49
EMPTY RCLK GND +3.3V GND VCCINT;H9

P7

FPGA_DB6 FPGA_DB7 FPGA_DB8

R506 1K

R505 1K +3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

FD17 FD16

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDT72265

Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

48 47 45 44 42 41 40 38 37 36 35 34 32 31 29 28 26 25

Q17 Q16
1

2

2

2

R501 10K
1

R502 10K
1

R503 10K
1

2

R504 10K +3.3V

+3.3V EPROM EPC1 8

+3.3V

B

FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2

Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
1 2

U502
P0 DCLK NSTATUS CONF_DONE 1 2 3 4

DATA DCLK OE NCS

VCC VCC NCASC GND

7 6 5 C501 0.1U FPGA_TCK FPGA_TDO

R509 1K

R508 1K

R507 1K

B

J502 1 3 5 7 2 4 6 8 10
+3.3V

J501
/DCLK CONF_DONE NCONFIG NSTATUS P0 +3.3V

FPGA_TMS

1 3 5 7 9

2 4 6 8 10 +3.3V
FPGA_TDI

9

FPGA Program Port

ProgramPort

A

FD1 FD0

A
C502
1 2

C503
1 2

C504
1 2

C505
1 2

C506
1 2

C507
1 2

C508
1 2

C509 0.1U
1 2

C510 0.1U

7910 Triad Center Dr. Greensboro, NC 27409 Title:

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

+3.3V;4,30,43,55 GND;5,24,27,33,39,46,59

AD6652BGA2 CUSTOMER EVAL. BD
Drawing Number: Date: 06/08/2003

6652CE02D
Filename:

Rev:

D
1

Drawn By: Design By: PLL TRM Sheet
6 of 7

6

5

4

3

2

2-10-2004_15:35

6
IEEE Std 1284-1994 PC Parallel Connector

5

4

3
LIA J604

2

1

Link Ports
SH1
27 1 14 2

LIB J605

J601 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
NSTROBE DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 NACK BUSY PERROR SELECT NFAULT NSTROBE NAUTOFD NINIT NSELECTIN 41 40 38 37 36 35 33 32 47 46 45 44 43 29 28 27 26 30 25 1
2

+5V 42 31 18

+3.3V 7

SH1

27

U601 B1 B2 B3 B4 B5 B6 B7 B8

VCC

VCC-CABLE

VCC-CABLE

VCC

E601

E602

D

E603

A1 A2 A3 A4 A5 A6 A7 A8

8 9 11 12 13 14 16 17 2 BBUSY

P0 P1 P2 P3 P4 P5
ADJ

1 14 2 15 3 16 PA0_LA0 4 17 PA1_LA1 5 18 PA2_LA2 6 19 PA3_LA3 7 20 PA4_LA4 8 21 PA5_LA5 9 22 PA6_LA6 10 23 PA7_LA7 11 24 PACH1_LACLKIN 12 25 PACH0_LACLKOUT 13 26 PBCH0_LBCLKOUT PBCH1_LBCLKIN PB7_LB7 PB6_LB6 PB5_LB5 PB4_LB4 PB3_LB3 PB2_LB2 PB1_LB1 PB0_LB0

21 22 23 24 25 26 27 28 29 30
NINIT NFAULT

D

VIN_D

VR601 ADP3338AKC-5 3
VI

4
VO

+5V 2
VO

15 3 16 4

1 2 FERRITE R604 SEL
1 2

F601

P6 P7 1

74LVX161284A Y9 Y10 Y11 Y12 Y13 C14 C15 C16 C17 PLH HLHIN GND GND GND GND HD A9

J606
2 NSTATUS

LM317 (Alternate) R603=806, R604=267 C605=10uF

1

R605 332

C608 10U

17 5 18 6 19 7 20

3 A10 4 A11 5 A12 6 A13 20 A14 21 A15 22 A16 23 A17

FULL_FLAG 1 INIT_DONE R/W DS 1 ASTROBE

C605

C606 10U
1

R603 0

C607
1 2

2

J607
2 CONF_DONE

31 32 33 34

10U

10U

CR601 +5V Red

J608
2 NCONFIG

8 21 9 22

C
NSELECTIN

35 36

C

C36DRPF

PLHIN

19 24 48 PDIR
1

HLH DIR

J609 1 2 NSTROBE PARALLEL PORT A J602 PAIQ PA15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PBIQ PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7_LB7 PB6_LB6 PB5_LB5 PB4_LB4 PB3_LB3 PB2_LB2 PB1_LB1 PB0_LB0 PBACK GND PBREQ GND PCLK GND PBCH1_LBCLKIN PBCH0_LBCLKOUT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 PARALLEL PORT B J603 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

10 23 11 24 12 25 13 26

39

34

15

10

R601 2K GND
2 3
2 1

R602 2K

+3.3V +3.3V
1

PA14 PA13 PA12 PA11 PA10 PA9

J610

SH2

28

SH2

28

26PM-RMCA-26JL-AD

26PM-RMCA-26JL-AD

B

PA8 PA7_LA7 PA6_LA6 PA5_LA5 PA4_LA4 PA3_LA3 PA2_LA2 PA1_LA1 PA0_LA0 +3.3V +5V PAACK GND C601
1 1 2 2

B

C602
1 2

C603 0.1U
1 2

C604 0.1U

PAREQ GND PCLK GND PACH1_LACLKIN PACH0_LACLKOUT

0.1U

0.1U

A

A
7910 Triad Center Dr. Greensboro, NC 27409 Title:

AD6652BGA2 CUSTOMER EVAL BD
Drawing Number: Date: 06-08-03

HEADER50

HEADER50

AD6652CE02D
Filename:

Rev:

D

Drawn By: Design By: PLL TRM Sheet 7 of 7

6

5

4

3

2

2-10-2004_16:05

1