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CDX-828
SERVICE MANUAL
US Model Canadian Model AEP Model UK Model E Model
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
CDX-805 MG-250C-137 KSS-521A/J2N
SPECIFICATIONS
COMPACT DISC CHANGER
MICROFILM
CDX-828
7-6. SCHEMATIC DIAGRAM RF/SW Boards · See page 39 for Waveforms. · See page 45 for IC Block Diagrams.
(Page 33)
The components identified by mark ! or dotted line with mark ! are critical for safety. Replace only with part number specified.
Les composants identifiés par une marque ! sont critiques pour la sécurité. Ne les remplacer que par une piéce portant le numéro spécifié.
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CDX-828
7-9. SCHEMATIC DIAGRAM MAIN Board (1/3) · See page 39 for Waveforms. · See page 46 for IC Block Diagrams.
(Page 28)
(Page 37)
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34
CDX-828
7-10. SCHEMATIC DIAGRAM MAIN Board (2/3) · See page 40 for Waveforms. · See page 47 for IC Block Diagrams.
(Page 43)
(Page 38)
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36
CDX-828
7-11. SCHEMATIC DIAGRAM MAIN Board (3/3) · See page 40 for Waveforms. · See page 47 for IC Block Diagrams.
(Page 34)
(Page 35)
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· Waveforms RF Board MAIN Board (1/3)
1 IC11 #£ (RF O) 500 mV/DIV, 500 ns/DIV 1 IC101 @¶ (MDP) 6 IC101 ^TM (RFCK)
2.5 Vp-p
1.4 Vp-p
5.7 Vp-p
7.6 µs
2 IC11 2 (FEI) 50 mV/DIV, 1 µs/DIV 2 IC101 #§ (V16M)
137 µs
7 IC101 &º (C4M)
Approx. 110 mVp-p
6.8 Vp-p
6.6 Vp-p
3 IC11 $¶ (TEI) 200 mV/DIV, 500 µs/DIV
120 ns
3 IC101 $ª (WDCK)
236 ns
8 IC101 &¢ (WFCK)
Approx. 280 mVp-p
6.6 Vp-p
5.5 Vp-p
11.4 µs
4 IC101 %º (LRCK)
137 µs
9 IC101 *ª (XTAI)
6.6 Vp-p
3.3 Vp-p
22.7 µs
5 IC101 %¢ (BCKO)
59.2 ns
!º IC201 #¡ (EXTAL)
6.6 Vp-p
3.2 Vp-p
472 ns
125 ns
39
MAIN Board (2/3)
!¡ IC603 4
MAIN Board (3/3)
! IC401 !ª (LRCK) @º IC401 7 (RFCK)
4.7 Vp-p
6.2 Vp-p
5.7 Vp-p
59.2 ns
!TM IC601 4 (XTO)
22.7 µs
!§ IC401 !¶ (BCK)
137 µs
@¡ IC401 5 (C4M)
6.4 Vp-p
6.2 Vp-p
6.6 Vp-p
59.2 ns
!£ IC601 7 (BCK)
472 ns
!¶ IC401 !£ (WDCI)
236 ns
@TM IC401 3, IC501&¶ (WFCK)
7.4 Vp-p
7.7 Vp-p
5.5 Vp-p
472 ns
!¢ IC601 9 (LRCK)
11.4 µs
!· IC401 !TM (LRCI) @£ IC403 1
137 µs
7.4 Vp-p
6.6 Vp-p
6.6 Vp-p
22.7 µs
22.7 µs
!ª IC401 9 (BCKI)
11.4 µs
@¢ IC501 @ª (EXTAL)
6.6 Vp-p
3.2 Vp-p
472 ns
100 ns
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CDX-828
7-13. SCHEMATIC DIAGRAM DIGITAL OUT/JACK Boards
(Page 36)
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44
· IC Block Diagrams RF Board IC11 CXA1992BR
RFTC RF M PD1 RF O CC1 PD2 CC2
28
PD
LD
CP
39
38
37
36
35
34
33 32
31 30
CB
29
27
PD 2 I-V AMP
PD 1 I-V AMP
PD AMP
LD AMP
RF SUMMING AMP
FOCUS OK COMPARATOR
VCC
IFB1 IFB6
LASER POWER CONTROL PEAK/BOTTOM HOLD MIRR COMPARATOR DEFECT AMP IIL TTL
FE 40 BIAS FOCUS BIAS WINDOW COMPARATOR
PEAK/BOTTOM HOLD
LDON
LPCL
TGFL
MIRR
DFCT1
VEE F 41 F I-V AMP E I-V AMP TGFL
FOCUS ERROR AMP
FOH
LPC
FOL
FOK CC1
RF I
E 42 EI 43 VEE 44 TEO 45
TRACKING GAIN WINDOW COMPARATOR
TGH TGL BALH BALL ATSC IIC DATA REGISTER, INPUT SHIFT REGISTER, ADDRESS DECODER, SENSE SELECTOR, OUTPUT DECODER
IIL TTL
26 SENS2 25 SENS1 24 C. OUT
VEE
TOG1 TOG4
BAL1 BAL4
TTL IIL
23 22 21 20 19
XRST DATA XLT CLK LOCK
TG1 TG2
IFB1 IFB6 BAL1 BAL4 TOG1 TOG4
TM1 TM7
PS1 PS4
FS1 FS4
DFCTO
LPFI 46 TEI 47 ATSC 48
E-F BALANCE WINDOW COMPARATOR ATSC WINDOW COMPARATOR TZC COMPARATOR TM1 DFCT
TZC
FZC
VCC VCC ISET
18 VCC
TM6
17 ISET
TZC 49
16 SL O 15 SL M TRACKING PHASE COMPENSATION
TDFCT 50
TG1 VCC CENTER VOLTAGE GENERATOR FZC COMPARATOR FOCUS PHASE COMPENSATION VCC VEE CHARGE UP FS1
TM5
VEE VCC TM7 TM4
VC 51 FZC 52
DFCT
FS4
FS2 FSET TG2 TM3
VEE 1 2 3 4 5 6 7 8 9 10 11 12
VEE 13
FSET
FEO
FDFCT
SRCH
45
TA M
FE M
TA O
FE O
FLB
TGU
FGD
TG2
FEI
+ TM2
14 SL P
+
IC52 BA6287F
OUT1 1
8 GND
VM 2
7 OUT2
DRIVER TSD
DRIVER
VCC 3
CONTROL LOGIC
6 VREF
POWER SAVE FIN 4 5 RIN
MAIN Board IC101 CXD2530Q
MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
WFCK TES5 EMPH
TES6 VDD VSS EXCK SBSO SCOR
80 79 78 77 76 75 74 73 72
71 70 69 68
DOUT C4M FSTT XTSL
NC VSS VDD NC TES7 NC VSS XVDD XTAI XTAO XVSS VSS NC TES8 NC VDD VSS NC NC XRST
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 LRCK 49 WDCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0
ERROR CORRECTOR EFM DEMODULATOR
D/A INTERFACE
ASYMMETRY CORRECTOR
16K RAM
DIGITAL OUT
DIGITAL PLL
SUB CODE PROCESSOR
OSC
CLOCK GENERATOR TIMING LOGIC SERVO AUTO SEQUENCER
CPU INTERFACE
DIGITAL CLV
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VDD VSS LMUT RMUT TES2 CKOUT
XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI
SQCK SQSO SENS DATA XLAT
CLOK SEIN CNIN DATO
46
IC202
AT24C16N-10SI-TR
IC301
BA6287F
OUT1 1
START STOP LOGIC
8 GND
SERIAL EN CONTROL LOGIC LOAD COMP LOAD INC DATA WORD ADDR/COUNTER
H.V. PUMP/TIMING 8 VCC DATA RECOVERY 7 TST
VM 2
7 OUT2
DEVICE ADDRESS COMPARATOR A0 1 A1 2 A2 3 GND 4 R/W
DRIVER TSD
DRIVER
X DEC
6 SDL E2PROM 5 SDA
VCC 3
CONTROL LOGIC
6 VREF
Y DEC
SERIAL MUX
POWER SAVE FIN 4 5 RIN
DIN DOUT
DOUT/ACK LOGIC
IC302
BA8272F-E2
DATA OUT LINK OFF CLK OUT
IC401
CXD2522Q
XEMP SDTO XSOE SCK SDTI XLT XRDE XWRE SPSL A4 A5 A6 A7 A8 XOE XCAS D2 OSCE
DATA IN
BUS ON
VCC
RESET
51 50 49 48 47 46 45 44 43
42
VSS
41
40 39 38 37 36 35 34 33
14
13
12
11
10
9
8
XWIH AM4 AM3 AM2 AM1 AM0 VDD XQOK 52 53 54 55 56 57 58 59 CPU I/F 32 31 30 29 28 27 26 25 24 23 22 D3 D0 D1 XWE XRAS A9 VDD A0 A1 A2 A3
RESET SWITCH
ADDRESS MONITOR WRITE BASE COUNTER READ BASE COUNTER VWA DRAM I/F
1
BUS ON OUT
2
BUS ON IN
3
GND
4
BUS CLK
5
VREF
6
BUS DATA
7
BUS RESET
SELECTOR TIMING GEN. GSCR 60 SCOR 61 NC 62 NC 63 NC 64 1 2 3 4 5 6 7 8
GRST XRST WFCK DIN C4M XROI RFCK GTOP
21 C176
DATA LINKING CONTROL
DSP I/F
DAC I/F
DIGITAL OUT
20 DOUT
9 10 11 12 13 14 15
BCKI VSS DATI LRCI WDCI TEST XTAO
16
XTAI
17 18 19
BCK DATA LRCK
47
IC402
MSM514400D-60TS-K
DQ1 DQ2 WE
1 2 3 WRITE CLOCK GENERATOR DATA INPUT BUFFER DATA OUTPUT BUFFER
26 VSS 25 DQ4 24 DQ3
CLOCK GENERATOR 2
COLUMN SENSE AMP DECODER I/O GATE
4M BIT MEMORY CELL ROW DECODER BOARD BIAS GENERATOR
23 CAS 22 OE
CLOCK GENERATOR 1
RAS
4
MODE CONTROL
PREADDRESS BUFFER DECODER
REFRESH ADDRESS COUNTER
A9 A0 A1 A2 A3 VCC
5 9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
IC502
KM62256DLG-7LT
IC601
AK4321-VF-E2
AOUTR AOUTL VCOM DEM1
13 12
AVDD
BVDD
AVSS
VREF
DIF1
28 VCC 27 WE 26 25 24 23 A13 A8 A9 A11
24 23 22
21 20
19 18 17 16 15
14
A14 A12 A7 A6 A5
1 2 3 4 5
LEVEL SHIFT
BUFFER
ROW DECODER
MEMORY MATRIX 512X512
SERIAL INPUT INTERFACE MODULATOR MODULATOR 8× INTERPOLATOR 8× INTERPOLATOR
22 OE 21 A10
CTF
SCF
CTF
SCF
A4 A3 A2 A1 A0
6 7 8 9 10
LEVEL SHIFT
BUFFER
I/O GATE COLUMN DECODER
CLOCK OSC/DIVIDER 20 CE 19 18 17 16 15 I/O8 I/O7 I/O6 I/O5 I/O4 DE-EMPHASIS CONTROL 1 2 3 4 5 6 7 8 9 10 11
DVDD
DIF0
DZF
TTL
SDATA
SMUTE
I/O1 11 I/O2 12 I/O3 13 GND 14
LEVEL SHIFT
BUFFER
I/O BUFFER
48
DEMO
DVSS
BICK
LRCK
CKS
XTO
DFS
XTI
PD
7-14.
IC PIN FUNCTION DESCRIPTION
· MAIN BOARD IC201 CXP84332-208Q (SYSTEM CONTROLLER) Pin No. 1 to 3 4 5 6 7 8 9 10 11 12 13 to 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin Name -- CH.F CH.R LOAD2 LOAD1 SENS2 LIM.SW EE.INIT EE.CLK EE.DATA -- SINGLE XRST FOK SENS GFS GRSRT XQOK SDTI XSOE ESPXLT RST EXTAL XTAL VSS TX TEX AVSS AVREF MCK EHS H.TEMP XRDE XWRE A.MUTE EMP ML GRSCOR I/O O O O I I I I I O I/O O I O I I I O O I O O I I O -- O I -- I I I I O O O O O I Not used (open) Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) "L" active *1 Motor drive signal (save direction) output to the chucking motor drive (IC52) "L" active *1 Chucking end detect switch (SW11) input terminal "L": When completion of the disc chucking operation Save end detect switch (SW12) input terminal "L": When completion of the disc chucking operation Internal status signal (sense signal) input from the CXA1992BR (IC11) Sled limit in detect switch (SW1) input terminal "L": When the optical pick-up is inner position Initialize signal input for the EEPROM (IC202) "H": format Fixed at "L" in this set Serial data transfer clock signal output to the EEPROM (IC202) Two-way data bus with the EEPROM (IC202) Not used (open) Setting terminal for the single disc/multiple discs mode "L": single mode, "H": multiple discs mode (fixed at "H") System reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q (IC401) "L": reset Focus OK signal input from the CXA1992BR (IC11) "L": NG, "H": OK Internal status signal (sense signal) input from the CXD2530Q (IC101) Guard frame sync signal input from the CXD2530Q (IC101) "L": NG, "H": OK Reset signal output to the CXD2522Q (IC401) "L": reset Subcode Q OK pulse signal output to the CXD2522Q (IC401) "L" active ESP status signal input from the CXD2522Q (IC401) ESP status read enable signal output to the CXD2522Q (IC401) "L" active ESP latch pulse signal output to the CXD2522Q (IC401) "L" active System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" Main system clock input terminal (8 MHz) Main system clock output terminal (8 MHz) Ground terminal Sub system clock output terminal Not used (open) Sub system clock input terminal Not used (fixed at "L") Ground terminal (for A/D converter) Reference voltage (+5V) input terminal (for A/D converter) Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator position (A/D input) Elevator height position detect input from the RV202 (elevator height sensor) (A/D input) High temperature sensor input terminal Not used (fixed at "L") D-RAM read enable signal output to the CXD2522Q (IC401) "L" active D-RAM write enable signal output to the CXD2522Q (IC401) "L" active Audio line muting on/off control signal output terminal "H": muting on Emphasis mode output to the D/A converter (IC601) "H": emphasis on Fast speed dubbing control signal output to the D/A converter (IC601) "L": fast speed Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401) Function
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Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pin Name D/A.RESET SCK SI SO SCLK SUBQ -- C.OUT BUS.ON A/D.SW MGLK ELV.F -- MAG.SW BU.CHK W.UP SCOR EJECT CD.CLK CD.XLT CD.DATA CD.ON ELV.ON ELV.R -- VDD NC (VDD) BUSY RESET REQ CCCLK CSO CSI ADJ
I/O O I I O O I O I I I I O O I I I I I O O O O O O O -- -- I O I O O I I
Function Reset signal output to the D/A converter (IC601) "L": reset Serial data transfer clock signal input from the SONY bus interface (IC302) Serial data input from the SONY bus interface (IC302) Serial data output to the SONY bus interface (IC302) Subcode Q data reading clock signal output to the CXD2530Q (IC101) Subcode Q data input from the CXD2530Q (IC101) Not used (open) Track number count signal input from the CXA1992BR (IC11) Bus on/off control signal input from the SONY bus interface (IC302) Analog/digital select switch (SW801) input terminal Magazine eject operation completion detect switch (SW201) input "H": bus on "L": digital, "H": analog "L": eject completed
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Magazine in/out detect switch (SW202) input Battery detection signal input terminal Bus on or eject switch (SW301) input terminal Eject switch (SW301) input terminal "L": magazine detected "H": bus on or eject switch pushing "H": battery on
Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) "H" active Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401) Serial data latch pulse signal output to the CXD2530Q (IC101) Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401) D/A converter and servo section power supply on/off control signal output Mechanism deck section power supply on/off control signal output "H": power on "H": power on
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Power supply terminal (+5V) Connected to the power supply (+5V) Busy monitor input from the CD text decoder (IC501) Reset signal output to the CD text decoder (IC501) "L": busy status "L" active "L": reset
Data request signal input from the CD text decoder (IC501) Command clock signal output to the CD text decoder (IC501) Command data output to the CD text decoder (IC501) Command data input from the CD text decoder (IC501)
Automatic/manual adjustment selection terminal "L": manual adjustment mode, "H": automatic adjustment mode (fixed at "H" in this set)
*1 chucking motor (M103) control Mode Terminal CH.F (pin 4) CH.R (pin 5) STOP "H" "H" LOAD CHUCKING "L" "H" SAVE "H" "L" BRAKE "L" "L"
*2 elevator motor (M104) control Mode Terminal ELV.F (pin %·) ELV.R (pin &º) STOP "H" "H" ELEVATOR ELEVATOR UP DOWN "L" "H" "H" "L" BRAKE "L" "L"
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· MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER) Pin No. 1, 2 3 4 5 6 7 8 9 10 11 to 18 19 Pin Name NC NC REQ CCLK CSI CSO SCLK SSI NC
ADD0 to ADD7
I/O O I O I I O O I O O I I/O I I O -- O O O O O O -- O I O O I I I I Not used (open) Not used (fixed at "L")
Function
Request signal output to the system controller (IC201) "L" active Serial data transfer clock signal input from the system controller (IC201) Serial data input from the system controller (IC201) Serial data output to the system controller (IC201) Clock signal output for subcode data reading to the CXD2530Q (IC101) Subcode data input from the CXD2530Q (IC101) Not used (open) Address signal output to the S-RAM (IC502) Not used (fixed at "L") Two-way data bus with the S-RAM (IC502) System reset signal input from the system controller (IC201), SONY bus interface (IC302) and reset signal generator (IC304) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" System clock input terminal (10 MHz) System clock output terminal (10 MHz) Ground terminal Not used (open) Busy signal output to the system controller (IC201) "L": busy status Not used (open) Chip enable signal output to the S-RAM (IC502) "L" active Data write enable signal output to the S-RAM (IC502) "L" active Address signal output to the S-RAM (IC502) Power supply terminal (+5V) Not used (open) Not used (fixed at "H") Address signal output to the S-RAM (IC502) Not used (open) Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101) Backup power supply detection signal input terminal (used also to reset standby) Not used (fixed at "L")
NC
20 to 27 DATA0 to DATA7 28 29 30 31 32 to 55 56 57 to 61 62 63 64 to 69 70 71, 72 73 74 75 76 77 78 79, 80 RST EXTAL XTAL VSS NC BUSY NC CE WE
ADD8 to ADD13
VDD NC NC ADD14 NC SCOR WFCK BUCK NC
51