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CDX-727
SERVICE MANUAL
US Model Canadian Model AEP Model UK Model E Model
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
CDX-715 MG-250C-137 KSS-521A/J2N
SPECIFICATIONS
COMPACT DISC CHANGER
MICROFILM
CDX-727
7-6. SCHEMATIC DIAGRAM RF/SW Boards · See page 41 for Waveforms. · See page 43 for IC Block Diagrams.
(Page 35)
The components identified by mark ! or dotted line with mark ! are critical for safety. Replace only with part number specified.
Les composants identifiés par une marque ! sont critiques pour la sécurité. Ne les remplacer que par une piéce portant le numéro spécifié.
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30
CDX-727
7-9. SCHEMATIC DIAGRAM MAIN Board (1/2) · See page 41 for Waveforms. · See page 44 for IC Block Diagrams.
(Page 30)
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36
CDX-727
7-10. SCHEMATIC DIAGRAM MAIN Board (2/2) · See page 42 for Waveforms. · See page 45 for IC Block Diagrams.
(Page 40)
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38
7-11.
PRINTED WIRING BOARD JACK Board
(Page 31)
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7-12.
SCHEMATIC DIAGRAM JACK Board
(Page 38)
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· Waveforms RF Board
1 IC11 #£ (RF O) 500 mV/DIV, 500 ns/DIV
MAIN Board (1/2)
1 IC101 @¶ (MDP) 6 IC101 ^TM (RFCK)
2.5 Vp-p
6.4 Vp-p 1.4 Vp-p
7.6 µs
2 IC11 2 (FEI) 50 mV/DIV, 1 µs/DIV 2 IC101 #§ (V16M)
13.6 µs
7 IC101 &º (C4M)
6.5 Vp-p
Approx. 110 mVp-p
6.3 Vp-p
119 ns
3 IC11 $¶ (TEI) 200 mV/DIV, 500 µs/DIV 3 IC101 $ª (WDCK)
119 ns
8 IC101 &¢ (WFCK)
6.3 Vp-p
5.8 Vp-p
Approx. 280 mVp-p
11.4 µs
4 IC101 %º (LRCK)
136 µs
9 IC101 *ª (XTAI)
6.2 Vp-p
6.2 Vp-p
22.7 µs
5 IC101 %¢ (BCKO)
59.4 ns
0 IC201 #¡ (EXTAL)
6.5 Vp-p
4.9 Vp-p
474 ns
124 ns
41
MAIN Board (2/2)
!¡ IC501 @ª (EXTAL) !§ IC401 9 (BCKI) @¡ IC401 !ª (LRCK)
3.1 Vp-p
6.5 Vp-p
5.6 Vp-p
100 ns
!TM IC501 &¶ (WRCK)
474 ns
!¶ IC401 !TM (LRCI)
22.7 µs
@TM IC601 !£ (MCK)
5.8 Vp-p
6.3 Vp-p
5.8 Vp-p
136 µs
!£ IC401 3 (WFCK)
22.7 µs
!· IC401 !£ (WDCI)
59.4 ns
@£ IC601 ! (XI)
5.8 Vp-p
6.9 Vp-p
2.5 Vp-p
136 µs
!¢ IC401 5 (C4M)
11.3 µs
!ª IC401 !§ (XTAI)
59.4 ns
@¢ IC601 @£ (BCK)
6.3 Vp-p
6.4 Vp-p
6.2 Vp-p
119 ns
! IC401 7 (RFCK)
59.4 ns
@º IC401 !¶ (BCK)
474 ns
@ IC601 @¢ (LRCK)
6.4 Vp-p
6.2 Vp-p
5.6 Vp-p
136 µs
474 ns
22.7 µs
42
· IC Block Diagrams RF Board IC11 CXA1992BR
RFTC RF M PD1 RF O CC1 PD2 PD CP CB CC2 28 MIRR LD FOK 27 IIL TTL DFCT1 CC1 RF I
39
38
37
36
35
34
33 32
31 30
29
PD 2 I-V AMP
PD 1 I-V AMP
PD AMP
LD AMP
RF SUMMING AMP
FOCUS OK COMPARATOR
VCC
IFB1 IFB6
LASER POWER CONTROL PEAK/BOTTOM HOLD MIRR COMPARATOR DEFECT AMP
FE 40 BIAS FOCUS BIAS WINDOW COMPARATOR FOH FOL
PEAK/BOTTOM HOLD
LDON
LPCL
VEE F 41 F I-V AMP E I-V AMP TGFL
FOCUS ERROR AMP
TGFL
LPC
E 42 EI 43 VEE 44 TEO 45
TRACKING GAIN WINDOW COMPARATOR
TGH TGL BALH BALL ATSC IIC DATA REGISTER, INPUT SHIFT REGISTER, ADDRESS DECODER, SENSE SELECTOR, OUTPUT DECODER
IIL TTL
26 SENS2 25 SENS1 24 C. OUT
VEE TOG1 TOG4 BAL1 BAL4
TTL IIL
23 22 21 20 19
XRST DATA XLT CLK LOCK
TG1 TG2
IFB1 IFB6 BAL1 BAL4 TOG1 TOG4
TM1 TM7
PS1 PS4
FS1 FS4
DFCTO
LPFI 46 TEI 47 ATSC 48
E-F BALANCE WINDOW COMPARATOR ATSC WINDOW COMPARATOR TZC COMPARATOR TM1 DFCT
TZC
FZC
VCC VCC ISET
18 VCC
TM6
17 ISET
TZC 49
16 SL O 15 SL M TRACKING PHASE COMPENSATION
TDFCT 50
TG1 VCC CENTER VOLTAGE GENERATOR FZC COMPARATOR FOCUS PHASE COMPENSATION VCC VEE CHARGE UP FS1
TM5
VEE VCC TM7 TM4
VC 51 FZC 52
DFCT
FS4
FS2 FSET TG2 TM3
VEE 1 FEO 2 FEI 3 FDFCT 4 FGD 5 FLB 6 FE O 7 FE M 8 SRCH 9 TGU 10 TG2 11 FSET 12 TA M
VEE 13 TA O
43
+ TM2 +
14 SL P
IC52
OUT1 1
BA6287F
8 GND
VM 2
7 OUT2
DRIVER TSD
DRIVER
VCC 3
CONTROL LOGIC
6 VREF
POWER SAVE FIN 4 5 RIN
MAIN Board IC101 CXD2530Q
MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 WFCK TES5 EMPH TES6 VDD VSS EXCK SBSO SCOR DOUT C4M FSTT XTSL 71 70 69 68
80 79 78 77 76 75 74 73 72
NC VSS VDD NC TES7 NC VSS XVDD XTAI XTAO XVSS VSS NC TES8 NC VDD VSS NC NC XRST
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 LRCK 49 WDCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0
ERROR CORRECTOR EFM DEMODULATOR
D/A INTERFACE
ASYMMETRY CORRECTOR
16K RAM
DIGITAL OUT
DIGITAL PLL
SUB CODE PROCESSOR
OSC
CLOCK GENERATOR TIMING LOGIC SERVO AUTO SEQUENCER
CPU INTERFACE
DIGITAL CLV
1 2 3 4 5 6 VDD VSS LMUT RMUT TES2 CKOUT
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO
44
IC202
AT24C16N-10SI-TR
IC301
OUT1 1
BA6287F
8 GND
START STOP LOGIC
SERIAL EN CONTROL LOGIC LOAD COMP LOAD INC DATA WORD ADDR/COUNTER
X DEC
H.V. PUMP/TIMING 8 VCC DATA RECOVERY 7 TST
TSD VM 2 7 OUT2
DEVICE ADDRESS COMPARATOR A0 1 A1 2 A2 3 GND 4 R/W
DRIVER
DRIVER
6 SDL E2PROM 5 SDA
VCC 3 CONTROL LOGIC 6 VREF
Y DEC
SERIAL MUX
POWER SAVE FIN 4 5 RIN
DIN DOUT
DOUT/ACK LOGIC
IC302
BUS ON VCC
BA8272F-E2
DATA OUT LINK OFF CLK OUT DATA IN RESET
IC401
CXD2522Q
XEMP SDTO XSOE SCK SDTI XLT XRDE XWRE SPSL A4 A5 A6 A7 A8 XOE XCAS D2
40 39 38 37 36 35 34 33
51 50 49 48 47 46 45 44 43
42
41
14
13
12
11
10
9
8
XWIH AM4 AM3 AM2 AM1 AM0 VDD XQOK 52 53 54 55 56 57 58 59 CPU I/F 32 31 30 29 28 27 26 25 24 23 22 D3 D0 D1 XWE XRAS A9 VDD A0 A1 A2 A3
RESET SWITCH
ADDRESS MONITOR WRITE BASE COUNTER READ BASE COUNTER VWA DRAM I/F
1
BUS ON OUT
2
BUS ON IN
3
GND
4
BUS CLK
5
VREF
6
BUS DATA
7
BUS RESET
OSCE
VSS
SELECTOR TIMING GEN. GSCR 60 SCOR 61 NC 62 NC 63 NC 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DATA LINKING CONTROL DSP I/F
21 C176
DAC I/F
DIGITAL OUT
20 DOUT
GRST XRST WFCK DIN C4M XROI RFCK GTOP
BCKI VSS DATI LRCI WDCI TEST XTAO
XTAI
45
BCK DATA LRCK
IC402
MSM514400D-60TS-K
26 VSS 25 DQ4 24 DQ3
DQ1 DQ2 WE
1 2 3 WRITE CLOCK GENERATOR DATA INPUT BUFFER DATA OUTPUT BUFFER
CLOCK GENERATOR 2
COLUMN SENSE AMP DECODER I/O GATE
4M BIT MEMORY CELL ROW DECODER BOARD BIAS GENERATOR
23 CAS 22 OE
CLOCK GENERATOR 1
RAS
4
MODE CONTROL
PREADDRESS BUFFER DECODER
REFRESH ADDRESS COUNTER
A9 A0 A1 A2 A3 VCC
5 9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
IC502
KM62256DLG-7LT
IC601
LRCK
TC9464FN-EL
(EMP) SH DATA GNDX ZD (SM) ATT (BS) LA BCK HS MCK GNDD VDX XO XI
28 VCC 27 WE 26 25 24 23 A13 A8 A9 A11
24 23 22
21
20
19
18
17
16
15
14 13
INTERFACE CIRCUIT
MICROCOMPUTER INTERFACE CIRCUIT
OSC
A14 A12 A7 A6 A5
1 2 3 4 5
LEVEL SHIFT
BUFFER
ROW DECODER
MEMORY MATRIX 512X512
22 OE 21 A10
DIGITAL FILTER CIRCUIT ATTENUATOR OPERATIONAL CIRCUIT DEEMPHASIS FILTER CIRCUIT D- MODULATION CIRCUIT
TIMING GENERATOR
A4 A3 A2 A1 A0
6 7 8 9 10
LEVEL SHIFT
BUFFER
I/O GATE COLUMN DECODER
20 CE 19 18 17 16 15 I/O8 I/O7 I/O6 I/O5 I/O4
TEST CIRCUIT
OUTPUT CIRCUIT ANALOG FILTER
OUTPUT CIRCUIT ANALOG FILTER
GNDA
GNDA
VDD
VDA
GND 14
46
VDA
P/S
RO
VR
LO
T1
I/O1 11 I/O2 12 I/O3 13
LEVEL SHIFT
BUFFER
I/O BUFFER
1
2
3 4
5
6
7
8
9
10 11 12
7-13.
IC PIN FUNCTION DESCRIPTION
· MAIN BOARD IC201 CXP84332-210Q (SYSTEM CONTROLLER) Pin No. 1 to 3 4 5 6 7 8 9 10 11 12 13 to 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin Name -- CH.F CH.R LOAD2 LOAD1 SENS2 LIM.SW EE.INIT EE.CLK EE.DATA -- SINGLE XRST FOK SENS GFS GRSRT XQOK SDTI XSOE ESPXLT RST EXTAL XTAL VSS TX TEX AVSS AVREF MCK EHS MODEL XRDE XWRE A.MUTE EMP ML GRSCOR I/O O O O I I I I I O I/O O I O I I I O O I O O I I O -- O I -- I I I I O O O O O I Not used (open) Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) "L" active *1 Motor drive signal (save direction) output to the chucking motor drive (IC52) "L" active *1 Chucking end detect switch (SW11) input terminal "L": When completion of the disc chucking operation Save end detect switch (SW12) input terminal "L": When completion of the disc chucking operation Internal status signal (sense signal) input from the CXA1992BR (IC11) Sled limit in detect switch (SW1) input terminal "L": When the optical pick-up is inner position Initialize signal input for the EEPROM (IC202) "H": format Fixed at "L" in this set Serial data transfer clock signal output to the EEPROM (IC202) Two-way data bus with the EEPROM (IC202) Not used (open) Setting terminal for the single disc/multiple discs mode "L": single mode, "H": multiple discs mode (fixed at "H") System reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q (IC401) "L": reset Focus OK signal input from the CXA1992BR (IC11) "L": NG, "H": OK Internal status signal (sense signal) input from the CXD2530Q (IC101) Guard frame sync signal input from the CXD2530Q (IC101) "L": NG, "H": OK Reset signal output to the CXD2522Q (IC401) "L": reset Subcode Q OK pulse signal output to the CXD2522Q (IC401) "L" active ESP status signal input from the CXD2522Q (IC401) ESP status read enable signal output to the CXD2522Q (IC401) "L" active ESP latch pulse signal output to the CXD2522Q (IC401) "L" active System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" Main system clock input terminal (8 MHz) Main system clock output terminal (8 MHz) Ground terminal Sub system clock output terminal Not used (open) Sub system clock input terminal Not used (fixed at "L") Ground terminal (for A/D converter) Reference voltage (+5V) input terminal (for A/D converter) Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator position (A/D input) Elevator height position detect input from the RV202 (elevator height sensor) (A/D input) Setting terminal for the destination (fixed at "H" in this set) D-RAM read enable signal output to the CXD2522Q (IC401) "L" active D-RAM write enable signal output to the CXD2522Q (IC401) "L" active Audio line muting on/off control signal output terminal "H": muting on Emphasis mode output to the D/A converter (IC601) "H": emphasis on Fast speed dubbing control signal output to the D/A converter (IC601) "L": fast speed Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401) Function
47
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pin Name D/A.RESET SCK SI SO SCLK SUBQ -- C.OUT BUS.ON -- MGLK ELV.F -- MAG.SW BU.CHK W.UP SCOR EJECT CD.CLK CD.XLT CD.DATA CD.ON ELV.ON ELV.R -- VDD NC (VDD) BUSY RESET REQ CCCLK CSO CSI --
I/O O I I O O I O I I I I O O I I I I I O O O O O O O -- -- I O I O O I I
Function Reset signal output terminal "L": reset Not used (open) Serial data transfer clock signal input from the SONY bus interface (IC302) Serial data input from the SONY bus interface (IC302) Serial data output to the SONY bus interface (IC302) Subcode Q data reading clock signal output to the CXD2530Q (IC101) Subcode Q data input from the CXD2530Q (IC101) Not used (open) Track number count signal input from the CXA1992BR (IC11) Bus on/off control signal input from the SONY bus interface (IC302) "H": bus on Not used (open) Magazine eject operation completion detect switch (SW201) input "L": eject completed Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Magazine in/out detect switch (SW202) input "L": magazine detected Battery detection signal input terminal "H": battery on Bus on or eject switch (SW301) input terminal "H": bus on or eject switch pushing Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Eject switch (SW301) input terminal "H" active Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401) Serial data latch pulse signal output to the CXD2530Q (IC101) Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401) D/A converter and servo section power supply on/off control signal output "H": power on Mechanism deck section power supply on/off control signal output "H": power on Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Power supply terminal (+5V) Connected to the power supply (+5V) Busy monitor input from the CD text decoder (IC501) "L": busy status Reset signal output to the CD text decoder (IC501) "L": reset Data request signal input from the CD text decoder (IC501) "L" active Command clock signal output to the CD text decoder (IC501) Command data output to the CD text decoder (IC501) Command data input from the CD text decoder (IC501) Not used (open)
*1 chucking motor (M103) control Mode Terminal CH.F (pin 4) CH.R (pin 5) STOP "H" "H" LOAD CHUCKING "L" "H" SAVE "H" "L" BRAKE "L" "L"
*2 elevator motor (M104) control Mode Terminal ELV.F (pin %·) ELV.R (pin &º) STOP "H" "H" ELEVATOR ELEVATOR UP DOWN "L" "H" "H" "L" BRAKE "L" "L"
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· MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER) Pin No. 1, 2 3 4 5 6 7 8 9 10 11 to 18 19 Pin Name NC NC REQ CCLK CSI CSO SCLK SSI NC
ADD0 to ADD7
I/O O I O I I O O I O O I I/O I I O -- O O O O O O -- O I I O O I I I I Not used (open) Not used (fixed at "L")
Function
Request signal output to the system controller (IC201) "L" active Serial data transfer clock signal input from the system controller (IC201) Serial data input from the system controller (IC201) Serial data output to the system controller (IC201) Clock signal output for subcode data reading to the CXD2530Q (IC101) Subcode data input from the CXD2530Q (IC101) Not used (open) Address signal output to the S-RAM (IC502) Not used (fixed at "L") Two-way data bus with the S-RAM (IC502) System reset signal input from the system controller (IC201), SONY bus interface (IC302) and reset signal generator (IC304) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" System clock input terminal (10 MHz) System clock output terminal (10 MHz) Ground terminal Not used (open) Busy signal output to the system controller (IC201) "L": busy status Not used (open) Chip enable signal output to the S-RAM (IC502) "L" active Data write enable signal output to the S-RAM (IC502) "L" active Address signal output to the S-RAM (IC502) Power supply terminal (+5V) Not used (open) Not used (fixed at "L") Not used (fixed at "H") Address signal output to the S-RAM (IC502) Not used (open) Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101) Backup power supply detection signal input terminal (used also to reset standby) Not used (fixed at "L")
NC
20 to 27 DATA0 to DATA7 28 29 30 31 32 to 55 56 57 to 61 62 63 64 to 69 70 71 72 73 74 75 76 77 78 79, 80 RST EXTAL XTAL VSS NC BUSY NC CE WE
ADD8 to ADD13
VDD NC NC NC ADD14 NC SCOR WFCK BUCK NC
49