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CDX-605
SERVICE MANUAL
US Model
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
CDX-505RF MG-250C-137 KSS-521A/J2N
SPECIFICATIONS
System Frequency response Wow and flutter Signal-to-noise ratio Outputs Current drain Operating temperature Dimensions Compact disc digital audio system 10 20,000 Hz Below the measurable limit 94 dB BUS control output (8 pins) Analog audio output (RCA pin) 800 mA (during CD playback) 800 mA (during loading or ejecting a disc) 10 °C to + 55 °C (14 °F to 131 °F) Approx. 262 × 90 × 181.5 mm (103/8 × 35/8 × 71/4 in.) (w/h/d) not incl. projecting parts and controls Approx. 2.1 kg (4 lb 10 oz) 12 V DC car battery (negative ground) Disc magazine (1) Parts for installation and connections (1 set)
Mass Power requirement Supplied accessories
Design and specifications subject to change without notice.
COMPACT DISC CHANGER
MICROFILM
CDX-605
7-3. SCHEMATIC DIAGRAM RF Section · See page 17 for Waveforms. · See page 31 for IC Block Diagrams.
(Page 27)
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CDX-605
7-6. SCHEMATIC DIAGRAM MAIN Section (1/2) · See page 17 for Waveforms. · See page 31 for IC Block Diagrams.
(Page 22)
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CDX-605
7-7. SCHEMATIC DIAGRAM MAIN Section (2/2) · See page 17 for Waveforms. · See page 31 for IC Block Diagrams.
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CDX-605
· IC Block Diagrams IC11 CXA1992BR (RF BOARD)
RF_M RF_O RFTC RF_I PD2 PD1 CC1 CC2 FOK PD CP CB LD
IC52 BA6287F (RF BOARD) IC301 BA6287F (MAIN BOARD)
OUT1 1 8 GND
39
38
37 VEE
36
35
34
33
32
31
30
29
28
27
+
+
PD2 IV AMP FE_BIAS 40
APC VEE
+
F 41
LASER POWER CONTROL F IV AMP
+ +
E 42
+
VCC
FE AMP
+ +
E IV AMP EI 43
+
+ +
IFB4
IFB2
IFB3
IFB5
BAL1
BAL2
BAL3
BAL4
IFB1
IFB6
TOG1
TOG2
TOG3
TOG4
VEE 44
VEE
TGFL
VEE
+
FO. BIAS WINDOW COMP.
TEO 45
+
MIRR
LPCL
TGFL
LPC
CC1
LPFI 46
+
+
E-F BALANCE WINDOW COMP.
DFCT1
LDON
+
80 79 78 77 76 75 74 73 72
20 CLK
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TEI 47
+
ATSC 48
+
FOH FOL TGH TGL BALH BALL ATSC TZC FZC
MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9
WFCK TES5 EMPH
TES6 VDD VSS EXCK SBSO SCOR
DOUT C4M FSTT XTSL
+
TRK. GAIN WINDOW COMP.
ATSC WINDOW COMP.
+
TZC 49
TZC COMP. TDFCT 50 VCC
DFCT TM1
TG1
TRACKING PHASE COMPENSATION
VC 51
VCC FZC 52
+
VEE
VDD VSS LMUT RMUT TES2 CKOUT
FS2 Charge up TG2
+
TM2
DFCT FZC COMP. FS4
FSET
VEE 1 2 3 4 5 6 7 8 9 10 11 12 13
FEO
FEI
FDFCT
FGD
FLB
FE_O
FE_M
SRCH
TGU
TG2
FSET
TA_M
31
TA_O
32
XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI
SQCK SQSO SENS DATA XLAT
CLOK SEIN CNIN DATO
VEE
+
VEE
+
FOCUS PHASE COMPENSATION
+
+
VCC
+
+
+
+
PD1 IV AMP
+ + +
RF SUMMING AMP
VM 2
+
7 OUT2
DRIVER 26 SENS2 TSD
DRIVER
VCC 3 IIL TTL
+
CONTROL LOGIC
6 VREF
25 SENS1 POWER SAVE 24 C. OUT FIN 4 5 RIN
VCC VCC
VEE
+
+
DFCT
23 XRST
VEE LEVEL S
FOK
+ +
VEE 22 DATA
+ +
VCC
MIRR
IIL TTL
IC101
TTL IIL 21 XLT
CXD2530Q (MAIN BOARD)
IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER VCC
19 LOCK
18 VCC
DFCTO
IFB1-6 BAL1-4 TOG1-4
FS1-4
TG1-2
TM1-7
PS1-4 ISET 17 ISET
VCC TM4 TM6
VCC 16 SL_O
15 SL_M VCC FS1 TM7 TM3 TM5 14 SL_P
NC VSS VDD NC TES7 NC VSS XVDD XTAI XTAO XVSS VSS NC TES8 NC VDD VSS NC NC XRST
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 LRCK 49 WDCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0
ERROR CORRECTOR EFM DEMODULATOR
D/A INTERFACE
ASYMMETRY CORRECTOR
16K RAM
DIGITAL OUT
DIGITAL PLL
SUB CODE PROCESSOR
OSC
CLOCK GENERATOR TIMING LOGIC SERVO AUTO SEQUENCER
CPU INTERFACE
DIGITAL CLV
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IC102
LRCI 1 BCKI 2 DI 3
SM5852FS-E2 (MAIN BOARD)
16 15 14 13 DB/DS MOD2 MOD1 OPT
IC204
BUS ON VCC
BA8272F-E2 (MAIN BOARD)
DATA OUT LINK OFF CLK OUT DATA IN RESET
INPUT INTERFACE
DIGITAL SIGNAL PROCESSOR
14
13
12
11
10
9
8
CLK 4 VSS 5 RSTN 6 TESTN 7 MUTEN 8
SYSTEM CLOCK
12 VDD
RESET SWITCH
SEQUENTIAL CONTROL MUTE CONTROL
OUTPUT INTERFACE
11 LRCO 10 BCKO 9 DOUT
1
BUS ON OUT
2
BUS ON IN
3
GND
4
BUS CLK
5
VREF
6
BUS DATA
7
BUS RESET
MODE CONTROL
IC401
LRCK
TC9464FN-EL (MAIN BOARD)
(EMP) SH GNDX ZD DATA (SM) ATT (BS) LA MCK GNDD VDX BCK HS XO
16
24 23 22
21
20
19
18
17
15
XI VDA
14 13
INTERFACE CIRCUIT
MICROCOMPUTER INTERFACE CIRCUIT
OSC
DIGITAL FILTER CIRCUIT ATTENUATOR OPERATIONAL CIRCUIT DEEMPHASIS FILTER CIRCUIT D- MODULATION CIRCUIT
TIMING GENERATOR
TEST CIRCUIT
OUTPUT CIRCUIT ANALOG FILTER
OUTPUT CIRCUIT ANALOG FILTER
1
2
3 4
5
6
7
8
9
10 11 12
T1
GNDA
GNDA
VDD
P/S VDA
RO
VR
LO
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7-8. IC PIN FUNCTION DESCRIPTION
· MAIN BOARD IC302 CXP84124-078Q (SYSTEM CONTROLLER) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 to 23 24 25 to 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46, 47 48 49 Pin Name LIM.SW BUSON EJECT LOAD1 LOAD2 A.MUTE EMPH CH.R CH.F -- ELV.R ELV.ON CD RST CDON -- AUTO ON/OFF -- RESET EXTAL XTAL VSS TX TEX AVSS AVREF ATRIBT MCK EHS H.TEMP -- MODE1 MODE2 MODE3 -- SCK SI I/O I I I I I O O O O O O O O O O I O I I O -- O I -- I I I I I O O O O O I I Function Sled limit in detect switch (SW1) input terminal "L": When the optical pick-up is inner position Bus on/off control signal input from the SONY bus interface (IC204) "H": bus on Eject switch (SW303) input terminal "H" active Save end detect switch (SW12) input terminal "L": When completion of the disc chucking operation Chucking end detect switch (SW11) input terminal "L": When completion of the disc chucking operation Audio line muting on/off control signal output terminal "H": muting on Emphasis mode output to the D/A converter (IC401) "L": emphasis on Motor drive signal (save direction) output to the chucking motor drive (IC52) "H" active *1 Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) "H" active *1 Not used (open) Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) "L" active *2 Mechanism deck section power supply on/off control signal output "H": power on System reset signal output to the CXA1992AR (IC11), CXD2530Q (IC101) and SM5852FS (IC102) "L": reset D/A converter and servo section power supply on/off control signal output "H": power on Not used (open) Setting terminal for the automatic adjustment "L": automatic adjustment, "H": manual adjustement (solder across the BP302 terminal) Normally: fixed at "L" Not used (open) System reset signal input from the reset signal generator (IC202) and SONY bus interface (IC204) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" Main system clock input terminal (8 MHz) Main system clock output terminal (8 MHz) Ground terminal Sub system clock output terminal Not used (open) Sub system clock input terminal Not used (fixed at "L") Ground terminal (for A/D converter) Reference voltage (+5V) input terminal (for A/D converter) Selection input of the custom file, D-BASS, etc. Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator position (A/D input) Elevator height position detect input from the RV302 (elevator height sensor) (A/D input) High temperature sensor input terminal Not used (open) Not used (open) D-BASS control signal output to the SM5852FS (IC102) D-BASS control signal output to the SM5852FS (IC102) D-BASS control signal output Not used (open) Not used (open) Serial data transfer clock signal input from the SONY bus interface (IC204) Serial data input from the SONY bus interface (IC204)
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Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 to 80
Pin Name SO SQCLK SUBQ -- -- MGLK SCOR SENS2 PWM -- MAG.SW BUCHECK W.UP C.OUT EEDATA EECLK EEINIT -- SINGLE FOK GFS SENS1 VDD NC (VDD) CDCLK CDXLT CDDATA --
I/O O O I O I I I I O O I I I I I/O O I O I I I I -- -- O O O O
Function Serial data output to the SONY bus interface (IC204) Subcode Q data reading clock signal output to the CXD2530Q (IC101) Subcode Q data input from the CXD2530Q (IC101) Not used (open) Not used (fixed at "H") Magazine eject operation completion detect switch (SW301) input terminal "L": eject completed Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Internal status signal (sense signal) input from the CXA1992AR (IC11) Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Magazine in/out detect switch (SW302) input terminal "L": magazine detected Battery detection signal input terminal "H": battery on Bus on or eject switch (SW303) input terminal "H": bus on or eject switch pushing Track number count signal input from the CXA1992AR (IC11) Two-way data bus with the EEPROM Not used (open) Serial clock signal output to the EEPROM Not used (open) Initialize signal input for the EEPROM "H": format Fixed at "L" in this set Not used (open) Setting terminal for the single disc/multiple discs mode "L": single mode, "H": multiple discs mode (fixed at "H") Focus OK signal input from the CXA1992AR (IC11) "L": NG, "H": OK Guard frame sync signal input from the CXD2530Q (IC101) "L": NG, "H": OK Internal status signal (sense signal) input from the CXD2530Q (IC101) Power supply terminal (+5V) Connected to the power supply (+5V) Serial data transfer clock signal output to the CXD2530Q (IC101) Serial data latch pulse signal output to the CXD2530Q (IC101) Serial data output to the CXD2530Q (IC101) Not used (open)
*1 chucking motor (M103) control Mode Terminal CH.F (pin 9) CH.R (pin 8) STOP "L" "L" LOAD CHUCKING "H" "L" SAVE "L" "H" BRAKE "H" "H"
*2 elevator motor (M104) control Mode Terminal PWM (pin %·) ELV.R (pin !¡) STOP "H" "H" ELEVATOR ELEVATOR UP DOWN "L" "H" "H" "L" BRAKE "L" "L"
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