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NT7534
132 X 65 RAM-Map STN LCD
Controller/Driver
V1.0




With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
Revision History....................................................................................................................................3

Features .................................................................................................................................................4

General Description..............................................................................................................................4

Pad Configuration.................................................................................................................................5

Block Diagram.......................................................................................................................................6

Pad Descriptions...................................................................................................................................7

Functional Descriptions .....................................................................................................................12

Commands ..........................................................................................................................................27

Command Description........................................................................................................................43

Absolute Maximum Rating.................................................................................................................46

Electrical Characteristics ...................................................................................................................46

Microprocessor Interface (for reference only) .................................................................................55

Bonding Diagram ................................................................................................................................62

Package Information...........................................................................................................................67

Ordering Information ..........................................................................................................................68




2 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Revision History

NT7534 Specification Revision History

Version Content Date

1.0 Released Dec. 2004




2004/12/06 3 Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Features
132 x 65-dot graphics display LCD controller/driver for black/white STN LCD
RAM capacity: 132 x 65 = 8,580 bits
8-bit parallel bus interface for both 8080 and 6800 series,
4-wire Serial Peripheral Interface (SPI)
Direct RAM data display using the display data RAM.
When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed.
(At normal display)
Many command functions:
Read/Write display data, display ON/OFF, Normal/Reverse display, page address set, display start
line set, LCD bias set, electronic contrast controls, V0 voltage regulation internal resistor ratio set,
read modify write, segment driver direction select, power save.
Other command functions:
Partial display, partial start line set, N-Line inversion.
Power supply voltage:
- VDD = 1.8 ~ 3.6 V
- VDD2 = 1.8 ~ 3.6 V
- V0 = 4.0 ~ 14.2 V
- VOUT = 14.2 V Max.
2X / 3X / 4X / 5X on chip DC-DC converter
On chip LCD driving voltage generator or external power supply selectable
64-step contrast adjuster and on chip voltage follower
On chip oscillation and hardware reset

General Description
The NT7534 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly
connectable to a microcomputer bus. It accepts 8-bit parallel or serial display data directly sent from a
microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent
of the microprocessor clock.
The set of the on-chip display RAM of 65 x 132 bits and a one-to-one correspondence between LCD
panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of
freedom. The NT7534 contain 65 common output circuits and 132 segment output circuits, so that a
single chip of NT7534 can make maximum 65 x 132 or 49 x 132 or 33 x 132 dots display with the pad
option (DUTY1, DUTY0).
No external operation clock is required for RAM read/write operations. Accordingly, this driver can be
operated with a minimum current consumption and its on-board low-current-consumption liquid crystal
power supply can implement a high-performance handy display system with minimum current
consumption and the smallest LSI configuration.




2004/12/06 4 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Pad Configuration




2004/12/06 5 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Block Diagram

SEG0 SEG131 COM0 COM63 COMS
VDD, VDD3
VSS, VSS3

V0
V1




COM S
V2 Common
V3 Segment driver
V4 driver
VSS2


Shift register
CAP1+
CAP1-
CAP2+
CAP2-
CAP3+ Power Supply
CAP4+ Circuit Display data latch

VOUT




Initial display line register
VDD2




line address decoder
VR
I/O buffer circuit




Line counter
VSS2
132*65-dot
IRS display data RAM
/HPM Output status
selector circuit



Column address decoder

Page address
register
DUTY0
8-bit column address counter
DUTY1

Display timing FRS
generator FR
circuit CL

/DOF
M/S



Bus holder Command decoder Bus holder Oscillator CLS




Microprocessor interface I/O buffer




/CS 1 CS2 A0 /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D1 D0
(E) (R/W) (SI) (SCL)




2004/12/06 6 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Pad Descriptions
Power Supply
Pad No. Designation I/O Description
42 ~ 44 VDD Power supply input. These pads must be connected to each
Supply
45 VDD3 other.

These are the power supply pads for the step-up voltage
46 ~ 49 VDD2 Supply circuit for the LCD. These pads must be connected to each
other.
16, 22,
VDD O Power supply output for pad option
97,103,107
50 ~ 52 VSS
Supply Ground. These pads must be connected to each other.
53 VSS3

54 ~ 57 VSS2 Supply Ground. These pads must be connected to each other.

13, 40,
VSS O Ground output for pad option.
100, 105

LCD driver supplies voltages. The voltage determined by the
94, 95 V0 LCD cell is impedance-converted by a resistive driver or an
operation amplifier for application. Voltages should be
according to the following relationship:
V0 V1 V2 V3 V4 VSS2
86, 87 V1 When the on-chip operating power circuit is on, the following
voltages are supplied to V1 to V4 by the on-chip power circuit.
Voltage selection is performed by the LCD Bias Set command.

88, 89 V2 I/O LCD bias V1 V2 V3 V4
1/4 bias 3/4V0 2/4V0 2/4V0 1/4V0
1/5 bias 4/5V0 3/5V0 2/5V0 1/5V0
90, 91 V3 1/6 bias 5/6V0 4/6V0 2/6V0 1/6V0
1/7 bias 6/7V0 5/7V0 2/7V0 1/7V0
1/8 bias 7/8V0 6/8V0 2/8V0 1/8V0
92, 93 V4
1/9 bias 8/9V0 7/9V0 2/9V0 1/9V0

Note: VDD and VDD3 pads must be connected together.




2004/12/06 7 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

LCD Power Supply
Pad No. Designation I/O Description
70 ~ 73 C1- O Capacitor 1- pad for internal DC/DC voltage converter.
74 ~ 77 C1+ O Capacitor 1+ pad for internal DC/DC voltage converter.
82 ~ 85 C2- O Capacitor 2- pad for internal DC/DC voltage converter.
78 ~ 81 C2+ O Capacitor 2+ pad for internal DC/DC voltage converter.
66 ~ 69 C3+ O Capacitor 3+ pad for internal DC/DC voltage converter.
62 ~ 65 C4+ O Capacitor 4+ pad for internal DC/DC voltage converter.
59 ~ 61 VOUT I/O DC/DC voltage converter output
Voltage adjustment pad. Applies voltage between V0 and VSS
96 VR I
using a resistive divider.
Configuration Pad
Pad No. Designation I/O Description
Select the maximum LCD driver duty
DUTY1 DUTY0 LCD driver duty
DUTY0 0 0 1/33
39, 41 I
DUTY1 0 1 1/49
1 * 1/65




2004/12/06 8 Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

System Bus Connection
Pad No. Designation I/O Description
23, 24 D0 This is an 8-bit bi-directional data bus that connects to an 8-bit
25, 26 D1 or 16-bit standard MPU data bus.
27, 28 D2 When the serial interface is selected (P/S="L"), then D7
29, 30 D3 serves as the serial data input terminal (SI) and D6 serves as
I/O
31, 32 D4 the serial clock input terminal (SCL). At this time, D0 to D5 are
33, 34 D5 set to high impedance.
35, 36 D6 (SCL) When the chip select is inactive, D0 to D7 are set to high
37, 38 D7 (SI) impedance.
This is connected to the least significant bit of the normal MPU
address bus, and it determines whether the data bits are data
18 A0 I or a command.
A0 = "H": Indicate that D0 to D7 are display data
A0 = "L": Indicates that D0 to D7 are control data
When /RES is set to "L", the settings are initialized. The reset
17 /RES I
operation is performed by the /RES signal level
This is the chip select signal. When /CS1="L" and CS2="H",
14 /CS1
I then the chip select becomes active, and data/command I/O is
15 CS2
enabled.
When connected to an 8080 MPU, it is active LOW. This pad
is connected to the /RD signal of the 8080MPU, and the
/RD NT7534 data bus is in an output status when this signal is "L".
21 I
(E) When connected to a 6800 Series MPU, this is active HIGH.
This is used as an enable clock input of the 6800 series
MPU
When connected to an 8080 MPU, this is active LOW. This
terminal connects to the 8080 MPU /WR signal. The signals
on the data bus are latched at the rising edge of the /WR
/WR signal.
19 I
(R/W) When connected to a 6800 Series MPU, this is the read/write
control signal input terminal.
When R/W = "H": Read
When R/W = "L": Write
This is the MPU interface switch terminal
101 C86 I C86 = "H": 6800 Series MPU interface
C86 = "L": 8080 Series MPU interface




2004/12/06 9 Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

System Bus Connection (continuous)
Pad No. Designation I/O Description
This is the parallel data input/serial data input switch terminal
P/S = "H": Parallel data input
P/S = "L": Serial data input
The following applies depending on the P/S status:
P/S Data/Command Data Read/Write Serial Clock
"H" A0 D0 to D7 /RD, /WR -
102 P/S I
"L" A0 SI (D7) Write only SCL (D6)

When P/S = "L", D0 to D5 are HZ. D0 to D5 may be "H", "L" or
Open. /RD (E) and /WR (R/W) are fixed to either "H" or "L".
With serial data input, RAM display data reading is not
supported.
Terminal to select whether enable or disable the display clock
internal oscillator circuit.
CLS = "H": Internal oscillator circuit for display is enabled
99 CLS I
CLS = "L": Internal oscillator circuit for display is disabled
(requires external input)
When CLS = "L", input the display clock through the CL pad.
This terminal selects the master/slave operation for the
NT7534 chips. Master operation outputs the timing signals
98 M/S I that are required for the LCD display, while slave operation
inputs the timing signals required for the liquid crystal display,
synchronizing the liquid crystal display system.
This is the display clock input terminal. When the NT7534
11 CL I/O chips are used in master/slave mode, the various CL terminals
must be connected.
This is the liquid crystal alternating current signal I/O terminal
M/S = "H": Output
10 FR I/O M/S = "L": Input
When the NT7534 chip is used in master/slave mode, the
various FR terminals must be connected.
This is the liquid crystal display blanking control terminal.
M/S = "H": Output
12 /DOF I/O M/S = "L": Input
When the NT7534 chip is used in master/slave mode, the
various /DOF terminals must be connected.
This is the output terminal for the static drive. This terminal is
only enabled when the static indicator display is ON in master
9 FRS O
operation mode, and is used in conjunction with the FR
terminal


2004/12/06 10 Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

System Bus Connection (continuous)
Pad No. Designation I/O Description
This terminal selects the resistors for the V0 voltage level
adjustment.
IRS = "H", Use the internal resistors
IRS = "L", Do not use the internal resistors
106 IRS I The V0 voltage level is regulated by an external resistive
voltage divider attached to the VR terminal. This pad is
enabled only when the master operation mode is selected. It
is fixed to either "H" or "L" when the slave operation mode is
selected
This is the power control terminal for the power supply circuit
for liquid crystal drive.
/HPM = "H", Normal power mode
104 /HPM I /HPM = "L", High power mode
This pad is enabled only when the master operation mode is
selected and it is fixed to either "H" or "L" when the slave
operation mode is selected.
Liquid Crystal Drive Pads
Pad No. Designation I/O Description
145 ~ 276 SEG0 - 131 O Segment signal output for LCD display.
133 ~ 143 COM10 ­ 0
117 ~ 130 COM24 ­ 11
108 ~ 114 COM31 ­ 25 Common signal output for LCD display. When in master/slave
O
277 ~ 288 COM32 ­ 43 mode, the same signal is output by both master and slave
291 ~ 304 COM44 ­ 57
2~7 COM58 ­ 63
These are the COM output terminals for the indicator. Both
terminals output the same signal. Do not connect these
8, 144 COMS O
terminals if they are not used. When in master/slave mode,
the same signal is output by both master and slave.
Test Pad
Pad No. Designation I/O Description
20 TEST0
I Test pads. No connection.
58 TEST1
No Connected Pad
Pad No. Designation I/O Description
1, 115, 116,
131, 132,
DUMMY - Dummy pads, No connection.
289, 290,
305


2004/12/06 11 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534


Functional Descriptions
Microprocessor Interface
Interface Type Selection
The NT7534 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI).
When high or low is selected for the parity of P/S pad either 8-bit parallel data input or serial data input
can be selected as shown in Table 1. When serial data input is selected, the RAM data cannot be read
out.
Table 1
P/S Type /CS1 CS2 A0 /RD /WR C86 D7 D6 D0 to D5
H Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D0 to D5
L Serial Input /CS1 CS2 A0 - - - SI SCL (HZ)
"-" Must always be high or low
Parallel Interface
When the NT7534 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series
microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2.
Table 2
C86 Type /CS1 CS2 A0 /RD /WR D0 to D7
H 6800 microprocessor bus /CS1 CS2 A0 E R/W D0 to D7
L 8080 microprocessor bus /CS1 CS2 A0 /RD /WR D0 to D7

Data Bus Signals
The NT7534 identifies the data bus signal according to A0, E, R/W (/RD, /WR) signals.
Table 3
Common 6800 processor 8080 processor
Function
A0 (R/W) /RD /WR
1 1 0 1 Reads display data
1 0 1 0 Writes display data
0 1 0 1 Reads status
0 0 1 0 Writes control data in internal register. (Command)




2004/12/06 12 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

Serial Interface
When the serial interface has been selected (P/S = "L"), then when the chip is in active state (/CS1 =
"L" and CS2 = "H"), the serial data input (SI) and the serial clock input (SCL) can be received. The
serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through
D0, in this order. This data is converted to 8 bits of parallel data in the rising edge of eighth serial clock
for processing.
The A0 input is used to determine whether or not the serial data input is display data, and when A0 =
"L" then the data is command data. The A0 input is read and used for detection of every 8th rising
edge of the serial clock after the chip becomes active. Figure 1 is the serial interface signal chart.
Figure 1

CS /CS1 = "L" and CS2 = "H"


SI

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4

SCL
1 2 3 4 5 6 7 8 9 10 11 12
A0

Note:
1. When the chip is not active, the shift registers and the counters are reset to their initial states.
2. Reading is not possible while in serial interface mode.
3. Caution is required on the SCL signal when it comes to line-end reflections and external noise.
We recommend that the operation can be rechecked on the actual equipment.
Chip Select Inputs
The NT7534 has two chip-select pads. /CS1 and CS2 can interface to a microprocessor when /CS1 is
low and CS2 is high. When these pads are set to any other combination. D0 to D7 are high impedance
and A0, E and R/W inputs are disabled. When serial input interface is selected, the shift register and
counter are reset.
Access to Display Data RAM and Internal Registers
The NT7534 can perform a series of pipeline processing between LSI's using the bus holder of the
internal data bus in order to match the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data from display RAM in the first read
(dummy) cycle, stores it in the bus holder, and outputs it onto the system bus in the next data read
cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in
display RAM until the next data write cycle starts.
When viewed from the microprocessor, the NT7534 access speed greatly depends on the cycle time
rather than access time to the display RAM (tACC). This view shows that the data transfer speed to /
from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert
the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the
display RAM read sequence. When an address is set, the specified address data is NOT output at the
immediately following read instruction. The address data is output during the second data read. A
single dummy read must be inserted after address setup and after the write cycle (refer to Figure 2).

2004/12/06 13 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

Figure 2


A0

MPU
E

R/W


DATA N N n n+1

Address preset


Read signal
Internal
timing
Preset Incremented
Column address N N+1 N+2


BUS holder N n n+1 n+2
Set address n Dummy read Data Read address n Data Read address n+1




Busy Flag
When the busy flag is "1" it indicates that the NT7534 chip is running internal processes, and at this
time no command aside from a status read will be received. The busy flag is outputted to D7 pad with
the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag
before each command. This makes vast improvements in MPU processing capabilities possible.
Display Data RAM
The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8
bit+1)*132 bit structure. It is possible to access the desired bit by specifying the page address and the
column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU
corresponds to the liquid crystal display common direction, there are few constraints at the time of
display common direction, and there are few constraints at the time of display data transfer when
multiple NT7534 chips are used, thus display structures can be created easily with a high degree of
freedom.
Moreover, reading from and writing to the display RAM from the MPU side is performed through the
I/O buffer, which is an independent operation from signal reading for the liquid crystal driver.
Consequently, even if the display data RAM is accessed asynchronously during the liquid crystal
display, it will not cause adverse effects on the display (such as flickering).
Figure 3

D0 0 1 1 1 0 COM0
D1 1 0 0 0 0 COM1
D2 0 0 0 0 0 COM2
D3 0 1 1 1 0 COM3
D4 1 0 0 0 0 COM4


Display data RAM Display on LCD

2004/12/06 14 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

The Page Address Circuit
As shown in Figure 4, page address of the display data RAM is specified through the Page Address
Set Command. The page address must be specified again when changing pages to perform access.
Page address8 (D3, D2, D1, D0 = 1, 0, 0, 0,) is the page for the RAM region used; only display data
D0 is used.
The Column Address
As shown in Figure 4, the display data RAM column address is specified by the Column Address Set
command. The specified column address is incremented (+1) with each display data read / write
command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination
of column addresses stops with 83H, because the column address is independent of the page address.
Thus, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to
specify both the page address and the column address.
Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command)
can be used to reverse the relationship between the display data RAM column address and the
segment output. Because of this, the constraints on the IC layout when the LCD module is assembled
can be minimized.
Table 4

SEG Output SEG0 SEG131

ADC "0" 0 (H) Column Address 83 (H)

(ADC) "1" 83 (H) Column Address 0 (H)

The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the line address relating to the COM output
when the contents of the display data RAM are displayed. Using the display start line address set
command, what is normally the top line of the display can be specified. This is the COM0 output when
the common output mode is normal and the COM63 output for NT7534, when the common output
mode is reversed. The display area is a 65-line area for the NT7534 from the display start line address.
If the line addresses are changed dynamically using the display start line address set command,
screen scrolling, page swapping, etc. can be performed.
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data that is output to the
liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status,
display ON/OFF status, and display all points ON/OFF commands control only the data within the latch,
they do not change the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when
M/S = "H" and CLS = "H". When CLS = "L" the oscillation stops, and the display clock is input through
the CL terminal.




2004/12/06 15 Ver 1.0
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information.
NT7534

Figure 4. Relationship between display data RAM and address. (if initial display line is 1DH)

Line COM
Page Address Data
Address output
D0 00 COM0
D1 01 COM1
D2 02 COM2
D3, D2, D1, D0 D3 03 COM3
0, 0, 0, 0 D4 Page0 04 COM4
D5 05 COM5
D6 06 COM6
D7 07 COM7
D0 08 COM8
D1 09 COM9
D2 0A COM10
D3 0B COM11
0, 0, 0, 1 Page1
D4 0C COM12
D5 0D COM13
D6 0E COM14
D7 0F COM15
D0 10 COM16
D1 11 COM17
D2 12 COM18
D3 13 COM19
0, 0, 1, 0 Page2
D4 14 COM20
D5 15 COM21
D6 16 COM22
D7 17 COM23
D0 18 COM24
D1 19 COM25
D2 1A COM26
D3 1B COM27
0, 0, 1, 1 Page3
D4 1C COM28
D5 1D COM29
D6 1E Start
COM30
D7 1F COM31
D0 20 COM32
D1 21 COM33
D2 22 COM34
D3 23 COM35
0, 1, 0, 0 Page4
D4 24 COM36
D5 25 COM37
D6 26 COM38
D7 27 COM39
D0 28 COM40
D1 29 COM41
D2 2A COM42
D3 2B COM43
0, 1, 0, 1 Page5
D4 2C COM44
D5 2D COM45
D6 2E COM46
D7 2F COM47
D0 30 COM48
D1 31 COM49
D2 32 COM50
D3 33 COM51
0, 1, 1, 0 Page6
D4 34 COM52
D5 35 COM53
D6 36 COM54
D7 37 COM55
D0 38 COM56
D1 39 COM57
D2 3A COM58
D3 3B COM59
0, 1, 1, 1 Page7
D4 3C COM60
D5 3D COM61
D6 3E COM62
D7 3F COM63
1, 0, 0, 0 D0 Page8 COMS
D0=0

00
01
02




81
82
83
address
Column




ADC
D0=1

83
82
81




02
01
00
SEG129
SEG130
SEG131
SEG0
SEG1
SEG2
OUT
LCD




2004/12/06 16 Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534

Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the
display data latch circuit using the display clock. The display data is latched into the display data latch
circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to
the display data liquid crystal driver circuits is completely independent of access to the display data
RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during
liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display.
Moreover, the display timing generator circuit generates the common timing and the liquid crystal
alternating current signal (FR) from the display clock. It generates a drive waveform using a 2 frames
alternating current drive method, as shown in Figure 5, for the liquid crystal drive circuit.
Figure 5
64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6
CL


FR


V0
COM0 V1

V4
VSS

V0
V1
COM1
V4
VSS


RAM
data

V0
SEGn V2
V3
VSS

When multiple NT7534 chips are used, the slave chip must be supplied with the display timing signals
(FR, CL, /DOF) from the master chip. Table 5 shows the status of the FR, CL, and /DOF signals.
Table 5
Operating Mode FR CL /DOF
Master The internal display oscillator is enabled (CLS = "H") Output Output Output
(M/S = "H") The internal display oscillator is disabled (CLS = "L") Output Input Output
Slave The internal display oscillator is disabled (CLS = "H") Input Input Input
(M/S = "L") The internal display oscillator is disabled (CLS = "L") Input Input Input




2004/12/06 17 Ver 1.0
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