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Versatile signal processor for lowand
mid-range TV applicationsversatile signal processor for lowand mid-range TV pplications
pls need manual service of PM5518 Pm54185 or shemas
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INTEGRATED CIRCUITS
DEVICE SPECIFICATION DATA SHEET
UOCIII series DIFFERENCES SSDIP90<-->QFP128 Versatile signal processor for lowand mid-range TV applications
Preliminary specification File under Integrated Circuits, Version: 1.02 2004 Jan 19 Previous date: 2003 Oct 09
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
GENERAL DESCRIPTION The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed Caption decoder. In addition the following functions can be added: · Adaptive digital (4H/2H) PAL/NTSC combfilter · Teletext decoder with 10 page text memory · Multi-standard stereo decoder · BTSC stereo decoder · Digital sound processing circuit · Digital video processing circuit The UOCIII series consists of the following 3 basic concepts: · Stereo versions. These versions contain the TV processor with a stereo audio selector, the TCG µ-Controller, the multi-standard stereo or BTSC decoder, the digital sound processing circuit and the digital video processing circuit. Options are the adaptive digital PAL/NTSC comb filter and a teletext decoder with 10 page text memory. · AV stereo versions. These versions contain the TV processor with stereo audio selector and the TCG µ-Controller. Options are the digital sound processing circuit, the digital video processing circuit, the adaptive digital PAL/NTSC comb filter and a teletext decoder with a 10 page text memory. · Mono sound versions. These versions contain the TV processor with a selector for mono audio signals and the TCG µ-Controller. Options are the adaptive digital PAL/NTSC combfilter and a teletext decoder with 10 page text memory. (NOT PLANNED FOR SSDIP90) The most important features of the complete IC series are given in the following feature lists. The exact feature content of the various ICs is given in Table 1 on page 8. The ICs are mounted in a QFP-128/SSDIP90 envelope(1) and can be used in economy television receivers with 90° and 110° picture tubes. They have supply voltages of 5V, 3.3V. Also an 1.8V supply is needed, but this can be simply derived by adding an emitter follower at a reference voltage from the device. UOCIII is supported by a comprehensive Global TV Software Development kit to enable easy programming and fast time-to-market (see also Chapter "LICENSE INFORMATION" on page 7.
(1) Both standard and "face down" versions of the QFP128 0.8mm pitch package are available. (SSDIP90 ONLY STANDARD PACKAGE AVAILABLE)
UOCIII series
FEATURES Analogue Video Processing (all versions) · Multi-standard vision IF circuit with alignment-free PLL demodulator · Internal (switchable) time-constant for the IF-AGC circuit · Switchable group delay correction and sound trap (with switchable centre frequency) for the demodulated CVBS signal · DVB/VSB IF circuit for preprocessing of digital TV signals. (FOR SSDIP90 SINGLE ENDED OUT ONLY) · Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as Y-input for Y/C signals. (2 FOR SSDIP90) However, only 2 Y/C sources can be selected because the circuit has 2 chroma inputs.(1 FOR SSDIP90) It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the YUV interface and the RGB/YPRPB input are not needed. (FOR SSDIP90 ADDITIONAL CVBSx INPUT AVAILABLE, NO YUV INTERFACE POSSIBLE) · Automatic Y/C signal detector · Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the chrominance signal. · Integrated luminance delay line with adjustable delay time · Picture improvement features with peaking (with switchable centre frequency, depeaking, variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone control, gamma control and blue- and black stretching. All features are available for CVBS, Y/C and RGB/YPBPR signals. · Switchable DC transfer ratio for the luminance signal · Only one reference (24.576 MHz) crystal required for the TCG µ-Controller, digital sound processor, Teletextand the colour decoder · Multi-standard colour decoder with automatic search system and various "forced mode" possibilities
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CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
· Internal base-band delay line · Indication of the Signal-to-Noise ratio of the incoming CVBS signal · Linear RGB/YPBPR input with fast insertion. · YUV interface. When this feature is not required some pins can be used as additional RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input (CVBS/YX and CX). (NOT FOR SSDIP90, ONLY ADDITIONAL CVBSx AVAILABLE) · Tint control for external RGB/YPBPR signals · Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages. · RGB control circuit with `Continuous Cathode Calibration', white point and black level off-set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. · Contrast reduction possibility during mixed-mode of OSD and Text signals · Adjustable `wide blanking' of the RGB outputs · Horizontal synchronization with two control loops and alignment-free horizontal oscillator · Vertical count-down circuit · Vertical driver optimized for DC-coupled vertical output stages · Horizontal and vertical geometry processing with horizontal parallelogram and bow correction and horizontal and vertical zoom · Low-power start-up of the horizontal drive circuit Analogue video processing (stereo versions) · The low-pass filtered `mixed down' I signal is available via a single ended or balanced output stage. (ONLY SINGLE ENDED FOR SSDIP90) Analogue video processing (mono versions) · The low-pass filtered `mixed down' I signal is available via a single ended output stage Digital Video Processing (some versions) · Double Window mode applications. It is possible to display a video and a text window or 2 text windows in parallel. · Linear and non-linear horizontal scaling of the video signal to be displayed. 2004 Jan 19 3
UOCIII series
Sound Demodulation (all versions) · Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation. · AM demodulator without extra reference circuit · The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this demodulator is optional for special applications. Normally the FM demodulators of the stereo demodulator/decoder part are used (see below).(FOR SSDIP90 STEREO AV+ VERSION, THE FM DEMOD of STEREO DEMOD/DEC. IS USED. FOR SSDIP90 STEREO, THE FM-PLL DEMOD IS USED) · The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second sound channel can be demodulated. In such an application it is necessary that an external bandpass filter is inserted. (ONLY POSSIBLE FOR SSDIP90 STEREO AT COST OF 1 FRONT-END VIDEO OUTPUT) · The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be demodulated.(ONLY FOR SSDIP90 STEREO) · Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF)(ONLY FOR SSDIP90 STEREO) Audio Interfaces and switching (stereo versions with Audio DSP) · Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R channel. Finally 1 stereo SPEAKER output with digital controls. ( FOR SSDIP90 STEREO AV+:3 STEREO AND 1 MONO INPUT, FOR SSDIP STEREO: 3 STEREO INPUTS) · AVL (Automatic Volume Levelling) circuit for the headphone channel. · Digital input crossbar switch for all digital signal sources and destinations · Digital output crossbar for exchange of channel processing functionality · Digital audio input interface (stereo I2S input interface) (NOT FOR SSDIP90 )
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
· Digital audio output interface (stereo I2S output interface) (NOT FOR SSDIP90) Audio interfaces and switching (AV stereo versions without Audio DSP) (FOR SSDIP90 NOT PLANNED) · Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo SPEAKER output with analogue volume control. · Analogue mono AVL circuit at left audio channel Audio interfaces and switching (mono versions) (NOT PLANNED FOR SSDIP90) · Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output · AVL circuit Stereo Demodulator and Decoder (full stereo versions) · Demodulator and Decoder Easy Programming (DDEP) · Auto standard detection (ASD) · Static Standard Selection (SSS) · DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation · NICAM decoding (B/G, I, D/K and L standard) · Two-carrier multistandard FM demodulation (B/G, D/K and M standard) · Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound · Adaptive de-emphasis for satellite FM · Optional AM demodulation for system L, simultaneously with NICAM · Identification A2 systems (B/G, D/K and M standard) with different identification time constants · FM pilot carrier present detector · Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option · BTSC MPX decoder · SAP decoder · dbx® noise reduction (3) · Japan (EIAJ) decoder · FM radio decoder · Soft-mute for DEMDEC outputs DEC, MONO and SAP · FM overmodulation adaptation option to avoid clipping and distortion
UOCIII series
Audio Multi Channel Decoder (stereo versions with Audio DSP) · Dolby® Pro Logic® (DPL) (1) · Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit this feature an external DAC is required.
(1) Dolby is a trademark of Dolby Laboratories
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CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
Volume and tone control for loudspeakers (stereo versions with Audio DSP) · Automatic Volume Level (AVL) control · Smooth volume control · Master volume control · Soft-mute · Loudness · Bass, Treble · Dynamic Bass Boost (DBB) (1) · Dynamic Virtual Bass (DVB) (2) · BBE® Sound processing (3) · Graphic equaliser · Processed or non processed subwoofer · Programmable beeper Reflection and delay for loudspeaker channels (stereo versions with Audio DSP) · Dolby® Pro Logic® Delay
(1)
UOCIII series
· Mode control for RDS/RBDS processing · Different RDS/RBDS block information output modes µ-Controller · 80C51 µ-controller core standard instruction set and timing · 0.4883 µs machine cycle · maximum of 256k x 8-bit flash programmable ROM · maximum of 8k x 8-bit Auxiliary RAM · 12-level Interrupt controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · One 24-bit Timer (16-bit timer with 8-bit Pre-scaler) · WatchDog timer · Auxiliary RAM page pointer · 16-bit Data pointer · Stand-by, Idle and Power Down modes · 24 general-purpose I/O pins (12 FOR SSDIP90) · 14 bits PWM for Voltage Synthesis Tuning · 8-bit A/D converter with 4 multiplexed inputs · 5 PWM (6-bits) outputs for analogue control functions (1FOR SSDIP90 ) · Remote Control Pre-processor (RCP) · Universal Asynchronous Receiver Transmitter (UART) Data Capture · Text memory up to 10 pages · Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) · Data Capture for US Closed Caption · Data Capture for 525/625 line WST, VPS (PDC system A) and 625 line Wide Screen Signalling (WSS) bit decoding · Automatic selection between 525 WST/625 WST · Automatic selection between 625 WST/VPS on line 16 of VBI · Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput · Automatic detection of FASTEXT transmission · Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters · Signal quality detector for video and WST/VPS data types
· Pseudo hall/matrix function Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (stereo versions with Audio DSP) · Extended Pseudo Stereo (EPS) (4) · Extended Spatial Stereo (ESS) (5) · Virtual Dolby® Surround (VDS 422,423) (1) · SRS 3D and SRS TruSurround®
(3)
RDS/RBDS (FOR SSDIP90 STEREO ONLY POSSIBLE WITH EXTERNAL FMRADIO DEMOD.) · Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data System (RBDS) signal · RDS and RBDS block detection · Error detection and correction · Fast block synchronisation · Synchronisation control (flywheel)
(1) Also referred to as "Dynamic UltraBass" (2) Also referred to as "Dynamic Bass Enhancement" (3) For the use of these products a licence is required. More details are given in the chapter "LICENSE INFORMATION" on page 7 (4) Also referred to as "I-Mono" or "Incredible Mono" (5) Also referred to as "I-Stereo" or "Incredible Stereo"
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CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
· Comprehensive teletext language coverage · Vertical Blanking Interval (VBI) data capture of WST data Display · Teletext and Enhanced OSD modes · Features of level 1.5 WST and US Close Caption · 50Hz/60Hz display timing modes · Two page operation for 16:9 screens · Serial and Parallel Display Attributes · Single/Double/Quadruple Width and Height for characters · Smoothing capability of both Double Size, Double Width & Double Height characters · Scrolling of display region · Variable flash rate controlled by software · Soft colours using CLUT with 4096 colour palette
UOCIII series
· Globally selectable scan lines per row (9/10/13/16/) and character matrix [12x9, 12x13, 12x16, 16x18, (VxH)] · Fringing (Shadow) selectable from N-S-E-W direction · Fringe colour selectable · Contrast reduction of defined area · Cursor · Special Graphics Characters with two planes, allowing four colours per character · 64 software redefinable On-Screen display characters · 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) · G1 Mosaic graphics, Limited G3 Line drawing characters · WST Character sets and Closed Caption Character set in single device · SVM for Text
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CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
LICENSE INFORMATION dbx
UOCIII series
dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For further information, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA. Tel: 1-508-478-9200, FAX: 1-508-478-0990 Dolby "Dolby", "Pro Logic" and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products are available to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103, USA, Tel: 1-415-558-0200, Fax: 1-415-863-1373 Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. BBE BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA. The use of BBE needs licensing from BBE Sound, Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728
The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporation and licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRS and TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chip TDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. Philips "Dynamic Ultra BassTM", "Dynamic Bass Enhancement", "I-Mono" and "I-Stereo" are denominators for Philips patented technologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but instead generic ones such as listed below. Generic name/ Philips name · Dynamic Virtual Bass (DVB)/Dynamic UltraBass · Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement · Extended Pseudo Stereo (EPS)/I-Mono · Extended Spatial Stereo (ESSI)/I-Stereo GTV Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V. Please contact your nearest Philips Semiconductors sales office for further details. 2004 Jan 19 7
CONFIDENTIAL
OVERVIEW OF THE VARIOUS VERSIONS
2004 Jan 19 8
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
Table 1
Overview of types COMB FILTER COLOUR DECODER STEREO FM RADIO MONO FM RADIO RDS/RBDS dbx® Dolby® ProLogic® Virtual Dolby® (VDS) SRS® 3D Stereo SRS® TruSurround BBETM DW / PANORAMA ROM SIZE (k) AUX RAM SIZE (k) DISPLAY RAM (k) DRCS RAM (k) SOUND SYSTEM NUMBER OF TELETEXT PAGES
TYPE NUMBER(1) STEREO AUDIO DECOMONO DSP DER TDA11000H/H1 TDA11001H/H1 TDA11010H/H1 TDA11011H/H1 TDA11020H/H1 TDA11021H/H1 TDA12000H/H1(2) BTSC(3) TDA12001H/H1(2) BTSC(3) TDA12006H/H1 TDA12007H/H1 TDA12008H/H1 TDA12009H/H1 TDA12010H/H1(2) TDA12011H/H1(2) TDA12016H/H1 TDA12017H/H1 TDA12018H/H1 TDA12019H/H1 TDA12020H/H1(2) TDA12021H/H1(2) TDA12026H/H1 TDA12027H/H1 TDA12028H/H1 TDA12029H/H1 TDA12060H/H1 BTSC(3) BTSC(3) BTSC(3) BTSC(3) MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI 0 10
NTSC NTSC MULTI MULTI MULTI MULTI NTSC NTSC NTSC NTSC NTSC NTSC MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI
128 128 128 128 128 128 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256
4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 10 10 2.25 2.25
CONFIDENTIAL
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25
Preliminary specification
10 10 10 10 10 10
2.25 2.25 2.25 2.25 2.25 2.25
UOCIII series
1.25 2.25
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Philips Semiconductors
COMB FILTER
COLOUR DECODER
STEREO FM RADIO
MONO FM RADIO
RDS/RBDS
dbx®
Dolby® ProLogic®
Virtual Dolby® (VDS)
SRS® 3D Stereo
SRS® TruSurround
BBETM
DW / PANORAMA
ROM SIZE (k)
AUX RAM SIZE (k)
DISPLAY RAM (k)
DRCS RAM (k)
SOUND SYSTEM TYPE NUMBER(1) STEREO AUDIO DECOMONO DSP DER TDA12061H/H1 TDA12062H/H1(2) TDA12063H/H1(2) TDA12066H/H1 TDA12067H/H1 TDA12068H/H1 TDA12069H/H1 TDA12070H/H1 TDA12071H/H1 TDA12072H/H1(2) TDA12073H/H1(2) TDA12076H/H1 TDA12077H/H1 TDA12078H/H1 TDA12079H/H1 Note
NUMBER OF TELETEXT PAGES
Versatile signal processor for low- and mid-range TV applications
0
10
MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI
128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 10 10 10 10 10 10 10 10 2.25 2.25 2.25 2.25 2.25 2.25 2.25 2.25
CONFIDENTIAL
1. The "standard" version is indicated with "H" and the "facedown" version with "H1" 2. For these versions the feature content can be found from the type number. More details are given in the next Section. 3. When the BTSC demodulation is active the EIAJ demodulation is also activated. Preliminary specification
UOCIII series
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
Type Number Definition and Feature Indication The complete type number of these versions is given below.
UOCIII series
TDA12000H1/N1VXY0AA
The explanation of the various parts of the type number is given below: · The first 8 characters indicate the type number, the last 2 characters vary depending on the version. · The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with "H" and the "face-down version" with "H1". · The first 3 characters after the slash (/) indicate the IC version. · The characters "X" and "Y" give an indication of the Feature Content. More information is given in the Tables 2 and 3. · The last 3 characters give an indication of the ROM code.
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CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
Table 2 FIRST INDICATION (X) Feature Indication, first character (X) Virtual Dolby® (VDS) ROM size / 0 = 128K
UOCIII series
0 1 2 3 4 5 6 7 8 9 A B C D E F Table 3 SECOND INDICATION (Y)
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Dolby® ProLogic® 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
dbx®
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Feature Indication, second character (Y)
SRS® TruSurround
SRS® 3D Stereo
0 1 2 3 4 5 6 7 2004 Jan 19
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
BBETM
0 0 1 1 0 0 1 1
DW / PANORAMA 0 1 0 1 0 1 0 1 11
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
SECOND INDICATION (Y)
UOCIII series
SRS® TruSurround
8 9 A B C D E F
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
2004 Jan 19
DW / PANORAMA 0 1 0 1 0 1 0 1
SRS® 3D Stereo
BBETM
12
CONFIDENTIAL
QUICK REFERENCE DATA
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Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
SYMBOL Supply VP IP VDDA IDDA VDDC/P IDDC/P VPAudio (1) IPAudio (1) Ptot Input voltages ViVIFrms) ViSIF(rms) ViSSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) ViY(p-p) ViU(p-p) / ViPB(p-p) ViV(p-p) / ViPR(p-p) Output signals Vo(IFVO)(p-p) Vo(QSSO)(rms) Vo(AMOUT)(rms) Vo(CVBSO)(p-p) Io(AGCOUT)
PARAMETER
MIN.
TYP.
MAX.
UNIT
analogue supply voltage TV processor supply current (5.0 V) digital supply TV processor / analogue supply periphery supply current (3.3 V) digital supply to core/periphery supply current (1.8 V) audio supply voltage supply current (5.0/8.0 V) total power dissipation
4.7 - 3.0 - 1.65 - 4.7 - - - - - - - - - - - -
5.0 190 3.3 36 1.8 440 8.0 0.5 1.87
5.3 - 3.6 - 1.95 - 8.4 - - 150 tbf - 1.3 1.4 1.0 0.8 - - -
V mA V mA V mA V mA W µV dBµV mV V V V V V V V
CONFIDENTIAL
video IF amplifier sensitivity (RMS value) QSS sound IF amplifier sensitivity (RMS value) sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) external chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) luminance input signal (peak-to-peak value) U / PB input signal (peak-to-peak value); note 2 V / PR input signal (peak-to-peak value); note 2
75 45 1.0 1.0 1.0 0.3 0.7 1.4 / 1.0 -1.33 / +0.7 -1.05 / +0.7
Preliminary specification
demodulated CVBS output (peak-to-peak value) sound IF intercarrier output (RMS value) demodulated AM sound output (RMS value) selected CVBS output (peak-to-peak value) tuner AGC output current range
- - - 1.0 - 0
2.0 100 250 - 2.0 -
- - - - - 1
UOCIII series
V mV mV V V mA
Vo(AUDIO)(rms)(1) non-controlled audio output signals (RMS value)
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Philips Semiconductors
SYMBOL VoRGB(p-p) IoHOUT IoVERT IoEWD Note
PARAMETER RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current -
MIN. 10 - - - 1 -
TYP. 1.2 - - -
MAX.
UNIT V mA mA mA
Versatile signal processor for low- and mid-range TV applications
1.2
1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is 2 Vrms. 2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
CONFIDENTIAL
Preliminary specification
UOCIII series
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
BLOCK DIAGRAMS 2004 Jan 19
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CONFIDENTIAL
IN SSDIP AV-STEREO SSIF QSSO/AMOUT SCART/CINCH IN/OUT I2S L R L R LS-OUT HP-OUT REFO
2004 Jan 19
SOUND PLL DEEMPHASIS AM ADC/DAC A/D CONVERTER ALL-STANDARD STEREO DECODER AUDIO SELECT RDS AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs
Philips Semiconductors
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES SCAVEM ON TEXT CON.
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
BL R
G
B
CR RO GO BO BRI
Versatile signal processor for low- and mid-range TV applications
YUV IN/OUT
C DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. Y YUV H/V VERTICAL & EAST-WEST GEOMETRY RGB/YPRPB INSERT YUV INTERFACE
16
Vo Uo Yo Yi Ui Vi V-DRIVE HOUT EWD EHTO BL G/Y R/PR B/PB B/PB SWO1 BL R/PR G/Y (CVBSx/Yx) (Cx)
VIDEO SWITCH VIDEO IDENT.
PEAKING SCAN VELOCITY MODULATION U/V DELAY
CONFIDENTIAL
SKIN TONE U/V TINT SATURATION SAT
VIDEO FILTERS
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
BCLIN BLKIN SVM RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
UOCIII series
(NOT IN SSDIP90)
Preliminary specification
Fig.1 Block diagram of the "Stereo" TV processor
SSIF SCART/CINCH IN/OUT I2S L R L R LS-OUT HP-OUT REFO
2004 Jan 19
SOUND PLL DEEMPHASIS AM RDS ADC/DAC AUDIO SELECT AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs
Philips Semiconductors
QSSO/AMOUT
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP. SCAVEM ON TEXT PEAKING CON.
BL R
G
B
CR RO GO BO BRI
Versatile signal processor for low- and mid-range TV applications
YUV IN/OUT
C DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. Y
17
H/V VERTICAL & EAST-WEST GEOMETRY RGB/YPRPB INSERT YUV INTERFACE Vo Uo Yo Yi Vi Ui V-DRIVE HOUT EWD EHTO BL G/Y
VIDEO SWITCH VIDEO IDENT.
CONFIDENTIAL
SCAN VELOCITY MODULATION U/V DELAY SKIN TONE U/V TINT SATURATION SAT
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4
VIDEO FILTERS
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
CVBSO/ PIP
BCLIN BLKIN SVM RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
R/PR B/PB
SWO1 BL
B/PB R/PR G/Y (CVBSx/Yx) (Cx)
Preliminary specification
UOCIII series
Fig.2 Block diagram of the "AV-stereo" TV processor with audio DSP
SSIF SCART/CINCH IN/OUT LS-OUT L R REFO
2004 Jan 19
SOUND PLL AUDIO SELECT VOLUME CONTROL DEEMPHASIS AM
Philips Semiconductors
QSSO/AMOUT
SIFIN/DVBIN
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR RDS
DVBO/IFVO/ FMRO DVBO/FMRO
I/Os
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP. SCAVEM ON TEXT PEAKING CON.
BL R
G
B
CR RO GO BO BRI RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
Versatile signal processor for low- and mid-range TV applications
C DIGITAL
YUV IN/OUT
18
2H/4H COMB FILTER Y DELAY ADJ. Y H/V VERTICAL & EAST-WEST GEOMETRY RGB/YPRPB INSERT YUV INTERFACE Vo Uo Yo Yi Vi Ui V-DRIVE HOUT EWD EHTO BL G/Y
VIDEO SWITCH VIDEO IDENT.
CONFIDENTIAL
SCAN VELOCITY MODULATION U/V DELAY SKIN TONE U/V TINT SATURATION SAT
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 CVBS3/Y3 C2/C3 CVBS4/Y4 C4
VIDEO FILTERS
CVBSO/ PIP
BCLIN BLKIN SVM RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
R/PR B/PB
SWO1 BL
B/PB R/PR G/Y (CVBSx/Yx) (Cx)
Preliminary specification
UOCIII series
Fig.3 Block diagram of the "AV-stereo" TV processor without audio DSP
(SSIF)
2004 Jan 19
AUDIO5 AUDIO4 AUDIO3 AUDIO2 AUDOUT/AMOUT (AVL)
Philips Semiconductors
SWITCH µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES SOUND PLL DEEMPHASIS AUDIO SWITCH AVL VOLUME CONTROL
QSSO/AMOUT AUDEEM
I/Os
SIFIN/DVBIN
DVBO/IFVO FMRO RDS PAL/SECAM/NTSC REF DECODER SCAVEM ON TEXT
QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
AGCOUT
VIFIN
VISION IF/AGC/AFC REF PLL DEMOD. DVB MIXER GROUP DELAY SOUND TRAP YUV IN/OUT
SVM COR R G B BL RO GO BO BCLIN YUV BLKIN
Versatile signal processor for low- and mid-range TV applications
IFVO/SVO/ CVBSI DIGITAL 4H/2H DELAY LINE COMB FILTER Y DELAY ADJ. BASE-BAND
19
Y VERTICAL + EW GEOMETRY V AND DRIVE U/V RGB/YUV/YPRPB INSERT YUV INTERFACE VO UO YO V-DRIVE (EWD) EHTO BL G/Y YI UI (REFO) HOUT
CVBS2/Y2
VIDEO SWITCH
CONFIDENTIAL
PEAKING SCAN VELOCITY MODULATION U/V DELAY VI
CVBS3/Y3 C2/C3 CVBS4/Y4
VIDEO IDENT.
C4
VIDEO FILTERS
CONTR/BRIGHTN OSD/TEXT INSERT BLUE STRETCH CCC WHITE-P. ADJ.
YSYNC
CVBSO/PIP
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT
SKIN TONE U/V TINT SATURATION BLACK STRETCH GAMMA CONTROL
H-DRIVE
R/PR B/PB
SWO1 BL G/Y B/PB R/PR (CVBS/Yx) (Cx)
UOCIII series
Preliminary specification
Fig. 4 Block diagram of the "Mono" TV processor
PINNING OF THE VARIOUS VERSIONS
2004 Jan 19 20
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
MONO
MONO
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+HPL VREF_POS_LSR+HPR VREF_NEG_HPL+HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG EWD/AVL (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1 2 3 4 - - - - - 10 11 12 13 14 15 16 17 18 19 20 21
1 2 3 4 - - - - - 10 11 12 13 14 15 16 17 18 19 20 21
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108
128 127 126 125 - - - - - 119 118 117 116 115 114 113 112 111 110 109 108
128 127 126 125 - - - - - 119 118 117 116 115 114 113 112 111 110 109 108
ground ground digital supply to SDACs (1.8V) supply (3.3 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) crystal oscillator input crystal oscillator output ground V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs) decoupling digital supply 1st supply voltage TV-processor (+5 V) phase-2 filter
CONFIDENTIAL
Preliminary specification
UOCIII series
phase-1 filter ground 1 for TV-processor SECAM PLL decoupling bandgap decoupling East-West drive output or AVL capacitor
2004 Jan 19 VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF 21 EHTO GND2
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
22 23 24 25 26 27 28
(2)
22 23 24 25 26 27 28 29 30 31 32 33
22 23 24 25 26 27 28 29 30 31 32 33
107 106 105 104 103 102 101 100 99 98 97 96
107 106 105 104 103 102 101 100 99 98 97 96
107 106 105 104 103 102 101 100 99 98 97 96
vertical drive B output vertical drive A output IF input 1 IF input 2 vertical sawtooth capacitor reference current input ground connection for IF amplifier SIF input 1 / DVB input 1 SIF input 2 / DVB input 2 tuner AGC output EHT/overvoltage protection input Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation audio 5 input audio-5 input (left signal) audio-5 input (right signal) audio output for SCART/CINCH (left signal)
CONFIDENTIAL
SIFIN1/DVBIN1
29 30 31 32 33
SIFIN2/DVBIN2 (2) AGCOUT
AVL/SWO/SSIF/ REFO/REFIN (2)(3) AUDIOIN5 AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM QSSO/AMOUT/AUDEEM (2)
- 34 35 36 37 38 39 40
- 34 35 36 37 38 39 40
34 - - - - 38 39 40
- 95 94 93 92 91 90 89
- 95 94 93 92 91 90 89
95 - - - - 91 90 89
Preliminary specification
UOCIII series
audio output for SCART/CINCH (right signal) decoupling sound demodulator QSS intercarrier output / AM output / deemphasis (front-end audio out) ground 2 for TV processor
2004 Jan 19 PLLIF VCC8V VP2 22 C4 C2/C3
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
41
(2)
41 42 43 44 45 - 47 48 - 49 50 51 52 - 53 54 55 - 56 57 58 59
41 42 43 - 45 - 47 48 49 - - 51 52 53 - - 55 56 - - 58 59
88 87 86 85 84 83 82 81 - 80 79 78 77 - 76 75 74 - 73 72 71 70
88 87 86 85 84 - 82 81 - 80 79 78 77 - 76 75 74 - 73 72 71 70
88 87 86 - 84 - 82 81 80 - - 78 77 76 - - 74 73 - - 71 70
IF-PLL loop filter AGC sound IF / internal-external AGC for DVB applications Digital Video Broadcast output / IF video output / FM radio output Digital Video Broadcast output / FM radio output 8 Volt supply for audio switches AGC capacitor second sound IF 2nd supply voltage TV processor (+5 V) IF video output / selected CVBS output / CVBS input audio 4 input audio-4 input (left signal) audio-4 input (right signal) CVBS4/Y4 input chroma-4 input audio 2 input audio 2 input (left signal) / sound IF input audio 2 input (right signal) CVBS2/Y2 input
SIFAGC/DVBAGC
42 43 44 45 46 47 48 - 49 50 51 52 -
DVBO/IFVO/FMRO (2) DVBO/FMRO
(2)
CONFIDENTIAL
AGC2SIF
IFVO/SVO/CVBSI (2) AUDIOIN4 AUDIOIN4L AUDIOIN4R CVBS4/Y4
AUDIOIN2 AUDIOIN2L/SSIF AUDIOIN2R CVBS2/Y2 AUDIOIN3 AUDIOIN3L AUDIOIN3R CVBS3/Y3
(3)
53 54 55 - 56 57 58 59
Preliminary specification
audio 3 input audio 3 input (left signal) audio 3 input (right signal) CVBS3/Y3 input chroma-2/3 input
UOCIII series
2004 Jan 19 SVM 23 HOUT YSYNC YOUT INSSW3 R/PRIN3 G/YIN3 B/PBIN3
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO - - 62 - - 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
MONO - - 67 - - 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AUDOUTLSL AUDOUTLSR AUDOUT/AMOUT/FMOUT AUDOUTHPL AUDOUTHPR CVBSO/PIP
60 61 - 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
62 63 - - - 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
69 68 - 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
67 66 - - - 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
audio output for audio power amplifier (left signal) audio output for audio power amplifier (right signal) audio output / AM output / FM output, volume controlled audio output for headphone channel (left signal) audio output for headphone channel (right signal) CVBS / PIP output scan velocity modulation output flyback input/sandcastle output or composite H/V timing output horizontal output ground connection for comb filter supply voltage for comb filter (5 V) V-input for YUV interface (2nd R input / PR input or CX input) U-input for YUV interface (2nd B input / PB input) Y-input for YUV interface (2nd G input / Y input or CVBS/YX input)) Y-input for sync separator Y-output (for YUV interface) U-output for YUV interface (2nd RGB / YPBPR insertion input)
CONFIDENTIAL
FBISO/CSY
VSScomb VDDcomb VIN (R/PRIN2/CX) UIN (B/PBIN2) YIN (G/YIN2/CVBS-YX)
UOUT (INSSW2) VOUT (SWO1)
Preliminary specification
V-output for YUV interface (general purpose switch output) 3rd RGB / YPBPR insertion input 3rd R input / PR input 3rd G input / Y input 3rd B input / PB input
UOCIII series
2004 Jan 19 GND3 VP3 BCLIN BLKIN RO GO BO VDDA1 24 VREFAD GNDA VSSadc P1.1/T0 VDDC2 VSSC2
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96 97 98 99 100 101
81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96 97 98 99 100 101
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33 32 31 30 29 28
48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33 32 31 30 29 28
ground 3 for TV-processor 3rd supply for TV processor beam current limiter input black current input Red output Green output Blue output analog supply for TCG µ-Controller and digital supply for TV-processor (+3.3 V) negative reference voltage (0 V) positive reference voltage (3.3 V) reference voltage for audio ADCs (3.3/2 V) ground analogue supply for audio ADCs (1.8 V) supply voltage SDAC (3.3 V) ground for video ADC and PLL supply voltage video ADC and PLL external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs) port 1.0 or external interrupt 1 port 1.1 or Counter/Timer 0 input digital supply to core (1.8 V) ground
CONFIDENTIAL
VREFAD_NEG VREFAD_POS
VDDA(1.8V) VDDA2(3.3)
VDDadc(1.8) INT0/P0.5 P1.0/INT1
Preliminary specification
UOCIII series
2004 Jan 19 P0.4 P0.3 P0.2 P0.1 25 P0.0 P1.3/T1 VDDC1
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
P0.4/I2SWS
102 - 103 - 104 - 105 - 106 - 107 108 109 110 111 112 113 114 115 116 117 118
- 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
- 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
27 - 26 - 25 - 24 - 23 - 22 21 20 19 18 17 16 15 14 13 12 11
- 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
- 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
port 0.4 or I2S word select port 0.4 port 0.3 or I2S clock port 0.3 port 0.2 or I2S digital output 2 port 0.2 port 0.1 or I2S digital output 1 port 0.1 port 0.0 or I2S digital input 1 or I2S digital output port 0.0 port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line supply to periphery and on-chip voltage regulator (3.3 V) port 2.0 or Tuning PWM output port 2.1 or PWM0 output port 2.2 or PWM1 output
P0.3/I2SCLK
CONFIDENTIAL
P0.2/I2SDO2
P0.1/I2SDO1
P0.0/I2SDI1/O
P1.6/SCL P1.7/SDA VDDP(3.3V) P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P3.0/ADC0 P3.1/ADC1
Preliminary specification
port 2.3 or PWM2 output port 3.0 or ADC0 input port 3.1 or ADC1 input digital supply to core (+1.8 V) decoupling 1.8 V supply
UOCIII series
DECV1V8
2004 Jan 19 VSSC/P VDDC3 VSSC3 26 P1.4/RX P1.5/TX Note
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
P3.2/ADC2 P3.3/ADC3
119 120 121 122 123 124 125 126 127 128
119 120 121 122 123 124 125 126 127 128
119 120 121 122 123 124 125 126 127 128
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 2.4 or PWM3 output port 2.5 or PWM4 output digital supply to core (1.8V) ground port 1.2 or external interrupt 2 port 1.4 or UART bus port 1.5 or UART bus
P2.4/PWM3 P2.5/PWM4
CONFIDENTIAL
P1.2/INT2
1. The function of this pin can be chosen by means of the AVLE bit. 2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4. 3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the "face down" versions these pin numbers are 96 and 76 respectively.
Preliminary specification
UOCIII series
Table 4
Pin functions for various modes of operation
2004 Jan 19 27
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
ANALOGUE TV MODE IC MODE DVB MODE FUNCTION IFA/IFB/IFC bits FMR bit FMI bit AVLE bit CMB2/CMB1/CMB0 bits AM bit Standard pin 21 pin 29 pin 30 pin 33 (1) Face-down pin 108 pin 100 pin 99 pin 96 (1) AVL EWD AVL - - SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO - IFVO - IFVO/SVO/CVBSI AUDOUT SWO/SSIF/REFO EWD AVL EWD SIFIN1 SIFIN2 AVL/SWO/SSIF/ REFO SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO AVL EWD AVL EWD DVBIN1 DVBIN2 SWO REFIN SIFIN1 SIFIN2 SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO 1 010/011 - 101/111 0 - 0 100 - 0 1 1 0 - 0 1 0 0 0 000/001/010/011/101/110 1 - - 1 FM-PLL MODE (QSS = 0) FM DEMODULATION QSS MODE (QSS = 1) QSS/AM DEMODULATION 000/001/010/011/100/110 0 1 0 1 QSS-FM DEMODULATION 101/111 1 - 0 FM RADIO MODE
CONFIDENTIAL
pin 39 pin 42 pin 43 (2) pin 44 (2) pin 48 (3) pin 62 (4) Note
pin 90 pin 87 pin 86 (2) pin 85 (2) pin 81 (3) pin 67 (4)
- DVBAGC DVBO DVBO SVO/CVBSI AUDOUT
AUDEEM
QSSO
AMOUT
QSSO
AMOUT
AUDEEM
AUDEEM SIFAGC FMRO FMRO IFVO/SVO/CVBSI
SIFAGC IFVO - IFVO/SVO/CVBSI AUDOUT AMOUT AUDOUT AMOUT AUDOUT
AUDOUT Preliminary specification
1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH. 2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H. 3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H. 4. This functionality is only valid for the mono versions. In the "stereo" and "AV-stereo" versions this pin has the function of audio output for the headphone channel (left signal).
UOCIII series
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
P1.7/SDA P1.6/SCL P1.3/T1 107 106 P0.0/I2SDI1 P0.1/I2SDO1 105 104 P0.2/I2SDO2 103 P0.3/I2SCLK 102 P0.4/I2SWS 101 VSSC2 100 VDDC2
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
113 112 111 110 109 108
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96 91 VREFAD 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
VSSP2 1 VSSC4 2 VDDC4 3 VDDA3(3.3V) 4 VREF_POS_LSL 5 VREF_NEG_LSL+LSR 6 VREF_POS_LSR+HPL 7 VREF_NEG_HPL+HPR 8 VREF_POS_HPR 9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 52 AUDIOIN2L 53 AUDIOIN2R/SSIF 54 CVBS2/Y2 55 AUDIOIN3L 56 AUDIOIN3R 57 CVBS3/Y3 58 SIFAGC/DVBAGC DVBO//IFVO/FMRO DVBO/FMRO VCC8V AGC2SIF VP2 SVO/IFOUT/CVBSI C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR AUDIOIN4R CVBS4/Y4 C4 AUDIOIN4L 60 61 62 63 CVBSO/PIP 64 33 34 41 42 49 50 35 36 37 38 43 44 45 46 GND2 PLLIF 51 59
2004 Jan 19
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Fig.5 Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
28
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
VSSC1/P P3.3/ADC3 119 P3.2/ADC2 118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
VDDC3 P2.5/PWM4 P2.4/PWM3
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
127 P1.4/RX 126 P1.2/INT2 125 VSSC3
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
124
123 122 121 120
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96 91 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
P1.7/SDA P1.6/SCL
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) -
1 2 3 4 5 6 7 8
9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 41 SIFAGC/DVBAGC 42 DVBO//IFVO/FMRO 43 - 44 VCC8V 45 - 46 VP2 SVO/IFOUT/CVBSI AUDIOIN2L/SSIF
P0.2
AUDIOIN3R
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Fig.6 Pin configuration of "AV stereo" versions without Audio DSP
2004 Jan 19
29
CVBS3/Y3 C2/C3 59 - 60 - 61 AUDOUTLSL 62 AUDOUTLSR 63 CVBSO/PIP 64
33 34
AUDIOIN4R CVBS4/Y4 C4
AUDIOIN4L
AUDIOIN2R CVBS2/Y2
AUDIOIN3L
GND2
PLLIF
52 53 54 55 56 57 58
35 36 37 38
49 50
51
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 91 90 VREFAD_POS 89 VREFAD_NEG 96 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
P1.7/SDA P1.6/SCL
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) -
1 2 3 4 5 6 7 8
9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 SIFAGC/DVBAGC DVBO//IFVO/FMRO VCC8V VP2 SVO/IFOUT/CVBSI DECSDEM AMOUT/QSSO/AUDEEM 60 61 AUDOUT/AMOUT 62 - 63 CVBSO/PIP 64 52 53 54 CVBS2/Y2 55 AUDIOIN3 56 - 57 CVBS3/Y3 58 C2/C3 59 AUDIOIN2 33 34 41 42 49 50 35 36 37 38 43 44 45 46 AUDIOIN4 CVBS4/Y4 C4 GND2 PLLIF 51
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5 -
Fig.7 Pin configuration "mono" versions
2004 Jan 19
30
P0.2
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
2004 Jan 19
31
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR
122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR
119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
115 114 113 112 111 110 109 108
105 104 103 102 101 100
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 DVBO/FMRO 84 VCC8V 83 AGC2SIF 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL P1.3/T1 P0.0/I2SDI1 P0.1/I2SDO1 21 22 23 24 25 26 27 28 29 30 31 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3L
AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR CVBSO/PIP
P0.2/I2SDO2
P0.3/I2SCLK P0.4/I2SWS VSSC2 VDDC2 P1.1/T0 P1.O/INT1 INT0/P0.5
QFP-128 0.8 mm pitch "face down version"
GNDA 37 VREFAD 38 VREFAD_POS 39 VREFAD_NEG 40
VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46
Fig.8 Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
2004 Jan 19
32
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 -
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
VSSP2
120 -
115 114 113 112 111 110 109 108
105 104 103 102 101 100
128
127
119
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3L
AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR CVBSO/PIP
QFP-128 0.8mm pitch "face down version"
VREFAD_POS 39 VREFAD_NEG 40 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46 VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 GNDA 37 - 38 HOUT 62 FBISO/CSY 63 SVM 64
Fig.9 Pin configuration of "AV stereo" versions without Audio DSP
2004 Jan 19
33
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 -
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
120 -
115 114 113 112 111 110 109 108
105 104 103 102 101 100
119
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5 94 93 92 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4 79 78 CVBS4/Y4 77 C4 76 AUDIOIN2 75 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3 CVBS3/Y3
C2/C3 AUDOUT/AMOUT CVBSO/PIP
QFP-128 0.8mm pitch "face down version"
39 40 VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46
GNDA VREFAD_POS VREFAD_NEG
Fig.10 Pin configuration "mono" versions
2004 Jan 19
34
HOUT 62 FBISO/CSY 63 SVM 64
37 38
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
TABEL PINNING SSDIP W.R.T. QFP128
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+HPL VREF_POS_LSR+HPR VREF_NEG_HPL+HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG EWD/AVL VDRB VDRA VIFIN1 VIFIN2 VSC
(1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 1 3 16 16 17 16 17 16 18 19 20 78 21 22 23 24 25 26 27 75 77 76 28 29 30
ground ground digital supply to SDACs (1.8V) supply (3.3 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) crystal oscillator input crystal oscillator output ground V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs) decoupling digital supply 1st supply voltage TV-processor (+5 V) phase-2 filter phase-1 filter ground 1 for TV-processor SECAM PLL decoupling bandgap decoupling East-West drive output or AVL capacitor vertical drive B output vertical drive A output IF input 1 IF input 2 vertical sawtooth capacitor
2004 Jan 19
35
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
IREF GNDIF SIFIN1/DVBIN1 (2) SIFIN2/DVBIN2 AGCOUT EHTO AVL/SWO/SSIF/ REFO/REFIN (2)
(2)
27 28 29 30 31 32 33
31 32 33 34 35 74 44
reference current input ground connection for IF amplifier SIF input 1 / DVB input 1 SIF input 2 / DVB input 2 tuner AGC output EHT/overvoltage protection input Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation audio 5 input audio-5 input (left signal) audio-5 input (right signal) audio output for SCART/CINCH (left signal) audio output for SCART/CINCH (right signal) decoupling sound demodulator QSS intercarrier output / AM output / deemphasis (front-end audio out) ground 2 for TV processor IF-PLL loop filter AGC sound IF / internal-external AGC for DVB applications Digital Video Broadcast output / IF video output / FM radio output Digital Video Broadcast output / FM radio output 8 Volt supply for audio switches AGC capacitor second sound IF 2nd supply voltage TV processor (+5 V) IF video output / selected CVBS output / CVBS input
AUDIOIN5 AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM QSSO/AMOUT/AUDEEM GND2 PLLIF SIFAGC/DVBAGC
(2) (2)
- 34 35 36 37 38 39 40 41 42 43 44 45 46 47
(2)
- -/36 37 38 64/36/39 40 41 42 43 44 45 46
DVBO/IFVO/FMRO (2) DVBO/FMRO (2) VCC8V AGC2SIF VP2 IFVO/SVO/CVBSI
48
2004 Jan 19
36
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
AUDIOIN4 AUDIOIN4L AUDIOIN4R CVBS4/Y4 C4 AUDIOIN2 AUDIOIN2L AUDIOIN2R CVBS2/Y2 AUDIOIN3 AUDIOIN3L AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUT/AMOUT/FMOUT AUDOUTHPL AUDOUTHPR CVBSO/PIP SVM FBISO/CSY HOUT VSScomb VDDcomb 2004 Jan 19
- 49 50 51 52 - 53 54 55 - 56 57 58 59 60 61 - 62 63 64 65 66 67 68 69
- 47 48 49 - 50 51 52 - 53 54 55 56 57 58 - 59 60 61 71 72 73 62 63
audio 4 input audio-4 input (left signal) audio-4 input (right signal) CVBS4/Y4 input chroma-4 input audio 2 input audio 2 input (left signal) audio 2 input (right signal) CVBS2/Y2 input audio 3 input audio 3 input (left signal) audio 3 input (right signal) CVBS3/Y3 input chroma-2/3 input audio output for audio power amplifier (left signal) audio output for audio power amplifier (right signal) audio output / AM output / FM output, volume controlled audio output for headphone channel (left signal) audio output for headphone channel (right signal) CVBS / PIP output scan velocity modulation output flyback input/sandcastle output or composite H/V timing output horizontal output ground connection for comb filter supply voltage for comb filter (5 V) 37
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
VIN (R/PRIN2/CX) UIN (B/PBIN2) YIN (G/YIN2/CVBS-YX) YSYNC YOUT UOUT (INSSW2) VOUT (SWO1) INSSW3 R/PRIN3 G/YIN3 B/PBIN3 GND3 VP3 BCLIN BLKIN RO GO BO VDDA1 VREFAD_NEG VREFAD_POS VREFAD GNDA VDDA(1.8V) VDDA2(3.3) 2004 Jan 19
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
-/64 65 66 67 68 69 70 79 80 81 82 83 84 85 86 87 88 89 87 90 88
V-input for YUV interface (2nd R input / PR input or CX input) U-input for YUV interface (2nd B input / PB input) Y-input for YUV interface (2nd G input / Y input or CVBS/YX input)) Y-input for sync separator Y-output (for YUV interface) U-output for YUV interface (2nd RGB / YPBPR insertion input) V-output for YUV interface (general purpose switch output) 3rd RGB / YPBPR insertion input 3rd R input / PR input 3rd G input / Y input 3rd B input / PB input ground 3 for TV-processor 3rd supply for TV processor beam current limiter input black current input Red output Green output Blue output analog supply for TCG µ-Controller and digital supply for TV-processor (+3.3 V) negative reference voltage (0 V) positive reference voltage (3.3 V) reference voltage for audio ADCs (3.3/2 V) ground analogue supply for audio ADCs (1.8 V) supply voltage SDAC (3.3 V) 38
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
VSSadc VDDadc(1.8) INT0/P0.5 P1.0/INT1 P1.1/T0 VDDC2 VSSC2 P0.4/I2SWS P0.4 P0.3/I2SCLK P0.3 P0.2/I2SDO2 P0.2 P0.1/I2SDO1 P0.1 P0.0/I2SDI1/O P0.0 P1.3/T1 P1.6/SCL P1.7/SDA VDDP(3.3V) P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P3.0/ADC0 P3.1/ADC1 2004 Jan 19
95 96 97 98 99 100 101 102 - 103 - 104 - 105 - 106 - 107 108 109 110 111 112 113 114 115 116
1 90 2 4 5 3 1 - - 50 - 51 6 7 8 9 10 11 47 48 12 13
ground for on-chip temperature sensor supply voltage video ADC external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs) port 1.0 or external interrupt 1 port 1.1 or Counter/Timer 0 input digital supply to core (1.8 V) ground port 0.4 or I2S word select port 0.4 port 0.3 or I2S clock port 0.3 port 0.2 or I2S digital output 2 port 0.2 port 0.1 or I2S digital output 1 port 0.1 port 0.0 or I2S digital input 1 or I2S digital output port 0.0 port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line supply to periphery and on-chip voltage regulator (3.3 V) port 2.0 or Tuning PWM output port 2.1 or PWM0 output port 2.2 or PWM1 output port 2.3 or PWM2 output port 3.0 or ADC0 input port 3.1 or ADC1 input 39
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION STEREO AV+ (SSDIP90) STEREO + AV STEREO (QFP128)
UOCIII series
SYMBOL
DESCRIPTION
STEREO/
MONO
VDDC1 DECV1V8 P3.2/ADC2 P3.3/ADC3 VSSC/P P2.4/PWM3 P2.5/PWM4 VDDC3 VSSC3 P1.2/INT2 P1.4/RX P1.5/TX
117 118 119 120 121 122 123 124 125 126 127 128
3 3 14 15 1 53 54 3 1 2 53 54
digital supply to core (+1.8 V) decoupling 1.8 V supply port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 2.4 or PWM3 output port 2.5 or PWM4 output digital supply to core (1.8V) ground port 1.2 or external interrupt 2 port 1.4 or UART bus port 1.5 or UART bus
2004 Jan 19
40
Preliminary specification
UOCIII series
PLLIF 40 SIFAGC/DVBAGC 41 DVBO//IFVO/FMRO 42 VCC8V 43 AGC2SIF/SWO/AVL/ 44 SSIF/REFIN/REFOUT VP2 45
2004 Jan 19
90 VDDA(1.8V) 89 VREFAD 88 VDDA3(3.3V) 87 86 85 84 83 82 GNDA2 VDDA2(3.3V.) BO GO RO BLKIN RO BLKIN 81 BCLIN 80 VP3 79 GND3 78 VGUARD/SWIO 77 VDRB 76 VDRA 75 AVL/EWD 74 EHTO HOUT FBISO/CSY SVM B/PB-3 G/Y-3 R/PR-3 INSSW3 YOUT YSYNC 64 DECSDEM 63 VDDcomb 62 VSScomb 61 CVBSO/PIP 60 AUDOUTHPR 59 AUDOUTHPL DECBG 27 VIFIN1 28 VIFIN2 29 VSC 30 IREF 31 GNDIF 32 DVBIN1/SIFIN1 33 DVBIN2/SIFIN2 34 GNDA2 VDDA2(3.3V.) BO GO 81 BCLIN 80 VP3 79 GND3 78 VGUARD/SWIO 77 VDRB 76 VDRA 75 AVL/EWD 74 EHTO 73 HOUT 72 FBISO/CSY 71 SVM 70 B/PB-3 69 G/Y-3 68 R/PR-3 67 INSSW3 66 YOUT 65 YSYNC 64 CVBSX 63 VDDcomb 62 VSScomb 61 CVBSO/PIP 60 AUDOUTHPR 59 AUDOUTHPL 58 AUDOUTLSR 57 AUDOUTLSL 56 C2/3 55 CVBS3/Y3 VSSC 1 P0.5/INT0//P1.2 2 VDDC(1.8)/RESET 3 P1.0/INT1 4 P1.1/T0 5 P1.3/T1 6 P1.6/SCL1 7 P1.7/SDA 8 VDDP(3.3) 9 P2.0/TPMW//P0.4 10 P2.1/PWM0//P0.1 11 P3.0/ADC0 12 P3.1/ADC1 13 87 86 85 84 83 82 90 VDDA(1.8V) 89 VREFAD 88 VDDA3(3.3V)
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
VSSC 1 P0.5/INT0//P1.2 2 VDDC(1.8)/RESET 3 P1.0/INT1 4 P1.1/T0 5 P1.3/T1 6 P1.6/SCL1 7 P1.7/SDA 8 VDDP(3.3) 9 P2.0/TPMW//P0.4 10 P2.1/PWM0//P0.1 11 P3.0/ADC0 12 P3.1/ADC1 13
(standard version)
(standard version)
HERCULES STEREO (SSDIP90)
HERCULES STEREO AV+ (SSDIP90)
41
AGCOUT 35 AMOUT/QSSO/AUDEEM 36 54 AUDIOIN3R//P1.5/P2.5 AUDOUTSL 37 AUDOUTSR 38 53 AUDIOIN3L//P1.4/P2.4 GND2 39 52 CVBS2/Y2 PLLIF 40 51 AUDIOIN2R//P0.0 SIFAGC/DVBAGC 41 50 AUDIOIN2L//P0.2 DVBO//IFVO/FMRO 42 49 CVBS4 48 AUDIOIN4R//P2.3 VCC8V 43 AGC2SIF/SWO/AVL/ 44 47 AUDIOIN4L//P2.2 SSIF/REFIN/REFOUT VP2 45 46 SVO/IFOUT/CVBSI
P3.2/ADC2 14 P3.3/ADC3 15 VDDA1(3.3V) 16 GNDA1 17 XTALIN 18 XTALOUT 19 VSSA1 20 DECDIG 21 VP1 22 PH2LF 23 PH1LF 24 GND1 25 SECPLL 26
P3.2/ADC2 14 P3.3/ADC3 15 VDDA1(3.3V) 16 GNDA1 17 XTALIN 18 XTALOUT 19 VSSA1 20 DECDIG 21 VP1 22 PH2LF 23 PH1LF 24 GND1 25 SECPLL 26
73 72 71 70 69 68 67 66 65
DECBG 27 VIFIN1 28 VIFIN2 29 VSC 30 IREF 31
GNDIF 32 DVBIN1/SIFIN1 33 DVBIN2/SIFIN2 34
AGCOUT 35 AUDIOIN5L 36
AUDOUTSL 37 AUDOUTSR 38 GND2 39
58 AUDOUTLSR 57 AUDOUTLSL 56 C2/3 55 CVBS3/Y3 54 AUDIOIN3R//P1.5/P2.5 53 AUDIOIN3L//P1.4/P2.4 52 CVBS2/Y2 51 AUDIOIN2R//P0.0 50 AUDIOIN2L//P0.2 49CVBS4 48AUDIOIN4R//P2.3 47AUDIOIN4L//P2.2 46 SVO/IFOUT/CVBSI
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
2004 Jan 19
42