Text preview for : UOCIII-v1.8.pdf part of PHILIPS TDA12xxx UOCIII series Versatile signal processor for lowand mid-range TV applications
pls need manual service of PM5518 Pm54185 or shemas
Back to : UOCIII-v1.8.pdf | Home
INTEGRATED CIRCUITS
DEVICE SPECIFICATION DATA SHEET
UOCIII series Versatile signal processor for lowand mid-range TV applications
Preliminary specification File under Integrated Circuits, Version: 18 2003 Nov 11 Previous date: 2003 Oct 09
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
GENERAL DESCRIPTION The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed Caption decoder. In addition the following functions can be added: · Adaptive digital (4H/2H) PAL/NTSC combfilter · Teletext decoder with 10 page text memory · Multi-standard stereo decoder · BTSC stereo decoder · Digital sound processing circuit · Digital video processing circuit The UOCIII series consists of the following 3 basic concepts: · Stereo versions. These versions contain the TV processor with a stereo audio selector, the TCG µ-Controller, the multi-standard stereo or BTSC decoder, the digital sound processing circuit and the digital video processing circuit. Options are the adaptive digital PAL/NTSC comb filter and a teletext decoder with 10 page text memory. · AV stereo versions. These versions contain the TV processor with stereo audio selector and the TCG µ-Controller. Options are the digital sound processing circuit, the digital video processing circuit, the adaptive digital PAL/NTSC comb filter and a teletext decoder with a 10 page text memory. · Mono sound versions. These versions contain the TV processor with a selector for mono audio signals and the TCG µ-Controller. Options are the adaptive digital PAL/NTSC combfilter and a teletext decoder with 10 page text memory. The most important features of the complete IC series are given in the following feature lists. The exact feature content of the various ICs is given in Table 1 on page 7. The ICs are mounted in a QFP-128 envelope(1) and can be used in economy television receivers with 90° and 110° picture tubes. They have supply voltages of 5V, 3.3V. Also an 1.8V supply is needed, but this can be simply derived by adding an emitter follower at a reference voltage from the device. UOCIII is supported by a comprehensive Global TV Software Development kit to enable easy programming and fast time-to-market (see also Chapter "LICENSE INFORMATION" on page 6.
(1) Both standard and "face down" versions of the QFP128 0.8mm pitch package are available.
UOCIII series
FEATURES Analogue Video Processing (all versions) · Multi-standard vision IF circuit with alignment-free PLL demodulator · Internal (switchable) time-constant for the IF-AGC circuit · Switchable group delay correction and sound trap (with switchable centre frequency) for the demodulated CVBS signal · DVB/VSB IF circuit for preprocessing of digital TV signals. · Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as Y-input for Y/C signals. However, only 2 Y/C sources can be selected because the circuit has 2 chroma inputs. It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the YUV interface and the RGB/YPRPB input are not needed. · Automatic Y/C signal detector · Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the chrominance signal. · Integrated luminance delay line with adjustable delay time · Picture improvement features with peaking (with switchable centre frequency, depeaking, variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone control, gamma control and blue- and black stretching. All features are available for CVBS, Y/C and RGB/YPBPR signals. · Switchable DC transfer ratio for the luminance signal · Only one reference (24.576 MHz) crystal required for the TCG µ-Controller, digital sound processor, Teletextand the colour decoder · Multi-standard colour decoder with automatic search system and various "forced mode" possibilities · Internal base-band delay line
2003 Nov 11
2
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
· Indication of the Signal-to-Noise ratio of the incoming CVBS signal · Linear RGB/YPBPR input with fast insertion. · YUV interface. When this feature is not required some pins can be used as additional RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input (CVBS/YX and CX). · Tint control for external RGB/YPBPR signals · Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages. · RGB control circuit with `Continuous Cathode Calibration', white point and black level off-set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. · Contrast reduction possibility during mixed-mode of OSD and Text signals · Adjustable `wide blanking' of the RGB outputs · Horizontal synchronization with two control loops and alignment-free horizontal oscillator · Vertical count-down circuit · Vertical driver optimized for DC-coupled vertical output stages · Horizontal and vertical geometry processing with horizontal parallelogram and bow correction and horizontal and vertical zoom · Low-power start-up of the horizontal drive circuit Analogue video processing (stereo versions) · The low-pass filtered `mixed down' I signal is available via a single ended or balanced output stage. Analogue video processing (mono versions) · The low-pass filtered `mixed down' I signal is available via a single ended output stage Digital Video Processing (some versions) · Double Window mode applications. It is possible to display a video and a text window or 2 text windows in parallel. · Linear and non-linear horizontal scaling of the video signal to be displayed.
UOCIII series
Sound Demodulation (all versions) · Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation. · AM demodulator without extra reference circuit · The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this demodulator is optional for special applications. Normally the FM demodulators of the stereo demodulator/decoder part are used (see below). · The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second sound channel can be demodulated. In such an application it is necessary that an external bandpass filter is inserted. · The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be demodulated. · Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF) Audio Interfaces and switching (stereo versions with Audio DSP) · Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R channel. Finally 1 stereo SPEAKER output with digital controls. · AVL (Automatic Volume Levelling) circuit for the headphone channel. · Digital input crossbar switch for all digital signal sources and destinations · Digital output crossbar for exchange of channel processing functionality · Digital audio input interface (stereo I2S input interface) · Digital audio output interface (stereo I2S output interface) Audio interfaces and switching (AV stereo versions without Audio DSP) · Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo SPEAKER output with analogue volume control. · Analogue mono AVL circuit at left audio channel
2003 Nov 11
3
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
Audio interfaces and switching (mono versions) · Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output · AVL circuit Stereo Demodulator and Decoder (full stereo versions) · Demodulator and Decoder Easy Programming (DDEP) · Auto standard detection (ASD) · Static Standard Selection (SSS) · DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation · NICAM decoding (B/G, I, D/K and L standard) · Two-carrier multistandard FM demodulation (B/G, D/K and M standard) · Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound · Adaptive de-emphasis for satellite FM · Optional AM demodulation for system L, simultaneously with NICAM · Identification A2 systems (B/G, D/K and M standard) with different identification time constants · FM pilot carrier present detector · Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option · BTSC MPX decoder · SAP decoder · dbx® noise reduction (4) · Japan (EIAJ) decoder · FM radio decoder · Soft-mute for DEMDEC outputs DEC, MONO and SAP · FM overmodulation adaptation option to avoid clipping and distortion Audio Multi Channel Decoder (stereo versions with Audio DSP) · Dolby® Pro Logic® (DPL) (1) · Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit this feature an external DAC is required.
UOCIII series
Volume and tone control for loudspeakers (stereo versions with Audio DSP) · Automatic Volume Level (AVL) control · Smooth volume control · Master volume control · Soft-mute · Loudness · Bass, Treble · Dynamic Bass Boost (DBB) (2) · Dynamic Virtual Bass (DVB) (3) · BBE® Sound processing (4) · Graphic equaliser · Processed or non processed subwoofer · Programmable beeper Reflection and delay for loudspeaker channels (stereo versions with Audio DSP) · Dolby® Pro Logic® Delay (1) · Pseudo hall/matrix function Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (stereo versions with Audio DSP) · Extended Pseudo Stereo (EPS) (5) · Extended Spatial Stereo (ESS) (6) · Virtual Dolby® Surround (VDS 422,423) (1) · SRS 3D and SRS TruSurround® (4) RDS/RBDS · Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data System (RBDS) signal · RDS and RBDS block detection · Error detection and correction · Fast block synchronisation · Synchronisation control (flywheel) · Mode control for RDS/RBDS processing · Different RDS/RBDS block information output modes
(2) Also referred to as "Dynamic UltraBass" (3) Also referred to as "Dynamic Bass Enhancement" (4) For the use of these products a licence is required. More details are given in the chapter "LICENSE INFORMATION" on page 6 (5) Also referred to as "I-Mono" or "Incredible Mono" (6) Also referred to as "I-Stereo" or "Incredible Stereo"
(1) Dolby is a trademark of Dolby Laboratories
2003 Nov 11
4
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
µ-Controller · 80C51 µ-controller core standard instruction set and timing · 0.4883 µs machine cycle · maximum of 256k x 8-bit flash programmable ROM · maximum of 8k x 8-bit Auxiliary RAM · 12-level Interrupt controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · One 24-bit Timer (16-bit timer with 8-bit Pre-scaler) · WatchDog timer · Auxiliary RAM page pointer · 16-bit Data pointer · Stand-by, Idle and Power Down modes · 24 general-purpose I/O pins · 14 bits PWM for Voltage Synthesis Tuning · 8-bit A/D converter with 4 multiplexed inputs · 5 PWM (6-bits) outputs for analogue control functions · Remote Control Pre-processor (RCP) · Universal Asynchronous Receiver Transmitter (UART) Data Capture · Text memory up to 10 pages · Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) · Data Capture for US Closed Caption · Data Capture for 525/625 line WST, VPS (PDC system A) and 625 line Wide Screen Signalling (WSS) bit decoding · Automatic selection between 525 WST/625 WST · Automatic selection between 625 WST/VPS on line 16 of VBI · Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput · Automatic detection of FASTEXT transmission · Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters · Signal quality detector for video and WST/VPS data types · Comprehensive teletext language coverage · Vertical Blanking Interval (VBI) data capture of WST data Display
UOCIII series
· Teletext and Enhanced OSD modes · Features of level 1.5 WST and US Close Caption · 50Hz/60Hz display timing modes · Two page operation for 16:9 screens · Serial and Parallel Display Attributes · Single/Double/Quadruple Width and Height for characters · Smoothing capability of both Double Size, Double Width & Double Height characters · Scrolling of display region · Variable flash rate controlled by software · Soft colours using CLUT with 4096 colour palette · Globally selectable scan lines per row (9/10/13/16/) and character matrix [12x9, 12x13, 12x16, 16x18, (VxH)] · Fringing (Shadow) selectable from N-S-E-W direction · Fringe colour selectable · Contrast reduction of defined area · Cursor · Special Graphics Characters with two planes, allowing four colours per character · 64 software redefinable On-Screen display characters · 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) · G1 Mosaic graphics, Limited G3 Line drawing characters · WST Character sets and Closed Caption Character set in single device · SVM for Text
2003 Nov 11
5
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
LICENSE INFORMATION dbx
UOCIII series
dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For further information, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA. Tel: 1-508-478-9200, FAX: 1-508-478-0990 Dolby "Dolby", "Pro Logic" and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products are available to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103, USA, Tel: 1-415-558-0200, Fax: 1-415-863-1373 Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. BBE BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA. The use of BBE needs licensing from BBE Sound, Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728
The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporation and licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRS and TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chip TDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. Philips "Dynamic Ultra BassTM", "Dynamic Bass Enhancement", "I-Mono" and "I-Stereo" are denominators for Philips patented technologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but instead generic ones such as listed below. Generic name/ Philips name · Dynamic Virtual Bass (DVB)/Dynamic UltraBass · Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement · Extended Pseudo Stereo (EPS)/I-Mono · Extended Spatial Stereo (ESSI)/I-Stereo GTV Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V. Please contact your nearest Philips Semiconductors sales office for further details. 2003 Nov 11 6
CONFIDENTIAL
OVERVIEW OF THE VARIOUS VERSIONS
2003 Nov 11
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
Table 1
Overview of types COMB FILTER COLOUR DECODER STEREO FM RADIO MONO FM RADIO RDS/RBDS dbx® Dolby® ProLogic® Virtual Dolby® (VDS) SRS® 3D Stereo SRS® TruSurround BBETM DW / PANORAMA ROM SIZE (k) AUX RAM SIZE (k) DISPLAY RAM (k) DRCS RAM (k) SOUND SYSTEM NUMBER OF TELETEXT PAGES
TYPE NUMBER(1) STEREO AUDIO DECOMONO DSP DER TDA11000H/H1 TDA11001H/H1 TDA11010H/H1 TDA11011H/H1 TDA11020H/H1 TDA11021H/H1 TDA12000H/H1(2) BTSC(3) TDA12001H/H1(2) BTSC(3) 7 TDA12006H/H1 TDA12007H/H1 TDA12008H/H1 TDA12009H/H1 TDA12010H/H1(2) TDA12011H/H1(2) TDA12016H/H1 TDA12017H/H1 TDA12018H/H1 TDA12019H/H1 TDA12020H/H1(2) TDA12021H/H1(2) TDA12026H/H1 TDA12027H/H1 TDA12028H/H1 TDA12029H/H1 BTSC(3) BTSC(3) BTSC(3) BTSC(3) MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI 0 10
NTSC NTSC MULTI MULTI MULTI MULTI NTSC NTSC NTSC NTSC NTSC NTSC MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI
128 128 128 128 128 128 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256
4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 10 10 2.25 2.25
CONFIDENTIAL
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25
Preliminary specification
10 10 10 10 10 10
2.25 2.25 2.25 2.25 2.25 2.25
UOCIII series
2003 Nov 11
Philips Semiconductors
COMB FILTER
COLOUR DECODER
STEREO FM RADIO
MONO FM RADIO
RDS/RBDS
dbx®
Dolby® ProLogic®
Virtual Dolby® (VDS)
SRS® 3D Stereo
SRS® TruSurround
BBETM
DW / PANORAMA
ROM SIZE (k)
AUX RAM SIZE (k)
DISPLAY RAM (k)
DRCS RAM (k)
SOUND SYSTEM TYPE NUMBER(1) STEREO AUDIO DECOMONO DSP DER TDA12060H/H1 TDA12061H/H1 TDA12062H/H1(2) TDA12063H/H1(2) TDA12066H/H1 TDA12067H/H1 TDA12068H/H1 TDA12069H/H1 TDA12070H/H1 TDA12071H/H1
NUMBER OF TELETEXT PAGES
Versatile signal processor for low- and mid-range TV applications
0
10
MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI MULTI
128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256 128/256
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 1.25 2.25 10 10 10 10 10 10 10 10 2.25 2.25 2.25 2.25 2.25 2.25 2.25 2.25
CONFIDENTIAL
8
TDA12072H/H1(2) TDA12073H/H1(2) TDA12076H/H1 TDA12077H/H1 TDA12078H/H1 TDA12079H/H1 Note
1. The "standard" version is indicated with "H" and the "facedown" version with "H1" 2. For these versions the feature content can be found from the type number. More details are given in the next Section. 3. When the BTSC demodulation is active the EIAJ demodulation is also activated. Preliminary specification
UOCIII series
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
Type Number Definition and Feature Indication The complete type number of these versions is given below.
UOCIII series
TDA12000H1/N1VXY0AA
The explanation of the various parts of the type number is given below: · The first 8 characters indicate the type number, the last 2 characters vary depending on the version. · The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with "H" and the "face-down version" with "H1". · The first 3 characters after the slash (/) indicate the IC version. · The characters "X" and "Y" give an indication of the Feature Content. More information is given in the Tables 2 and 3. · The last 3 characters give an indication of the ROM code.
Table 2 FIRST INDICATION (X)
Feature Indication, first character (X) Virtual Dolby® (VDS) ROM size / 0 = 128K
Table 3 SECOND INDICATION (Y)
Feature Indication, second character (Y)
Dolby® ProLogic®
SRS® TruSurround
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BBETM
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
2003 Nov 11
9
CONFIDENTIAL
DW / PANORAMA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SRS® 3D Stereo
dbx®
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
QUICK REFERENCE DATA SYMBOL Supply VP IP VDDA IDDA VDDC/P IDDC/P VPAudio (1) IPAudio Ptot Input voltages ViVIFrms) ViSIF(rms) ViSSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) ViY(p-p) ViU(p-p) / ViPB(p-p) ViV(p-p) / ViPR(p-p) Output signals Vo(IFVO)(p-p) Vo(QSSO)(rms) Vo(AMOUT)(rms) Vo(AUDIO)(rms) Io(AGCOUT) VoRGB(p-p) IoHOUT IoVERT IoEWD Note
(1) (1)
UOCIII series
PARAMETER
MIN.
TYP.
MAX.
UNIT
analogue supply voltage TV processor supply current (5.0 V) digital supply TV processor / analogue supply periphery supply current (3.3 V) digital supply to core/periphery supply current (1.8 V) audio supply voltage supply current (5.0/8.0 V) total power dissipation
4.7 - 3.0 - 1.65 - 4.7 - - - - - - - - - - - -
5.0 190 3.3 36 1.8 440 8.0 0.5 1.87
5.3 - 3.6 - 1.95 - 8.4 - - 150 tbf - 1.3 1.4 1.0 0.8 - - -
V mA V mA V mA V mA W µV dBµV mV V V V V V V V
video IF amplifier sensitivity (RMS value) QSS sound IF amplifier sensitivity (RMS value) sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) external chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) luminance input signal (peak-to-peak value) U / PB input signal (peak-to-peak value); note 2 V / PR input signal (peak-to-peak value); note 2
75 45 1.0 1.0 1.0 0.3 0.7 1.4 / 1.0 -1.33 / +0.7 -1.05 / +0.7
demodulated CVBS output (peak-to-peak value) sound IF intercarrier output (RMS value) demodulated AM sound output (RMS value) non-controlled audio output signals (RMS value) selected CVBS output (peak-to-peak value) tuner AGC output current range RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current
- - - 1.0 - 0 - 10 - -
2.0 100 250 - 2.0 - 1.2 - 1 -
- - - - - 1 - - - 1.2
V mV mV V V mA V mA mA mA
Vo(CVBSO)(p-p)
1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is 2 Vrms. 2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation. 2003 Nov 11 10
CONFIDENTIAL
QSSO/AMOUT SCART/CINCH IN/OUT I2S L R L R LS-OUT HP-OUT
2003 Nov 11
SSIF SOUND PLL DEEMPHASIS AM ADC/DAC A/D CONVERTER ALL-STANDARD STEREO DECODER AUDIO SELECT AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs
BLOCK DIAGRAMS
Philips Semiconductors
REFO
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO RDS
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF SCAVEM ON TEXT PEAKING SCAN VELOCITY MODULATION U/V DELAY YUV SVM VERTICAL & EAST-WEST GEOMETRY YUV INTERFACE RGB/YPRPB INSERT SKIN TONE U/V TINT SATURATION SAT Vo Uo Yo Yi Ui Vi RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL CON. BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
Versatile signal processor for low- and mid-range TV applications
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 YUV IN/OUT DIGITAL 2H/4H COMB FILTER Y DELAY ADJ.
BL R
G
B
CR RO GO BO
C
11
V-DRIVE EHTO BL G/Y EWD R/PR B/PB B/PB SWO1 BL R/PR G/Y (CVBSx/Yx) (Cx)
VIDEO SWITCH VIDEO IDENT.
VIDEO FILTERS
BRI
CONFIDENTIAL
Fig.1 Block diagram of the "Stereo" TV processor
CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
Y
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
BCLIN BLKIN
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V
Preliminary specification
UOCIII series
HOUT
SSIF SCART/CINCH IN/OUT I2S L R L R LS-OUT HP-OUT
2003 Nov 11
SOUND PLL DEEMPHASIS AM RDS ADC/DAC AUDIO SELECT AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs
QSSO/AMOUT
Philips Semiconductors
REFO
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF SCAVEM ON TEXT PEAKING CON. BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
Versatile signal processor for low- and mid-range TV applications
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 YUV IN/OUT DIGITAL 2H/4H COMB FILTER Y DELAY ADJ. SCAN VELOCITY MODULATION U/V DELAY
BL R
G
B
CR RO GO BO
C
12
VERTICAL & EAST-WEST GEOMETRY YUV INTERFACE RGB/YPRPB INSERT SKIN TONE U/V TINT SATURATION Vo Uo Yo Yi Vi Ui V-DRIVE EHTO BL G/Y B/PB SWO1 BL R/PR G/Y (CVBSx/Yx) (Cx) EWD
VIDEO SWITCH VIDEO IDENT.
CONFIDENTIAL
BRI SAT
CVBS3/Y3 C2/C3 CVBS4/Y4 C4
VIDEO FILTERS
CVBSO/ PIP
Y
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
BCLIN BLKIN SVM RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V
HOUT
R/PR B/PB
Preliminary specification
UOCIII series
Fig.2 Block diagram of the "AV-stereo" TV processor with audio DSP
SSIF SCART/CINCH IN/OUT LS-OUT L R
2003 Nov 11
SOUND PLL AUDIO SELECT VOLUME CONTROL DEEMPHASIS AM
QSSO/AMOUT
Philips Semiconductors
REFO
SIFIN/DVBIN
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
RDS
DVBO/IFVO/ FMRO DVBO/FMRO
AGCOUT PAL/SECAM/NTSC DECODER DELAY LINE REF SCAVEM ON TEXT PEAKING CON. BASE-BAND µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES
VIFIN
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
Versatile signal processor for low- and mid-range TV applications
IFVO/SVO/ CVBSI YSYNC CVBS2/Y2 YUV IN/OUT DIGITAL
BL R
G
B
CR RO GO BO
C
13
2H/4H COMB FILTER Y DELAY ADJ. SCAN VELOCITY MODULATION U/V DELAY VERTICAL & EAST-WEST GEOMETRY YUV INTERFACE RGB/YPRPB INSERT SKIN TONE U/V TINT SATURATION Vo Uo Yo Yi Vi Ui V-DRIVE EHTO BL G/Y B/PB SWO1 BL R/PR G/Y (CVBSx/Yx) (Cx) EWD
VIDEO SWITCH VIDEO IDENT.
CONFIDENTIAL
BRI SAT
CVBS3/Y3 C2/C3 CVBS4/Y4 C4
VIDEO FILTERS
CVBSO/ PIP
Y
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.
BCLIN BLKIN SVM RGB MATRIX BLUE STRETCH BLACK STRETCH GAMMA CONTROL
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
H/V
HOUT
R/PR B/PB
Preliminary specification
UOCIII series
Fig.3 Block diagram of the "AV-stereo" TV processor without audio DSP
(SSIF)
2003 Nov 11
AUDIO5 AUDIO4 AUDIO3 AUDIO2 AUDOUT/AMOUT (AVL)
Philips Semiconductors
SWITCH µ-PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES SOUND PLL DEEMPHASIS AUDIO SWITCH AVL VOLUME CONTROL
QSSO/AMOUT AUDEEM
I/Os
SIFIN/DVBIN
DVBO/IFVO FMRO RDS PAL/SECAM/NTSC REF DECODER COR DIGITAL 4H/2H DELAY LINE COMB FILTER Y DELAY ADJ. BASE-BAND SCAVEM ON TEXT
QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
AGCOUT
VIFIN
VISION IF/AGC/AFC REF PLL DEMOD. DVB MIXER GROUP DELAY SOUND TRAP YUV IN/OUT R G
SVM B BL RO GO BO BCLIN YUV BLKIN
Versatile signal processor for low- and mid-range TV applications
IFVO/SVO/ CVBSI
14
PEAKING SCAN VELOCITY MODULATION U/V DELAY Y VERTICAL + EW GEOMETRY AND DRIVE U/V RGB/YUV/YPRPB INSERT YUV INTERFACE VO UO YO V-DRIVE (EWD) EHTO BL G/Y YI UI VI (REFO)
CVBS2/Y2
VIDEO SWITCH
CONFIDENTIAL
SKIN TONE U/V TINT SATURATION BLACK STRETCH
CVBS3/Y3 C2/C3 CVBS4/Y4
VIDEO IDENT.
C4
VIDEO FILTERS
CONTR/BRIGHTN OSD/TEXT INSERT BLUE STRETCH CCC WHITE-P. ADJ.
YSYNC
CVBSO/PIP
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT
H-DRIVE
V
GAMMA CONTROL
HOUT
R/PR B/PB
SWO1 BL G/Y B/PB R/PR (CVBS/Yx) (Cx)
UOCIII series
Preliminary specification
Fig. 4 Block diagram of the "Mono" TV processor
PINNING OF THE VARIOUS VERSIONS
2003 Nov 11
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
MONO
MONO
VSSP2 VSSC4 VDDC4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1 2 3 4 - - - - - 10 11 12 13 14 15 16 17 18 19 20 21
1 2 3 4 - - - - - 10 11 12 13 14 15 16 17 18 19 20 21
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108
128 127 126 125 - - - - - 119 118 117 116 115 114 113 112 111 110 109 108
128 127 126 125 - - - - - 119 118 117 116 115 114 113 112 111 110 109 108
ground ground digital supply to SDACs (1.8V) supply (3.3 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) crystal oscillator input crystal oscillator output ground V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs) decoupling digital supply 1st supply voltage TV-processor (+5 V) phase-2 filter
CONFIDENTIAL
VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+HPL VREF_POS_LSR+HPR VREF_NEG_HPL+HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG EWD/AVL (1) 15
Preliminary specification
UOCIII series
phase-1 filter ground 1 for TV-processor SECAM PLL decoupling bandgap decoupling East-West drive output or AVL capacitor
2003 Nov 11 VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
22 23 24 25 26 27 28 29 30 31 32 33
22 23 24 25 26 27 28 29 30 31 32 33
22 23 24 25 26 27 28 29 30 31 32 33
107 106 105 104 103 102 101 100 99 98 97 96
107 106 105 104 103 102 101 100 99 98 97 96
107 106 105 104 103 102 101 100 99 98 97 96
vertical drive B output vertical drive A output IF input 1 IF input 2 vertical sawtooth capacitor reference current input ground connection for IF amplifier SIF input 1 / DVB input 1 SIF input 2 / DVB input 2 tuner AGC output EHT/overvoltage protection input Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation audio 5 input audio-5 input (left signal) audio-5 input (right signal) audio output for SCART/CINCH (left signal)
CONFIDENTIAL
SIFIN1/DVBIN1 (2) SIFIN2/DVBIN2 (2) AGCOUT EHTO AVL/SWO/SSIF/ REFO/REFIN (2)(3) AUDIOIN5 AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM QSSO/AMOUT/AUDEEM GND2
(2)
16
- 34 35 36 37 38 39 40
- 34 35 36 37 38 39 40
34 - - - - 38 39 40
- 95 94 93 92 91 90 89
- 95 94 93 92 91 90 89
95 - - - - 91 90 89
Preliminary specification
UOCIII series
audio output for SCART/CINCH (right signal) decoupling sound demodulator QSS intercarrier output / AM output / deemphasis (front-end audio out) ground 2 for TV processor
2003 Nov 11 PLLIF
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
41 42 43 44 45 46 47 48 - 49 50 51 52 -
(3)
41 42 43 44 45 - 47 48 - 49 50 51 52 - 53 54 55 - 56 57 58 59
41 42 43 - 45 - 47 48 49 - - 51 52 53 - - 55 56 - - 58 59
88 87 86 85 84 83 82 81 - 80 79 78 77 - 76 75 74 - 73 72 71 70
88 87 86 85 84 - 82 81 - 80 79 78 77 - 76 75 74 - 73 72 71 70
88 87 86 - 84 - 82 81 80 - - 78 77 76 - - 74 73 - - 71 70
IF-PLL loop filter AGC sound IF / internal-external AGC for DVB applications Digital Video Broadcast output / IF video output / FM radio output Digital Video Broadcast output / FM radio output 8 Volt supply for audio switches AGC capacitor second sound IF 2nd supply voltage TV processor (+5 V) IF video output / selected CVBS output / CVBS input audio 4 input audio-4 input (left signal) audio-4 input (right signal) CVBS4/Y4 input chroma-4 input audio 2 input audio 2 input (left signal) / sound IF input audio 2 input (right signal) CVBS2/Y2 input
SIFAGC/DVBAGC (2) DVBO/IFVO/FMRO DVBO/FMRO VCC8V AGC2SIF VP2 IFVO/SVO/CVBSI (2) 17 AUDIOIN4 AUDIOIN4L AUDIOIN4R CVBS4/Y4 C4 AUDIOIN2 AUDIOIN2L/SSIF AUDIOIN2R CVBS2/Y2 AUDIOIN3 AUDIOIN3L AUDIOIN3R CVBS3/Y3 C2/C3
(2) (2)
CONFIDENTIAL
53 54 55 - 56 57 58 59
Preliminary specification
audio 3 input audio 3 input (left signal) audio 3 input (right signal) CVBS3/Y3 input chroma-2/3 input
UOCIII series
2003 Nov 11
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO - - 62 - - 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
MONO - - 67 - - 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AUDOUTLSL AUDOUTLSR AUDOUT/AMOUT/FMOUT AUDOUTHPL AUDOUTHPR CVBSO/PIP SVM FBISO/CSY 18 HOUT VSScomb VDDcomb VIN (R/PRIN2/CX) UIN (B/PBIN2) YIN (G/YIN2/CVBS-YX) YSYNC YOUT UOUT (INSSW2) VOUT (SWO1) INSSW3 R/PRIN3 G/YIN3 B/PBIN3
60 61 - 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
62 63 - - - 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
69 68 - 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
67 66 - - - 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
audio output for audio power amplifier (left signal) audio output for audio power amplifier (right signal) audio output / AM output / FM output, volume controlled audio output for headphone channel (left signal) audio output for headphone channel (right signal) CVBS / PIP output scan velocity modulation output flyback input/sandcastle output or composite H/V timing output horizontal output ground connection for comb filter supply voltage for comb filter (5 V) V-input for YUV interface (2nd R input / PR input or CX input) U-input for YUV interface (2nd B input / PB input) Y-input for YUV interface (2nd G input / Y input or CVBS/YX input)) Y-input for sync separator Y-output (for YUV interface) U-output for YUV interface (2nd RGB / YPBPR insertion input)
CONFIDENTIAL
Preliminary specification
V-output for YUV interface (general purpose switch output) 3rd RGB / YPBPR insertion input 3rd R input / PR input 3rd G input / Y input 3rd B input / PB input
UOCIII series
2003 Nov 11 GND3 VP3 BCLIN BLKIN RO GO BO VDDA1 19
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96 97 98 99 100 101
81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96 97 98 99 100 101
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33 32 31 30 29 28
48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33 32 31 30 29 28
ground 3 for TV-processor 3rd supply for TV processor beam current limiter input black current input Red output Green output Blue output analog supply for TCG µ-Controller and digital supply for TV-processor (+3.3 V) negative reference voltage (0 V) positive reference voltage (3.3 V) reference voltage for audio ADCs (3.3/2 V) ground analogue supply for audio ADCs (1.8 V) supply voltage SDAC (3.3 V) ground for video ADC and PLL supply voltage video ADC and PLL external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs) port 1.0 or external interrupt 1 port 1.1 or Counter/Timer 0 input digital supply to core (1.8 V) ground
CONFIDENTIAL
VREFAD_NEG VREFAD_POS VREFAD GNDA VDDA(1.8V) VDDA2(3.3) VSSadc VDDadc(1.8) INT0/P0.5 P1.0/INT1 P1.1/T0 VDDC2 VSSC2
Preliminary specification
UOCIII series
2003 Nov 11 P0.4 P0.3
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
P0.4/I2SWS
102 - 103 - 104 - 105 - 106 - 107 108 109 110 111 112 113 114 115 116 117 118
- 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
- 102 - 103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118
27 - 26 - 25 - 24 - 23 - 22 21 20 19 18 17 16 15 14 13 12 11
- 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
- 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11
port 0.4 or I2S word select port 0.4 port 0.3 or I2S clock port 0.3 port 0.2 or I2S digital output 2 port 0.2 port 0.1 or I2S digital output 1 port 0.1 port 0.0 or I2S digital input 1 or I2S digital output port 0.0 port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line supply to periphery and on-chip voltage regulator (3.3 V) port 2.0 or Tuning PWM output port 2.1 or PWM0 output port 2.2 or PWM1 output
P0.3/I2SCLK
CONFIDENTIAL
P0.2/I2SDO2 P0.2 P0.1/I2SDO1 P0.1 20 P0.0/I2SDI1/O P0.0 P1.3/T1 P1.6/SCL P1.7/SDA VDDP(3.3V) P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P3.0/ADC0 P3.1/ADC1 VDDC1 DECV1V8
Preliminary specification
port 2.3 or PWM2 output port 3.0 or ADC0 input port 3.1 or ADC1 input digital supply to core (+1.8 V) decoupling 1.8 V supply
UOCIII series
2003 Nov 11 VSSC/P
Philips Semiconductors
"STANDARD" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO SYMBOL
"FACE DOWN" VERSION AV STEREO NO AUDIO DSP STEREO + AV STEREO DESCRIPTION
Versatile signal processor for low- and mid-range TV applications
MONO
MONO
P3.2/ADC2 P3.3/ADC3
119 120 121 122 123 124 125 126 127 128
119 120 121 122 123 124 125 126 127 128
119 120 121 122 123 124 125 126 127 128
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 2.4 or PWM3 output port 2.5 or PWM4 output digital supply to core (1.8V) ground port 1.2 or external interrupt 2 port 1.4 or UART bus port 1.5 or UART bus
P2.4/PWM3 P2.5/PWM4 VDDC3 VSSC3 P1.2/INT2 21 P1.4/RX P1.5/TX Note
CONFIDENTIAL
1. The function of this pin can be chosen by means of the AVLE bit. 2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4. 3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the "face down" versions these pin numbers are 96 and 76 respectively.
Preliminary specification
UOCIII series
Table 4
Pin functions for various modes of operation
2003 Nov 11
Philips Semiconductors
Versatile signal processor for low- and mid-range TV applications
ANALOGUE TV MODE IC MODE DVB MODE FUNCTION IFA/IFB/IFC bits FMR bit FMI bit AVLE bit CMB2/CMB1/CMB0 bits 1 010/011 - Face-down pin 108 pin 100 pin 99
(1)
FM-PLL MODE (QSS = 0) FM DEMODULATION
QSS MODE (QSS = 1) QSS/AM DEMODULATION 000/001/010/011/100/110 QSS-FM DEMODULATION
FM RADIO MODE
101/111 0 - 0 100 - EWD AVL - - SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO - IFVO - IFVO/SVO/CVBSI AUDOUT EWD 0 1 0 - 0
101/111 1 1 - 0 - AVL EWD AVL 1 - EWD 0 1 1
0 0 1 1 AVL 0 EWD SIFIN1 SIFIN2 SWO/SSIF/REFO AVL/SWO/SSIF/ REFO SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO 0 000/001/010/011/101/110
CONFIDENTIAL
AM bit Standard pin 21 pin 29 pin 30 pin 33 22 AVL
DVBIN1 DVBIN2 SWO REFIN
SIFIN1 SIFIN2 SWO/ SSIF/ REFO AVL/ SWO/ SSIF/ REFO
pin 96
(1)
pin 39 pin 42 pin 43 pin 44
(2) (2)
pin 90 pin 87 pin 86 pin 85
(2) (2)
- DVBAGC DVBO DVBO SVO/CVBSI AUDOUT
AUDEEM
QSSO
AMOUT
QSSO
AMOUT
AUDEEM
AUDEEM SIFAGC FMRO FMRO IFVO/SVO/CVBSI
SIFAGC IFVO - IFVO/SVO/CVBSI AUDOUT AMOUT AUDOUT AMOUT AUDOUT
pin 48 (3) pin 62 (4) Note
pin 81 (3) pin 67 (4)
AUDOUT Preliminary specification
1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH. 2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H. 3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H. 4. This functionality is only valid for the mono versions. In the "stereo" and "AV-stereo" versions this pin has the function of audio output for the headphone channel (left signal).
UOCIII series
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
P1.7/SDA P1.6/SCL P1.3/T1 107 106 P0.0/I2SDI1 P0.1/I2SDO1 105 104 P0.2/I2SDO2 103 P0.3/I2SCLK 102 P0.4/I2SWS
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
101 VSSC2 100 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
113 112 111 110 109 108
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96 91 VREFAD 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO RO BLKIN 84 83 BCLIN 85 82 VP3 81 GND3 80 B/PB-3 79 G/Y-3 78 R/PR-3 77 76 75 74 73 72 71 70 69 68 67 66 65 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
VSSP2 1 VSSC4 2 VDDC4 3 VDDA3(3.3V) 4 VREF_POS_LSL 5 VREF_NEG_LSL+LSR 6 VREF_POS_LSR+HPL 7 VREF_NEG_HPL+HPR 8 VREF_POS_HPR 9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 52 AUDIOIN2L 53 AUDIOIN2R/SSIF 54 CVBS2/Y2 55 AUDIOIN3L 56 AUDIOIN3R 57 CVBS3/Y3 58 SIFAGC/DVBAGC DVBO//IFVO/FMRO DVBO/FMRO VCC8V AGC2SIF VP2 SVO/IFOUT/CVBSI C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR AUDIOIN4R CVBS4/Y4 C4 AUDIOIN4L 60 61 62 63 CVBSO/PIP 64 33 34 41 42 49 50 35 36 37 38 43 44 45 46 GND2 PLLIF 51 59
2003 Nov 11
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Fig.5 Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
23
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
VSSC1/P P3.3/ADC3 119 P3.2/ADC2 118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2
VDDC3 P2.5/PWM4 P2.4/PWM3
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
127 P1.4/RX 126 P1.2/INT2 125 VSSC3
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
124
123 122 121 120
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96 91 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
P1.7/SDA P1.6/SCL
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG
1 2 3 4 5 6 7 8 9 10
11 12 13 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD 21 VDRB 22 VDRA 23 VIFIN1 24 VIFIN2 25 VSC 26 IREF 27 GNDIF 28 DVBIN1/SIFIN1 29 DVBIN2/SIFIN2 30 AGCOUT 31 EHTO 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 41 SIFAGC/DVBAGC 42 DVBO//IFVO/FMRO 43 - 44 VCC8V 45 - 46 VP2 SVO/IFOUT/CVBSI AUDIOIN2L/SSIF
P0.2
AUDIOIN3R
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM
Fig.6 Pin configuration of "AV stereo" versions without Audio DSP
2003 Nov 11
24
CONFIDENTIAL
CVBS3/Y3 C2/C3 59 - 60 - 61 AUDOUTLSL 62 AUDOUTLSR 63 CVBSO/PIP 64
33 34
AUDIOIN4R CVBS4/Y4 C4
AUDIOIN4L
AUDIOIN2R CVBS2/Y2
AUDIOIN3L
GND2
PLLIF
52 53 54 55 56 57 58
49 50
35 36 37 38
51
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 P2.3/PWM2 114
127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2
P2.1/PWM0 P2.0/PMW VDDP(3.3V)
P2.2/PWM1
P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1
128 P1.5/TX
107 P1.3/T1 106 P0.0 105 P0.1
113 112 111 110 109 108
104 103 102 101 100
97 INT0/P0.5 VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 91 90 VREFAD_POS 89 VREFAD_NEG 96 88 VDDA1(3.3V.) 87 BO 86 GO 85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
P1.7/SDA P1.6/SCL
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) -
1 2 3 4 5 6 7 8
9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO 21 22 23 24 25 26 27 28 29 30 31 32
QFP-128 0.8mm pitch "standard version"
39 40 47 48 SIFAGC/DVBAGC DVBO//IFVO/FMRO VCC8V VP2 SVO/IFOUT/CVBSI DECSDEM AMOUT/QSSO/AUDEEM 60 61 AUDOUT/AMOUT 62 - 63 CVBSO/PIP 64 52 AUDIOIN2 53 - 54 CVBS2/Y2 55 AUDIOIN3 56 - 57 CVBS3/Y3 58 C2/C3 59 33 34 41 42 49 50 35 36 37 38 43 44 45 46 AUDIOIN4 CVBS4/Y4 C4 GND2 PLLIF 51
AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5 -
Fig.7 Pin configuration "mono" versions
2003 Nov 11
25
CONFIDENTIAL
P0.2
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR
122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR
119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
115 114 113 112 111 110 109 108
105 104 103 102 101 100
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 DVBO/FMRO 84 VCC8V 83 AGC2SIF 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL P1.3/T1 P0.0/I2SDI1 P0.1/I2SDO1 21 22 23 24 25 26 27 28 29 30 31 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3L
AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR CVBSO/PIP
P0.2/I2SDO2
P0.3/I2SCLK P0.4/I2SWS VSSC2 VDDC2 P1.1/T0 P1.O/INT1 INT0/P0.5
QFP-128 0.8 mm pitch "face down version"
GNDA 37 VREFAD 38 VREFAD_POS 39 VREFAD_NEG 40
VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46
Fig.8 Pin configuration "stereo" and "AV-stereo" versions with Audio DSP
2003 Nov 11
26
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 -
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
VSSP2
120 -
115 114 113 112 111 110 109 108
119
105 104 103 102 101 100
128
127
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3L
AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR CVBSO/PIP
QFP-128 0.8mm pitch "face down version"
VREFAD_POS 39 VREFAD_NEG 40 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46 VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 GNDA 37 - 38
Fig.9 Pin configuration of "AV stereo" versions without Audio DSP
2003 Nov 11
27
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
UOCIII series
XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO
127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 -
128 VSSP2
107 VDRB 106 VDRA
99 DVBIN2/SIFIN2 98 AGCOUT
PH1LF GND1 SECPLL
VIFIN1 VIFIN2 VSC
IREF GNDIF DVBIN1/SIFIN1
DECDIG VP1 PH2LF
DECBG AVL/EWD
120 -
115 114 113 112 111 110 109 108
119
105 104 103 102 101 100
97 EHTO AVL/SWO/SSIF/ 96 REFIN/REFOUT 95 AUDIOIN5 94 93 92 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2 88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4 79 78 CVBS4/Y4 77 C4 76 AUDIOIN2 75 74 73 72 71 70 69 68 67 66 65
P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8 9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32 P3.3/ADC3
CVBS2/Y2 AUDIOIN3 CVBS3/Y3
C2/C3 AUDOUT/AMOUT CVBSO/PIP
QFP-128 0.8mm pitch "face down version"
39 40 VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51 INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46
GNDA VREFAD_POS VREFAD_NEG
Fig.10 Pin configuration "mono" versions
2003 Nov 11
28
CONFIDENTIAL
HOUT 62 FBISO/CSY 63 SVM 64
37 38
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
FUNCTIONAL DESCRIPTION OF THE 80C51 The functionality of the micro-controller used on this device is described here with reference to the industry standard 80C51 micro-controller. A full description of its functionality can be found in the 80C51 based 8-bit micro-controllers - Philips Semiconductors (ref. IC20). Features of the 80c51 · 80C51 micro-controller core standard instruction set and timing · 0.4883µs machine cycle (Xtal frequency 24.576MHz) · Maximum 256Kx8bit Flash Program ROM · Maximum of 8Kx8bit Auxiliary RAM · 12-Level Interrupt Controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · Additional 24-bit Timer (16-bit timer with 8-bit pre-scaler) · WatchDog Timer · Auxiliary RAM Page Pointer · 16-bit Data pointer · Stand-by, IDLE and Power Down (PD) modes · 24 General I/O via individual addressable controls · Five 6-bit Pulse Width Modulator (PWM) outputs for control of TV analogue signals · One 14-bit PWM for Voltage Synthesis tuning control · 8-bit ADC with 4 multiplexed inputs · High-speed I 2C for ISP (up to 1.2 Mb/s) · Remote Control Pre-processor (RCP) · Universal Asynchronous Receiver Transmitter (UART) Memory Organisation The device has the capability of a maximum of 256K Bytes of PROGRAM ROM and 8K Bytes of AUX DATA RAM for internally. ROM Organisation The 256K is arranged in eight banks of 32K. One of the 32K banks is common and is always addressable. The other banks (Bank0 to Bank6) can be accessed by selecting the right bank via the SFR ROMBK bits 2/1/0.
00 H FF H 128B RAM only Indirect addressing 80 H 7F H Lower 128 Byte RAM Direct & Indirect addressing 128B SFR only Direct addressing
UOCIII series
Fig.11 ROM Bank switching memory map
RAM Organisation The Internal Data RAM is organised into two areas, Data Memory and Special Function Registers (SFRs) as shown in Fig.12.
Internal RAM : "I-Data"
Special Function Registers = extension method for 80c51
30..7F H
RAM
Register-Bank select bits in PSW
20..2F H Bit-addressable space 18..1F H Register-Bank3 10..17 H Register-Bank2 08..0F H Register-Bank1 00..07 H Register-Bank0
R-Bank
R7 R6 R5 R4 R3 R2 R1 R0
· Different addressing method for upper 128 Bytes accesses RAM or SFR
Fig.12 Internal Data Memory DATA MEMORY The Data memory is 256 x 8-bits and occupies the address range 00 to FF Hex when using Indirect addressing and 00 to 7F Hex when using direct addressing. The SFRs occupy the address range 80 Hex to FF Hex and are accessible using Direct addressing only. The lower 128 Bytes of Data memory are mapped as shown in Fig.12. The lowest 32 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. The upper 128 bytes are not allocated for any special area or functions. 29
2003 Nov 11
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
SFR MEMORY The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and display control, etc. These registers can only be accessed by direct addressing.
UOCIII series
Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 5.
ADD
80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W P0
Names
BIT7
Reserved SP<7> DPL<7> DPH<7> DAT<7> SMOD TF1 GATE TL0<7> TL1<7> TH0<7> TH1<7> RA<7> RB<11> P1<7> TP2L<7> TP2H<7> TP2PR<7> Reserved Reserved SSD_ON SM<0> S0BUF<7> RB<7> TP2CL<7> TP2CH<7> P1CFGA<7> P1CFGB<7>
BIT6
Reserved SP<6> DPL<6> DPH<6> DAT<6> ARD TR1 C/T TL0<6> TL1<6> TH0<6> TH1<6> RA<6> RB<10> P1<6> TP2L<6> TP2H<6> TP2PR<6> Reserved Reserved SM<1> S0BUF<6> RB<6> TP2CL<6> TP2CH<6> P1CFGA<6> P1CFGB<6>
BIT5
P0<5> SP<5> DPL<5> DPH<5> DAT<5> RFI TF0 M1 TL0<5> TL1<5> TH0<5> TH1<5> RA<5> RB<9> P1<5> TP2L<5> TP2H<5> TP2PR<5> P0CFGA<5> P0CFGB<5> SM<2> S0BUF<5> RB<5> TP2CL<5> TP2CH<5> P1CFGA<5> P1CFGB<5>
BIT4
P0<4> SP<4> DPL<4> DPH<4> EX2 PX2 DAT<4> WLE TR0 M0 TL0<4> TL1<4> TH0<4> TH1<4> RA<4> RB<8> P1<4> TP2L<4> TP2H<4> TP2PR<4> P0CFGA<4> P0CFGB<4> DC_COMP REN S0BUF<4> RB<4> TP2CL<4> TP2CH<4> P1CFGA<4> P1CFGB<4>
BIT3
P0<3> SP<3> DPL<3> DPH<3> ERDS PRDS DAT<3> GF1 IE1 GATE TL0<3> TL1<3> TH0<3> TH1<3> RA<3> RA<11> P1<3> TP2L<3> TP2H<3> TP2PR<3> DAT<11> P0CFGA<3> P0CFGB<3> SAD<3> TB8 S0BUF<3> RB<3> TP2CL<3> TP2CH<3> P1CFGA<3> P1CFGB<3>
BIT2
P0<2> SP<2> DPL<2> DPH<2> EUART PUART DAT<2> GF0 IT1 C/T TL0<2> TL1<2> TH0<2> TH1<2> RA<2> RA<10> P1<2> TP2L<2> TP2H<2> TP2PR<2> DAT<10> P0CFGA<2> P0CFGB<2> SAD<2> RB8 S0BUF<2> RB<2> TP2CL<2> TP2CH<2> P1CFGA<2> P1CFGB<2>
BIT1
P0<1> SP<1> DPL<1> DPH<1> ET2PR PT2PR DAT<1> PD IE0 M1 TL0<1> TL1<1> TH0<1> TH1<1> RA<1> RA<9> P1<1> TP2L<1> TP2H<1> TP2PR<1> TP2CRL<1> DAT<9> P0CFGA<1> P0CFGB<1> SAD<1> TI S0BUF<1> RB<1> TP2CL<1> TP2CH<1> P1CFGA<1> P1CFGB<1>
BIT0
P0<0> SP<0> DPL<0> DPH<0> EBUSY PBUSY DAT<0> IDL IT0 M0 TL0<0> TL1<0> TH0<0> TH1<0> RA<0> RA<8> P1<0> TP2L<0> TP2H<0> TP2PR<0> TP2CRL<0> DAT<8> P0CFGA<0> P0CFGB<0> SAD<0> RI S0BUF<0> RB<0> TP2CL<0> TP2CH<0> P1CFGA<0> P1CFGB<0>
SP DPL DPH IEN1 IP1 RCP1 PCON TCON TMOD TL0 TL1 TH0 TH1 RCP3 RCP4 P1 TP2L TP2H TP2PR TP2CRL RCP2 P0CFGA P0CFGB SADB S0CON S0BUF RCP5 TP2CL TP2CH P1CFGA P1CFGB
2003 Nov 11
30
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
ADD
A0H A1H
UOCIII series
R/W
R/W R/W P2
Names
BIT7
Reserved 0
BIT6
Reserved CC_TXT B 9FF<11> BFE<6> BFE<14> Reserved Reserved ES2 NOT B <2>
BIT5
P2<5> ACTIVE PAGE
BIT4
P2<4> 1V8GUARD
BIT3
P2<3> GPF<11>
BIT2
P2<2> GPF<10>
BIT1
P2<1> GPF<9>
BIT0
P2<0> GPF<8>
TXT31
A2H A3H A4H A5H A6H A7H A8H A9H
R R R R/W R/W R/W R/W R/W
TXT32 TXT33 TXT34 Video_process P2CFGA P2CFGB IE TXT23
GPF<11> BFE<7> BFE<15> Reserved Reserved EA NOT B <3>
9FF<10> BFE<5> BFE<13> P2CFGA<5> P2CFGB<5> ECC NOT B <1>
9FF<9> BFE<4> BFE<12> P2CFGA<4> P2CFGB<4> EDET NOT B <0>
9FF<8> BFE<3> BFE<11> P2CFGA<3> P2CFGB<3> ET1 East/West B
9FF<7> BFE<2> BFE<10> P2CFGA<2> P2CFGB<2> EX1 DRCS B ENABLE TEXT IN B
9FF<6> BFE<1> BFE<9> DW_PA<1> P2CFGA<1> P2CFGB<1> ET0 BS B<1>
9FF<5> BFE<0> BFE<8> DW_PA<0> P2CFGA<0> P2CFGB<0> EX0 BS B<0>
AAH
R/W
TXT24
BKGND OUT B
BKGND IN B
CORB OUT B
CORB IN B
TEXT OUT B
PICTURE ON OUT B PICTURE ON OUT B BOX ON 1-23 B PAGE B<1>
PICTURE ON IN B PICTURE ON IN B BOX ON 0B PAGE B<0>
ABH
R/W
TXT25
BKGND OUT B
BKGND IN B
CORB OUT B
CORB IN B
TEXT OUT B
TEXT IN B
ACH
R/W
TXT26
EXTENDED DRCS DISPLAY BANK B<3> ADJUST E0<7> ADJUST E1<7> Reserved NOT<3> TEN DRCS ENABLE
TRANS B
0
0
SHADOW ENABLE B PAGE B<3>
BOX ON 24 B PAGE B<2>
ADH
R/W
TXT28
DISPLAY BANK B<2> ADJUST E0<6> ADJUST E1<6> Reserved NOT<2> TC<2> OSD PLANES
DISPLAY BANK B<1> ADJUST E0<5> ADJUST E1<5> Reserved NOT<1> TC<1> EXTENDED SPECIAL GRAPHICS CHAR SIZE<1> GPF<5> 0 PCC FORCE ACQ<0> 0
DISPLAY BANK B<0> ADJUST E0<4> ADJUST E1<4> Reserved NOT<0> TC<0> CHAR SELECT ENABLE CHAR SIZE<0> GPF<4> CS<4> PDET FORCE DISP<1> WSS<3:0> ERROR WSS<7:4> ERROR
AEH
R
ADJUST_E0
ADJUST E0<3>
ADJUST E0<2> ADJUST E1<2> P3<2> SCR B<2> 0 0 OSD LAN<2>
ADJUST E0<1> ADJUST E1<1> P3<1> SCR B<1> BS<1> TS<1> OSD LAN<1>
ADJUST E0<0> ADJUST E1<0> P3<0> SCR B<0> BS<0> TS<0> OSD LAN<0>
AFH
R
ADJUST_E1
ADJUST E1<3>
B0H B1H B2H B3H B4H
R/W R/W R/W R/W R/W
P3 TXT27 TXT18 TXT19 TXT20
P3<3> RDS ON 0 0 OSD LANG ENABLE
B5H
R/W
TXT21
DISP LINE<1>
DISP LINES<0> GPF<6> 0 PES2 FORCE ACQ<1> 0
Reserved (0)
CC ON
I2C PORT EN
CC/TXT
B6H B7H B8H B9H
R R/W R/W R/W
TXT22 CCLIN IP TXT17
GPF<7> 0 0 0
GPF<3> CS<3> PT1 FORCE DISP<0> WSS<3>
GPF<2> CS<2> PX1 SCREEN COL<2> WSS<2>
GPF<1> CS<1> PT0 SCREEN COL<1> WSS<1>
GPF<0> CS<0> PX0 SCREEN COL<0> WSS<0>
BAH
R
WSS1
0
BBH
R
WSS2
0
0
0
WSS<7>
WSS<6>
WSS<5>
WSS<4>
2003 Nov 11
31
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
ADD
BCH
UOCIII series
R/W
R
Names
WSS3
BIT7
WSS<13:11> ERROR ADJUST E2<7> Reserved Reserved X24 POSN
BIT6
WSS<13>
BIT5
WSS<12>
BIT4
WSS<11>
BIT3
WSS<10:8> ERROR ADJUST E2<3>
BIT2
WSS<10>
BIT1
WSS<9>
BIT0
WSS<8>
BDH
R
ADJUST_E2
ADJUST E2<6> Reserved Reserved DISPLAY X24
ADJUST E2<5> Reserved Reserved AUTO FRAME
ADJUST E2<4> Reserved Reserved DISABLE HEADER ROLL X26 OFF
ADJUST E2<2> P3CFGA<2> P3CFGB<2> DISABLE FRAME
ADJUST E2<1> P3CFGA<1> P3CFGB<1> VPS ON
ADJUST E2<0> P3CFGA<0> P3CFGB<0> INV ON
BEH BFH C0H
R/W R/W R/W
P3CFGA P3CFGB TXT0
P3CFGA<3> P3CFGB<3> DISPLAY STATUS ROW ONLY Reserved
C1H
R/W
TXT1
EXT PKT OFF
8 BIT
ACQ OFF
FIELD POLARITY SC<2>
H POLARITY
V POLARITY
C2H
R/W
TXT2
ACQ BANK<0> ACQ BANK<3> OSD BANK ENABLE
REQ<3>
REQ<2>
REQ<1>
REQ<0>
SC<1>
SC<0>
C3H
R/W
TXT3
ACQ BANK<2> QUAD WIDTH ENABLE BKGND IN
ACQ BANK<1> EAST/WEST
PRD<4>
PRD<3>
PRD<2>
PRD<1>
PRD<0>
C4H
R/W
TXT4
DISABLE DOUBLE HEIGHT CORB IN
0
0
TRANS ENABLE
SHADOW ENABLE
C5H
R/W
TXT5
BKGND OUT
CORB OUT
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON OUT BOX ON 1-23
PICTURE ON IN PICTURE ON IN BOX ON 0
C6H
R/W
TXT6
BKGND OUT
BKGND IN
CORB OUT
CORB IN
TEXT OUT
TEXT IN
C7H
R/W
TXT7
STATUS ROW TOP (Reserved) 0 CURSOR FREEZE CHAR 16/12 D<7> 525/625 SYNC
CURSOR ON
REVEAL
BOTTOM/TOP
DOUBLE HEIGHT PKT 26 RECEIVED R<3>
BOX ON 24
C8H
R/W
TXT8
FLICKER STOP ON CLEAR MEMORY -
HUNT
DISABLE SPANISH R<4>
WSS RECEIVED R<2>
WSS ON
(Reserved) 0 R<0>
C9H
R/W
TXT9
A0
R<1>
CAH
R/W
TXT10
C<5>
C<4>
C<3>
C<2>
C<1>
C<0>
CBH CCH
R/W R
TXT11 TXT12
D<6> ROM VER<4>
D<5> ROM VER<3>
D<4> ROM VER<2>
D<3> ROM VER<1>
D<2> ROM VER<0>
D<1> 1
D<0> VIDEO SIGNAL QUALITY PAGE<0>
CDH
R/W
TXT14
DISPLAY BANK<3> MICRO BANK<3> ADJUST E3<7> C ADJUST E4<7> TD<7> TPWE P3DCXOMUX
DISPLAY BANK<2> MICRO BANK<2> ADJUST E3<6> AC ADJUST E4<6> TD<6> 0 P3DCXOCAP S<6> Reserved (0) 0
DISPLAY BANK<1> MICRO BANK<1> ADJUST E3<5> F0 ADJUST E4<5> TD<5> TD<13> P3DCXOCAP S<5> PW0V<5> PW1V<5>
DISPLAY BANK<0> MICRO BANK<0> ADJUST E3<4> RS1 ADJUST E4<4> TD<4> TD<12> P3DCXOCAPS <4> PW0V<4> PW1V<4>
PAGE<3>
PAGE<2>
PAGE<1>
CEH
R/W
TXT15
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
CFH
R
ADJUST_E3
ADJUST E3<3>
ADJUST E3<2> OV ADJUST E4<2> TD<2> TD<10> P3DCXOCAP S<2> PW0V<2> PW1V<2>
ADJUST E31>
ADJUST E3<0> P ADJUST E4<0> TD<0> TD<8> P3DCXOCAPS <0> PW0V<0> PW1V<0>
D0H D1H
R/W R
PSW ADJUST_E4
RS0 ADJUST E4<3>
ADJUST E4<1> TD<1> TD<9> P3DCXOCAPS <1> PW0V<1> PW1V<1>
D2H D3H D4H
R/W R/W R/W
TDACL TDACH P3DCXOCTR L PWM0 PWM1
TD<3> TD<11> P3DCXOCAPS <3> PW0V<3> PW1V<3>
D5H D6H
R/W R/W
PW0E PW1E
2003 Nov 11
32
CONFIDENTIAL
Philips Semiconductors
Preliminary specification
Versatile signal processor for low- and mid-range TV applications
ADD
D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H
UOCIII series
R/W
R R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Names
CCDAT1 S1CON S1STA S1DAT S1ADR PWM3 PWM4 HSBIR FSBIR ACC TXT29
BIT7
CCD1<7> EN_I2CINT STAT<4> DAT<7> ADR<6> PW3E PW4E 0 F/S ACC<7> TEN B
BIT6
CCD1<6> ENSI STAT<3> DAT<6> ADR<5> 0 0 0 FSB<6> ACC<6> TS B <1>
BIT5
CCD1<5> STA STAT<2> DAT<5> ADR<4> PW3V<5> PW4V<5> 0 FSB<5> ACC<5> TS B <0>
BIT4
CCD1<4> STO STAT<1> DAT<4> ADR<3> PW3V<4> PW4V<4> HSB<4> FSB<4> ACC<4> OSD PLANES B BOTTOM/TOP B
BIT3
CCD1<3> SI STAT<0> DAT<3> ADR<2> PW3V<3> PW4V<3> HSB<3> FSB<3> ACC<3> OSD LANG ENABLE B DOUBLE HEIGHT B F1<3> PW2V<3> COEF<11>
BIT2
CCD1<2> AA 0 DAT<2> ADR<1> PW3V<2> PW4V<2> HSB<2> FSB<2> ACC<2> OSD LAN B <2> STATUS ROW TOP B
BIT1
CCD1<1> 0 0 DAT<1> ADR<0> PW3V<1> PW4V<1> HSB<1> FSB<1> ACC<1> OSD LAN B <1> DISPLAY X24 B
BIT0
CCD1<0> 0 0 DAT<0> GC PW3V<0> PW4V<0> HSB<0> FSB<0> ACC<0> OSD LAN B <0> DISPLAY STATUS ROW ONLY B F1<0> PW2V<0> COEF<8>
E2H
R/W
TXT30
TC B <2>
TC B <1>
TC B <0>
E3H E4H E5H
R/W R/W R/W
RDS_F0_F1 PWM2 RDS_COEF_ H RDS_COEF_ L CCDAT2 SAD RDS_STAT RDS_LDATH RDS_LDATL RDS_PDATH RDS_PDATL RCP6 B RDS_CNT1 RDS_CNT2 RDS_CTRL1 RDS_CTRL2 RDS_CTRL3 I2S TXT35 TXT13
F0<3> PW2E COEF<15>
F0<2> 0 COEF<14>
F0<1> PW2V<5> COEF<13>
F0<0> PW2V<4> COEF<12>
F1<2> PW2V<2> COEF<10>
F1<1> PW2V<1> COEF<9>
E6H
R/W
COEF<7>
COEF<6>
COEF<5>
COEF<4>
COEF<3>
COEF<2>
COEF<1>
COEF<0>
E7H E8H E9H EAH EBH ECH EDH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H
R R/W R R R R R R/W R/W R R R/W R/W R/W R/W R R/W
CCD2<7> VHI SYNC LDAT<15> LDAT<7> PDAT<15> PDAT<7> RCP ON B<7> BBC<5> GBC<5> SYM<1> DAC<1> I2S_CLK<1> 9FF<15> VPS RECEIVED
CCD2<6> CH<1> DOFL LDAT<14> LDAT<6> PDAT<14> PDAT<6> NFP B<6> BBC<4> GBC<4> RBDS SYM<0> DAC<0> I2S_CLK<0> 9FF<14> PAGE CLEARING
CCD2<5> CH<0> RSTD LDAT<13> LDAT<5> PDAT<13> PDAT<5> NGP B<5> BBC<3> GBC<3> MBBL<5> MGBL<5> NWSY EN_I2S_DI1 9FF<13> 525 DISPLAY
CCD2<4> ST LBIN<2> LDAT<12> LDAT<4> PDAT<12> PDAT<4> 0 B<4> BBC<2> GBC<2> MBBL<4> MGBL<4> MBBG<4> EN_I2SDO1 9FF<12> 525 TEXT
CCD2<3> SAD<7> LBIN<1> LDAT<11> LDAT<3> PDAT<11> PDAT<3> 0 B<3> BBC<1> GBC<1> MBBL<3> MGBL<3> MBBG<3> E