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SERVICE MANUAL
PT92 CHASSIS
Modification reserved
PT-92 Chassis Service Manual
CONTENTS
PAGE
1.Technical Data 2. Recommendation for service repairs 3. Handling of MOS chip components 4. X-Ray radiation precaution 5. Service Menu 6. Specification of the connector (Euroscart) 7. Component descriptions 8. Block Diagrams 9. Fault tracing diagram-power supply 10. Power Supply circuit diagram 11. Troubleshooting guide for main PCB 12. Descriptions of the integrated circuits
TDA16846 TDA935X TDA9875A TDA9870A TDA24C16 TDA8351 TDA8356 TDA2616 TDA2615 TDA7056 TDA7057AQ TDA7050 TDA6107Q TCDT1100 TDA9830 SAA7710T BU2508AF BU508DF SPP03N60S5 SPP04N60S5 SMPS IC UOC IC TV SOUND IC (STEREO) TV SOUND IC (G. STEREO) EEPROM VERTICAL IC (110O) VERTICAL IC (90O) STEREO AUDIO AMPLIFIER (110O) STEREO AUDIO AMPLIFIER (90O) MONO AUDIO AMPLIFIER (90O) HP AMPLIFIER HP AMPLIFIER VIDEO OUTPUT AMPLIFIER OPTOCOUPLER TV SOUND AM DEMODULATOR DOLBY PRO LOGIC SURROUND HORIZONTAL TRANSISTOR (110O) HORIZONTAL TRANSISTOR (90O) SMPS MOSFET (90O) SMPS MOSFET (110O)
4 5 5 5 6 9 10 11 14 15 16 17 21 28 35 45 47 51 55 57 60 62 64 67 69 71 75 80 83 86 88 90 93
13. Dolby and secam L mono board and circuits diagrams 14. Oscilloscope shapes
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PT-92 Chassis Service Manual
TECHNICAL DATA
CRT PANEL Visible Picture Deflection Angle Vertical Frequency Horizontal Frequency
47" / 50 cm / 66 cm 90o / 110o 50Hz 15.625Hz
ELECTRONIC
Program Number Teletext Tuner TV System Music Power 100+AV Flof text Cable tuner - 8 MHz spacing for Hyper Band European CCIR system 90o 2x8 Watt Rms 10% distortion 110o 2x4 Watt Rms 10% distortion
CONNECTIONS
Euro AV Socket Include
MAIN STAGE
Mains Voltage Mains Frequency Power Consumption In Stby Mode 165-260VAC 50Hz 110o 126 W; 90o 75 W 110o 8 W; 90o 5 W
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PT-92 Chassis Service Manual
RECOMMENDATION FOR SERVICE REPAIRS
1- Use only original spare parts. Only use components with the same specifications for replacement. 2- Original fuse value only should be used. 3- Main leads and connecting leads should be checked for external damage before connection. Check the insulation. 4- Parts contributing to the safety of the product must not be damaged or obviously unsuitable. This is valid especially for insulators and insulating parts. 5- Thermally loaded solder pads are to be sucked off and re-soldered. 6- Ensure that the ventilation slots are not obstructed. 7- Potentials as high as 25 KV are present when this receiver is operating. Operation of the receiver outside the cabinet or with back cover removed involve a shock hazard from the receiver. Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions necessary when working on high voltage equipment. Perfectly discharge the high potential of the picture tube before handling the tube. The picture tube is highly evacuated and if broken. Glass fragments will be violently expelled. Always discharge the picture tube anode to the receiver chassis to keep of the shock hazard before removing the anode cap. 8- Keep wire away from the high voltage or high temperature components. 9- When replacing a wattage resistor in circuit board, keep the resistor 10 mm away from circuit board.
HANDLING OF MOS CHIP COMPONENTS
MOS circuit requires special attention with regard to static charges. Static charges may occur with any highly insulating plastics and can be transferred to persons wearing clothes and shoes made of synthetic materials. Protective circuits on the inputs and outputs of mos circuits give protection to a limited extend only due to time of reaction. Please observe the following instructions to protect the components against damage from static charges. 1- Keep mos components in conductive package until they are used. Most components must never be stored in styropor materials or plastic magazines. 2- Persons have to rid themselves of electrostatic charges by touching MOS components. 3- Hold the component by the body touching the terminals. 4- Use only grounded instruments for testing and processing purposes. 5- Remove or connect MOS ICs when operating voltage is disconnected.
X-RAY RADIATION PRECAUTION
1- Excessive high voltage can be produce potentially hazardous X-RAY radiation. To avoid such hazard, the high voltage must not be above the specified limit. The nominal value of the high voltage of this receiver is 25KV at zero beam current (minimum brightness) under 220V AC power source. The high voltage must not under any circumstance, exceed 30KV. It is recommended the reading of the high voltage be recorded as a part of the service record. It is important to use an accurate and reliable high voltage meter. 2- The primary source of X-RAY radiation in this TV receiver is the picture tube. For continued X-RAY radiation protection, the replacement tube must be exactly the same type tube as specified in the part list.
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PT-92 Chassis Service Manual
SERVICE MENU
The service menu is entered by pressing the key on the RC and VOLUME-DOWN key on the TV simultaneously when the TV is in TV- mode. The service menu is left by pressing the key. When entering the service mode the first menu item is IF (selection of normal IF). Next items can be selected using the keys and . The value of each item can be changed using the keys and . The item values are displayed as decimal values, except for the tuner-band-selection, BITS and option items. They are displayed as hexa-decimal values. All values are stored in non-volatile memory when the service menu is left. The "INIT CTV832U" item initializes the NVM: It clears all names and tuning information of all programs and writes default values for the service alignments and preset values in NVM. While doing so, the OSD displays "BUSY". When the initialization is finished, the message "READY" is written on the screen.
Item IF IFL1 HP HB EW PW UCP LCP TC HP4:3 HB4:3 EW4:3 PW4:3 UCP4:3 LCP4:3 TC4:3 HS VS VA SC VSD VSH VX BLR BLG WPR WPG WPB Ys Yn YP
DefauIt 38.9 33.9 31 31 37 18 13 13 28 31 31 45 15 35 25 31 31 31 31 31 off 31 25 7 7 31 31 31 15 8 0
Explanation IF selection (58.8, 45.8, 38.9 or 38.00 MHz) IF for SECAM-L1 selection (33.4 or 33.9 MHz) Horizontal parallelogram Horizontal bow East-west Width for picture setting 16:9 East-west Parabola for picture setting 16:9 East-west Upper Corner parabola for picture setting 16:9 East-west Lower Corner parabola for picture setting 16:9 East-west Trapezium for picture setting 16:9 Horizontal parallelogram for picture setting 4:3 Horizontal bow for picture setting 4:3 East-west Width for picture setting 4:3 East-west Parabola for picture setting 4:3 East-west Upper Corner parabola for picture setting 4:3 East-west Lower Corner parabola for picture setting 4:3 East-west Trapezium for picture setting 4:3 Horizontal Shift Vertical Slope Vertical Amplitude S-Correction Vertical Scan Disable Vertical Shift Vertical zoom (East-west only) Black Level Red Black Level Green White point correction Red White point correction Green White point correction Blue Y-delay adjustment for SECAM Y-delay adjustment for NTSC Y-delay adjustment for PAL 6
PT-92 Chassis Service Manual
Yo AGC CL Bits Bits1
Y-delay adjustment for external sources AGC take over Cathode drive level (ACL=0; FCO= 0; SVO= 0; HP2= 0; FSL= 0; OSO= 0) (FFI= 0; TV= 0; AV-1= 0; AV-2= 0; AV-2S= 0; AV-3= 0; AV-3S= 0; AV = 0) OptByte1 (Default=E3) PAL-BG = Selection PAL-BG (1) PAL-DK = Selection PAL-DK (1) PAL-I = Selection PAL-I (0) PAL-M = Selection PAL-M (0) PAL-N = Selection PAL-N (0) NTSC-M = Selection NTSC-M (1) NTSC-443 = Selection NTSC-443 (1) SECAM-BG = Selection SECAM-BG (1) *(1) Selected, (0) Not Selected OptByte2 (Default=07) SECAM-DK = Selection SECAM-DK (1) FRANCE = Selection FRANCE (1) WEB = Enable/Disable (1/0) PalBG Scr = When the PalBG Scr selected, TV searches only PalBG. Otherwise it searches all. (0) AV2 = Selection AV2 (0) *(1) Selected, (0) Not Selected OptByte3 (Default=E8) = (0) JR = (0) HP = (0) Vol Bar = (1) Sub Wof = (0) Presets = (1) Lock = (1) Hotel = (0) When the Hotel mode selected, It's impossible to nter menu settings.lt selects the Hotel mode. (1) *(1) Selected, (0) Not Selected OptByte4 (Default=B8) 16:9 = Set 16:9 mode active (1) 110 = Selection 110/90 Tube (1/0) Hpol = Default (0) Vpol = DefauIt (0) Field = Default (1) FE-Out = Default (1) Sw-on = When the power on the TV, it Enables or Disables Standby Mode. (1/0) Vg-Check = Default (1) *(1) Selected, (0) Not Selected OptByte5 (Default=09) Clock = Enable/Disable Clock Menu (1) AM/PM = (1) AVL = Auto Volume Level (1) = (0) 1-norma = Default (0) Flof-Txt = (0) TR = (0) DVD Start = (0) *(1) Selected, (0) Not Selected 7
0 4 4 00 00
PT-92 Chassis Service Manual
OptByte6 UOC-J ignrSUP ignrNDF Pal-BG/DK Pal-L Eco WEB ST WSS TSL TEL TSM TEM TSH TEH TBL TBN TBH 45 118 118 400 400 863 03 06 85
(Default=00) = = = = = = = = Default Default Default (0) (0) (0) (0) (0) (0) (0) (0)
Start frequency of the low-band in MHz End frequency of the low-band Start frequency of the mid-band End frequency of the mid-band Start frequency of the high-band End frequency of the high-band hex Value needed for switching to the low-band hex Value needed for switching to the mid-band hex Value needed for switching to the high-band
16:9 / 4:3 Adjustment
The CTV832U software uses two sets of parameters for the registers HP (horizontal parallelogram), HB (horizontal bow), EW (EW width), PW (parabola/width), UCP (upper corner parabola), LCP (lower corner parabola) and IC (EW trapezium). They occur in the service menu for 16:9 screen with the listed abbreviations. For the 4:3 screen there is a second set of these registers. They occur in the service menu with the extension `4:3' (i.e. HP4:3, HB4:3,...). Each register set must be adjusted under the right conditions i.e. the 16:9 settings are adjusted with a 16:9 picture the 4:3 settings with a 4:3 picture. The inenu items EW, PW, UCP, LCP, TC, HP4:3, HB4:3,... TC4:3 and VX will only be in the service menu if the option 16:9 is set in 4 th option byte.
TUNER PARAMETER IN SERVICE AND DEFINITION TSL TEL TSM TEM TSH TEH TBL TBN TBH Start frequency of the low-band in MHz End frequency of the low-band Start frequency of the mid-band End frequency of the mid-band Start frequency of the high-band End frequency of the high-band hex Value needed for switching to the low-band hex Value needed for switching to the mid-band hex Value needed for switching to the high-band
PHILIPS 45 160 160 440 440 863 A1 92 34
OREGA 45 118 118 400 400 865 03 06 85
TEMIC 45 150 150 440 440 865 01 02 04
SAMSUNG 45 150 150 425 425 865 01 02 08
ALPS 45 180 180 465 465 900 01 02 0C
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PT-92 Chassis Service Manual
SPECIFICATIONS OF THE CONNECTOR
(EURO SCART)
I- Audio output 1. right channel 0.5 VRMS/10k 0 7- RGB input, blue (B) 8- Switch signal video (status) 9- GND 10- Reserved for clock signals (not connected) 11- RGB input, green (G) 12- Reserved for remote control (not connected) 13- GND 14- GND switch signal RGB 15- RGB input, red (R) 16- Switch signal RGB 17- GND (video) 18- GND19- Video output 1 Vpp/75 ohm 20- Video input 1 Vpp/75 ohm 21- Shield
1
3
5
7
9
11 13 15 17 19 21
2
4
6
8 10 12 14 16 18 20
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PT-92 Chassis Service Manual
POWER CORD
SAW FILTER
IR SENSOR
VOLTAGE REGULATOR
ON/OFF SWITCH
COMPONENT DESCRIPTIONS
LINE FILTER PTC NPN TRANSISTOR PNP TRANSISTOR CERAMIC FILTER COIL LINEARITY COIL FUSIBLE RESISTOR IW METAL OXIDE RESISTOR 1/2W METAL OXIDE RESISTOR 1/4 OR 1/6W CARBON FILM RESISTOR CERAMIC CAPACITOR /POLYESTER CAPACITOR ELECTROLYTIC CAPACITOR DIODE ZENER DIODE SWITCH JUMPER NET (INPUT) NET (OUTPUT) TACT SWITCH 10 10
PT-92 Chassis Service Manual
PT92 110o STEREO CHASSIS
I2C UV1316 PLL Tuner
STEREO I2C TDA2616 TDA9870A/75A Sound Processor Sound Amplifier R L
AGC SAV Filter
Scarts L/R
Sub
IF RGB Iblack Sound Trap TDA935X/6X/8X Vdrive PAL/SECAM/NTSC Externals L/R TV Signal Proc. Teletext Decoder µ-Controller RGB Processing Guard TDA8351 DC Vertical Amplifier Beam Current BU2525AF Hdrive Flyback Horizontal Deflection & EHT E/W (110o) RGB 12.000 Hor. EHT Ver. TDA6107Q Triple RGB Output Amplifier 110o
CVBS
Supply TDA16846 IC PCA8521 RC-5 Transmitter 16K EEPROM
2
Degaussing Mains 220
SMPS
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PT-92 Chassis Service Manual
PT92 90o STEREO CHASSIS
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PT-92 Chassis Service Manual
PT92 90o MONO CHASSIS
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PT-92 Chassis Service Manual
FAULT TRACING DIAGRAM-POWER SUPPLY
Switched mode power supply defective,+145V is missing or level is wrong
DP 01 ÷ 04 CP 01 ÷ 04 CP 06, TP01
YES
Fuse F1 defective
NO RP 07, RP 05 open and short circuit NO
Voltage at drain TP 01
YES
Voltage at IP 01 PIN 11 < 1V
YES RP 06
NO YES RP 11, DP 07
Start-up voltage (6) PIN 14 < 8V
NO YES TP 01
Start-up voltage varies ca. 8V
NO
IP 01
Measure +145 V
NO VAP 1, RP 03
+145V adjustable with VAP 01
YES
Control range of switched-mode power supply
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PT-92 Chassis Service Manual
POWER SUPPLY
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PT-92 Chassis Service Manual
TROUBLESHOOTING GUIDE FOR MAIN PCB
TROUBLE
No color Horizontal linearity Horizontal size Flue picture Dark picture Noise picture Interference No sound Sound distortion Memory No video on the SCART No audio on the SCART No picture CV37, CV38, XV01 LD02, RD20, DD06
CHECK POINTS
+B voltage, CD18, CD20, CD27, CD08, TV06 RD17, RD06, RD62, R001, Focus adjust Screen adjust, EHT voltage TU01, AGC adjust, If adjust TV01, TV04, TU01 IA50, IA51, IA01, DP17, DP12, RA51, X301, I302, IV01 I302, IC01, L304, CA07, CA06, RA06, RA07, IA01, IA50, IA51 IC02, IV01, TC10 IV01, TE01, TE04 I302, TV03 TD01, TD02, DD01, TD04, DD03, DD04, ID50, RD56, IV01
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PT-92 Chassis Service Manual
TDA16846
Controller For Switch Mode Power Supplies
The TDA16846 is suited for TV-, VCR-sets and SAT receivers. It also can be good used in PC monitors. The TDA 16847 is identical with TDA16846 but has an additional power measurement output (pin 8) which can be used a Temporary High Power Circuit.
Pin Configuration (top view)
DTC PCS RZI SRC OCI FC2 SYN
1 2 3 4 5 6 7
U
14 13 12 11 10 9 8
VCC OUT GND PVC FC1 REF N.C./PMO
Pin Definitions and Functions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol OTC PCS RZI SRC OCI FC2 SYN N.C./PMO REF FC1 PVC GND OUT VCC Function Off Time Circuit Primary Current Simulation Regulation and Zero Crossing Input Soft-Start and Regulation Capacitor Opto Coupler Input Fault Comparator 2 Synchronization Input Not Connected (TDA16846) Reference Voltage and Current Fault Comparator 1 Primary Voltage Check Ground Output Supply Voltage
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PT-92 Chassis Service Manual
TDA16846 Block Diagrams
PVC D4 SYN KSY R7 5V 30k R8 R4 Fold Back Point Correction R6x1/3 11 Primary Voltage Check 1V
+
R6 1.5V
PVA
D5
R3
+
+
15k 75k Control Voltage Limit 5V OTC 1 CS1 Off Time Comparator G1 1 ED2 RSTC/RSTF Eror Amplifier D2
3.5V + VCC 9 8 G4 1 R2 ErrorFlipflop S R Q 6 + FC2 1.2V REF N.C. FC2
+ -
3.5V
5V
RZI
3
+ D3 Buffer for Control Voltage
4 SRC OCI 5
+ + R1 20k
On Time Comparator
& S G2 I1 R Q
G3 &
Output Driver 13 OUT
PCS
2
5V
+
ED1 1.5V D1 Startup Diode 14 12 16V <25mV Overvoltage Comparator Supply Voltage Comparator FC1 1V Zero Crossing Signal
VCC GND
+ -
15.8V
+ -
10
+
1) The input with the lower voltage becomes operative
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PT-92 Chassis Service Manual
ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
All voltages listed are referenced to ground (0V, Vss) except where noted.
Parameter Supply Voltage at Pin 14 Voltage at Pin 1, 4, 5, 6, 7, 9, 10 Voltage at Pin 2, 8, 11 Voltage at Pin 3 Current into Pin 3 Current into Pin 9 Current into Pin 13 ESD Protection REF OUT -100 2 Symbol Vcc RZI -10 -1 100 Limit Values Min. -0.3 -0.3 -0.3 Typ. 17 6 17 6 Unit V V V V mA mA mA mA kV Remarks V3 < - 0.3V V13 > - Vcc V13 < - 0V MIIL STD 883C methot 3015.6, 100 PF, 1500 Storage Temperature Operating Junction Temperature Thermal Resistance Junction-Ambient Soldering Temperature Soldering Time 10 260 s
o
Tstg Tj RthJA
-65 -
125 125 110
o o
C C
P-DIP-14-3 -
K/W C
-
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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PT-92 Chassis Service Manual
Short Description of the Pin Functions
Pin 1
Functions A parallel RC-circuit between this pin and ground determines the ringing suppression time and the standby-frequency. A capacitor between this pin and ground and a resistor between this pin and the positive terminal of the primary elcap quantifies the max. possible output power of the SMPS. This is the input of the error amplifier and the zero crossing input. The output of a voltage divider between the control winding and ground is connected to this input. If the pulses at pin 3 exceed a 5 V threshold, the control voltage at pin 4 is lowered. This is the pin for the control voltage. A capacitor has to be connected between this pin and ground. The value of this capacitor determines the duration of the softstart and the speed of the control. If an opto coupler for the control is used, it's output has to be connected between this pin and ground. The voltage divider at pin 3 has then to be changed, so that the pulses at pin 3 are below 5 V. Fault comparator 2: If a voltage > 1.2 V is applied to this pin, the SMPS stops. If fixed frequency mode is wanted, a parallel RC circuit has to be connected between this pin and ground. The RC-value determines the frequency. If synchronized mode is wanted, sync pulses have to be fed into this pin. Not connected (TDA16846). / This is the power measurement output of the Temporary High Power Circuit. A capacitor and a RC-circuit has to be connected between this pin and ground. Output for reference voltage (5 V). With a resistor between this pin and ground the fault comparator 2 (pin 6) is enabled. Fault comparator i: If a voltage > 1 V is applied to this pin, the SMPS stops. This is the input of the primary voltage check. The voltage at the anode of the primary elcap has to be fed to this pin via a voltage divider. If the voltage of this pin falls below 1 V, the SMPS is switched off. A second function of this pin is the primary voltage dependent fold back point correction (only active in free running mode). Common ground. Output signal. This pin has to be connected across a serial resistor with the gate of the power transistor. Connection for supply voltage and startup capacitor. After startup the supply voltage is produced by the control winding of the transformer and rectified by an external diode.
2
3
4
5
6 7
8
9
10 11
12 13
14
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PT-92 Chassis Service Manual
TDA935X/6X/8X
TV signal processor-Teletext decoder with embedded µ-Controller
GENERAL DESCRIPTION
The various versions of the TDA935X/6X/8X series combine the functions of a n/ signal processor together with a µ-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1 or 10 page text. The ICs are intended to be used in economy television receivers with 90o and 110o picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they are mounted in S-DIP envelope with 64 pins. The features are given in the following feature list. The differences between the various ICs are given in the table on page 4.
FEATURES
TV-signal processor · Multi-standard vision IF circuit with alignment-free PLL demodulator · Internal (switchable) time-constant for the IF-AGC circuit · A choice can be made between versions with mono intercarrier sound FM demodulator and versions with QSS IF amplifier. · The mono intercarrier sound versions have a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. · Source selection between 'internal' CVBS and external CVBS or Y/C signals · Integrated chrominance trap circuit · Integrated luminance delay line with adjustable delay time · Asymmetrical `delay line type' peaking in the luminance channel · Black stretching for non-standard luminance signals · Integrated chroma band-pass filter with switchable centre frequency · Only one reference (12 MHz) crystal required for the CL-Controller, Teletext- and the colour decoder · PAL/NTSC or multi-standard colour decoder with automatic search system · Internal base-band delay line · RGB control circuit with `Continuous Cathode Calibration', white point and black level off set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. · Linear RGB or YUV input with fast blanking for external RGB/YUV sources. The Text/OSD signals are internally supplied from the µ-Controller/Teletext decoder · Contrast reduction possibility during mixed-mode of OSD and Text signals · Horizontal synchronization with two control loops and alignment-free horizontal oscillator · Vertical count-down circuit · Vertical driver optimized for DC-coupled vertical output stages · Horizontal and vertical geometry processing · Horizontal and vertical zoom function for 16 : 9 applications · Horizontal parallelogram and bow correction for large screen picture tubes
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PT-92 Chassis Service Manual
µ-CONTROLLER
· 80C51 µ-controller core standard instruction set and timing · 1 µs machine cycle · 32 - 128Kx8-bit late programmed ROM · 3 - 12Kx8-bit Auxiliary RAM (shared with Display and Acquisition) · Interrupt controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · WatchDog timer · Auxiliary RAM page pointer · 16-bit Data pointer · IDLE and Power Down (PD) mode · 14 bits PWM for Voltage Synthesis Tuning · 8-bit A/D converter · 4 pins which can be programmed as general I/O pin, ADC input or PWM (6-bit) output
DISPLAY
· · · · · · · · · · · · · · · · Teletext and Enhanced OSD modes Features of level 1.5 WST and US Close Caption Serial and Parallel Display Attributes Single/Double/Quadruple Width and Height for characters Scrolling of display region Variable flash rate controlled by software Enhanced display features including overlining, underlining and italics Soft colours using CLUT with 4096 colour palette Globally selectable scan lines per row (9/10/13/16) and character matrix [12x10, 12x13, 12x16 (VxH)] Fringing (Shadow) selectable from N-S-E-W direction Fringe colour selectable Meshing of defined area Contrast reduction of defined area Cursor Special Graphics Characters with two planes, allowing four colours per character 32 software redefinable On-Screen display characters 4 WST Character sets (GO/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) G1 Mosaic graphics, Limited G3 Line drawing characters WST Character sets and Closed Caption Character set in single device.
DATA CAPTURE
· Text memory for 1 or 10 pages · In the 10 page versions inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) · Data Capture for US Closed Caption · Data Capture for 525/625 line WST, VPS (PDC system A) and Wise Screen Signalling (WSS) bit decoding · Automatic selection between 525 WST/625 WST · Automatic selection between 625 WST/VPS on line 16 of VBI · Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput · Automatic detection of FASTEXT transmission · Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters · Signal quality detector for video and WST/VPS data types · Comprehensive teletext language coverage · Full Field and Vertical Blanking Interval (VBI) data capture of WST data · · ·
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PT-92 Chassis Service Manual
Block Diagram
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PT-92 Chassis Service Manual
QUICK REFERENCE DATA
SYMBOL Supply VP Ip Input voltages ViSIF(rms) ViVIF(rms) ViAUDIO(rms) ViCVBS(p-p) video IF amplifier sensitivity (RMS value) QSS sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) (peak-to-peak value) ViRGB(p-p) ViYIN(p-p) ViUVIN(p-p) Output signals Vo(IFVO(p-p) Vo(QSSO)(rms) Io(AGCOUT) VoRGB(p-p) Io HOUT Io VERT Io EWD demodulated CVBS output (peak-to-peak value) sound IF intercarrier output in QSS versions (RMS value) tuner AGC output current range RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current 0 10 1 1.2 2.5 100 500 2.0 5 V mV mV mV V mA mA mA RGB inputs (peak-to-peak value) luminance input signal (peak-to-peak value) U/V input signal (peak-to-peak value) 0.7 1.4 1.33/1.05 V V V 35 60 500 1.0 0.3 µV µV mV V V supply voltage supply current 8.0/3.3 tbf V mA PARAMETER Min. Typ. Max. Unit
ViCHORAMA(p-p) external chroma input voltage (burst amplitude)
Vo(AMOUT)(rms) demodulated AM sound output in QSS versions (RMS value)
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PT-92 Chassis Service Manual
PINNING
SYMBOL P1.3TT1 P1.6/SCL P1.7/SDA P2. O/TPWM P3.0/ADC0 P3.1/ADCI P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1 GND2 SNDPLL/SIFAGC HOUT FBISO AUDEXT/ QSSO/AMOUT EHTO PLLIF IFVO/SVO VP1 CVBSINT
(1) (1) (1) (1) (1) (1)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DESCRIPTION port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line port 2.0 or Tuning PWM output port 3.0 or ADC0 input port 3.1 or ADC1 input port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 0.5 (8 mA current sinking capability for direct drive of LEDs) port 0.6 (8 mA current sinking capability for direct drive of LEDs) analog ground of Teletext decoder and digital ground of TV- processor SECAM PLL decoupling 2nd supply voltage TV-processor (+8V) decoupling digital supply of TV-processor phase-2 filter phase-1 filter ground 3 for TV-processor bandgap decoupling Automatic Volume Levelling /East-West drive output vertical drive B output vertical drive A output IF input 1 IF input 2 reference current input vertical sawtooth capacitor tuner AGC output audio deemphasis or SIF input 1 decoupling sound demodulator or SIF input 2 ground 2 for TV-processor narrow band PLL filter / AGC sound IF Automatic Volume Levelling / subcarrier reference output/AM output (non controlled) horizontal output flyback input/sandcastle output external audio input/QSS intercarrier out /AM audio output (non controlled) EHT/overvoltage protection input IF-PLL loop filter IF video output / selected CVBS output main supply voltage TV-processor (+8 V) internal CVBS input
DECSDEM/SIFIN2
AVL/REF0/AMOUT
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PT-92 Chassis Service Manual
PINNING
SYMBOL GND1 CVBS/Y CHROMA AUDOUT / AMOUT INSSW2 R2/VIN G2 YIN B2 UIN BCLIN BLKIN RO GO BO VDDA VPE VDDC OSCGND XTALIN XTALOUT RESET VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 Note
1. The function of pin 20, 28, 29, 31, 32, 35 and 44 is dependent on the IC version (mono irtercarrier FM demodulator / QSS IF amplifier and East-West output or not) and on some software control bits. The valid combinations are given in table 1.
(1)
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
DESCRIPTION ground 1 for TV-processor external CVBS/Y input chrominance input (SVHS) audio output / AM audio output (volume controlled) 2nd RGB /YUV insertion input 2nd R input / V (R-Y) input 2nd G input Y input 2nd B input / U (B-Y) input beam current limiter input/V-guard input black current input Red output Green output Blue output analog supply of Teletext decoder and digital supply of TV-processor (3.3 V) OTP Programming Voltage digital supply to core (3.3V) oscillator ground supply crystal oscillator input crystal oscillator output reset digital supply to periphery (+3.3 V) port 1.0 or external interrupt 1 input port 1.1 or Counter/Timer 0 input port 1.2 or external interrupt 0 input
Table 1 Pin functions for various versions IC version East-West Y/N CMB1/CMB0 bits AM bit Pin 20 Pin 28 Pin 29 Pin 31 Pin 32 Pin 35 Pin 44 REFO N AVL 00 EWD AUDEEM DECSDEM SNDPLL AVL AUDEXT AUDOUT REFO AMOUT AUDEX REFO QSSO AMOUT FM-PLL version Y 01/10/11 00 N 01/10/11 0 AVL SIFIN1 SIFIN2 SIFAGC AMOUT AUDEXT REFO QSSO AMOUT 1 QSS version Y 00 01/10/11 0 EWD 1
controlled AM out
26
PT-92 Chassis Service Manual
Pin configuration (SDIP 64)
P1.3TT1 P1.G/SCL P1.7/SDA
P2.0TPMW
1 2 3 4 5 6 7 8 9 10 11 12
U
64 63 62 61 60 59 58 57 56 55 54 53
P1.2/ONTO P1.1/TO P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VPE VDDA BO GO RO BLKIN BCLIN B2/UIN G2/YIN R2/VIN INSSW2 AUDOUT/AMOUT CHROMA CVBS/Y GND1
P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1 DECSDEM/SIFIN(2) GND2 SNDPLL/SIFAGC AVLIREFO/AMOUT
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA935X/6X/8X
27
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CVBSINT VP1 IFVO/SVO PLLIF EHTO AUDEXT/QSSO/ AMOUT FBISO HOUT
PT-92 Chassis Service Manual
TDA9875A
Digital TV sound processor (DTVSP)
FEATURES
1.1 Demodulator and decoder section · Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources · SIF AGC with 24 dB control range · SIF 8-bit Analog-to-Digital Converter (ADC) · DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation · NICAM decoding (B/G, I and L standard) · Two-carrier multistandard FM demodulation (B/G, D/K and M standard) · Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound · Optional AM demodulation for system L, simultaneously with NICAM · Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 DSP section · Digital crossbar switch for all digital signal sources and destinations · Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute · Plop-free volume control · Automatic Volume Level (AVL) control · Adaptive de-emphasis for satellite · Programmable beeper · Monitor selection for FM/AM DC values and signals, with peak detection option · I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. 1.3 Analog audio section · Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output · User defined full-level/-3 dB scaling for SCART outputs · Output selection of mono, stereo, dual A/B, dual A or dual B · 20 kHz bandwidth for SCART-to-SCART copies · Standby mode with functionality for SCART copies · Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 kHz 28
· Dual audio ADC from analog inputs to DSP · Two dual audio Digital-to-Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.
2 GENERAL DESCRIPTION
The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and digital multi-channel sound systems in TV sets and satellite receivers. 2.1 Supported standards The muItistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, 1, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator stage, however this gives limited performance. Korea has a stereo sound system similar to Europe and is supported by the TDA9875A. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in Table 1. The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2 carrier systems).
PT-92 Chassis Service Manual
2.1.1 ANALOG 2-CARRIER SYSTEMS
Table 1 Frequency modulation
STANDARD M M B/G I D/K D/K SOUND SYSTEM mono A2+ A2 mono A2 A2* CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.5/6.742 6.5/6.742 6.5/6.258 FM DEVIATION (kHz) NOM./MAX./OVER 15/25/50 15/25/50 27/50/80 27/50/80 27/50/80 27/50/80 MODULATION SC1 mono 1/2 (L + R) 1/2 (L + R) mono 1/2 (L + R) 1/2 (L + R) SC2 1/2 (L - R) R R R BANDWIDTH DE-EMPHASIS (kHz/µs) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50
Table 2 Identification for A2 systems
PARAMETER Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth A2/A2* 54.6875 kHz = 3.5 x line frequency 117.5 Hz = line frequency 133 274.1Hz = line frequency 57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency 149.9 Hz = line frequency 105 276.0 Hz = line frequency 57 50%
2.1.2 2-CARRIER SYSTEMS WITH NICAM
Table 3 NICAM
SC1 MODULATION STANDARD FREQUENCY (MHz) TYPE INDEX (%) NOM./MAX. 54/100 DEVIATION (kHz) NOM./MAX. 27/50 27/50 27/50 SC2 (MHz) NICAM DE-EMPHASIS ROLL-OFF (%) NICAM CODING
B/G I D/K L
5.5 6.0 6.5 6.5
FM FM FM AM
5.85 6.552 5.85 5.85
J17 J17 J17 J17
40 100 40 40
note 1 note 1 note 2 note 1
Notes
1. See "EBU specification" or equivalent specification. 2. Not yet defined
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PT-92 Chassis Service Manual
2.1.3 SATELLITE SYSTEMS
An important for satellite TV reception is the `Astra specification". The TDA9875A is suited for the reception of Astra and other satellite signals. Table 4 FM satellite sound
CARRIER TYPE CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 MODULATION INDEX MAXIMUM FM DEVIATION (kHz) 85 50 50 50 50 MODULATION BANDWIDTH DE-EMPHASIS (kHz/µs) 15/50(1) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3)
main sub sub sub sub
0.26 0.15 0.15 0.15 0.15
mono m/st/d(2) m/st/d(2) m/st/d(2) m/st/d(2)
Notes 1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 µs, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis = compatible to transmitter specification.
3 ORDERING INFORMATION
TYPE NUMBER NAME TDA9875A SDIP64 PACKAGE DESCRIPTION plastic shrink dual-in-line package; 64 leads (750 mil) VERSION SOT274-1
30
PT-92 Chassis Service Manual
Block Diagram
SIF2
10 9 20 3 13 4 5
SIF1
12
P1 P2 ADDR1 ADDR2 SCL SDA
7
IC
2
INPUT SWITCH AGC, ADC
SUPPLY SIF
6 11 8
VDEC1 VSSA1 Vref 1 Iref
IDENTIFICATION
FM (AM) DEMODULATION
NICAM DEMODULATION
2 1
NICAM PCLK SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL
XTALI XTALO
18 19
CLOCK
21
A2 DECODER & SAT DECODER
33 34
NICAM DECODER ANALOG CROSSBAR SWITCH
SYSCLK
36 37 31 32 29
47 48 51 52 63 62
PEAK DETECTION
LEVEL ADJUST
LEVEL ADJUST
SDI1 SDI2 SDO1 SDO2 SCK WS VDDD1 VDDD2 VSSD1 VSSD2 VSSD3 VSSD4 CRESET
27 26 25 24 22 23 41
I2S
DIGITAL SELECT
ADC (2)
42 44 45
i.c. i.c. i.c. i.c.
15 64 14 49 35 17 16 59
DIGITAL SUPPLY
DAC (2)
54 55
PCAPR PCAPL VDDA VDEC2 Vref(p) Vref(n) Vref2 Vref3 VSSA2 VSSA3 VSSA4
TDA9875A
AUDIO PROCESSING
SUPPLY SCART, DAC, ADC
38 39 40
46 53
TEST1 TEST2
28 30
TEST
DAC (2)
DAC (2)
43 56 50
61
60
58
57
MOL MOR
AUXOL AUXOR
31
PT-92 Chassis Service Manual
Pin configuration
PCLK NICAM
ADDR1 SCL SDA VSSA1 VDEC1 Iref
1 2 3 4 5 6 7 8 9 10 11 12 13
U
64 63 62 61 60 59 58 57 56 55 54 53 52
VDDD2 LOR LOL MOL MOR VDDA AUXOL AUXOR VSSA3 PCAPL PCAPR Vref3 SCOL2 SCOR2 VSSA4 VSSD2 SCOL1 SCOR1 Vref2 i.c. i.c. VSSA2 i.c. i.c.
P1 SIF2
Vref1
SIF1
ADDR2
VDDD1 CRESET VSSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA9875A
32
VSSD1
14
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vref(n) Vref(p) VDEC2 SCIL2 SCIR2 VSSD3 SCIL1 SCIR1
PT-92 Chassis Service Manual
SYMBOL PCLK NICAM
ADDR1 SCL SDA VSSA1 VDEC1 Iref
PIN 1
2 3 4 5 6 7 8 9
I/O O
O I I I/O supply I/O
DESCRIPTION NICAM clock output at 728 Khz
serial NICAM data output at 728 kHz first I2C-bus slave address modifier I2C-bus clock I2C-bus data supply ground 1; analog front-end circuitry positive power supply voltage 1 decoupling; analog front-end circuitry resistor for reference current generator; analog front-end circuitry first general purpose I/O pin
P1 SIF2
Vref1
10
11
-
sound IF input 2
reference voltage; analog front-end circuitry
SIF1
ADDR2
12
13
I
I supply supply
sound IF input 1
second I2C-bus slave address modifier supply ground 1; digital circuitry digital supply voltage 1; digital circuitry
VSSD1 VDDD1 CRESET VSSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL SCIR1 SCIL1 VSSD3 SCIR2 SCIL2 VDEC2
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
supply
capacitor for power-on reset
supply ground 4; digital circuitry
I O I/O O I/O I/O O O I I I I I I I I I supply I I -
crystal oscillator input crystal oscillator output
second general purpose I/O pin
system clock output
I2C-bus clock I2C-bus word select I2C-bus data output 2 I2C-bus data output 1 I2C-bus data input 2 I2C-bus data input 1
first test pin; connected to VSSD1 for normal operation audio mono input second test pin; connected to VSSD1 for normal operation external audio input right channel external audio input left channel SCART 1 input right channel SCART 1 input left channel
supply ground 3; digital circuitry
SCART 2 input right channel SCART 2 input left channel
positive power supply voltage 2 decoupling; audio analog to digital converter circuitry
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PT-92 Chassis Service Manual
SYMBOL Vref(p) PCLKVref(n)
i.c. i.c. VSSA2 i.c. i.c. Vref2 SCOR1 SCOL1 VSSD2 VSSA4 SCOR2 SCOL2 Vref3 PCAPR PCAPL VSSA3 AUXOR AUXOL VDDA MOR MOL LOL LOR VDDD2
PIN 39
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O -
DESCRIPTION
positive reference voltage; audio analog to digital converter circuitry reference voltage ground; audio analog-to-digital converter circuitry internally connected; note 1 internally connected; note 2
supply supply ground; audio analog-to-digital converter circuitry O O supply supply O O supply O O O O supply O O supply internally connected; note 2 internally connected; note 1 reference voltage; audio analog-to-digital converter circuitry SCART 1 output right channel SCART 1 output left channel supply ground 2; digital circuitry supply ground 4; audio operational amplifier circuitry SCART 2 output right channel SCART 2 output left channel reference voltage; audio digital to analog converter and operational amplifier circuitry post filter capacitor pin right channel, audio digital-to-analog converter post filter capacitor pin left channel, audio digital-to-analog converter supply ground 3; audio analog-to-digital converter circuitry headphone (auxiliary) output right channel headphone (auxiliary) output left channel positive analog power supply voltage; analog circuitry loudspeaker (Main) output right channel loudspeaker (Main) output left channel line output left channel line output right channel digital supply voltage 2; digital circuitry
Notes
1. Test pin, CMOS level input, pull-up resistor, can be connected to VSS. 2. Test pin, CMOS 3-state stage, can be connected to VSS.
34
PT-92 Chassis Service Manual
TDA9870A
Digital TV sound processor (DTVSP)
FEATURES
1.1 Demodulator and decoder section · Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources · SIF AGC with 24 dB control range · SIF 8-bit Analog-to-Digital Converter (ADC) · Two-carrier multistandard FM demodulation (B/G, D/K and M standard) · Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound · Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 DSP section · Digital crossbar switch for all digital signal sources and destinations · Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute · Plop-free volume control · Automatic Volume Level (AVL) control · Adaptive de-emphasis for satellite · Programmable beeper · Monitor selection for FM/AM DC values and signals, with peak detection option · I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. 1.3 Analog audio section · Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output · User defined full-level/-3 dB scaling for SCART outputs · Output selection of mono, stereo, dual A/B, dual A or dual B · 20 kHz bandwidth for SCART-to-SCART copies · Standby mode with functionality for SCART copies · Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 kHz · Dual audio ADC from analog inputs to DSP · Two dual audio Digital-to-Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.
2 GENERAL DESCRIPTION
The TDA9870A is a single-chip Digital TV Sound Processor (DTVSP) for analog multi-channel sound systems in TV sets and satellite receivers. 2.1 Supported standards The multistandard/multi-stereo capability of the TDA9870A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. Korea has a stereo sound system similar to Europe and is supported by the TDA9870A. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in.(Table 1). The analog multi-channel sound systems (A2, A2+ and AP) are sometimes also named 2CS (2 carrier systems).
35
PT-92 Chassis Service Manual
2.1.1 ANALOG 2-CARRIER SYSTEMS
Table 1 Frequency modulation
STANDARD M M B/G I D/K D/K SOUND SYSTEM mono A2+ A2 mono A2 A2* CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.0 6.5/6.742 6.5/6.258 FM DEVIATION (kHz) NOM./MAX./OVER 15/25/50 15/25/50 27/50/80 27/50/80 27/50/80 27/50/80 MODULATION SC1 mono 1/2 (L + R) 1/2 (L + R) mono 1/2 (L + R) 1/2 (L + R) SC2 1/2 (L - R) R R R BANDWIDTH DE-EMPHASIS (kHz/µs) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50
Table 2 Identification for A2 systems
PARAMETER Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth A2/A2* 54.6875 kHz = 3.5 x line frequency 117.5 Hz = line frequency 133 274.1Hz = line frequency 57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency 149.9 Hz = line frequency 105 276.0 Hz = line frequency 57 50%
2.1.2 SATELLITE SYSTEMS
An important for satellite TV reception is the `Astra specification". The TDA9875A is suited for the reception of Astra and other satellite signals.
Table 3 FM satellite sound
CARRIER TYPE CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 MODULATION INDEX MAXIMUM FM DEVIATION (kHz) 85 50 50 50 50 MODULATION BANDWIDTH DE-EMPHASIS (kHz/µs) 15/50(1) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3)
main sub sub sub sub
0.26 0.15 0.15 0.15 0.15
mono m/st/d(2) m/st/d(2) m/st/d(2) m/st/d(2)
Notes
1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 µs, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis = compatible to transmitter specification.
3 ORDERING INFORMATION
TYPE NUMBER NAME TDA9875A SDIP64 PACKAGE DESCRIPTION plastic shrink dual-in-line package; 64 leads (750 mil) VERSION SOT274-1
36
PT-92 Chassis Service Manual
Block Diagram
SIF2
10 9 20 3 13 4 5
SIF1
12
P1 P2 ADDR1 ADDR2 SCL SDA
7
IC
2
INPUT SWITCH AGC, ADC
SUPPLY SIF
6 11 8
VDEC1 VSSA1 Vref 1 Iref
IDENTIFICATION
FM (AM) DEMODULATION
XTALI XTALO
18 19
CLOCK
21
A2 DECODER & SAT DECODER ANALOG CROSSBAR SWITCH
33 34 36 37 31 32 29
SYSCLK
SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL
47 48 51 52 63 62
PEAK DETECTION
LEVEL ADJUST
SDI1 SDI2 SDO1 SDO2 SCK WS VDDD1 VDDD2 VSSD1 VSSD2 VSSD3 VSSD4 CRESET
27 26 25 24 22 23 41
I2S
DIGITAL SELECT
ADC (2)
42 44 45
i.c. i.c. i.c. i.c.
15 64 14 49 35 17 16 59
DIGITAL SUPPLY
DAC (2)
54 55
PCAPR PCAPL VDDA VDEC2 Vref(p) Vref(n) Vref2 Vref3 VSSA2 VSSA3 VSSA4
TDA9870A
AUDIO PROCESSING
SUPPLY SCART, DAC, ADC
38 39 40
46 53
TEST1 TEST2
28 30
TEST
DAC (2)
DAC (2)
43 56 50
61
60
58
57
MOL MOR
AUXOL AUXOR
37
PT-92 Chassis Service Manual
SYMBOL i.c.
i.c. ADDR1 SCL SDA VSSA1 VDEC1 Iref
PIN 1
2 3 4 5 6 7 8 9
I/O I I I/O supply I/O
DESCRIPTION internal connected; note 1 internal connected; note 1
first I2C-bus slave address modifier I2C-bus clock I2C-bus data supply ground 1; analog front-end circuitry positive power supply voltage 1 decoupling; analog front-end circuitry resistor for reference current generator; analog front-end circuitry first general purpose I/O pin
P1 SIF2
Vref1
10
11
-
sound IF input 2
reference voltage; analog front-end circuitry
SIF1
ADDR2
12
13
I
I supply supply
sound IF input 1
second I2C-bus slave address modifier supply ground 1; digital circuitry digital supply voltage 1; digital circuitry
VSSD1 VDDD1 CRESET VSSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL SCIR1 SCIL1 VSSD3 SCIR2 SCIL2 VDEC2
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
supply
capacitor for power-on reset
supply ground 4; digital circuitry
I O I/O O I/O I/O O O I I I I I I I I I supply I I -
crystal oscillator input crystal oscillator output
second general purpose I/O pin
system clock output
I2C-bus clock I2C-bus word select I2C-bus data output 2 I2C-bus data output 1 I2C-bus data input 2 I2C-bus data input 1
first test pin; connected to VSSD1 for normal operation audio mono input second test pin; connected to VSSD1 for normal operation external audio input right channel external audio input left channel SCART 1 input right channel SCART 1 input left channel
supply ground 3; digital circuitry
SCART 2 input right channel SCART 2 input left channel
positive power supply voltage 2 decoupling; audio analog to digital converter circuitry
38
PT-92 Chassis Service Manual
SYMBOL Vref(p) Vref(n)
i.c. i.c. VSSA2 i.c. i.c. Vref2 SCOR1 SCOL1 VSSD2 VSSA4 SCOR2 SCOL2 Vref3 PCAPR PCAPL VSSA3 AUXOR AUXOL VDDA MOR MOL LOL LOR VDDD2
PIN 39
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O supply O O supply supply O O supply O O supply O O O O supply
DESCRIPTION
positive reference voltage; audio analog to digital converter circuitry reference voltage ground; audio analog-to-digital converter circuitry internally connected; note 2 internally connected; note 3 supply ground; audio analog-to-digital converter circuitry internally connected; note 3 internally connected; note 2 reference voltage; audio analog-to-digital converter circuitry SCART 1 output right channel SCART 1 output left channel supply ground 2; digital circuitry supply ground 4; audio operational amplifier circuitry SCART 2 output right channel SCART 2 output left channel reference voltage; audio digital to analog converter and operational amplifier circuitry post filter capacitor pin right channel, audio digital-to-analog converter post filter capacitor pin left channel, audio digital-to-analog converter supply ground 3; audio analog-to-digital converter circuitry headphone (auxiliary) output right channel headphone (auxiliary) output left channel positive analog power supply voltage; analog circuitry loudspeaker (Main) output right channel loudspeaker (Main) output left channel line output left channel line output right channel digital supply voltage 2; digital circuitry
Notes
1. Test pin, CMOS 3-state stage, pull-up resistor, can be connected to VSS. 2. Test pin, CMOS level input, pull-up resistor, can be connected to VSS. 3. Test pin, CMOS 3-state stage, can be connected to VSS.
39
PT-92 Chassis Service Manual
Pin configuration
i.c.
i.c. ADDR1 SCL SDA VSSA1 VDEC1 Iref
1 2 3 4 5 6 7 8 9 10 11 12 13
U
64 63 62 61 60 59 58 57 56 55 54 53 52
VDDD2 LOR LOL MOL MOR VDDA AUXOL AUXOR VSSA3 PCAPL PCAPR Vref3 SCOL2 SCOR2 VSSA4 VSSD2 SCOL1 SCOR1 Vref2 i.c. i.c. VSSA2 i.c. i.c.
P1 SIF2
Vref1
SIF1
ADDR2
VDDD1 CRESET VSSD4 XTALI XTALO P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA9870A
40
VSSD1
14
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vref(n) Vref(p) VDEC2 SCIL2 SCIR2 VSSD3 SCIL1 SCIR1
PT-92 Chassis Service Manual
FUNCTIONAL DESCRIPTION
Description of the demodulator and decodersection
6.1.1 SIF INPUT Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internal switchable -10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 AGC The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen (see table 14; subaddress 0). The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10). 6.1.3 MIXER The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. 6.1.4 FM AND AM DEMODULATION An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. 6.1.5 FM AND AM DEMODULATION The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. 6.1.6 CRYSTAL OSCILLATOR The crystal oscillator (XO) is illustrated in Fig.8 (see Chapter 12). The circuitry of the XO is fully integrated, only the external 24.576 MHz crystal is needed.
6.1.7 TEST PINS Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1. Test functions are fo manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors. 6.1.8 POWER-ON RESET FLIP-FLOP The power-on reset flip-flop monitors the internal power supply for the digital part of the device. If the supply has temporary been lower than the specified lower limit, the power-on reset bit FOR, transmitter register subaddress O (see Section 10.4.1), will be set to HIGH. The CLRPOR bit, slave register subaddress 1 (see Section 10.3.2), resets the power-on reset flip-flop to LOW.
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Description of the DSP
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6.2.1 LEVEL SCALING
All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of ±15 dB. It is recommended to scale all input channels to be 15 dB below full scale (-15 dB full scale) under nominal conditions.
6.2.2 FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator, due to carrier frequency offsets, and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The de-emphasis function offers fixed settings for the supported standards (50 µs, 60 µs and 75 µs). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2 stereo, dual and mono signals.
6.2.3 MONITOR
This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the outputs of the ADC. Source selection and data read-out is performed via the I2C-bus. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection.
and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between +12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and -93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking.
6.2.5 HEADPHONE (AUXILIARY) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to -83 dB with 1 dB resolution. There is also a mute position.
6.2.4 LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of -23 dB full scale for input levels between 0 and -29 dB full scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s. Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the 12C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left
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For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the 12C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between +12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the 12C-bus data byte +8 sets the new value to +8 dB). The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and -93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking.
6.2.8 CHANNEL TO THE ANALOG CROSSBAR PATH
Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB.
6.2.9 DIGITAL CROSSBAR SWITCH (See Fig.6)
Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path and from the loudspeaker channel path after matrix and AVL. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. The I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals.
6.2.10 GENERAL
There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full scale (15 dB full scale). This means that a volume setting of, say, +15 dB would just produce a full scale output signal and not cause clipping, if the signal level is nominal. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions.
6.2.6 FEATURE INTERFACE
The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a range of ±15 dB with 1 dB resolution. Outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2. One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel.
6.2.11 EXPERT MODE
The TDA9870A provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. More information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available
6.2.7 CHANNEL FROM THE AUDIO ADC
The signal level at the output of the ADC can be adjusted in a range of ±15 dB with 1 dB resolution. The audio ADC itself is scaled to a gain of -6 dB.
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ST24C16, ST25C16, ST24W16, ST25W16
Serial 16 K (2K x 8) Eeprom
· 1 million erase/write cycles, with 40 years data retention · Single supply voltage: - 4.5V to 5.5V for ST24x16 versions - 2.5V to 5.5V for ST25x16 versions · Hardware write control versions: ST24W16 and ST25W16 · Two wire serial interface, fully I2C Bus compatible · Byte and Multibyte write (up to 8 bytes) for the ST24C16 · Page write (up to 16 bytes) · Byte, random and sequent>al read modes · Self timed programming cycle · Automatic address incrementing · Enhanced ESD/Latch up performances
8 8 1 PSDIP8 (B) 0.25mm Frame 1 SO8 (M) 150 mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 16K bits I2C bus EEPROM products, the ST24/25C16 and the ST24/25W16. In the text, products are referred to as ST24/25x16 where "X" is: "C" for Standard version and "W" for hardware Write Control version. The ST24/25x16 are 16K bit electrically erasable programmable memories (EEPROM), organized as 8 blocks of 256 x 8 bits. These are manufactured in SGSThomson's Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The ST25x16 operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are Available.
VCC
2 PBO-PB1 PRE SCL MODE/WC*
ST24x16 ST25x16
SDA
Table 1. Signal Names
PRE PB0, PB1 SDA SCL MODE WC Vcc Vss Write Protect Enable Protect Block Select Serial Data Address Input/Output Serial Clock Multybyte/Page Write Mode (C version) Write Control (W version) Supply Voltage Ground
Note: WC signal is only available for ST24/25W16 products VSS
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DIP Pin Connections
ST24x16 ST25x16
PRE
PBO PB1 VSS
SO8 Pin Connections
ST24x16 ST25x16
VCC MODE/WC SCL SDA
1 2 3 4
U
8 7 6 5
PRE
PBO PB1 VSS
1 2 3 4
U
8 7 6 5
VCC MODE/WC SCL SDA
Table 2. Absolute Maximum Ratings
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering
(1)
Value -40 to 125 -65 to 150 (SO8) (PSDIP8) 40 sec 10 sec 215 260 -0.6 to 6.5 -0.3 to 6.5 4000 500
Unit
o
C C C C
o
o o
Input or Output Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body Model) (2) Electrostatic Discharge Voltage (Machine Model) (3)
V V V V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500; MIL-STD-883C, 3015.7 3. 200pF through 0; EIAJ IC-121 (condition C)
DESCRIPTION
The memories are compatible with the I2C standard two wire serial interface which uses a bi-directional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The memories behave as slave devices in the I2C protocol with all memory with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 block select bits, plus one read/write bit and terminated by an acknowledge bit. When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition .
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TDA8351
DC-coupled vertical deflection circuit
FEATURES
· Few external components · Highly efficient fully DC-coupled verti