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XTR101
SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
Precision, Low Drift 4-20mA TWO-WIRE TRANSMITTER
FEATURES
D INSTRUMENTATION AMPLIFIER INPUT:
- Low Offset Voltage, 30µV max - Low Voltage Drift, 0.75µV/°C max - Low Nonlinearity, 0.01% max
DESCRIPTION
The XTR101 is a microcircuit, 4-20mA, two-wire transmitter containing a high accuracy instrumentation amplifier (IA), a voltage-controlled output current source, and dual-matched precision current reference. This combination is ideally suited for remote signal conditioning of a wide variety of transducers such as thermocouples, RTDs, thermistors, and strain gauge bridges. State-of-theart design and laser-trimming, wide temperature range operation, and small size make it very suitable for industrial process control applications. In addition, the optional external transistor allows even higher precision. The two-wire transmitter allows signal and power to be supplied on a single wire pair by modulating the power-supply current with the input signal source. The transmitter is immune to voltage drops from long runs and noise from motors, relays, actuators, switches, transformers, and industrial equipment. It can be used by OEMs producing transmitter modules or by data acquisition system manufacturers.
IREF1 IREF2 10 e1 3 - 11 +VCC 8 Optional External Transistor
D TRUE TWO-WIRE OPERATION:
- Power and Signal on One Wire Pair - Current Mode Signal Transmission - High Noise Immunity
D D D D
DUAL MATCHED CURRENT SOURCES WIDE SUPPLY RANGE: 11.6V to 40V SPECIFICATION RANGE: -40°C to +85°C SMALL DIP-14 PACKAGE, CERAMIC AND PLASTIC
APPLICATIONS
D INDUSTRIAL PROCESS CONTROL:
- Pressure Transmitters - Temperature Transmitters - Millivolt Transmitters
D D D D D D D
RESISTANCE BRIDGE INPUTS THERMOCOUPLE INPUTS RTD INPUTS CURRENT SHUNT (mV) INPUTS PRECISION DUAL CURRENT SOURCES AUTOMATED MANUFACTURING POWER/PLANT ENERGY SYSTEM MONITORING
e2 4 + 14 7 Span 6 XTR101 5
12(1) B
9 13(1) E 2 IOUT
1
Optional Offset Null NOTE: (1) Pins 12 and 13 are used for optional BW control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1986-2004, Texas Instruments Incorporated
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XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply, +VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Input Voltage, e1 or e2 . . . . . . . . . . . . . . . . . . . . VOUT, +VCC Storage Temperature Range, Ceramic . . . . . . . . . -55°C to +165°C Plastic . . . . . . . . . . -55°C to +125°C Lead Temperature (soldering, 10s) G, P . . . . . . . . . . . . . . . +300°C (wave soldering, 3s) U . . . . . . . . . . . . . . +260°C Output Short-Circuit Duration . . . . . . . Continuous +VCC to IOUT Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +165°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT PACKAGELEAD Ceramic DIP-14 XTR101 Plastic DIP-14 SO-16
(1)
PACKAGE DESIGNATOR(1)
SPECIFIED TEMPERATURE RANGE
PACKAGE MARKING XTR101AG
JD -40°C to +85°C
XTR101BG XTR101AP XTR101AU
N DW
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
PIN CONFIGURATION
Top View DIP Top View SO
Zero Adjust Zero Adjust Zero Adjust -In +In Span Span Out 1 2 3 4 5 6 7 DIP 14 13 12 11 10 9 8 Zero Adjust Zero Adjust Bandwidth B Control +In IREF2 IREF1 E Out +VCC NC Span Span -In
1 2 3 4 5 6 7 8 SOL-16 Surface-Mount
16 15 14 13 12 11 10 9
Zero Adjust Bandwidth B Control IREF2 IREF1 E +VCC NC
NC = No Connection
2
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
At TA = +25°C, +VCC = 24VDC, and RL = 100 with external transistor connected, unless otherwise noted.
XTR101AG PARAMETER CONDITIONS MIN 4 3.8 28 ±3.9 ±10.5 ±20 +11.6 TYP MAX 20 22 38 ±10 ±20 ±40 ±40 600 1400 MIN XTR101BG TYP MAX MIN XTR101AP TYP MAX MIN XTR101AU TYP MAX UNIT mA mA mA µA
ppm, FS/°C
OUTPUT AND LOAD CHARACTERISTICS Current Linear Operating Region Derated Performance Current Limit Offset Current Error IOS, IO = 4mA vs Temperature IOS/T Full-Scale Output Current Full-Scale = 20mA Error Power-Supply Voltage VCC, Pins 7 and 8, Compliance (1) At VCC = +24V, IO = 20mA At VCC = +40V, IO = 20mA SPAN Output Current Equation Span Equation vs Temperature Untrimmed Error(2) Nonlinearity Hysteresis Dead Band INPUT CHARACTERISTICS Impedance: Differential Common-Mode Voltage Range, Full-Scale Offset Voltage vs Temperature Power-Supply Rejection Bias Current vs Temperature Offset Current vs Temperature Common-Mode Rejection (4) Common-Mode Range CURRENT SOURCES Magnitude Accuracy RS in , e1 and e2 in V RS in Excluding TCR of RS SPAN NONLINEARITY
±2.5 ±8 ±15
±6 ±15 ±30
31 ±8.5 ±10.5 ±30
±19 ±20 ±60
31 ±8.5
±19 ±60
±30
µA VDC
Load Resistance
S S e2 * e1
I
O
+ 4mA ) 0.016amps volt ) 40 R
S + 0.016amps volt ) 40 R -5 ±30 -2.5 0 0 0.4 3 10 3 ±100 0 0.01
122
A/V ppm/°C % % % % G pF G pF V µV µV/°C dB nA nA/°C nA nA/°C dB
e = (e2 - e1)(3) VOS VOS/T VCC/PSRR = VOS Error IB IB/T IOSI IOSI/T DC
e1 and e2 with Respect to Pin 7
0 ±30 ±0.75 125 60 0.30 10 0.1 100
1 ±60 ±1.5 150 1 ±30 0.3
±20 ±0.35
110
90 4
6 1
±30 ±0.75
±20
±0.075 ±50
122
±0.2
±100
±100
V mA
VCC = 24V, VPIN 8 - VPIN 10, 11 = 19V, R2 = 5k, see Figure 5
±0.06 ±50 ±3 ±8
±0.1 7 ±80
±0.02 5 ±30
±0.37
±0.2
±0.37
% ppm/°C ppm/V
ppm/month
vs Temperature vs VCC vs Time Compliance Voltage Ratio Match Accuracy vs Temperature vs VCC vs Time Output Impedance TEMPERATURE RANGE Specification Operating Storage
With Respect to Pin 7 Tracking (1 - IREF1/IREF2) × 100%
0
VCC - 3.5 ±0.01 4 ±10 ±1 20 +85 +125 +165 ±0.0 6 ±15
±0.04 10
±0.031
±0.088
±0.031
±0.088
V % ppm/°C ppm/V
ppm/month
±0.00 9
10 -40 -55 -55
-40 -55
15
-40 -55 +85 +125
15
M °C °C °C
+85 +125
(1) See the Typical Characteristics. (2) Span error shown is untrimmed and may be adjusted to zero. (3) e1 and e2 are signals on the -In and +In terminals with respect to the output, pin 7. While the maximum permissible e is 1V, it is primarily intended for much lower signal levels, for instance, 10mV or 50mV full-scale for the XTR101A and XTR101B grades, respectively. 2mV FS is also possible with the B grade, but accuracy will degrade due to possible errors in the low value span resistance and very high amplification of offset, drift, and noise. (4) Offset voltage is trimmed with the application of a 5V common-mode voltage. Thus, the associated common-mode error is removed. See the Application Information section.
Same as XTR101AG.
3
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 24VDC, unless otherwise noted.
SPAN vs FREQUENCY 80 RS = 25 60 RS = 100 RS = 400 40 RS = 2k 20 RS = ) CC = 0 20 Output Current (mA) Transconductance (20 Log m 0 100 1k 10k Frequency (Hz) FULL-SCALE INPUT VOLTAGE vs RS RS (k ) 0 0.08 2 4 6 8 0.8 120 100 eIN Full-Scale (V) eIN Full-Scale (V) 0.06 0 to 800mV and 0 to 8kscale 0.04 0.4 0.6 80 CMR (dB) 60 40 20 0 0 100 200 RS () POWER-SUPPLY REJECTION vs FREQUENCY 140 Power-Supply Rejection (dB) 120 Bandwidth (Hz) 100 80 60 40 20 0 0.1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 1 0.1 1 10 100k 10k 1k 300 400 0 0.1 1 100k 1M 0.02 0 to 80mV (low-level signals) and 0 to 400scale 0 25
STEP RESPONSE
RS = RS = 25
15
10
5
0 0 200 400 600 800 1000 Time (µs)
COMMON-MODE REJECTION vs FREQUENCY
0.2
10
100 Frequency (Hz)
1k
10k
100k
BANDWIDTH vs PHASE COMPENSATION
RS = RS = 400
RS = 100 100 RS = 25 10
100
1k
10k
100k
1M
Bandwidth Control, CC (pF)
4
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 60 Input Noise Voltage (nV/ Hz) Input Noise Current (pA/ Hz) 50 40 30 20 10 0 1 10 100 1k 10k 100k Frequency (Hz) 6 5 4 3 2 1 0 1
INPUT CURRENT NOISE DENSITY vs FREQUENCY
10
100
1k
10k
100k
Frequency (Hz) OUTPUT CURRENT NOISE DENSITY vs FREQUENCY 6
Output Noise Current (nA/ Hz)
5 4 3 2 1 0 1 10 100 1k 10k 100k Frequency (Hz)
5
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
THEORY OF OPERATION
A simplified schematic of the XTR101 is shown in Figure 1. Basically, the amplifiers A1 and A2 act as a single power-supply instrumentation amplifier controlling a current source, A3 and Q1. Operation is determined by an internal feedback loop. e1 applied to pin 3 will also appear at pin 5, and similarly, e2 will appear at pin 6. Therefore, the current in RS (the span setting resistor) will be IS = (e2 - e1)/RS = eIN/RS. This current combines with the current I3 to form I1. The circuit is configured such that I2 is 19 times I1. From this point, the derivation of the transfer function is straightforward but lengthy. The result is shown in Figure 1.
Examination of the transfer function shows that IO has a lower range-limit of 4mA when eIN = e2 - e1 = 0V. This 4mA is composed of 2mA quiescent current exiting pin 7 plus 2mA from the current sources. The upper range limit of IO is set to 20mA by the proper selection of RS based on the upper range limit of eIN. Specifically, RS is chosen for a 16mA output current span for the given full-scale input voltage span.
For example, 0.016 amps 40 ) e IN full-scale + 16mA. volt RS
Note that since IO is unipolar, e2 must be kept larger than e1 (that is, e2 e1 or eIN 0). Also note that in order not to exceed the output upper range limit of 20mA, eIN must be kept less than 1V when RS = and proportionately less as RS is reduced.
-
eIN RS
+
(e1) 5 I3
IS I4
(e2) 6
R3 1.25k +VCC IB1
R4 1.25k +VCC +VCC 8 D1
(e1) -In3 eIN
A1
A2
IB2 +In4 (e2) VPS 100µA
7 Q1 +VCC +VCC I1 R1 1k R2 52.6 I2 IO Voltage-Controlled Current Source 10 IREF1 11 IREF2 2.5k A3
IO + eL 2mA - RL
I O + 4mA )
0.016
amps 40 ) e e + e2 * e1 volt RS IN, IN
Figure 1. Simplified Schematic of the XTR101
6
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
INSTALLATION AND OPERATING INSTRUCTIONS
BASIC CONNECTION
See Figure 1 for the basic connection of the XTR101. A difference voltage applied between input pins 3 and 4 will cause a current of 4-20mA to circulate in the two-wire output loop (through RL, VPS, and D1). For applications requiring moderate accuracy, the XTR101 operates very cost-effectively with just its internal drive transistor. For more demanding applications (high accuracy in high gain), an external NPN transistor can be added in parallel with the internal one. This keeps the heat out of the XTR101 package and minimizes thermal feedback to the input stage. Also, in such applications where the eIN full-scale is small (< 50mV) and RSPAN is small (< 150), caution should be taken to consider errors from the external span circuit plus high amplification of offset drift and noise.
OPTIONAL EXTERNAL TRANSISTOR
The optional external transistor, when used, is connected in parallel with the XTR101 internal transistor. The purpose is to increase accuracy by reducing heat change inside the XTR101 package as the output current spans from 4-20mA. Under normal operating conditions, the internal transistor is never completely turned off, as shown in Figure 2. This maintains frequency stability with varying external transistor characteristics and wiring capacitance. The actual current sharing between internal and external transistors is dependent on two factors: 1. 2. relative geometry of emitter areas, and relative package dissipation (case size and thermal conductivity).
For best results, the external device should have a larger base-emitter area and smaller package. It will, upon turn-on, take about [0.95(IO - 3.3mA)]mA. However, it will heat faster and take a greater share after a few seconds.
4mA 16mA +VCC 8 750 3.5mA 0.5mA XTR101 B 12
(2)
20mA
12V, 200mW
QEXT 23.6V, 377mW 2N2222
(1)
QINT 18mW
Other Suitable Types Package Type 210 1.5mA Quiescent 52.6 0.95V, 17mW 3.47V, 60mW 9 E 2N4922 TIP29B TIP31B TO-225 TO-220 TO-220
VPS 40V
7 11 10
I OUT Short-Circuit Worst-Case RL 250
1mA
1mA 2mA
18mA 20mA
NOTES: (1) An external transistor is used in the manufacturing test circuit for testing electrical specifications. (2) This resistor is required for the 2N2222 with VPS > 24V to limit power dissipation.
Figure 2. Power Calculation of the XTR101 with an External Transistor
7
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
Although any NPN of suitable power rating will operate with the XTR101, two readily available transistors are recommended: 1. 2N2222 in the TO-18 package. For power-supply voltages above 24V, a 750, 1/2W resistor should be connected in series with the collector. This will limit the power dissipation to 377mW under the worst-case conditions; see Figure 2. Thus, the 2N2222 will safely operate below its 400mW rating at the upper temperature of +85°C. Heat sinking the 2N2222 will result in greatly reduced accuracy improvement and is not recommended. TIP29B in the TO-220 package. This transistor will operate over the specified temperature and output voltage range without a series collector resistor. Heat sinking the TIP29B will result in slightly less accuracy improvement. It can be done, however, when mechanical constraints require it.
MAJOR POINTS TO CONSIDER WHEN USING THE XTR101
1. 2. 3. The leads to RS should be kept as short as possible to reduce noise pick-up and parasitic resistance. +VCC should be bypassed with a 0.01µF capacitor as close to the unit as possible (pin 8 to pin 7). Always keep the input voltages within their range of linear operation, +4V to +6V (e1 and e2 measured with respect to pin 7). The maximum input signal level (eINFS) is 1V with RS = and proportionally less as RS decreases. Always return the current references (pins 10 and 11) to the output (pin 7) through an appropriate resistor. If the references are not used for biasing or excitation, connect them together to pin 7. Each reference must have between 0V and +(VCC - 4V) with respect to pin 7. Always choose RL (including line resistance) so that the voltage between pins 7 and 8 (+VCC) remains within the 11.6V to 40V range as the output changes between the 4-20mA range (as shown in Figure 4). It is recommended that a reverse polarity protection diode (D1 in Figure 1) be used. This will prevent damage to the XTR101 caused by a momentary (such as a transient) or long-term application of the wrong polarity of voltage between pins 7 and 8. Consider PC board layout which minimizes parasitic capacitance, especially in high gain.
4. 5.
2.
6.
ACCURACY WITH AND WITHOUT AN EXTERNAL TRANSISTOR
The XTR101 has been tested in a circuit using an external transistor. The relative difference in accuracy with and without an external transistor is shown in Figure 3. Notice that a dramatic improvement in offset voltage change with supply voltage is evident for any value of load resistor. 7.
8.
30 25
Self-Heating Temperature (_C)
Span = IO = 16mA Without External Transistor
60 1500 1250 RL max = 1000 750 500 250 0 0 10 20 30 40 50 60 Power-Supply Voltage, VPS (V) Operating Region 50 40
VOS (µV)
20 15 10 5 0 10 With External Transistor RL = 100 20 VCC (V) RL = 600 30 RL = 1k RL = 100 RL = 600 R L = 1k
30 20 10 0 40
Figure 3. Thermal Feedback Due to Change in Output Current
Load Resistance, RL ()
VPS - 11.6V 20mA
Figure 4. Power-Supply Operating Range
8
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
SELECTING THE RS
RSPAN is chosen so that a given full-scale input span (eINFS) will result in the desired full-scale output span of IOFS: amps 0.016 ) 40 volt RS Solving for RS:
- 11 10 e1 3 - 5 2mA eIN + e2 4 RS Adj. 6 7 IO Offset Adjust
I + 4mA ) 0.016 amps 40 ) e IN volt R S
D1 8 4-20mA
DeIN + DI O + 16mA.
XTR101
0.01µF + 24V + eL - RL -
+ 1 1M
2
14
RS +
40 amps DI O De IN * 0.016 volt
+ e'2
(1)
0.01µF R2 2.5k 2mA +5V
For example, if eINFS = 100mV for IOFS = 16mA,
O
RS +
40 40 + 0.16 * 0.016 16mA 100mV * 0.016 + 40 + 278W 0.144
e IN + e 2
Figure 5. Basic Connection for Floating Voltage Source
See the Typical Characteristics for a plot of RS vs eINFS. Note that in order not to exceed the 20mA upper range limit, eIN must be less than 1V when RS = and proportionately smaller as RS decreases.
e1 3 1mA 1mA 5 + eIN - RS 6
11 - 10 8
D1
BIASING THE INPUTS
Because the XTR operates from a single supply, both e1 and e2 must be biased approximately 5V above the voltage at pin 7 to assure linear response. This is easily done by using one or both current sources and an external resistor, R2. Figure 5 shows the simplest case--a floating voltage source e 2. The 2mA from the current sources flows through the 2.5k value of R2 and both e1 and e2 are raised by the required 5V with respect to pin 7. For linear operation the constraint is: +4V e1 +6V +4V e2 +6V The offset adjustment is used to remove the offset voltage of the input amplifier. When the input differential voltage (eIN) equals zero, adjust for 4mA output. Figure 6 shows a similar connection for a resistive transducer. The transducer could be excited either by one (as shown) or both current sources. Also, the offset adjustment has higher resolution compared to Figure 5.
XTR101
0.01µF + 24V + eL - RL -
4 e2 + e2 - RT
2 14 1 100k 1M R2 2.5k 2mA +5V 0.01µF
+
7 Offset Adjust
Alternate circuitry shown in Figure 8.
I
O
+ 4mA )
0.016
e IN + e 2 + 1mA
amps 40 ) e IN volt R S RT
Figure 6. Basic Connection for Resistive Source
CMV AND CMR
The XTR101 is designed to operate with a nominal 5V common-mode voltage at the input and will function properly with either input operating over the range of 4V to 6V with respect to pin 7. The error caused by the 5V CMV is already included in the accuracy specifications. If the inputs are biased at some other CMV, then an input offset error term is (CMV - 5)/CMRR, where CMR is in dB, and CMRR is in V/V.
9
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
SIGNAL SUPPRESSION AND ELEVATION
In some applications, it is desired to have suppressed zero range (input signal elevation) or elevated zero range (input signal suppression). This is easily accomplished with the XTR101 by using the current sources to create the suppression/elevation voltage. The basic concept is shown in Figure 7 and Figure 8(a). In this example, the sensor voltage is derived from RT (a thermistor, RTD, or other variable resistance element) and excited by one of the 1mA current sources. The other current source is used to create the elevated zero range voltage. Figure 8(b), (c), and (d) show some of the possible circuit variations. These circuits have the desirable feature of noninteractive span and suppression/elevation adjustments. Note: It is not recommended to use the optional offset voltage null (pins 1, 2, and 14) for elevation/suppression. This trim capability is used only to null the amplifier's input offset voltage. In many applications the already low offset voltage (typically 20µV) will not need to be nulled at all. Adjusting the offset voltage to non-zero values will disturb the voltage drift by ±0.3µV/°C per 100µV or induced offset.
1mA 1mA eIN - + + R4 e'2 - 2mA eIN = (e'2 - V4) V4 = 1mA × R4 e'2 = 1mA × RT (a) Elevated Zero Range eIN = (e'2 + V4) V4 = 1mA × R4 e'2 = 1mA × RT (b) Suppressed Zero Range + RT e'2 - + R4 2mA - RT 1mA 1mA - eIN +
+ V4 -
V4
2mA
- eIN +
2mA - e'2 +
- eIN +
+ V4 - R4 + e'2 - 2mA eIN = (e'2 - V4) V4 = 2mA × R4 (c) Elevated Zero Range eIN = (e'2 + V4) V4 = 2mA × R4 (d) Suppressed Zero Range + V4 - 2mA R4
20
Span Adjust
15 IO (mA)
10 Elevated Zero Range Suppressed Zero Range
Figure 8. Elevation and Suppression Circuits
5
APPLICATION INFORMATION
The small size, low offset voltage and drift, excellent linearity, and internal precision current sources make the XTR101 ideal for a variety of two-wire transmitter applications. It can be used by OEMs producing different types of transducer transmitter modules and by data acquisition systems manufacturers who gather transducer data. Current-mode transmission greatly reduces noise interference. The two-wire nature of the device allows economical signal conditioning at the transducer. Thus the XTR101 is, in general, very suitable for individualized and special-purpose applications.
0 -0+ eIN (V)
Figure 7. Elevation and Suppression Graph
10
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
EXAMPLE 1
An RTD transducer is shown in Figure 9. Given a process with temperature limits of +25°C and +150°C, configure the XTR101 to measure the temperature with a platinum RTD which produces 100 at 0°C and 200 at +266°C (obtained from standard RTD tables). Transmit 4mA for +25°C and 20mA for +150°C. COMPUTING RS: The sensitivity of the RTD is R/T = 100/266°C. When excited with a 1mA current source for a 25°C to 150°C range (a 125°C span), the span of eIN is 1mA × (100/266°C) × 125°C = 47mV = eIN.
+ V4 - R4 + e'2 - e2 RT R2 e1 3 - 11 10 8 D1
5 - eIN + RS 6 7 XTR101
0.01µF + 24V + eL - RL -
4
+
40 From Equation 1, R S + amps DI O De IN * 0.016 volt 40 RS + + 40 + 123.3W 0.3244 16mA 47mV * 0.016A V
Span adjustment (calibration) is accomplished by trimming RS. COMPUTING R4:
0.01µF
Figure 9. Circuit for Example 1
EXAMPLE 2
A thermocouple transducer is shown in Figure 10. Given a process with temperature (T1) limits of 0°C and +1000°C, configure the XTR101 to measure the temperature with a type J thermocouple that produces a 58mV change for 1000°C change. Use a semiconductor diode for cold junction compensation to make the measurement relative to 0°C. This is accomplished by supplying a compensating voltage (VR6) equal to that normally produced by the thermocouple with its cold junction (T2) at ambient. At a typical ambient of +25°C, this is 1.28mV (obtained from standard thermocouple tables with reference junction of 0°C). Transmit 4mA for T1 = 0°C and 20mA for T1 = +1000°C. Note: eIN = e2 - e1 indicates that T1 is relative to T2.
At ) 25 oC, e 2 + 1mA(RT ) DRT) + 1mA 100W ) 100W 25 oC 266 oC + 1mA(109.4W) + 109.4mV
In order to make the lower range limit of 25°C correspond to the output lower range limit of 4mA, the input circuitry shown in Figure 9 is used. eIN, the XTR101 differential input, is made 0 at 25°C or:
e
2 25 oC
* V4
2 25 oC
thus, V 4 + e R4 +
+ 109.4mV
V4 + 109.4mV + 109.4W 1mA 1mA
1mA 1mA R5 2k D R6 51 eIN XTR101 3 11 - 10 8
COMPUTING R2 AND CHECKING CMV:
At ) 25 C, e 2 + 109.4mV At ) 150 oC, e 2 + 1mA(RT ) DRT)
o
+ 1mA 100W ) 100W 266 oC + 156.4mV
150 oC
Thermocouple TTC
+ e1 -
Since both e 2 and V4 are small relative to the desired 5V common-mode voltage, they may be ignored in computing R2 as long as the CMV is met.
4 VTC Temperature T1 + V4 - R4 + e2 -
+ 0.01µF
7
R 2 + 5V + 2.5kW 2mA e 2 min + 5V ) 0.1094V e 2 max + 5V ) 0.1564V e 1 + 5V ) 0.1094V
2.5k Temperature T2 = TD
The 4V to 6V CMV requirement is met.
Figure 10. Thermocouple Input Circuit with Two Temperature Regions and Diode (D) Cold Junction Compensation
11
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
ESTABLISHING RS: The input full-scale span is 58mV (eINFS = 58mV). RS is found from Equation 1.
R5 is chosen as 2k to be much larger than the resistance of the diode. Solving for R6 yields 51.
RS +
40 amps DI O De IN * 0.016 volt 40 + + 40 + 153.9W 0.2599 16mA 58mV * 0.016A V
+ VD - D
1mA
R5
SELECTING R4: R4 is chosen to make the output 4mA at TTC = 0°C (VTC = -1.28mV) and TD = +25°C (VD = 0.6V); see Figure 10. VTC will be -1.28mV when TTC = 0°C and the reference junction is at +25°C. e1 must be computed for the condition of TD = +25°C to make eIN = 0V.
+ V5 - + V6 -
R6
V D 25oC + 600mV e 1 25oC + 600mV 51 + 14.9mV 2051 e IN + e2 * e1 + V TC ) V4 * e1
With eIN = 0 and VTC = -1.28mV,
Figure 11. Cold Junction Compensation Circuit
THERMOCOUPLE BURN-OUT INDICATION
In process control applications it is desirable to detect when a thermocouple has burned out. This is typically done by forcing the two-wire transmitter current to either limit when the thermocouple impedance goes very high. The circuits of Figure 16 and Figure 17 inherently have downscale indication. When the impedance of the thermocouple gets very large (open) the bias current flowing into the + input (large impedance) will cause IO to go to its lower range limit value (about 3.8mA). If upscale indication is desired, the circuit of Figure 18 should be used. When TC opens, the output will go to its upper range limit value (about 25mA or higher).
V 4 + e1 ) eIN * VTC + 14.9mV ) 0V * (* 1.28mV) 1mA(R 4) + 16.18mV R 4 + 16.18W
COLD JUNCTION COMPENSATION: A temperature reference circuit is shown in Figure 11. The diode voltage has the form:
V D + KT ln q
I DIODE I SAT
OPTIONAL INPUT OFFSET VOLTAGE TRIM
The XTR101 has provisions for nulling the input offset voltage associated with the input amplifiers. In many applications the already low offset voltages (30µV max for the B grade and 60µV max for the A grade) will not need to be nulled at all. The null adjustment can be done with a potentiometer at pins 1, 2, and 14; see Figure 5 and Figure 6. Either of these two circuits may be used. NOTE: It is not recommended to use this input offset voltage nulling capability for elevation or suppression. See the Signal Suppression and Elevation section for the proper techniques.
Typically at T2 = +25°C, VD = 0.6V and VD/T = -2mV/°C. R5 and R6 form a voltage divider for the diode voltage VD. The divider values are selected so that the gradient VD/T equals the gradient of the thermocouple at the reference temperature. At +25°C this is approximately 52µV/°C (obtained from a standard thermocouple table); therefore,
DT C DVD R6 + DT DT R 5 ) R 6 52mV 2000mV R6 + °C °C R5 ) R6
(2)
12
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
OPTIONAL BANDWIDTH CONTROL
Low-pass filtering is recommended where possible and can be done by either one of two techniques; see Figure 12. C2 connected to pins 3 and 4 will reduce the bandwidth with a cutoff frequency given by:
1mA R3(1) 1mA C2 R1 3 - 11
0.0047µF
f CO +
15.9 (R1 ) R2 ) R3 ) R 4)(C2 ) 3pF)
XTR101
This method has the disadvantage of having fCO vary with R1, R2, R3, R4, and it may require large values of R3 and R4. The other method, using C1, will use smaller values of capacitance and is not a function of the input resistors. It is, however, more subject to nonlinear distortion caused by slew rate limiting. This is normally not a problem with the slow signals associated with most process control transducers. The relationship between C1 and fCO is shown in the Typical Characteristics.
R4(1) R2
4
+ 12 C1
13
NOTE: (1) R3 and R 4 should be equal if used. Internally eNOISE RTI = e2INPUT STAGE + e2OUTPUT STAGE Gain
2
Figure 12. Optional Filtering
APPLICATION CIRCUITS
Voltage Reference + VR = 2.5V - 100pF V+ IO (4-20 mA) R1 125 OPA27 V- R2 500 IO (0-20mA) MC1403A
XTR101
R1 NOTE: I O + 1 ) R
2
V I O * R + 1.25 I O * 5mA R2
Other conversions are readily achievable by changing the reference and ratio of R1 to R2.
Figure 13. 0-20mA Output Converter
13
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
0.9852mA
2mA 1.0147mA 1.8k -
LM129 6.9V Voltage Ref
R 300
R RS R +
XTR101
R
0.01µF
4.7k
Figure 14. Bridge Input, Voltage Excitation
R 300 R
R
2mA -
1mA
1mA 2k -
This circuit has downscale burn-out indication.
Type J - + 51 RS
R RS J + 2.2k Zero Adjust XTR101 20
XTR101
+
2.5k
Figure 15. Bridge Input, Current Excitiation
Figure 17. Thermocouple Input with Diode Cold Junction Compensation
1mA Type J - RTD 100 +
1mA -
This circuit has downscale burn-out indication.
1mA 1mA + - -
This circuit has upscale burn-out indication.
20 Zero Adjust
RS XTR101 15 RTD 100
20 Zero Adjust
RS
XTR101
15
+ 2.5k
+ 2.5k
Figure 16. Thermocouple Input with RTD Cold Junction Compensation
Figure 18. Thermocouple Input with RTD Cold Junction Compensation
14
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
11 +VCC 10 8 - 3
I1
I2 +VCC OPA21
VREF Out
15V
0.01µF
XTR101
R1
R2
7
+
4 2.5k VREF = ImA R2
Figure 19. Dual Precision Current Sources Operated from One Supply
Isolation Barrier - 8 +V2 C2 -V2 4-20 mA eIN XTR101 + 30V - 722 P+ 1k V+ E V- +15V 1µF 1µF +15V
C1 +V1 -V1
7 +
1M + 15
10 12 1M -15V
7 250 ISO100 9 8
2 4 3 VOUT(1) +1V to +5V IREF2
17
- 18
16 IREF1 NOTE: (1) Can be shifted and amplified using ISO100 current sources.
Figure 20. Isolated Two-Wire Current Loop
15
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
DETAILED ERROR ANALYSIS
The ideal output current is:
EXAMPLE 3
See the circuit in Figure 9 with the XTR101BG specifications and the following conditions: RT = 109.4 at 25°C, RT = 156.4 at 150°C, IO = 4mA at 25°C, IO = 20mA at 150°C, RS = 123.3, R4 = 109, RL = 250, RLINE = 100, VDI = 0.6V, and VPS = 24V ± 0.5%. Determine the % error at the upper and lower range values.
I O IDEAL + 4mA ) K e IN
where K is the span (gain) term, 0.016 amps ) 40 volt RS
(3)
In the XTR101 there are three major components of error: 1. 2. 3. O = errors associated with the output stage. S = errors associated with span adjustment. I = errors associated with the input stage.
A. AT THE LOWER RANGE VALUE (T = +255C)
s O + I OS RTO +" 6mA DVCC s I + V OSI ) I BI DR ) I OSI R4 ) ) PSRR
e )e 1 2 2
* 5V CMRR
The transfer function including these errors is:
I O ACTUAL + 4mA ) s O ) K 1 ) sS (e IN ) s I)
(4)
When this expression is expanded, second-order terms (S, I) dropped, and terms collected, the result is:
IO ACTUAL + 4mA ) s O ) K e IN ) Ks I ) Ks S e IN
DR + RT 25oC * R4 + 109.4 * 109 [ 0 DVCC + (24 0.005) ) 4mA(250W ) 100W) ) 0.6V + 120mV ) 1400mV ) 600mV + 2120mV
(5)
The error in the output current is IO ACTUAL - IO IDEAL and can be found by subtracting Equation 3 from Equation 5.
e 1 + 2mA 2.5kW ) 1mA + 5.109V e 2 + 2mA 2.5kW ) 1mA + 5.1094V e1 ) e2 * 5V + 0.1092V 2 PSRR + 3.16 CMRR + 31.6 105 for 110dB 10 3 for 90dB
109W 109.4W
I O ERROR + sO ) KsI ) KsS e IN
(6)
This is a general error expression. The composition of each component of error depends on the circuitry inside the XTR101 and the particular circuit in which it is applied. The circuit of Figure 9 will be used to illustrate the principles.
s O + I OS RTO s S + eNONLINEARITY ) eSPAN
sI + VOSI ) IB1 ) R4 * IB2 R T ) DVCC ) PSRR
e 1)e 2 2
(7) (8)
* 5V
CMRR
(9)
The term in parentheses may be written in terms of offset current and resistor mismatches as IB1 R + IOS R4. VOSI(1) = input offset voltage. IB1(1), IB2(1) = input bias current. IOSI(1) = input offset current. IOS RTO
(1)
s 1 + 30mV ) (150nA 0 ) 20nA 109W) ) 2120mV ) 0.1092V (10) 3.16 10 5 3.16 10 3 + 30mV ) 2.18mV ) 6.7mV ) 3.46mV + 42.34mV s S + eNONLIN ) eSPAN + 0.0001 ) 0 assumes trim of R S I O ERROR + sO ) K sI ) K sS e IN K + 0.016 ) 40 + 0.016 ) 40 123.3W RS amps + 0.340 volts e IN + e2 * V4 + I REF1 R T 25oC * I REF2 R4
Since RT 25°C = R4: e IN + I REF1 * IREF2 R 4 + 0.4mA + 43.6mV 109W
= output offset current error.
R = RT - R4 = mismatch in resistor. VCC = change supply voltage between pins 7 and 8 away from 24V nominal. PSRR (1) = power-supply rejection ratio. CMRR (1) = common-mode rejection ratio. NONLIN
(1)
Since the maximum mismatch of the current references is 0.04% of 1mA = 0.4µA: I O error + 6mA ) 0.34A V 42.34mV ) 0.34A V 0.0001 43.6mV + 6mA ) 14.40mA ) 0.0015mA + 20.40mA 20.40mA 100% % error + 16mA 0.13% of span at lower range value.
= span nonlinearity.
SPAN(1) = span equation error. Untrimmed error = 5% max. May be trimmed to zero.
(1) 16 These items can be found in the Electrical Characteristics.
XTR101
www.ti.com SBOS146A - OCTOBER 1986 - REVISED AUGUST 2004
B. AT THE UPPER RANGE VALUE (T = +150°C)
DR + R T 150oC * R 4 + 156.4 * 109.4 + 47W DV CC + 24 0.005 ) 20mA 250W ) 100W ) 0.6V + 7720mV e 1 + 5.109V e 2 + 2mA 2.5kW ) 1mA + 5.156V e1 * e2 * 5V + 0.1325V 2 s O + 6mA s 1 + 30mV ) 150nA 47W ) 20nA 190W ) 7720mV ) 0.1325V 3.16 105 3.16 10 3 + 30mV ) 9.23mV ) 24mV ) 4.19mV + 67.42mV s S + 0.0001 e IN + e 2 * V 4 + IREF1 R T 150oC * IREF2 R 4 + 1mA + 47mV 156.4W * 1mA 109W
CONCLUSIONS
Lower Range: From Equation 10, it is observed that the predominant error term is the input offset voltage (30µV for the B grade). This is of little consequence in many applications. VOS RTI can, however, be nulled using the plots shown in Figure 5 and Figure 6. The result is an error of 0.06% of span instead of 0.13% of span. Upper Range: From Equation 11, the predominant errors are IOS RTO (6µA), VOS RTI (30µV), and IB (150nA), max, B grade. Both IOS and VOS can be trimmed to zero; however, the result is an error of 0.09% of span instead of 0.19% of span.
156.4W
RECOMMENDED HANDLING PROCEDURES FOR INTEGRATED CIRCUITS
All semiconductor devices are vulnerable, in varying degrees, to damage from the discharge of electrostatic energy. Such damage can cause performance degradation or failure, either immediate or latent. As a general practice, we recommend the following handling procedures to reduce the risk of electrostatic damage: 1. Remove the static-generating materials (such as untreated plastic) from all areas that handle microcircuits. Ground all operators, equipment, and work stations. Transport and ship microcircuits, or products incorporating microcircuits, in static-free, shielded containers. Connect together all leads of each device by means of a conductive material when the device is not connected into a circuit. Control relative humidity to as high a value as practical (50% recommended).
I O error + sO ) K s I ) K s S eIN + 6mA ) 0.34A V 67.42mV ) 0.34A V 0.0001 47000mV + 6mA ) 22.92mA ) 1.60mA + 30.52mA 30.52mA % error + 100% 16mA
0.19% of span at upper range value.
(11)
2. 3.
4.
5.
17
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device XTR101AG XTR101AP XTR101APG4 XTR101AU XTR101AU/1K XTR101AU/1KG4 XTR101AUG4 XTR101BG
(1)
Status (1) NRND ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE NRND
Package Type CDIP SB PDIP PDIP SOIC SOIC SOIC SOIC CDIP SB
Package Drawing JD N N DW DW DW DW JD
Pins Package Eco Plan (2) Qty 14 14 14 16 16 16 16 14 27 25 25 48 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI
MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR N / A for Pkg Type
1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 48 27 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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