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decoder with embedded m-Controller
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INTEGRATED CIRCUITS
DEVICE SPECIFICATION DATA SHEET
TDA935X/6X/8X PS/N2 series TV signal processor-Teletext decoder with embedded µ-Controller
Tentative Device Specification File under Integrated Circuits, Version: 2.85 2001 Apr 12 Previous date: 2000 Nov 29
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
GENERAL DESCRIPTION The various versions of theTDA935X/6X/8X PS/N2 series combine the functions of a TV signal processor together with a µ-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they are mounted in S-DIP envelope with 64 pins. The features are given in the following feature list. The differences between the various ICs are given in the table on page 4.
TDA935X/6X/8X PS/N2 series
FEATURES TV-signal processor · Multi-standard vision IF circuit with alignment-free PLL demodulator · Internal (switchable) time-constant for the IF-AGC circuit · A choice can be made between versions with mono intercarrier sound FM demodulator and versions with QSS IF amplifier. · The mono intercarrier sound versions have a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. · Source selection between `internal' CVBS and external CVBS or Y/C signals · Integrated chrominance trap circuit · Integrated luminance delay line with adjustable delay time · Picture improvement features with peaking (with variable centre frequency and positive/negative overshoot ratio) and black stretching · Integrated chroma band-pass filter with switchable centre frequency · Only one reference (12 MHz) crystal required for the µ-Controller, Teletext- and the colour decoder · PAL/NTSC or multi-standard colour decoder with automatic search system · Internal base-band delay line 2001 Apr 12 2
· RGB control circuit with `Continuous Cathode Calibration', white point and black level offset adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. · Linear RGB or YUV input with fast blanking for external RGB/YUV sources. The Text/OSD signals are internally supplied from the µ-Controller/Teletext decoder · Contrast reduction possibility during mixed-mode of OSD and Text signals · Horizontal synchronization with two control loops and alignment-free horizontal oscillator · Vertical count-down circuit · Vertical driver optimized for DC-coupled vertical output stages · Horizontal and vertical geometry processing · Horizontal and vertical zoom function for 16 : 9 applications · Horizontal parallelogram and bow correction for large screen picture tubes · Low-power start-up of the horizontal drive circuit
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
µ-Controller · 80C51 µ-controller core standard instruction set and timing · 1 µs machine cycle · 32 - 128Kx8-bit late programmed ROM · 3 - 12Kx8-bit Auxiliary RAM (shared with Display and Acquisition) · Interrupt controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · One 16 bit Timer with 8-bit Pre-scaler · WatchDog timer · Auxiliary RAM page pointer · 16-bit Data pointer · Stand-by, Idle and Power Down (PD) mode · 14 bits PWM for Voltage Synthesis Tuning · 8-bit A/D converter · 4 pins which can be programmed as general I/O pin, ADC input or PWM (6-bit) output Data Capture · Text memory for 0, 1 or 10 pages · In the 10 page versions inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) · Data Capture for US Closed Caption · Data Capture for 525/625 line WST, VPS (PDC system A) and Wide Screen Signalling (WSS) bit decoding · Automatic selection between 525 WST/625 WST · Automatic selection between 625 WST/VPS on line 16 of VBI · Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput · Automatic detection of FASTEXT transmission · Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters · Signal quality detector for video and WST/VPS data types · Comprehensive teletext language coverage · Full Field and Vertical Blanking Interval (VBI) data capture of WST data Display
TDA935X/6X/8X PS/N2 series
· Teletext and Enhanced OSD modes · Features of level 1.5 WST and US Close Caption · Serial and Parallel Display Attributes · Single/Double/Quadruple Width and Height for characters · Scrolling of display region · Variable flash rate controlled by software · Enhanced display features including overlining, underlining and italics · Soft colours using CLUT with 4096 colour palette · Globally selectable scan lines per row (9/10/13/16) and character matrix [12x10, 12x13, 12x16 (VxH)] · Fringing (Shadow) selectable from N-S-E-W direction · Fringe colour selectable · Meshing of defined area · Contrast reduction of defined area · Cursor · Special Graphics Characters with two planes, allowing four colours per character · 32 software redefinable On-Screen display characters · 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) · G1 Mosaic graphics, Limited G3 Line drawing characters · WST Character sets and Closed Caption Character set in single device
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3
FUNCTIONAL DIFFERENCE BETWEEN THE VARIOUS IC VERSIONS
2001 Apr 12 4
Philips Semiconductors
TV signal processor-Teletext decoder with embedded µ-Controller
IC VERSION (TDA) TV range Mono intercarrier multi-standard sound demodulator (4.5 - 6.5 MHz) with switchable centre frequency Audio switch Automatic Volume Levelling Automatic Volume Levelling or subcarrier output (for comb filter applications) QSS sound IF amplifier with separate input and AGC circuit AM sound demodulator without extra reference circuit PAL decoder SECAM decoder NTSC decoder Horizontal geometry (E-W) Horizontal and Vertical Zoom ROM size User RAM size Teletext Closed captioning
9350 9351 9352 9353 9360 9361 9362 9363 9364 9365 9366 9367 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 90° 90° 90° 110° 90° 90° 110° 110° 110° 110° 90° 90° 90° 90° 90° 110° 110° 110° 110° 90° 110° 110°
32- 32- 32- 32- 64- 64- 64- 64- 64- 64- 64- 64- 16- 16- 16- 16- 16- 16- 16- 16- 16- 1664 k 64 k 64 k 64 k 128k 128k 128k 128k 128k 128k 128k 128k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 1k 1k 1k 1k 2k 2k 2k 2k 2k 2k 2k 2k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1 1 1 1 10 10 10 10 10 10 10 10 page page page page page page page page page page page page
TDA935X/6X/8X PS/N2 series
Tentative Device Specification
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
QUICK REFERENCE DATA SYMBOL Supply VP IP Input voltages ViVIFrms) ViSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) ViYIN(p-p) ViUVIN(p-p) Vo(IFVO)(p-p) Vo(QSSO)(rms) video IF amplifier sensitivity (RMS value) QSS sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) external chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) luminance input signal (peak-to-peak value) U/V input signal (peak-to-peak value) supply voltages supply current PARAMETER
TDA935X/6X/8X PS/N2 series
MIN. - - - - - - - - - - - - - 0 - 10 1 1.2
TYP. - - - - - - - - -
MAX.
UNIT
8.0/3.3 135/60
V mA µV µV mV V V V V V
75 60 500 1.0 0.3 0.7 1.4
1.33/1.05 - 2.5 100 500 - 2.0 - - - - - - 5 - - - -
Output signals demodulated CVBS output (peak-to-peak value) sound IF intercarrier output in QSS versions (RMS value) V mV mV mA V mA mA mA
Vo(AMOUT)(rms) demodulated AM sound output in QSS versions (RMS value) Io(AGCOUT) VoRGB(p-p) IoHOUT IoVERT IoEWD tuner AGC output current range RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current
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5
SNDIF
RESET
VPE
LED OUT (2x) SCL SDA
VST OUT
AUDEXT
AUDOUT
Philips Semiconductors
TUNERAGC 10/11 (20) 29 28 (32) 35 1+62-64 DEEMPHASIS ENHANCED 1/10 PAGE MEMORY 80C51 CPU VST PWM-DAC I/O PORTS AUDIO SWITCH (AVL) VOLUME CONTROL I2C-BUS TRANSCEIVER 5-8 44 60 55 59 58 57 3 4 9 2 12 54 56 61
27
37
38
(32) 31
23
IFIN
24
VISION IF ALIGNMENT-FREE PLL DEMOD. AGC/AFC VIDEO AMP.
ADC IN (4x)
I/O PORTS (4x)
2001 Apr 12
+3.3 V H CVBS ROM/RAM ACQUISITION V TELETEXT TELETEXT/OSD DISPLAY AGC CIRCUIT NARROW BAND PLL DEMODULATOR SYNC BASE-BAND DELAY LINE COR R G B BL CONTR/BRIGHTN OSD/TEXT INSERT CCC WHITE-P. ADJ. R G B H-DRIVE V-DRIVE + V GEOMETRY (EW GEOMETRY) U V 34 16 33 25 26 22 21 36 (20) 46 47 48 45 2nd LOOP H-SHIFT RGB/YUV INSERT Y RGB/YUV MATRIX SATURATION YUV/RGB MATRIX 51 52 53 49 50 RO GO B0 BCLIN BLKIN
BLOCK DIAGRAM
SOUND TRAP
40
VIDEO SWITCH
CVBS/Y
42
VIDEO IDENT.
CHROMA 43
VIDEO FILTERS
REF LUMA DELAY PEAKING BLACK STRETCH
TV signal processor-Teletext decoder with embedded µ-Controller
6
HOUT V-DRIVE EHTO EWD
13
REF
PAL/SECAM/NTSC DECODER (32)
30
41
18
+8V
39
H/V SYNC SEP.
14
H-OSC. + PLL
19
H
15
17
R/V G/Y B/U BL
TDA935X/6X/8X PS/N2 series
Tentative Device Specification
Fig. 1 Block diagram TDA935X/6X8X PS/N2 with mono intercarrier sound demodulator
AUDEXT
SIFIN
RESET
VPE
LED OUT (2x) SCL SDA
VST OUT
QSSOUT/AMOUT
AMOUT
Philips Semiconductors
TUNERAGC (20) 10/11 (35) 44 (32) 31 60 55 59 1+62-64 58 57 3 4 9 ENHANCED 10 PAGE MEMORY 80C51 CPU VST PWM-DAC I/O PORTS I2C-BUS TRANSCEIVER 5-8 28 29 2 12 54 56 61
27 QSS SOUND IF AGC QSS MIXER AM DEMODULTOR
37
38
(35)
23
IFIN
24
VISION IF ALIGNMENT-FREE PLL DEMOD. AGC/AFC VIDEO AMP.
REF LUMA DELAY PEAKING ROM/RAM ACQUISITION V BLACK STRETCH SYNC BASE-BAND DELAY LINE CVBS TELETEXT H TELETEXT/OSD DISPLAY
40
VIDEO SWITCH
CVBS/Y
42
VIDEO IDENT.
CHROMA 43 COR
VIDEO FILTERS
ADC IN (4x)
I/O PORTS (4x)
2001 Apr 12
+3.3 V R G B BL CONTR/BRIGHTN OSD/TEXT INSERT CCC WHITE-P. ADJ. R G B H-DRIVE V-DRIVE + V GEOMETRY EW GEOMETRY U V 34 16 33 25 26 22 21 36 (20) 2nd LOOP H-SHIFT RGB/YUV INSERT Y RGB/YUV MATRIX SATURATION YUV/RGB MATRIX 46 47 48 45 51 52 53 49 50 RO GO BO BCLIN BLKIN
SOUND TRAP
TV signal processor-Teletext decoder with embedded µ-Controller
7
HOUT V-DRIVE EHTO EWD
13
REF
PAL/SECAM/NTSC DECODER (32)
30
41
18
+8V
39
H/V SYNC SEP.
14
H-OSC. + PLL
19
H
15
17
R/V G/Y B/U BL
TDA935X/6X/8X PS/N2 series
Tentative Device Specification
Fig. 2 Block diagram TDA 935X/6X/8X PS/N2 with QSS IF sound channel
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
PINNING SYMBOL P1.3/T1 P1.6/SCL P1.7/SDA P2.0/TPWM P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD (1) VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1(1) DECSDEM/SIFIN2(1) GND2 SNDPLL/SIFAGC(1) AVL/SNDIF/REF0/ AMOUT(1) HOUT FBISO AUDEXT/ QSSO/AMOUT(1) EHTO PLLIF IFVO/SVO VP1 CVBSINT GND1 CVBS/Y CHROMA AUDOUT /AMOUT(1) 2001 Apr 12 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
TDA935X/6X/8X PS/N2 series
DESCRIPTION port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line port 2.0 or Tuning PWM output port 3.0 or ADC0 input port 3.1 or ADC1 input port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 0.5 (8 mA current sinking capability for direct drive of LEDs) port 0.6 (8 mA current sinking capability for direct drive of LEDs) analog ground of Teletext decoder and digital ground of TV-processor SECAM PLL decoupling 2nd supply voltage TV-processor (+8V) decoupling digital supply of TV-processor phase-2 filter phase-1 filter ground 3 for TV-processor bandgap decoupling Automatic Volume Levelling /East-West drive output vertical drive B output vertical drive A output IF input 1 IF input 2 reference current input vertical sawtooth capacitor tuner AGC output audio deemphasis or SIF input 1 decoupling sound demodulator or SIF input 2 ground 2 for TV processor narrow band PLL filter /AGC sound IF Automatic Volume Levelling / sound IF input / subcarrier reference output /AM output (non controlled) horizontal output flyback input/sandcastle output external audio input /QSS intercarrier out /AM audio output (non controlled) EHT/overvoltage protection input IF-PLL loop filter IF video output / selected CVBS output main supply voltage TV-processor (+8 V) internal CVBS input ground 1 for TV-processor external CVBS/Y input chrominance input (SVHS) audio output /AM audio output (volume controlled) 8
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
SYMBOL INSSW2 R2/VIN G2/YIN B2/UIN BCLIN BLKIN RO GO BO VDDA VPE VDDC OSCGND XTALIN XTALOUT RESET VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 Note PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TDA935X/6X/8X PS/N2 series
DESCRIPTION
2nd RGB / YUV insertion input 2nd R input / V (R-Y) input 2nd G input / Y input 2nd B input / U (B-Y) input beam current limiter input / (V-guard input, note 2) black current input / (V-guard input, note 2) Red output Green output Blue output analog supply of Teletext decoder and digital supply of TV-processor (3.3 V) OTP Programming Voltage digital supply to core (3.3 V) oscillator ground supply crystal oscillator input crystal oscillator output reset digital supply to periphery (+3.3 V) port 1.0 or external interrupt 1 input port 1.1 or Counter/Timer 0 input port 1.2 or external interrupt 0 input
1. The function of pin 20, 28, 29, 31, 32, 35 and 44 is dependent on the IC version (mono intercarrier FM demodulator / QSS IF amplifier and East-West output or not) and on some software control bits. The valid combinations are given in table 1. 2. The vertical guard function can be controlled via pin 49 or pin 50. The selection is made by means of the IVG bit in subaddress 2BH. Table 1 Pin functions for various versions FM-PLL version QSS version
IC version
East-West Y/N N Y N Y CMB1/CMB0 bits 00 01/10/11 00 01/10/11 00 01/10/11 00 01/10/11 AM bit - - - - - 0 1 - 0 1 Pin 20 AVL EWD AVL EWD Pin 28 AUDEEM SIFIN1 Pin 29 DECSDEM SIFIN2 Pin 31 SNDPLL SIFAGC REFO(2) AMOUT REFO(2) Pin 32 SNDIF(1) REFO(2) AVL/SNDIF(1) REFO(2) AMOUT Pin 35 AUDEXT AUDEXT QSSO AMOUT AUDEXT QSSO AMOUT Pin 44 AUDOUT controlled AM or audio out Note 1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This function is selected by means of SIF bit in subaddress 28H. 2. The reference output signal is only available for the CMB1/CMB0 setting of 0/1. For the other settings this pin is a switch output (see also table 67).
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9
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA935X/6X/8X PS/N2 series
P1.3/T1
handbook, halfpage
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56
P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VPE VDDA BO GO RO BLKIN BCLIN B2/UIN G2/YIN R2/VIN INSSW2 AUDOUT/AMOUT CHROMA CVBS/Y GND1 CVBSINT VP1 IFVO/SVO PLLIF EHTO AUDEXT/QSSO/ AMOUT FBISO HOUT
P1.6/SCL P1.7/SDA P2.0/TPMW P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1 DECSDEM/SIFIN2 GND2 SNDPLL/SIFAGC AVL/SNDIF/ REFO/AMOUT
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA935X/6X/8X PS/N2
10
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MXXxxx
XXX
Fig. 3 Pin configuration (SDIP 64)
2001 Apr 12
10
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
FUNCTIONAL DESCRIPTION OF THE 80C51 The functionality of the micro-controller used on this device is described here with reference to the industry standard 80C51 micro-controller. A full description of its functionality can be found in the 80C51 based 8-bit micro-controllers - Philips Semiconductors (ref. IC20). Features of the 80c51 · 80C51 micro-controller core standard instruction set and timing. · 1µs machine cycle. · Maximum 128K x 8-bit Program ROM. · Maximum of 12K x 8-bit Auxiliary RAM. · 2K (OSD only version) Auxiliary RAM, maximum of 1.25K required for Display · 3K (1 page teletext version) Auxiliary RAM, maximum of 2K required for Display · 12K (10 page teletext version) Auxiliary RAM, maximum of 10K required for Display · 8-Level Interrupt Controller for individual enable/disable with two level priority. · Two 16-bit Timer/Counters. · Additional 16-bit Timer with 8-bit Pre-scaler. · WatchDog Timer. · Auxiliary RAM Page Pointer. · 16-bit Data pointer · Idle, Stand-by and Power-Down modes. · 13 General I/O. · Four 6-bit Pulse Width Modulator (PWM) outputs for control of TV analogue signals. · One 14-bit PWM for Voltage Synthesis tuner control. · 8-bit ADC with 4 multiplexed inputs. · 2 high current outputs for directly driving LED's etc. · I2C Byte Level bus interface. Memory Organisation The device has the capability of a maximum of 128K Bytes of PROGRAM ROM and 12K Bytes of DATA RAM. The OSD (& Closed Caption) only version has a 2K RAM and a maximum of 64K ROM, the 1 page teletext version has a 3K RAM and also a maximum of 64K ROM whilst the 10 page teletext version has a 12K RAM and a maximum of 128K ROM. ROM Organisation The 64K device has a continuous address space from 0 to 64K. The 128K is arranged in four banks of 32K. One of 2001 Apr 12 11
Lower 128 Upper 128
8000H
TDA935X/6X/8X PS/N2 series
the 32K banks is common and is always addressable. The other three banks (Bank0, Bank1, Bank2) can be accessed by selecting the right bank via the SFR ROMBK bits 1/0.
FFFFH Bank0 32K
FFFFH Bank1 32K
FFFFH Bank2 32K
8000H
8000H
7FFFH Common 32K
0000H
Fig.4 ROM Bank Switching memory map RAM Organisation The Internal Data RAM is organised into two areas, Data Memory and Special Function Registers (SFRs) as shown in Fig.5.
FFH Accessible by Indirect Addressing only 80H 7FH Accessible by Direct and Indirect Addressing 00H Data Memory Special Function Registers Accessible by Direct Addressing only
Fig.5 Internal Data Memory DATA MEMORY The Data memory is 256 x 8-bits and occupies the address range 00 to FF Hex when using Indirect addressing and 00 to 7F Hex when using direct addressing. The SFRs occupy the address range 80 Hex to FF Hex and are accessible using Direct addressing only. The lower 128 Bytes of Data memory are mapped as shown in Fig.6. The lowest 32
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA935X/6X/8X PS/N2 series
bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. The upper 128 bytes are not allocated for any special area or functions.
7FH
2FH Bank Select Bits in PSW 20H 1FH 11 = BANK3 18H 17H 10 = BANK2 10H 0FH 01 = BANK1 08H 07H 00 = BANK0 00H
Fig.6 Lower 128 Bytes of Internal RAM SFR MEMORY The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and display. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 2.
ADD 80H 81H 82H 83H 84H 85H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 91H
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Names P0 SP DPL DPH IEN1 IP1 PCON TCON TMOD TL0 TL1 TH0 TH1 P1 TP2L
BIT7 Reserved SP<7> DPL<7> DPH<7> 0 TF1 GATE TL0<7> TL1<7> TH0<7> TH1<7> P1<7> TP2L<7>
BIT6 P0<6> SP<6> DPL<6> DPH<6> ARD TR1 C/T TL0<6> TL1<6> TH0<6> TH1<6> P1<6> TP2L<6>
BIT5 P0<5> SP<5> DPL<5> DPH<5> RFI TF0 M1 TL0<5> TL1<5> TH0<5> TH1<5> Reserved TP2L<5>
BIT4 Reserved SP<4> DPL<4> DPH<4> WLE TR0 M0 TL0<4> TL1<4> TH0<4> TH1<4> Reserved TP2L<4>
4 Banks of 8 Registers R0 - R7
Bit Addressable Space (Bit Addresses 0-7F)
BIT3 Reserved SP<3> DPL<3> DPH<3> GF1 IE1 GATE TL0<3> TL1<3> TH0<3> TH1<3> P1<3> TP2L<3>
BIT2 Reserved SP<2> DPL<2> DPH<2> GF0 IT1 C/T TL0<2> TL1<2> TH0<2> TH1<2> P1<2> TP2L<2>
BIT1 Reserved SP<1> DPL<1> DPH<1> PD IE0 M1 TL0<1> TL1<1> TH0<1> TH1<1> P1<1> TP2L<1>
BIT0 Reserved SP<0> DPL<0> DPH<0> ET2 PT2 IDL IT0 M0 TL0<0> TL1<0> TH0<0> TH1<0> P1<0> TP2L<0>
Table 2
SFR Map
2001 Apr 12
12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
ADD 92H 93H 94H 96H 97H 98H 9CH 9DH 9EH 9FH A0H A6H A7H A8H B0H B2H B3H B4H R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Names TP2H TP2PR TP2CRL P0CFGA P0CFGB SADB TP2CL TP2CH P1CFGA P1CFGB P2 P2CFGA P2CFGB IE P3 TXT18 TXT19 TXT20 BIT7 TP2H<15> TP2PR<7> Reserved Reserved TP2CL<7> TP2CH<7>
P1CFGA<7>
TDA935X/6X/8X PS/N2 series
BIT6 TP2H<14> TP2PR<6> P0CFGA<6>
BIT5 TP2H<13> TP2PR<5> P0CFGA<5>
BIT4 TP2H<12> TP2PR<4> Reserved Reserved DC_COMP TP2CL<4> TP2CH<4> Reserved Reserved P2CFGA<4>
BIT3 TP2H<11> TP2PR<3> Reserved Reserved SAD<3> TP2CL<3> TP2CH<3>
P1CFGA<3>
BIT2 TP2H<10> TP2PR<2> Reserved Reserved SAD<2> TP2CL<2> TP2CH<2>
P1CFGA<2>
BIT1 TP2H<9> TP2PR<1> TP2CRL<1> Reserved Reserved SAD<1> TP2CL<1> TP2CH<1>
P1CFGA<1>
BIT0 TP2H<8> TP2PR<0> TP2CRL<0> Reserved Reserved SAD<0> TP2CL<0> TP2CH<0>
P1CFGA<0>
P0CFGB<6> TP2CL<6> TP2CH<6>
P1CFGA<6>
P0CFGB<5> TP2CL<5> TP2CH<5> Reserved Reserved P2CFGA<5>
P1CFGB<7> Reserved Reserved Reserved EA Reserved NOT<3> TEN DRCS ENABLE DISP LINE<1> GPF1<7> 0 0 0
P1CFGB<6> P2CFGA<6>
P1CFGB<3> P2CFGA<3>
P1CFGB<2> P2CFGA<2>
P1CFGB<1> P2CFGA<1>
P1CFGB<0> P2<0>
P2CFGA<0>
P2CFGB<6> EBUSY Reserved NOT<2> TC<2> OSD PLANES DISP LINES<0> GPF1<6> 0 PBUSY FORCE ACQ<1> 0
P2CFGB<5> ES2 Reserved NOT<1> TC<1> 0
P2CFGB<4> ECC Reserved NOT<0> TC<0> 0
P2CFGB<3> ET1 P3<3> 0 0 OSD LANG ENABLE Reserved
P2CFGB<2> EX1 P3<2> 0 0 OSD LAN<2> CC ON
P2CFGB<1> ET0 P3<1> BS<1> TS<1> OSD LAN<1> I2C PORT0
P2CFGB<0> EX0 P3<0> BS<0> TS<0> OSD LAN<0> CC/TXT
B5H
R/W
TXT21
CHAR SIZE<1> GPF1<5> 0 PES2 FORCE ACQ<0> 0
CHAR SIZE<0> GPF1<4> CS<4> PCC FORCE DISP<1> WSS<3:0> ERROR WSS<7:4> ERROR WSS<11>
B6H B7H B8H B9H
R R/W R/W R/W
TXT22 CCLIN IP TXT17
GPF1<3> CS<3> PT1 FORCE DISP<0> WSS<3>
GPF1<2> CS<2> PX1 SCREEN COL<2> WSS<2>
GPF1<1> CS<1> PT0 SCREEN COL<1> WSS<1>
GPF1<0> CS<0> PX0 SCREEN COL<0> WSS<0>
BAH
R
WSS1
0
BBH
R
WSS2
0
0
0
WSS<7>
WSS<6>
WSS<5>
WSS<4>
BCH
R
WSS3
WSS<13:11> ERROR
WSS<13>
WSS<12>
WSS<10:8> ERROR
P3CFGA<3>
WSS<10>
WSS<9>
WSS<8>
BEH BFH C0H
R/W R/W R/W
P3CFGA P3CFGB TXT0
Reserved Reserved X24 POSN
Reserved Reserved DISPLAY X24
Reserved Reserved AUTO FRAME
Reserved Reserved DISABLE HEADER ROLL
P3CFGA<2>
P3CFGA<1>
P3CFGA<0>
P3CFGB<3> DISPLAY STATUS ROW ONLY
P3CFGB<2> DISABLE FRAME
P3CFGB<1> VPS ON
P3CFGB<0> INV ON
Table 2
SFR Map
2001 Apr 12
13
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
ADD C1H R/W R/W Names TXT1 BIT7 EXT PKT OFF ACQ BANK OSD BANK ENABLE BIT6 8 BIT BIT5 ACQ OFF BIT4 X26 OFF
TDA935X/6X/8X PS/N2 series
BIT3 FULL FIELD REQ<0> PRD<3> B MESH ENABLE
BIT2 FIELD POLARITY SC<2> PRD<2> C MESH ENABLE
BIT1 H POLARITY SC<1> PRD<1> TRANS ENABLE
BIT0 V POLARITY SC<0> PRD<0> SHADOW ENABLE
C2H C3H C4H
R/W W R/W
TXT2 TXT3 TXT4
REQ<3> QUAD WIDTH ENABLE BKGND IN
REQ<2> EAST/WES T
REQ<1> PRD<4> DISABLE DOUBLE HEIGHT CORB IN
C5H
R/W
TXT5
BKGND OUT BKGND OUT STATUS ROW TOP (Reserved) 0 CURSOR FREEZE 0 D<7> 525/625 SYNC
CORB OUT
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON OUT BOX ON 1-23 WSS ON
PICTURE ON IN PICTURE ON IN BOX ON 0
C6H
R/W
TXT6
BKGND IN
CORB OUT
CORB IN
TEXT OUT
TEXT IN
C7H
R/W
TXT7
CURSOR ON FLICKER STOP ON CLEAR MEMORY 0 D<6> ROM VER<4>
REVEAL
BOTTOM/ TOP DISABLE SPANISH R<4>
DOUBLE HEIGHT PKT 26 RECEIVED R<3>
BOX ON 24
C8H
R/W
TXT8
HUNT
WSS RECEIVED R<2>
CVBS1/ CVBS0 R<0>
C9H
R/W
TXT9
A0
R<1>
CAH CBH CCH
R/W R/W R
TXT10 TXT11 TXT12
C<5> D<5> ROM VER<3>
C<4> D<4> ROM VER<2>
C<3> D<3> ROM VER<1>
C<2> D<2> ROM VER<0>
C<1> D<1> 1
C<0> D<0> VIDEO SIGNAL QUALITY PAGE<0>
CDH
R/W
TXT14
0
0
0
DISPLAY BANK MICRO BANK RS1 TD<4> TD<12> PW0V<4> PW1V<4> CCD1<4> STO STAT<1> DAT<4> ADR<3> PW3V<4> ACC<4> PW2V<4>
PAGE<3>
PAGE<2>
PAGE<1>
CEH
R/W
TXT15
0
0
0
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
D0H D2H D3H D5H D6H D7H D8H D9H DAH DBH DCH E0H E4H
R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W
PSW TDACL TDACH PWM0 PWM1 CCDAT1 S1CON S1STA S1DAT S1ADR PWM3 ACC PWM2
C TD<7> TPWE PW0E PW1E CCD1<7> CR<2> STAT<4> DAT<7> ADR<6> PW3E ACC<7> PW2E
AC TD<6> 1 1 1 CCD1<6> ENSI STAT<3> DAT<6> ADR<5> 1 ACC<6> 1
F0 TD<5> TD<13> PW0V<5> PW1V<5> CCD1<5> STA STAT<2> DAT<5> ADR<4> PW3V<5> ACC<5> PW2V<5>
RS0 TD<3> TD<11> PW0V<3> PW1V<3> CCD1<3> SI STAT<0> DAT<3> ADR<2> PW3V<3> ACC<3> PW2V<3>
OV TD<2> TD<10> PW0V<2> PW1V<2> CCD1<2> AA 0 DAT<2> ADR<1> PW3V<2> ACC<2> PW2V<2>
TD<1> TD<9> PW0V<1> PW1V<1> CCD1<1> CR<1> 0 DAT<1> ADR<0> PW3V<1> ACC<1> PW2V<1>
P TD<0> TD<8> PW0V<0> PW1V<0> CCD1<0> CR<0> 0 DAT<0> GC PW3V<0> ACC<0> PW2V<0>
Table 2
SFR Map
2001 Apr 12
14
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
ADD E7H E8H F0H F8H R/W R R/W R/W R/W Names CCDAT2 SAD B TXT13 BIT7 CCD2<7> VHI B<7> VPS RECEIVED XRAMP<7> STANDBY TEST<7> WKEY<7> WDV<7> BIT6 CCD2<6> CH<1> B<6> PAGE CLEARING XRAMP<6>
IIC_LUT<1>
TDA935X/6X/8X PS/N2 series
BIT5 CCD2<5> CH<0> B<5> 525 DISPLAY XRAMP<5>
IIC_LUT<0>
BIT4 CCD2<4> ST B<4> 525 TEXT
BIT3 CCD2<3> SAD<7> B<3> 625 TEXT
BIT2 CCD2<2> SAD<6> B<2> PKT 8/30
BIT1 CCD2<1> SAD<5> B<1> FASTEXT
BIT0 CCD2<0> SAD<4> B<0> 0
FAH FBH FDH FEH FFH
R/W R/W R W R/W
XRAMP ROMBK TEST WDTKEY WDT
XRAMP<4> 0 TEST<4> WKEY<4> WDV<4>
XRAMP<3> 0 TEST<3> WKEY<3> WDV<3>
XRAMP<2> 0 TEST<2> WKEY<2> WDV<2>
XRAMP<1> ROMBK<1> TEST<1> WKEY<1> WDV<1>
XRAMP<0> ROMBK<0> TEST<0> WKEY<0> WDV<0>
TEST<6> WKEY<6> WDV<6>
TEST<5> WKEY<5> WDV<5>
Table 2
SFR Map
A description of each of the SFR bits is shown in Table 3, The SFRs are in alphabetical order.
Names ACC ACC<7:0> B B<7:0> CCDAT1 CCD1<7:0> CCDAT2 CCD2<7:0> CCLIN CS<4:0> DPH DPH<7:0> DPL DPL<7:0> IE EA EBUSY ES2 ECC
ADD E0H
BIT7 ACC<7>
BIT6 ACC<6>
BIT5 ACC<5>
BIT4 ACC<4>
BIT3 ACC<3>
BIT2 ACC<2>
BIT1 ACC<1>
BIT0 ACC<0>
RESET 00H
Accumulator value. F0H B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> 00H
B Register value. D7H CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0> 00H
Closed Caption first data byte. E7H CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0> 00H
Closed Caption second data byte. B7H 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> 15H
Closed Caption Slice line using 525 line number. 83H DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0> 00H
Data Pointer High byte, used with DPL to address display and auxiliary memory. 82H DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0> 00H
Data pointer low byte, used with DPH to address display and auxiliary memory. A8H EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 00H
Disable all interrupts (0), or use individual interrupt enable bits (1). Enable BUSY Interrupt. Enable I2C Interrupt. Enable Closed Caption Interrupt.
Table 3
SFR Bit description
2001 Apr 12
15
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names ET1 EX1 ET0 EX0 IEN1 ET2 IP PBUSY PES2 PCC PT1 PX1 PT0 PX0 IP1 PT2 P0 P0<6:5> P1 P1<7:6> P1<3:0> P2 P2<6:0> P3 P3<3:0> P0CFGA P0CFGB ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
Enable Timer 1 Interrupt. Enable External Interrupt 1. Enable Timer 0 Interrupt. Enable External Interrupt 0. 84H ET2 00H
Enable Timer 2 Interrupt. B8H 0 PBUSY PES2 PCC PT1 PX1 PT0 PX0 00H
Priority EBUSY Interrupt. Priority ES2 Interrupt. Priority ECC Interrupt. Priority Timer 1 Interrupt. Priority External Interrupt 1. Priority Timer 0 Interrupt. Priority External Interrupt 0. 85H PT2 00H
Priority Timer 2 Interrupt. 80H Reserved P0<6> P0<5> Reserved Reserved Reserved Reserved Reserved FFH
Port 0 I/O register connected to external pins. 90H P1<7> P1<6> Reserved Reserved P1<3> P1<2> P1<1> P1<0> FFH
Port 1 I/O register connected to external pins. Port 1 I/O register connected to external pins. A0H Reserved P2<6> P2<5> P2<4> P2<3> P2<2> P2<1> P2<0> FFH
Port 2 I/O register connected to external pins. B0H Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0> FFH
Port 3 I/O register connected to external pins. 96H 97H Reserved Reserved
P0CFGA<6> P0CFGB<6> P0CFGA<5> P0CFGB<5>
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
FFH 00H
P0CFGB/P0CFGA = 00 P0CFGB/P0CFGA = 01 P0CFGB/P0CFGA = 10 P0CFGB/P0CFGA = 11 P1CFGA P1CFGB
9EH 9FH P1CFGA<7> P1CFGB<7>
MODE 0 Open Drain. MODE 1 Quasi Bi-Directional. MODE2 High Impedance. MODE3 Push Pull.
P1CFGA<6> P1CFGB<6>
Reserved Reserved
Reserved Reserved
P1CFGA<3> P1CFGB<3>
P1CFGA<2> P1CFGB<2>
P1CFGA<1> P1CFGB<1>
P1CFGA<0> P1CFGB<0>
FFH 00H
Table 3
SFR Bit description 16
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
P1CFGB/P1CFGA = 00 P1CFGB/P1CFGA = 01 P1CFGB/P1CFGA = 10 P1CFGB/P1CFGA = 11 P2CFGA P2CFGB A6H A7H Reserved Reserved
MODE 0 Open Drain. MODE 1 Quasi Bi-Directional. MODE2 High Impedance. MODE3 Push Pull.
P2CFGA<6> P2CFGB<6> P2CFGA<5> P2CFGB<5> P2CFGA<4> P2CFGB<4> P2CFGA<3> P2CFGB<3> P2CFGA<2> P2CFGB<2> P2CFGA<1> P2CFGB<1> P2CFGA<0> P2CFGB<0>
FFH 00H
P2CFGB/P2CFGA = 00 P2CFGB/P2CFGA = 01 P2CFGB/P2CFGA = 10 P2CFGB/P2CFGA = 11 P3CFGA P3CFGB BEH BFH Reserved Reserved
MODE 0 Open Drain. MODE 1 Quasi Bi-Directional. MODE2 High Impedance. MODE3 Push Pull. Reserved Reserved Reserved Reserved Reserved Reserved
P3CFGA<3> P3CFGB<3> P3CFGA<2> P3CFGB<2> P3CFGA<1> P3CFGB<1> P3CFGA<0> P3CFGB<0>
FFH 00H
P3CFGB/P3CFGA = 00 P3CFGB/P3CFGA = 01 P3CFGB/P3CFGA = 10 P3CFGB/P3CFGA = 11 PCON SMOD ARD RFI WLE GF1 GF0 PD IDL PSW C AC F0 RS<1:0> 87H SMOD
MODE 0 Open Drain. MODE 1 Quasi Bi-directional. MODE2 High Impedance. MODE3 Push Pull. ARD RFI WLE GF1 GF0 PD IDL 00H
UART Baud Rate Double Control. Auxiliary RAM Disable, All MOVX instructions access the external data memory. Disable ALE during internal access to reduce Radio Frequency Interference. Watch Dog Timer enable. General purpose flag. General purpose flag. Power-down activation bit. Idle mode activation bit. D0H Carry Bit. Auxiliary Carry bit. Flag 0, General purpose flag. Register Bank selector bits. RS<1:0> = 00, Bank0 (00H - 07H). RS<1:0> = 01, Bank1 (08H - 0FH). RS<1:0> = 10, Bank2 (10H - 17H). RS<1:0> = 11, Bank3 (18H - 1FH). C AC F0 RS<1> RS<0> OV P 00H
OV
Overflow flag.
Table 3
SFR Bit description 17
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names P PWM0 PW0E ADD Parity bit. D5H PW0E 1 PW0V<5> PW0V<4> BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
PW0V<3>
PW0V<2>
PW0V<1>
PW0V<0>
40H
0 - Disable Pulse Width Modulator 0. 1 - Enable Pulse Width Modulator 0. Pulse Width Modulator high time. D6H PW1E 1 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> 40H
PW0V<5:0> PWM1 PW1E
0 - Disable Pulse Width Modulator 1. 1 - Enable Pulse Width Modulator 1. Pulse Width Modulator high time. E4H PW2E 1 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> 40H
PW1V<5:0> PWM2 PW2E
0 - Disable Pulse Width Modulator 2. 1 - Enable Pulse Width Modulator 2. Pulse Width Modulator high time. DCH PW3E 1 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> 40H
PW2V<5:0> PWM3 PW3E
0 - Disable Pulse Width Modulator 3. 1 - Enable Pulse Width Modulator 3. Pulse Width Modulator high time. FBH STANDBY
IIC_LUT<1> IIC_LUT<0>
PW3V<5:0> ROMBK STANDBY
0
0
0
ROMBK<1>
ROMBK<0>
00H
0 - Disable Stand-by Mode 1 - Enable Stand-by Mode IIC Lookup table selection: IIC_LUT<1:0>=00, 558 Normal Mode. IIC_LUT<1:0>=01, 558 Fast Mode. IIC_LUT<1:0>=10, 558 Slow Mode. IIC_LUT<1:0>=11, Reserved. ROM Bank selection ROMBK<1:0>=00, Bank0 ROMBK<1:0>=01, Bank1 ROMBK<1:0>=10, Bank2 ROMBK<1:0>=11, Reserved
IIC_LUT<1:0 >
ROMBK<1:0 >
S1ADR ADR<6:0> GC
DBH
ADR<6>
ADR<5>
ADR<4>
ADR<3>
ADR<2>
ADR<1>
ADR<0>
GC
00H
I2C Slave Address. 0 - Disable I2C general call address. 1 - Enable I2C general call address. D8H CR<2> ENSI STA STO SI AA CR<1> CR<0> 00H
S1CON CR<2:0>
Clock rate bits. IIC rates are selectable (three tables) 0 - Disable I2C interface. 1 - Enable I2C interface.
ENSI
Table 3
SFR Bit description
2001 Apr 12
18
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names STA ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: -A START condition is generated in master mode. -The own slave address has been received during AA=1. -The general call address has been received while S1ADR.GC and AA=1. -A data byte has been received or transmitted in master mode (even if arbitration is lost). -A data byte has been received or transmitted as selected slave. A STOP or START condition is received as selected slave receiver or transmitter While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software. Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions -Own slave address is received. -General call address is received(S1ADR.GC=1). -A data byte is received, while the device is programmed to be a master receiver. -A data byte is received, while the device is selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. DAH I2C Data. D9H STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 F8H DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H
STO
SI
AA
S1DAT DAT<7:0> S1STA STAT<4:0> SAD VHI
I2C Interface Status. E8H VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4> 00H
0 - Analogue input voltage less than or equal to DAC voltage. 1 - Analogue input voltage greater then DAC voltage. ADC Input channel select. CH<1:0> = 00,ADC3. CH<1:0> = 01,ADC0. CH<1:0> = 10,ADC1. CH<1:0> = 11,ADC2. Initiate voltage comparison between ADC input Channel and SADB<3:0> value. Note: Set by Software and reset by Hardware. Most Significant nibble of DAC input word 98H 0 0 0 DC_COMP SAD<3> SAD<2> SAD<1> SAD<0> 00H
CH<1:0>
ST
SAD<7:4> SADB DC_COMP
0 - Disable DC Comparator mode. 1 - Enable DC Comparator mode. 4-bit SAD value. 81H SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0> 07H
SAD<3:0> SP SP<7> TCON TF1
Stack Pointer. 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine.
Table 3
SFR Bit description
2001 Apr 12
19
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names TR1 TF0 TR0 IE1 IT1 IE0 IT0 TDACH TPWE ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off. Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off. Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed. Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts. Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed. Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts. D3H TPWE 1 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> 40H
0 - Disable Tuning Pulse Width Modulator. 1 - Enable Tuning Pulse Width Modulator. Tuning Pulse Width Modulator High Byte. D2H TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> 00H
TD<13:8> TDACL TD<7:0> TH0 TH0<7:0> TH1 TH1<7:0> TL0 TL0<7:0> TL1 TL1<7:0> TMOD
Tuning Pulse Width Modulator Low Byte. 8CH TH0<7> TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0> 00H
Timer 0 high byte. 8DH TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0> 00H
Timer 1 high byte. 8AH TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0> 00H
Timer 0 low byte. 8BH TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0> 00H
Timer 1 low byte. 89H GATE C/T M1 M0 GATE C/T M1 M0 00H
Timer / Counter 1 GATE C/T M1,M0 Gating Control Timer /Counter 1. Counter/Timer 1 selector.
Timer / Counter 0
Mode control bits Timer/Counter 1. M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler. M1,M0 = 01, 16 bit time interval or event counter. M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1. M1,M0 = 11, stopped. Gating control Timer/Counter 0. Counter/Timer 0 selector.
GATE C/T
Table 3
SFR Bit description
2001 Apr 12
20
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names M1,M0 ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
Mode Control bits Timer/Counter 0. M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler. M1,M0 = 01, 16 bit time interval or event counter. M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0. M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter. 9CH TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0> 00H
TP2CL TP2CL<7:0> TP2CH TP2CH<7:0> TP2H TP2H<7:0> TP2L TP2L<7:0> TP2PR TP2H<7:0> TP2CRL TP2CRL<0>
Indicate the low byte of the Time 2 current value. 9DH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0> 00H
Indicate the high byte of the Time 2 current value. 92H TP2H<7> TP2H<6> TP2H<5> TP2H<4> TP2H<3> TP2H<2> TP2H<1> TP2H<0> 00H
Timer 2 high byte, never change unless updated by the software. 91H TP2L<7> TP2L<6> TP2L<5> TP2L<4> TP2L<3> TP2L<2> TP2L<1> TP2L<0> 00H
Timer 2 low byte, never change unless updated by the software. 93H TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0> 00H
Timer 2 Pre-scaler, never change unless updated by the software. 94H TP2CRL<1> TP2CRL<0>
00H
Timer 2 Control. 0 - Timer 2 disabled. 1 - Timer 2 enabled. Timer 2 Status. 0 - No Overflow. 1 - Overflow. FDH TEST<7> TEST<6> TEST<5> TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> 00H
TP2CRL<1>
TEST TEST<2:0>
Program Type bit SEL<2:0>. 011 - Display Dram test. 001 - Acquisition1 test. 010 - Acquisition2 test Functional test mode bits, set via mode select logic. Dram Size. 000 - 1.5K x 16. 001 - 2K x 16. 010 - 6K x 16. 011 - 7K x 16. 100 - 12K x 16. 101 - 14K x 16. 110 - 1K x 16. 111 - 11K x 16.
TEST<4:3> TEST<7:5>
TXT0
C0H
X24 POSN
DISPLAY X24
AUTO FRAME
DISABLE HEADER ROLL
DISPLAY STATUS ROW ONLY
DISABLE FRAME
VPS ON
INV ON
00H
X24 POSN
0 - Store X/24 in extension memory 1 - Store X/24 in basic page memory with packets 0 to 23
Table 3
SFR Bit description 21
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names DISLAY X24 ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
0 - Display row 24 from basic page memory 1 - Display row 24 from appropriate location in extension memory 0 - Normal Frame output 1 - Frame output is switched off automatically if any video displayed 0 - Write rolling headers and time to current display page 1 - Disable writing of rolling headers and time to into memory 0 - Display normal page rows 0 to 24 1- Display only row 24 0 - Normal Frame output 1 - Force Frame output to be low (0) 0 - VPS acquisition off 1 - VPS acquisition on 0 - Inventory page off 1 - Inventory page on C1H EXT PKT OFF 8 BIT ACQ OFF ACQ OFF FULL FIELD FIELD POLARITY H POLARITY V POLARITY 00H
AUTO FRAME DISABLE HEADER ROLL DISPLAY STATUS ROW ONLY DISABLE FRAME VPS ON
INV ON
TXT1
EXT PKT OFF 8 BIT
0 - Acquire extension packets X/24,X/27,8/30/X 1 - Disable acquisition of extension packets 0 - Error check and/or correct packets 0 to 24 1 - Disable checking of packets 0 to 24 written into memory 0 - Write requested data into display memory 1 - Disable writing of data into Display memory 0 - Enable automatic processing of X/26 data 1 - Disable automatic processing of X/26 data 0 - Acquire CC data only on selected line. 1 - Acquire CC data on any TV line (for test purposes).
ACQ OFF
X26 OFF
FULL FIELD
FIELD POLARIY H POLARITY
0 - Vsync pulse in first half of line during even field. 1 - Vsync pulse in second half of line during even field. 0 - Hsync reference edge is positive going 1 - Hsync reference edge is negative going 0 - Vsync reference edge is positive going 1 - Vsync reference edge is negative going C2H ACQ BANK REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0> 00H
V POLARITY
TXT2
ACQ_BANK
0 - Select Acquisition bank 0 1 - Select Acquisition bank 1 Page request Start column of page request C3H Page Request data PRD<4> PRD<3> PRD<2> PRD<1> PRD<0> 00H
REQ<3:0> SC<2:0> TXT3 PRD<4:0>
Table 3
SFR Bit description 22
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names TXT4 ADD C4H BIT7 OSD BANK ENABLE BIT6 QUAD WIDTH ENABLE BIT5
EAST/WEST
TDA935X/6X/8X PS/N2 series
BIT4 DISABLE DBL HEIGHT
BIT3 B MESH ENABLE
BIT2 C MESH ENABLE
BIT1 TRANS ENABLE
BIT0 SHADOW ENABLE
RESET 00H
OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST
0 - Only alpha numeric OSD characters available, 32 locations 1 - Alternate OSD location available via graphic attribute, additional 32 location 0 - Disable display of Quadruple width characters 1 - Enable display of Quadruple width characters 0 - Western language selection of character codes A0 to FF 1 - Eastern character selection of character codes A0 to FF 0 - Allow normal decoding of double height characters 1 - Disable normal decoding of double height characters 0 - Normal display of black background 1 - Enable meshing of black background 0 - normal display of coloured background 1 - Enable meshing of coloured background 0 - Display black background as normal 1 - Display black background as video 0 - Disable display of shadow/fringing 1 - Display shadow/ fringe (default SE black) C5H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 03H
DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE TXT5
BKGND OUT
0 - Background colour not displayed outside teletext boxes 1 - Background colour displayed outside teletext boxes 0 - Background colour not displayed inside teletext boxes 1 - Background colour displayed inside teletext boxes 0 - COR not active outside teletext and OSD boxes 1 - COR active outside teletext and OSD boxes 0 - COR not active inside teletext and OSD boxes 1 - COR active inside teletext and OSD boxes 0 - TEXT not displayed outside teletext boxes 1 - TEXT displayed outside teletext boxes 0 - TEXT not displayed inside teletext boxes 1 - TEXT displayed inside teletext boxes
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON IN TXT6
0 - VIDEO not displayed outside teletext boxes 1 - VIDEO displayed outside teletext boxes 0 - VIDEO not displayed inside teletext boxes 1 - VIDEO displayed inside teletext boxes C6H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 03H
BKGND OUT
0 - Background colour not displayed outside teletext boxes 1 - Background colour displayed outside teletext boxes
Table 3
SFR Bit description
2001 Apr 12
23
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names BKGND IN ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
0 - Background colour not displayed inside teletext boxes 1 - Background colour displayed inside teletext boxes 0 - COR not active outside teletext and OSD boxes 1 - COR active outside teletext and OSD boxes 0 - COR not active inside teletext and OSD boxes 1 - COR active inside teletext and OSD boxes 0 - TEXT not displayed outside teletext boxes 1 - TEXT displayed outside teletext boxes 0 - TEXT not displayed inside teletext boxes 1 - TEXT displayed inside teletext boxes 0 - VIDEO not displayed outside teletext boxes 1 - VIDEO displayed outside teletext boxes 0 - VIDEO not displayed inside teletext boxes 1 - VIDEO displayed inside teletext boxes C7H STATUS ROW TOP CURSOR ON REVEAL BOTTOM/ TOP DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 00H
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON IN TXT7
STATUS ROW TOP CURSOR ON
0 - Display memory row 24 information below teletext page (on display row 24) 1 - Display memory row 24 information above teletext page (on display row 0) 0 - Disable display of cursor 1 - Display cursor at position given by TXT9 and TXT10 0 - Display as spaces characters in area with conceal attribute set 1 - Display characters in area with conceal attribute set 0 - Display memory rows 0 to 11 when double height bit is set 1 - Display memory rows 12 to 23 when double height bit is set 0 - Display each characters with normal height 1 - Display each character as twice normal height. 0 - Disable display of teletext boxes in memory row 24 1 - Enable display of teletext boxes in memory row 24 0 - Disable display of teletext boxes in memory row 1 to 23 1 - Enable display of teletext boxes in memory row 1 to 23 0 - Disable display of teletext boxes in memory row 0 1 - Enable display of teletext boxes in memory row 0 C8H (Reserved) 0 FLICKER STOP ON HUNT DISABLE SPANISH PKT 26 RECEIVED WSS RECEIVED WSS ON (Reserved) 0 00H
REVEAL
BOTTOM/TO P DOUBLE HEIGHT BOX ON 24
BOX ON 1-23
BOX ON 0
TXT8
FLICKER STOP ON HUNT
0 - Enable `Flicker Stopper' circuitry 1 - Disable `Flicker Stopper' circuitry 0 - Allow automatic hunting for amplitude of data to be acquired 1 - Disable automatic hunting for amplitude 0 - Enable special treatment of Spanish packet 26 characters 1 - Disable special treatment of Spanish packet 26 characters
DISABLE SPANISH
Table 3
SFR Bit description
2001 Apr 12
24
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names PKT 26 RECEIVED ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
0 - No packet 26 data has been processed 1 - Packet 26 data has been processed. Note: This flag is set by Hardware and must be reset by Software 0 - No Wide Screen Signalling data has been processed 1 - Wide Screen signalling data has been processed Note: This flag is set by Hardware and must be reset by Software. 0 - Disable acquisition of WSS data. 1 - Enable acquisition of WSS data. C9H CURSOR FREEZE CLEAR MEMORY A0 R<4> R<3> R<2> R<1> R<0> 00H
WSS RECEIVED
WSS ON
TXT9
CURSOR FREEZE CLEAR MEMORY
0 - Use current TXT9 and TXT10 values for cursor position. 1 - Lock cursor at current position 01 - Clear memory block pointed to by TXT15 Note: This flag is set by Software and reset by Hardware 0 - Access memory block pointed to by TXT15 1 - Access extension packet memory Current memory ROW value. Note: Valid range TXT mode 0 to 24, CC mode 0 to 15 CAH 0 0 C<5> C<4> C<3> C<2> C<1> C<0> 00H
A0
R<4:0>
TXT10 C<5:0>
Current memory COLUMN value. Note: Valid range TXT mode 0 to 39, CC mode 0 to 47 CBH D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> 00H
TXT11 D<7:0> TXT12
Data value written or read from memory location defined by TXT9, TXT10 and TXT15 CCH 625/525 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEO SIGNAL QUALITY xxxxx x1xB
625/525 SYNC ROM VER<4:0>
0 - 625 line CVBS signal is being received 1 - 525 line CVBS signal is being received Mask programmable identification for character set Rom Version <4> : 0 - Spanish Flicker Stopper Disabled. 1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6). Reserved 0 - Acquisition can not be synchronised to CVBS input. 1 - Acquisition can be synchronised to CVBS F8H VPS RECEIVED
PAGE CLEARING
1 VIDEO SIGNAL QUALITY TXT13
525 DISPLAY
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
0
xxxxx xx0B
VPS RECEIVED PAGE CLEARING
01 - VPS data 0 - No page clearing active 1 - Software or Power On page clear in progress
Table 3
SFR Bit description 25
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names 525 DISPLAY ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
0 - 625 Line synchronisation for Display. 1 - 525 Line synchronisation for Display. 0 - 525 Line WST not being received 1 - 525 line WST being received 0 - 625 Line WST not being received 1 - 625 line WST being received 0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected 1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected 0 - No Packet x/27 data detected 1 - Packet x/27 data detected Reserved CDH 0 0 0 DISPLAY BANK PAGE<3> PAGE<2> PAGE<1> PAGE<0> 00H
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
0 TXT14
DISPLAY BANK PAGE<3:0> TXT15
0 - Select lower bank for Display 1 - Select upper bank for Display Current Display page CEH 0 0 0 MICRO BANK BLOCK<3 > BLOCK<2 > BLOCK<1 > BLOCK<0 > 00H
MICRO BANK BLOCK<3:0> TXT17
0 - Select lower bank for Micro 1 - Select upper bank for Micro Current Micro block to be accessed by TXT9, TXT10 and TXT11 B9H 0 FORCE ACQ<1> FORCE ACQ<0> FORCE DISP<1> FORCE DISP<0> SCREEN COL2 SCREEN COL1 SCREEN COL0 00H
FORCE ACQ<1:0>
00 - Automatic Selection 01 - Force 525 timing, Force 525 Teletext Standard 10 - Force 625 timing, Force 625 Teletext Standard 11 - Force 625 timing, Force 525 Teletext Standard 00 - Automatic Selection 01 - Force Display to 525 mode (9 lines per row) 10 - Force Display to 625 mode (10 lines per row) 11 - Not Valid (default to 625) Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components 000 - Transparent 001 - CLUT entry 9 010 - CLUT entry 10 011- CLUT entry 11 100 - CLUT entry 12 101 - CLUT entry 13 110- CLUT entry 14 111 - CLUT entry 15 B2H NOT<3> NOT<2> NOT<1> NOT<0> 0 0 BS<1> BS<0> 00H
FORCE DISP<1:0>
SCREEN COL<2:0>
TXT18 NOT<3:0> BS<1:0>
National Option table selection, maximum of 32 when used with East/West bit Basic Character set selection
Table 3
SFR Bit description 26
2001 Apr 12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names TXT19 TEN ADD B3H BIT7 TEN BIT6 TC<2> BIT5 TC<1> BIT4 TC<0>
TDA935X/6X/8X PS/N2 series
BIT3 0
BIT2 0
BIT1 TS<1>
BIT0 TS<0>
RESET 00H
0 - Disable Twist function 1- Enable Twist character set Language control bits (C12/C13/C14) that has Twisted character set Twist Character set selection B4H DRCS ENABLE OSD PLANES 0 0 OSD LANG ENABLE OSD LAN<2> OSD LAN<1> OSD LAN<0> 00H
TC<2:0> TS<1:0> TXT20
DRCS ENABLE OSD PLANES OSD LANG ENABLE OSD LAN<2:0> TXT21
0 - Normal OSD characters used 1 - Re-map column 9 to DRCS (TXT and CC modes), 0 - Character code columns 8 and 9 defined as single plane characters 1- Character code columns 8 and 9 defined as double plane characters Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
Alternative C12/C13/C14 bits for use with OSD menus
B5H
DISP LINES<1>
DISP LINES<0>
CHAR SIZE<1>
CHAR SIZE<0>
Reserved
CC ON
I2C PORT0
CC/TXT
02H
DISP LINES<1:0>
The number of display lines per character row. 00 - 10 lines per character (defaults to 9 lines in 525 mode) 01 - 13 lines per character 10 - 16 lines per character 11 - reserved Character matrix size. 00 - 10 lines per character (matrix 12x10) 01 - 13 lines per character (matrix 12x13) 10 - 16lines per character (matrix 12x16) 11 - reserved 0 - Closed Caption acquisition off 1 - Closed Caption acquisition on
CHAR SIZE<1:0>
CCON
I2C PORT0
0 - Disable I2C PORT0 1 - Enable I2C PORT0 selection (P1.7/SDA0, P1.6/SCL0) 0 - Display configured for TXT mode 1 - Display configured for CC mode B6H GPF<7> GPF<6> GPF<5> GPF<4> GPF<3> GPF<2> GPF<1> GPF<0> XXH
CC/TXT
TXT22 GPF<7:6> GPF<5>
General purpose register, bits defined by mask programmable bits 0 - Standard Painter device 1 - Enhanced Painter device 0 - Choose 6 page teletext device 1 - Choose 10 page teletext device 0 - PWM0, PWM1, PWM2 & PWM3 output on Port 3.0 to Port 3.3 respectively 1 - PWM0, PWM1, PWM2 & PWM3 output on Port 2.1 to Port 2.4 respectively
GPF<4> (Used for software only) GPF<3>
Table 3
SFR Bit description
2001 Apr 12
27
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names GPF<2> ADD BIT7 BIT6 BIT5 BIT4
TDA935X/6X/8X PS/N2 series
BIT3
BIT2
BIT1
BIT0
RESET
0 - Disable Closed Caption acquisition 1 - Enable Closed Caption acquisition 0 - Disable Text acquisition 1 - Enable Text acquisition 0 - Standalone (Painter1_Plus) mode 1 - UOC mode
GPF<1>
GPF<0> (Polarity reversed in Painter1_Plus standalone) WDT WDv<7:0> WDTKEY WKEY<7:0>
FFH
WDV<7>
WDV<6>
WDV<5>
WDV<4>
WDV<3>
WDV<2>
WDV<1>
WDV<0>
00H
Watch Dog Timer period FEH WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0> 00H
Watch Dog Timer Key. Note: Must be set to 55H to disable Watch dog timer when active. BAH 0 0 0 WSS<3:0> ERROR WSS<3> WSS<2> WSS<1> WSS<0> 00H
WSS1
WSS<3:0> ERROR WSS<3:0> WSS2
0 - No error in WSS<3:0> 1 - Error in WSS<3:0> Signalling bits to define aspect ratio (group 1) BBH 0 0 0 WSS<7:4> ERROR WSS<7> WSS<6> WSS<5> WSS<4> 00H
WSS<7:4> ERROR WSS<7:4> WSS3
0 - No errors in WSS<7:4> 1 - Error in WSS<7:4> Signalling bits to define enhanced services (group 2) BCH WSS<13:11 < ERROR WSS<13> WSS<12> WSS<11> WSS<10:8> ERROR WSS<10> WSS<9> WSS<8> 00H
WSS<13:11> ERROR WSS<13:11> WSS<10:8> ERROR WSS<10:8> XRAMP XRAMP<7:0>
0 - No error in WSS<13:11> 1 - Error in WSS<13:11> Signalling bits to define reserved elements (group 4) 0 - No error in WSS<10:8> 1 - Error in WS<10:8> Signalling bits to define subtitles (group 3)
FAH XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0>
00H
Internal RAM access upper byte address.
Table 3
SFR Bit description
2001 Apr 12
28
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
External (Auxiliary + Display) Memory The normal 80C51 external memory area has been mapped internally to the device, this means that the MOVX instruction accesses data memory internal to the device. The movx memory map is shown in Fig.7.
TDA935X/6X/8X PS/N2 series
consecutive bytes. XRAMP only works on internal MOVX memory.
FFH (XRAMP)=FFH 00H FFH (XRAMP)=FEH FF00H FEFFH FFFFH
7FFFH
FFFFH
MOVX @Ri, A MOVX A, @Ri
00H
FE00H
MOVX @DPTR,A MOVX A,@DPTR
FFH
01FFH (XRAMP)=01H
4800H 47FFH
00H FFH
0100H 00FFH (XRAMP)=00H
8C00H 8BFFH Dynamically Re-definable Characters 8800H 87FFH Display Registers 87F0H 871FH 2000H CLUT 8700H 845FH Data RAM(1) 0000H Lower 32K bytes Display RAM for Closed Caption(3) 8000H Upper 32K bytes
00H
0000H
Display RAM for TEXT PAGES(2)
Fig.8 Indirect addressing (Movx address space) Power-on Reset Power on reset is generated internally to the TDA935X/6x/8x device, hence no external reset circuitry is required. The TV processor die shall generate the master reset in the system, which in turn will reset the microcontroller die A external reset pin is still present and is logically ORed with the internal Power on reset. This pin will only be used for test modes and OTP/ISP programming. The active high reset pin incorporates an internal pull-down, thus it can be left unconnected in application. Power Saving modes of Operation There are three Power Saving modes, Idle, Stand-by and Power Down, incorporated into the Painter1_Plus die. When utilizing either mode, the 3.3v power to the device (Vddp, Vddc & Vdda) should be maintained, since Power Saving is achieved by clock gating on a section by section basis. STAND-BY MODE During Stand-by mode, the Acquisition and Display sections of the device are disabled. The following functions remain active:· 80c51 CPU Core · Memory Interface · I2C · Timer/Counters · WatchDog Timer · SAD and PWMs
07FFH
(1) Amount of Data RAM depends on device, PainterOSD 64K has 0.75K, Painter1.1 has 1K and Painter1.10 has 2K (2) Amount of Display RAM depends on the device, PainterOSD 64K has 1.25K, Painter1.1 has 2K and Painter1.10 has 10K (3) Display RAM for Closed Caption and Text is shared
Fig.7 Movx Address Map Auxiliary RAM Page Selection The Auxiliary RAM page pointer is used to select one of the 256 pages within the auxiliary RAM, not all pages are allocated, refer to Fig.8. A page consists of 256
2001 Apr 12
29
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
To enter Stand-by mode, the STAND-BY bit in the ROMBANK register must be set. Once in Stand-By, the XTAL oscillator continues to run, but the internal clock to Acquisition and Display are gated out. However, the clocks to the 80c51 CPU Core, Memory Interface, I2C, Timer/Counters, WatchDog Timer and Pulse Width Modulators are maintained. Since the output values on RGB and VDS are maintained the display output must be disabled before entering this mode. This mode may be used in conjunction with both Idle and Power-Down modes. Hence, prior to entering either Idle or Power-Down, the STAND-BY bit may be set, thus allowing wake-up of the 80c51 CPU core without fully waking the entire device (This enables detection of a Remote Control source in a power saving mode). IDLE MODE During Idle mode, Acquisition, Display and the CPU sections of the device are disabled. The following functions remain active:· Memory Interface · I2C · Timer/Counters · WatchDog Timer · SAD & PWMs To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be disabled prior to entering Idle to prevent the device being reset. Once in Idle mode, the XTAL oscillator continues to run, but the internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory Interface, I2C, Timer/Counters, WatchDog Timer and Pulse Width Modulators are maintained. The CPU state is frozen along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values. Since the output values on RGB and VDS are maintained the Display output must be disabled before entering this mode. There are three methods available to recover from Idle:· Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode. · A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit. When Painter is configured in this mode, detection of an analogue threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be 2001 Apr 12 30
TDA935X/6X/8X PS/N2 series
executed will be the one following the instruction that put the device into Idle. · The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is running, the hardware reset need only be active for two machine cycles (24 clocks at 12MHz) to complete the reset operation. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all other RAM values. Code execution commences with the Program Counter set to '0000'. POWER DOWN MODE In Power Down mode the XTAL oscillator still runs, and differential clock transmitter is active. The contents of all SFRs and Data memory are maintained, however, the contents of the Auxiliary/Display memory are lost. The port pins maintain the values defined by their associated SFRs. Since the output values on RGB and VDS are maintained the Display output must be made inactive before entering Power Down mode. The power down mode is activated by setting the PD bit in the PCON register. It is advised to disable the WatchDog timer prior to entering Power down. Recovery from Power-Down takes several milli-seconds as the oscillator must be given time to stabilise. There are three methods of exiting power down:· An External interrupt provides the first mechanism for waking from Power-Down. Since the clock is stopped, external interrupts needs to be set level sensitive prior to entering Power-Down. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Power-Down mode. · A second method of exiting Power-Down is via an Interrupt generated by the SAD DC Compare circuit. When Painter is configured in this mode, detection of a certain analogue threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Power-Down. · The third method of terminating the Power-Down mode is with an external hardware reset. Reset defines all SFRs and Display memory, but maintains all other RAM values. Code execution commences with the Program Counter set to '0000'.
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
I/O Facility I/O PORTS The IC has 13 I/O lines, each is individually addressable, or form part of 4 parallel addressable ports which are port0, port1, port2 and port3. PORT TYPE All individual ports can be programmed to function in one of four modes, the mode is defined by two Port Configuration SFRs. The modes available are Open Drain, Quasi-bidirectional, High Impedance and Push-Pull.
TDA935X/6X/8X PS/N2 series
Open Drain The Open drain mode can be used for bi-directional operation of a port. It requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5V, to allow connection of the device into a 5V environment. Quasi bi-directional The quasi-bidirectional mode is a combination of open drain and push pull. It requires an external pull-up resistor to VDDp (nominally 3.3V). When a signal transition from 0->1 is output from the device, the pad is put into push-pull mode for one clock cycle (166ns) after which the pad goes into open drain mode. This mode is used to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset. High Impedance The high impedance mode can be used for Input only operation of the port. When using this configuration the two output transistors are turned off. Push-Pull The push pull mode can be used for output only. In this mode the signal is driven to either 0V or VDDp, which is nominally 3.3V.
Interrupt System Th