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Contents ................................................................................................................................................................................... 1 Safety Precautions ................................................................................................................................................................... 2 TV Set switched off .................................................................................................................................................................. 2 Measurements .......................................................................................................................................................................... 2 PERI-TV SOCKET ................................................................................................................................................................... 2 SCART 1 ................................................................................................................................................................................... 2 SCART 2 ................................................................................................................................................................................... 2 INTRODUCTION ...................................................................................................................................................................... 2 SMALL SIGNAL PART WITH TDA884X .................................................................................................................................. 2-3 TUNER ...................................................................................................................................................................................... 4 VIDEO SWITCH TEA6415C .................................................................................................................................................... 4 AM DEMODULATOR TDA9830 ............................................................................................................................................... 4-5 DIGITAL TV SOUND PROCESSOR TDA9875 ....................................................................................................................... 5 SOUND OUTPUT STAGE TDA2614/TDA2615/TDA2616Q .................................................................................................... 5 VERTICAL OUTPUT STAGE WITH TDA8351/TDA8356 ........................................................................................................ 6 VIDEO OUTPUT AMPLIFIER TDA6107Q ............................................................................................................................... 6 SINGLE/MULTISTANDARD VIF/SIF-PLL and FM-PLL/AM DEMODULATOR TDA9818 ....................................................... 6 COMB FILTER SAA4961 ......................................................................................................................................................... 6 POWER SUPPLY (SMPS) ....................................................................................................................................................... 6 MICROCONTROLLER SDA525X ............................................................................................................................................ 6 SERIAL ACCESS CMOS 8K (1024*8) EEPROM ST24C08 ................................................................................................... 6 CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................................................... 7 SAW FILTERS .......................................................................................................................................................................... 7 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ....................................................................................................... 7 TDA8840/TDA8842/TDA8844 ........................................................................................................................................... 7-8 UV1315/UV1316/UV1336 .................................................................................................................................................. 9-10 TEA6415C .......................................................................................................................................................................... 10 TDA9830 ............................................................................................................................................................................ 10 TDA2614/TDA2615/TDA2616Q ......................................................................................................................................... 11-12 TDA8351/TDA8356 ............................................................................................................................................................ 12 TDA6107Q ......................................................................................................................................................................... 13 SAA4961 ............................................................................................................................................................................ 13-14 MC44604 ............................................................................................................................................................................ 14-15 SDA525X ............................................................................................................................................................................ 16-17 TDA9875 ............................................................................................................................................................................ 17-18 TDA9818 ............................................................................................................................................................................ 18 ST24C08 ............................................................................................................................................................................ 18 TDA1308 ............................................................................................................................................................................ 18 G1965M .............................................................................................................................................................................. 18 TDA9855 ............................................................................................................................................................................ 19 AK19 CHASSIS MANUAL ADJUSTMENT PROCEDURE ...................................................................................................... 20 For Adjust Settings ............................................................................................................................................................. 20 WHITE BALANCE ADJUSTMENT .................................................................................................................................... 20 AGC ADJUSTMENT .......................................................................................................................................................... 20 IF-PLL NEGATIVE ADJUSTMENT .................................................................................................................................... 20 IF-PLL POSITIVE ADJUSTMENT ..................................................................................................................................... 20 LUMINANCE DELAY ADJUSTMENT ................................................................................................................................ 20 VERTICAL ZOOM ADJUSTMENT .................................................................................................................................... 20 VERTICAL SCROLL ADJUSTMENT ................................................................................................................................. 20 4 : 3 HORIZONTAL SHIFT ADJUSTMENT ................................................................................................................... 20 4 : 3 VERTICAL SLOPE ADJUSTMENT ....................................................................................................................... 20 4 : 3 VERTICAL AMPLITUDE ADJUSTMENT .............................................................................................................. 21 4 : 3 S-CORRECTION ADJUSTMENT .......................................................................................................................... 21 4 : 3 VERTICAL SHIFT ADJUSTMENT ......................................................................................................................... 21 4 : 3 EW WIDTH ADJUSTMENT ................................................................................................................................... 21 4 : 3 EW PARABOLA WIDTH ADJUSTMENT .............................................................................................................. 21 4 : 3 EW CORNER PARABOLA ADJUSTMENT ........................................................................................................................ 21 4 : 3 EW TRAPEZIUM ADJUSTMENT ........................................................................................................................................ 21 16 : 9 HORIZONTAL SHIFT ADJUSTMENT ................................................................................................................................. 21 16 : 9 VERTICAL SLOPE ADJUSTMENT ..................................................................................................................................... 21 16 : 9 VERTICAL AMPLITUDE ADJUSTMENT ........................................................................................................................... 21 16 : 9 S-CORRECTION ADJUSTMENT ......................................................................................................................................... 21 16 : 9 VERTICAL SHIFT ADJUSTMENT ....................................................................................................................................... 21 16 : 9 EW WIDTH ADJUSTMENT .................................................................................................................................................. 21 16 : 9 EW PARABOLA WIDTH ADJUSTMENT ........................................................................................................................... 21 16 : 9 EW CORNER PARABOLA ADJUSTMENT ....................................................................................................................... 22 16 : 9 EW TRAPEZIUM ADJUSTMENT ....................................................................................................................................... 22 For Option Settings ..................................................................................................................................................................................... 22 OPTION 00 .......................................................................................................................................................................................... 22 OPTION 01 .......................................................................................................................................................................................... 23 OPTION 02 .......................................................................................................................................................................................... 23 OPTION 03 .......................................................................................................................................................................................... 23-24 OPTION 04 .......................................................................................................................................................................................... 24 OPTION 05 .......................................................................................................................................................................................... 24 OPTION 06 .......................................................................................................................................................................................... 24 OPTION 07 .......................................................................................................................................................................................... 24-25 OPTION 08 .......................................................................................................................................................................................... 25 OPTION 09 .......................................................................................................................................................................................... 25 OPTION 10 .......................................................................................................................................................................................... 25 GENERAL BLOCK DIAGRAM OF CHASSIS AK19 .............................................................................................................................. 26 ELECTRONIC COMPONENT PART LIST ............................................................................................................................................... 27-28
CONTENTS
1
DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCH OFF The mains supply side of the switch mode power supply transformer is live. Use an isolating transformer. The receivers fulfill completely the safety requirements. Safety precautions: Servicing of this TV should only be carried out by a qualified person. - Components marked with the warning symbol on the circuit diagram are critical for safety and must only be replaced with an identical component. - Power resistor and fusable resistors must be mounted in an identical manner to the original component. - When servicing this TV, check that the EHT does not exceed 26kV. TV Set switched off: Make short-circuit between HV-CRT clip and CRT ground layer. Short C804 (150mF) before changing IC802 or other components in primary side of SMPS. Measurements: Voltage readings and oscilloscope traces are measured under following conditions. Antenna signal 60dB from colourbar generator. (100% white, 75% colour saturation) Brightness, contrast, colour set for a normal picture. Mains supply, 220VAC, 50Hz.
PERI-TV SOCKET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SCART 1 (SC050) Audio right output 0.5Vrms / 1K Audio right input 0.5Vrms / 10K Audio left output 0.5Vrms / 1K Ground AF Ground Blue Audio left input 0.5Vrms / 10K Blue input 0.7Vpp / 75ohm AV switching input 0-12VDC /10K Ground Green Green input 0.7Vpp / 75ohm Ground Red Ground Blanking Red input 0.7Vpp / 75ohm Blanking input 0-0.4VDC, 1-3VDC / 75ohm Ground CVS output Ground CVS input CVS output 1Vpp / 75ohm CVS input 1Vpp / 75ohm Ground
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SCART 2 (SC051) Audio right output 0.5Vrms / 1K Audio right input 0.5Vrms / 10K Audio left output 0.5Vrms / 1K Ground AF Ground Blue Audio left input 0.5Vrms / 10K Blue input 0.7Vpp / 75ohm AV switching input 0-12VDC /10K Ground Green Ground Red Ground Blanking Ground CVS output Ground CVS input CVS output 1Vpp / 75ohm CVS input 1Vpp / 75ohm Ground
INTRODUCTION
Ak18 is a 100Hz double scan color television capable of driving 28 4:3/16:9 and 33 4:3 picture tubes. The chassis is capable of operation both in PAL, SECAM, NTSC playback color standards and multiple transmission standards as B/G, D/K, I/I+, and L/L´. Sound system output is supplying 12W (10%Thd) for left, right and center outputs of 8ohm speakers and 7W for 2 surround outputs of two 8ohm speakers. TV has Megatext or Tvtext teletext system. The chassis is equipped with 1 full EuroScart, 2 other Scarts for AV input/output, front-AV/back-AV, headphone output, SVHS input, VGA input, two external speaker output, one center speaker and two surround speaker outputs.
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IF PART
TDA4470/TDA4472 The TDA44XX is an integrated bipolar circuit for multistandard video/sound IF (VIF/SIF) signal processing in TV/VCR and multimedia applications. The circuit processes all TV video IF signals with negative modulation (e.g., B/Gstandard), positive modulation (e.g., L standard) and the AM, FM/NICAM sound IF signals. Active carrier generation by FPLL (frequency phase-locked loop) is the principle for true synchronous demodulation. VCO circuit is operating on picture carrier frequency, The VCO frequency is switchable for L´-mode. AFC without external reference circuit is alignmentfree and polarity of The AFC curve is switchable. VIF-AGC for negative modulated signals operates on peak sync detection principle and for positive modulation on peak white/black level detection principle. Tuner AGC is adjustable with determining take over point. It has alignment-free quasi parallel sound (QPS) mixer for FM/NICAM sound IF signals. Intercarrier output sound is gain controlled (necessary for digital sound processing). AM- demodulator is completely alignment-free with gain controlled AF output. Operation of the AM demodulator and QPS mixer (for NICAM-L stereo sound is parallel.TDA4472 is used for negative modulation and TDA4470 is used for both negative and positive modulation.
100Hz FEATURE BOX
SDA9205/SDA9257/SDA9254/SDA9220/SDA9280 The SDA9205 is a single IC containing three separate 8-bit analog to digital converters for video (YUV) applications. It provides 30-Mhz sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several control inputs. The SDA9257 is the clock sync generator. It is I2C controlled. It has PLL locked-in behaviour is locked to TV mode. It clamps CVBS inputs and provides all horizontal and vertical sync signals and clocks for PAMUX, analog circuit decoder, the A/D converters, PSDN and Feature-box. SDA9220 is a memory sync controller which is responsible for driving the picture memory devices and generating sync signals. Together with the other devices of feature-box it enhances picture quality and offers special operating modes. It is set via I2C bus. The memory controller produces driving signals for the memory devices and the clock generator consists essentially of a PLL which generates the internal and exported system clocks from input clock LL3 or LL1.5 and synchronises them with the horizontal blanking signal. SDA9280 is the display processor is an integrated triple 9-bit D/A converter which performs digital enhancements and manipulations of digital video component signals. It has 8-bit amplitude resolution for each input component with input sample frequency up to 30Mhz. DCTI (Digital color transient improvement), luminance peaking, 16:9 compatibility, delay for luminance and chrominance signals, zoom facility are tasks which are performed by this IC. The SDA9254 is a dynamic sequential access memory for 100Hz TV applications. It is a triple port dynamic sequential-access memory for high-data-rate video applications It is organised for the storage of planes of at TV field (NTSC, PAL, SECAM, MAC) in standard quality.
COMB FILTER
SAA4961 The SAA4961 is a single chip PAL/NTSC comb filter with internal delay lines, filters, clock control, synchronisation and signal switches. The comb filter function is realised in a switched-capacitor technic, so it has time discrete but amplitude continuos processing. The Y/CVBS input is first clamped and then fed to the delay-line and comb filter section via low pass pre-filter. This signal is also fed to the sync separator, where horizontal and vertical reference pulses are created. Bypass mode for secam mode can be forced by a control pin (BYP). FSC is the sub-carrier input which is connected to the color decoder.
POWER SUPPLY (SMPS)
TDA4605 The Dc voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC TDA4605 which is designed for driving, controlling, and protecting switching transistor of SMPS. Two optocouplers are used to control the regulation of line voltage and stand-by power consumption. Line voltage value is supplied by an oprtocoupler (CQY80NG) to the control input of SMPS IC on the primary side and regulation is controlled by variable resistor on secondary side of the stage. An ON/OFF signal comes from microcontroller and drives an optocoupler (MOC3023) to connect and disconnect the 220V AC line. A second transformer which is driven directly from mains AC input generates the necessary 5V DC stand-by voltage. Transformer produces 148/150V DC for FBT input, +/-16V DC for audio output 8.5V, 16V, 22V and 33V for the other parts of the chassis. The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, It controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations. The required control information is taken from the input voltage during the switch on period and from a regulation winding during the switch off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. The power supply is operating in the burst mode at typical 20 to 40Khz.
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TUNER
UV1316 The UV1316 tuner belongs to the UV1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L´, I and I´, D/K. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. The tuning is available through built-in digitally controlled I2C bus (PLL).
Channel coverage of UV1316: BAND OFF-AIR CHANNELS CHANNELS RANGE (MHz) E2 to C E5 to E12 E21 to E69 FREQUENCY 48.25 to 82.25 (1) 175.25 to 224.25 471.25 to 855.25 (2) CABLE CHANNELS CHANNELS S01 to S08 S09 to S38 S39 to S41 FREQUENCY RANGE (MHz) 69.25 to 154.25 161.25 to 439.25 447.25 to 463.25
Low Band Mid Band High Band
(1). Enough margin is available to tune down to 45.25 MHz. (2). Enough margin is available to tune up to 863.25 MHz.
Noise
Typical Low band : 5dB Mid band : 5dB High band : 6dB
Max. 9dB 9dB 9dB
Min. All channels : 38dB Gain Taper (of-air channels) : -
Gain
Typical 44dB -
Max. 52dB 8dB
Channel Coverage UV1336: BAND Low Band Mid Band High Band CHANNELS 2 to D E to PP QQ to 69 FREQUENCY RANGE (MHz) 55.25 to 139.25 145.25 to 391.25 397.25 to 801.25
Noise is typically 6dB for all channels. Gain is minimum 38dB and maximum 50dB for all channels. Channel Coverage of UV1315: BAND OFF-AIR CHANNELS CHANNELS E2 to C E5 to E12 E21 to E69 FREQUENCY RANGE (MHz) 48.25 to 82.25 (1) 175.25 to 224.25 471.25 to 855.25 (2) CABLE CHANNELS CHANNELS S01 to S10 S11 to S39 S40 to S41 FREQUENCY RANGE (MHz) 69.25 to 168.25 231.25 to 447.25 455.25 to 463.25
Low Band Mid Band High Band
(1). Enough margin is available to tune down to 45.25 MHz. (2). Enough margin is available to tune up to 863.25 MHz. Noise Typ. Low band : 6dB Mid band : 6dB High band : 6dB Max. 9dB 10dB 11dB Gain All Channels Gain Taper (off-air channels) Min. 38dB Typ. 44dB Max. 50dB 8dB
DIGITAL DEFLACTION PART
SDA9362 The SDA9362is a highly integrated deflection controller for TV receivers with doubled line and doubled field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All adjustable outputs are I2C bus controlled. Inputs are doubled HSYNC and doubled VSYNC signals coming from sync switching IC which takes its inputs from TDA9143 IC and VGA sync input. It has also horizontal and vertical EHT-compensation input against beam current run away. The protection circuit watches an EHT reference and the sawtooth of the vertical output stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails. H- and V-blanking time is adjusted via I2C bus.
4
DIGITAL TV SOUND PROCESSING
MSP3410D The MSP3410D is a I2C controlled single-chip multistandard sound processors for applications in analog and digital TV sets. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out is performed in a single-chip covering all European TV-standards. It is designed to simultaneously perform digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM or AM-mono TV sound. Alternatively, two carrier FM systems according to the German or Korean terrestrial specs of the satellite specs can be processed within the IC. It has two selectable analog sound IF inputs: TV and SAT-IF sources. There is AGC for analog inputs:0.14-3Vpp. All demodulation and filtering is performed on chip and is individually programmable. All digital NICAM standards (B/G, I and L) are realised. FM-demodulation of all satellite and terrestrial standards are possible. Only one crystal clock (18.432Mhz) is necessary. External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilising the frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431Mhz as closely as possible. By means of standardised I2S interface, additional feature processors (TMS37600, Dolby Prologic digital audio signal processor for this chassis) can be connected to the IC. I2S bus interface consists of five pins: I2S_DA_IN1 and I2S_DA_IN2; For input, Four channels (two channels per line) per sampling cycle 32Khz. I2DA_OUT; For output, two channels per sampling rate of 32Khz. I2S_CL; For timing of the transmission of I2S serial data, 1.024Mhz. I2S_WS; The word strobe line defining the left and right sample.
DOLBY PRO LOGIC DASP (Digital audio signal processing IC)
TMS37600 The TMS37600 IC is a digital audio signal processor used when Dolby Pro Logic option is available. It gets digitised sound from the audio processor IC MSP3410D for both 4 channels via I2S_DA_OUT pin and processes these information to give two outputs for MSP3410D: I2S_DA_IN1 (for right and left channels) and I2S_DA_IN2 (for center and surround channels). Synchronisation is obtained by 2 I2S busses: I2S_CL; For timing of the transmission of I2S serial data, 1.024Mhz and I2S_WS; The word strobe line defining the left and right sample at 32Khz. The IC is also I2C bus controlled to select the sound feature (stereo, ^D-phonic and Dolby Pro Logic). It operates with a external DRAM in order to download some data which processes sound for sound features and sound modes. It has an external clock generator cycling at 27.576Mhz.
AUDIO AND VIDEO INPUT AND OUTPUT SOURCE SWITCHING
TEA6415/TEA6420 Video switching is performed by TEA6415 and audio switching is performed by TEA6420. Inputs for audio switch are: Three Scart left and right audio signals, front-AV audio for left and right channels. Outputs for audio switch are: Three Scart left and right audio signals, one left and right audio signal output for Scart_1 Left and Right input of MSP3410D. The audio switch IC is I2C bus controlled and gain of each input-output matrices are 0dB. Inputs for video switch are: front-end CVBS, three Scart video signals, and front-AV video signal and Y input from SVHS source. Outputs of video switch are three Scart video signals, one video output for PIP-video input and one output for switched Y or CVBS input of the comb filter. The video switch IC is also I2C bus controlled and gain of each input-output matrices are 0dB.
HEADPHONE OUTPUT
TDA1308 The TDA1308 is an integrated class AB stereo headphone driver. It gets its input from Scart2 left and right audio outputs of MSP3410D and has gain adjusting feedback from output to input signal.
VIDEO OUTPUT AMPLIFIER STAGE
TDA611Q The TDA6111Q is a video output amplifier with 16Mhz bandwidth. It has a high slew rate. Automatic black-current stabilisation is possible by black-current measurement output. It has two cathode outputs: one for DC currents and one for transient currents. A feedback output is separated from the cathode outputs. An internal protection exists against positive appearing cathode-ray-tube flashover discharges with ESD protection.
5
VERTICAL OUTPUT STAGE
TDA8351 The TDA8351 vertical deflection circuit can be used in 1100 deflection systems with field frequency from 50 up to 120Hz. With its bridge configuration the deflection output can be DC coupled with few external components. Only a single supply voltage for the scan and a second supply for the flyback are needed. The drive voltage is amplified by an amplifier and fed to two amplifiers, one is inverting and the other is a non inverting amplifier. The outputs are connected to the series connection of the vertical deflection coil and feedback resistor Rsense. The voltage across Rsense is fed via pin9 to correction amplifier, to obtain a deflection current which is proportional to the drive voltage. The supply voltage for the TDA8351 is 15V DC at pin 3. The supply voltage generator has a separate supply voltage of 45V DC at pin 6.
SAW FILTERS
K9453 : Two channel switchable sound IF saw filter of BG, DK, I, L systems for input channel 2 and of L´ system for input channel 1. K3953 : Two channel switchable video IF saw filter of BG, DK, I, L systems for input channel 2 and of L´system for input channel 1. J3950 : Video IF saw filter for I system
YUV VIDEO AND SYNC PROCESSOR
TDA9143 The TDA9143 is an I2c bus controlled, alignment-free PAL/NTSC/SECAM decoder and sync processor. It has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter. The IC can process both CVBS input signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastel, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When HA pulse is selected a line locked clock (LLC) signal is available at the output port pin. A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal. IC has inputs Y C or CVBS from comb filter board. RGB signals coming from Scart1 are also injected into the IC. UV signal input and output are also ready for chromaninance delay line. One CVBS output is for teletext operation and it enters The Megatext IC or Tvtext controller. Outcoming YUV signals enter the feature box for double scan 100Hz digital video processing. Horizontal and vertical sync pulses are added and they enter the feature box for production of double scan vertical and horizontal sync pulses and synchronisation signal LL1_5X.
RGB OUTPUT AND BLACK-CURRENT STABILISATION
TDA4780 The TDA4780 is I2C bus controlled post video signal processor with a baseband signal interface and two sets of analog RGB inputs. Doubled frequency color difference signals YUV coming from feature box are matrixed with the luminance signal to obtain the RGB signals driving the RGB output stage (TDA6111Q). Three analog input sets are available, one luminance/color-difference input signals and two sets of RGB and fast-blanking signals. One input set is used for RGB+fb signal coming from Megatext IC (for OSD and teletext) and the other set is used for RGB+fb signals coming from full Scart1. Different RGB matrices can be selected via I2Cbus, either PAL/SECAM matrix or the NTSC matrix. Saturation, contrast, and brightness controls are individually adjusted via I2C bus (for the luminance/color difference and RGB inputs). All adjustments can be synchronised with the vertical blanking interval. It expands lower signal levels, while higher signal levels are compressed to enlarge the contrast ratio and thus expands the portrayal in the direction of black. Adaptive black level control acts on the luminance signal, the darkest level of the active picture is detected and controlled to the internal reference black level. The automatic cut-off control measures the cut-off currents of the CRT using artificial black level signals provided on the outputs during three successive lines, the provided artificial black level equals the clamping level of the RGB or Y input signals. A luminance signal for scan velocity modulation of a line deflection can be provided if required.
6
AUDIO OUTPUT
TDA7264 The TDA7264 is a 25W+25W stereo sound amplifier with mute/stand-by facility. STPA control signal coming from microcontroller (when it is at high level) activates the mute function. IC is muted when mute port is at low level. Two stereo audio signals coming from audio module is injected to the inputs of the IC and a power of 12Wrms (10%) is obtained. An external pop-noise circuitry pulls AF inputs of the IC in order to eliminate pop noise when TV is turned on or off
via mains supply connection.
SERIAL ACCESS 32K EEPROM
24LC32A The IC s 32Kbit electrically erasable programmable memory. The memory is compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock.
MEGATEXT TELETEXT AND OSD GENERATOR
SDA5273 The SDA5273 is a single-chip IC for teletext, VPS, PDC, telecaption and OSD generator. Its input is analog CVBS with on-chip clamping circuit. It has analog RGB+fb output which enters into the RGB processor (TDA4780). It is I2C bus controlled or 3-wire USART-interface is selected. IC has two independent clock systems for acquisition and display. Its main functions are the decoding and display of teletext information coming from analog sources and the generation of OSD which can provide the TV with status information or menu (user interface) assistance. The Megatext is a real single chip solution which combines data slicer, teletext processor, VPS-decoder, page/pixel memory and display controller. The memory is extended by external DRAM to increase the teletext capacity up to 512 pages. The Megatext IC delivers analog RGB-output signals with a maximum amplitude of 2V peal to peak. The contrast/brightness of the RGB output signal can be controlled by software in linear steps without decreasing the amplitude resolution. IC is controlled by an external controller (SDA30264) via M3L-Bus (USART, 2+1 wires). M3L-Bus increases the maximum data rate up to 1Mbits/sec and is thus 10 times faster than the I2C bus in standard mode.
MICROTEXT CONTROLLER (with TVTEXT option)
SDA5253 The device is TVTEXT tuning and control system and designed for a low cost TV-SET. The system offers an on screen display /OSD) and IR remote control of all functions. Display of program number, channel number, TV standard, analog values, sleep timer, parental control, mute and user interface are done by OSD. There is dual color single LED for IR active, and stand-by indication. There is 3 lines for external selection, 2 lines for TV standard selection, one stand-by line, 2 lines for PIP mode, Vga line and sound output mute line. System configuration is also controlled by the IC with service mode facility.
MICROTEXT CONTROLLER (with Megatext option)
SDA30C264 The SDA30C264 is the microcontroller used with Megatext option. Its architecture and instruction set are based upon that of the 8051 microcomputer. Like the 8051 it has many features which increase programming ease; extended internal data memory-space , variable manipulation in internal data memory, free stack location in data RAM, 4 register banks, special function registers, memory mapped I/O, individually addressable bits and a Boolean processor which gives the programmer the ability to improve the power of the software development. The IC communicates with the EPROM and produce the following input or output control signals; Agc_con, Pal_secam,Pip_mod_sw,On_off (stand-by) Pip_sel, Sdat and SclT (M3L bus) for Megatext IC, Scx_in_av (pin 8 information from 3 Scarts), AFC, Vga_fb, STPA (to mute audio output IC), IICENx.
PORT EXPANDER
PCF8574 The PCF8574 is an I2C bus controlled IC for standard selection control lines for the IF IC (TDA447X). The IC has inputs for standard and L´ control from the microcontroller and outputs for IF IC.
7
VGA SYNC POLARITY CONVERTER
74HC86 The 74HC86 is an exor logic IC. Its inputs are Vga horizontal and vertical sync signals of positive or negative polarity. Whatever their polarity, they are converted to higher polarity and IC has always positive polarity Vga horizontal and vertical sync signals
SOURCE SWITCH BETWEEN TV AND VGA SYNC SIGNALS
HEF4053B The HEF4053B is a switch IC used to select sync signals entering feature box to provide correct sync signal between VGA and normal TV sync signals. Selection of sync couple is controlled by VGA_fb control signal coming from microcontroller.
CHROMINANCE DELAY LINE
TDA4665 The TDA4665 is a chrominance delay line. Its inputs are U-V signals and sandcastel signal coming from video processor (TDA9143). Output is the 1H delayed U-V signals entering into video processor.
DRAM
HYB514400BJ The HYB514400BJ is the new generation dynamic RAM organised as 1M by 4-bit. it utilises CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. This DRAM is used with Megatext IC to store teletext pages and with Dolby IC to download related coefficients of the ROM for different sound features.
EPROM
ST27C2001 The ST27C2001 is 2097 152-bit, ultra-violet erasable, electrically programmable read-only memory. This device is fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by series 74TTL circuits without the use of external pull-up resistors. Each output can drive one series 74 TTL circuit without external resistors. Software for user interface and control of hardware circuitry are stored in this eprom IC. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM n n n n n n n n n n n n n n n n n n n n n TDA4470/TDA4472 SDA9205/SDA9257/SDA9254/SDA9220/SDA9280 SAA4961 TDA4605 TUNER (UV1315,UV1316,UV1336) SDA9362 MSP3410D TMS37600 TEA6415 / TEA6420 TDA1308 TDA611Q TDA8351 TDA9143 TDA4780 TDA7264 SDA5273 SDA5253 SDA30C264 TDA4665 HYB514400BJ ST27C2001
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TDA4470 / TDA4472 :
The TDA4470 is an integrated bipolar circuit for multistandard video / sound IF (VIF / SIF) signal prosessing in TV / VCR and Multimedia applications. The circuit processes all TV video IF signals with negative modulation (e.g. L standard) and the AM, FM / NICAM sound IF signals. Features: n 5V supply voltage; low power consumption n Active carrier generation by FPLL principle (frequency-phase-locked-loop) for true synchronous demodulation n Very linear video demodulation, good pulse response and excellent intermodulation figures n VCO circuit is operating on picture carrier frequency, the VCO frequency is switchable for the Lmode n Alignment-free AFC without external reference circuit, polarity of the AFC curve is switchable n VIF-AGC for negative modulated signals (peak sync detection) and for positive modulation (peak white/black level detector) n TunerAGC with adjustable take over point n Alignment-free quasi parallel sound (QPS) mixer for FM/NICAM sound IF sihnals n Intercarrier output signal is gain controlled (necessary for digital sound processing) n Complete alignament-free AM demodulator with gain controlled AF output n Separate SIF-AGC with average detection n Two independent SIF inputs n Parallel operation of the AM demodulator and QPS mixer (for NICAM-L stereo sound) n Package and relevant pinning is compatible with the single standard version TDA 4472; simplifies the desihn of an universal IF module PINNING 1. Input sensitivity, RMS value 2. Input sensitivity, RMS value 3. SIF Input selector switch 4. Ground 5. IF gain control range 6. Input sensitivity, RMS value 7. Input sensitivity, RMS value 8. IF gain control range 9. Ground 10. Aveilable tuner-AGC current 11. Aveilable tuner-AGC current 12. Video output 13. Standard switch 14. Lswitch 15. IF gain control range 16. Ground 17. Internal reference voltage 18. FPLL and VCO 19. AFC switch 20. FPLL and VCO 21. FPLL and VCO 22. AFC output 23. DC supplay 24. DC output voltage 25. AF output-AM 26. FPLL and VCO 27. Input sensitivity, RMS value 28. Input sensitivity, RMS value PIN VALUE : 80mVrms : 80mVrms : 2.0 V : : : : : : : : : : : : : : : : : : : : : : 65dB 80mVrms 80mVrms 65dB 2mA Min : 0.3V Min : 1.8V Min : 0V Min : 0V 65dB Max : 13.5V Max : 2.2V Max : 0.8V Max : 3.0V
Min : 1mA Max : 4mA Min : 0V Max : 0.8V Min : 1mA Max : 4mA Min : 1mA Max : 4mA 0.7 mA/kHz Min : 4.5V Max : 9.0V 2V 2.2V Min : 1mA Max : 4mA 80mVrms 80mVrms
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SDA 9205:
The SDA9205 is a single monolithic IC containing three separate 8-bit analog to digital converters for video (YUV) applications. It utilizes an advanced VLSI 1.2mA CMOS process process providing 30-MHz sampling rates at 8 bits. Different digital output multiplex are selectable on chip via several control inputs, compatible to inputs of all Siamens Featureboxes, Siemens TV-SAM, and CCIR 656 output format. The ADCs have no missing codes over the full operating temparature range of 0 to + 70 °C. Operation is from +5 V DC-power supply. Features: n Three equivalent CMOS A/D converters on chip n 30-MHz sample rate n 8-bit resolution n No external sample & hold required n On-chip input buffer for each analog channel n Internal clamping circuits for each of the ADCs n Different digital output multiplex formats : - 3 independent unmultiplexed 8-bit outputs - Multiplexed formats compatiple to inputs of all Siemens Featureboxes and Siemens TV-SAM - CCIR 656 output format n Overflow and underflow outputs PINNING 1. Digital outputs of ADC C (port C) C1 least significant bit 2. Digital outputs of ADC C (port C) C0 least significant bit 3. Output stages supply ground of port C 4. Underflow data output of ADC C 5. Overflow data output of ADC C 6. Output aneble of port C 7. Binary / twos complement output port C 8. Control inputs for different digital output multiplex formatsrefer to logic table 9. Control inputs for different digital output multiplex formatsrefer to logic table 10.Reference voltage high of ADC C (+2.5V) 11. Control inputs for different digital output multiplex formatsrefer to logic table 12.Analog positive supply voltage of ADC C (+5V) 13.Analog ground of ADC C 14.Reference voltage low of ADC C (+5V) 15.Analog voltage input of ADC C 16.Reference voltage high of ADC B (+2.5V) 17.Control inputs for different digital output multiplex formatsrefer to logic table 18.Analog positive supply voltage of ADC B (+5V) 19.Analog ground ADC B 20.Referece voltage low of ADC B (+0.5V) 21.Analog voltage input ADC B 22.Reference voltage high of ADC A (+2.5V) 23.Analog positive supply voltage ADC A (+5V) 24.Analog ground of ADC A 25.Analog voltage input of ADC A 26.Reference voltage low of ADC A (+0.5V) 27.Factory use only, connect to 0V 28.Binary / twos complement output port A 29.Factory use only, connect to 0V 30.Clamp input for all three channels 31.Underflow data output of ADC A 32.Overflow data output of ADC A 33.Output stage supply ground of port A 34.Digital outputs of ADC A (port A) A7 least significant bit 35.Digital outputs of ADC A (port A) A6 least significant bit 36.Digital outputs of ADC A (port A) A5 least significant bit 37.Digital outputs of ADC A (port A) A4 least significant bit 38.Digital outputs of ADC A (port A) A3 least significant bit 39.Digital outputs of ADC A (port A) A2 least significant bit 40.Digital outputs of ADC A (port A) A1 least significant bit 41.Digital outputs of ADC A (port A) A0 least significant bit 42.Output enable of port A
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43.Output stages supply voltage of port A 44.Output enable of port B 45.Underflow data output ADC B 46.Overflow data output ADC B 47.Output stages supply ground of port B 48.Digital outputs of ADC B (port B) B7 least significant bit 49.Digital outputs of ADC B (port B) B6 least significant bit 50.Digital outputs of ADC B (port B) B5 least significant bit 51.Digital outputs of ADC B (port B) B4 least significant bit 52.Digital outputs of ADC B (port B) B3 least significant bit 53.Digital outputs of ADC B (port B) B2 least significant bit 54.Digital outputs of ADC B (port B) B1 least significant bit 55.Digital outputs of ADC B (port B) B0 least significant bit 56.Output stages supply voltage of port B 57.Clock input 58.Digitai ground 59.Format sync input 60.Binary / twos complement output port B 61.Digital positive supply voltage (+5V) 62.Output stages supply voltage of port C 63.Digital outputs of ADC C (port C) C7 least significant bit 64.Digital outputs of ADC C (port C) C6 least significant bit 65.Digital outputs of ADC C (port C) C5 least significant bit 66.Digital outputs of ADC C (port C) C4 least significant bit 67.Digital outputs of ADC C (port C) C3 least significant bit 68.Digital outputs of ADC C (port C) C2 least significant bit
SAA4961:
The SAA4961 is an adaptive alignment-free one chip comb filter compatible with both PAL and NTSC systems and provides high performance in Y/C separation. Features: n One chip adaptive multi-standard comb filter n Time discrete but continuous amplitude signal processing with analogue interfaces n Internal delay lines, filters, clock processing and signal switches n Alignment-free n No hanging dots or residual cross colour on vertical transients n Few external components It is possible to switch the comb filter into one of the following 3 modes: 1. Comb mode : In this mode, luminance and chrominance comb filter function are active. Chrominance output pin (pin12) outputs comb filtered chrominance signal, luminance output pin (pin 14) outputs comb filtered luminance signal and CVBS output pin (pin15) outputs delay compensated CVBS signal. 2. Comboff mode : In this mode, luminance comb filter function is turned off, but chrominance comb filter function operates. Chrominance output pin (pin 12) outputs comb filtered chrominance signal, luminance output pin (pin14) outputs delay compensated CVBS signal and CVBS output pin (pin 15) outputs delay compensated CVBS signal. 3. Bypass mode : In this mode, no IC-function is active. Cext is bypassed to chrominance output pin (pin12) and Yext/CVBS is bypassed to luminance output pin (pin 14) and CVBS output pin (pin 15). PINNING 1. Subcarrier frequency input 2. Internal connected 3. Bypass mode forcing 4. Internal connected 5. Decoupling capacitor 6. Internal connected 7. Analogue supply voltage 8. Analogue supply voltage output buffer 9. Analogue ground 10.External chrominance input 11. Analogue ground output buffer 12.Chrominance output signal 13.fsc reference selection 14.Luminance output signal PIN VALUE : 200mVpp, Min : 100mVpp, Max : 400mVpp : HIGH level input voltage Min : 2.4VDC, Max : Vcc : 1.25VDC, Min : 1.1VDC, Max : 1.4VDC : 5VDC, Min : 4.75VDC, Max : 5.5VDC : 5VDC, Min : 4.75VDC, Max : 5.5VDC : 0.7Vpp, Max : 1Vpp : 0mV, Min : -400mV, (DC offset voltage related to input) Max:+400mV BYPASS-mode:Co/Cext : 0dB, Min : -1dB, Max : +1dB : HIGH level input voltage Min : 2V, Max : Vcc : Low level input voltage Min : 0V, Max : 0.8V : 1Vpp, Min : 0.6Vpp, Max : 1.54Vpp
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15.CVBS and Y output signal 16.Internal connected 17.CVBS and Y input signal 18.Disable prefilter 19.Storage Capacitor 20.Standard select 1 21.Digital ground 22.Digital supply voltage 23.Standard select 2 24.Decoupling capacitor 25.Controlling I/O pin 26.Analogue ground PLL 27.Analogue supply voltage PLL 28.Internal connected
: 1Vpp, Min : 0.6Vpp, Max : 1.54Vpp : 1Vpp, Min : 0.7Vpp, Max : 1.4Vpp : HIGH level input voltage Min : 2.0VDC, Max : Vcc LOW level input voltage Min : 0VDC, Max : 0.8VDC : 2.5VDC, Min : 1.8VDC, Max : Vcc : HIGH level input voltage Min : 2.0VDC, Max : Vcc LOW level input voltage Min : 0VDC, Max : 0.8VDC : 5VDC, Min : 4.75VDC, Max : 5.5VDC : HIGH level input voltage Min : 2.0VDC, Max : Vcc LOW level input voltage Min : 0VDC, Max : 0.8VDC : 1.25VDC, Min : 1.1VDC, Max : 1.4VDC : HIGH level input voltage Min : 2.4VDC, Max : Vcc LOW level input voltage Min : 0VDC, Max : 1.5VDC : 5VDC, Min : 4.75VDC, Max : 5.5VDC
TDA4605 :
The IC TDA 4605 controls the MOS-power transistor and performs all necessary control and protection functions in free running flyback converters. Because of the fact that a wide load range is achieved, this IC is applicable for consumer as well as industrial power supplies. The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch-on period of the transistor, energy is stored in the tronasformer. During the switch-off period the energy is fed to the load via the secondery winding. By varying switch-on time of the power transistor, the Ic controls each portion of energy transferred to the secondary side such that the output voltage remains nearýl independent of load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period. A vew cycle will start if the trasformer has trasfered the stored energy completely into the load In the different load renges the switched-mode power supply (SMPS) behaves as follows : No load operation The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be a little bit higher or lower than the nominal value depending of the design of the transformer and the resistors of the control voltage divider. Nominal operation The switching frequency is reduced with increasing load and decreasing AC-voltage. The output voltage is only dependent on the load. Overload point Maximal output power is available at this point of the output characteristic. Overload The energy trasferred per operation cycle is limited at the top. Therefore the output voltages declines by secondary overloading. Features: n Fold-back characteristics provides overload protection for external components. n Burst operation under secondary short-circuit condition implemented. n Protection against open or a short of the control loop n Switch-off if line voltage is too low (undervoltage switch-off) n Line voltage depending compensation of fold-back point n Soft-start for quiet start-up without noise generated (thermal shutdown) n On-chip ringing suppression circuit against parasitic oscillations of the transformer n AGC-voltage reduction at low load PINNING 1. Information Input Concerning Secondary Voltage 2. Information Input Regarding the Primary Current 3. Input for Primary Voltage Monitoring 4. Ground 5. Output 6. Supply Voltage Input 7. Input for Soft-Start 8. Input for the Oscillation Feedback
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UV1315, UV1316, UV1336
General description of UV1315: The UV1315 tuner belongs to the UV 1300 familiy of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L, I and I. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of UV1315: n Member of the UV1300 family small sized UHF/VHF tuners n Systems CCIR:B/G, H, L, L, I and I; OIRT:D/K n Voltage synthesized tuning (VST) n Off-air channels, S-cable channels and Hyperband n Standardized mechanical dimensions and pinning n Compact size PINNING 1. Gain control voltage (AGC) 2. Tuning voltage 3. High band switch 4. Mid band switch 5. Low band switch 6. Supply voltage 7. Not connected 8. Not connected 9. Not connected 10.Symmetrical IF output 1 11. Symmetrical IF output 2 Bandswitching table: Pin 3 Low band 0V Mid band 0V High band +5V Pin 4 0V +5V 0V PIN VALUE : 4.0V, Max:4.5V : : : : 5V, Min:4.75V, Max:5.5V 5V, Min:4.75V, Max:5.5V 5V, Min:4.75V, Max:5.5V 5V, Min:4.75V, Max:5.5V
Pin 5 +5V 0V 0V
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L, I and I. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of UV1316: n Member of the UV1300 family small sized UHF/VHF tuners n Systems CCIR: B/G, H, L, L, I and I; OIRT: D/K n Digitally controlled (PLL) tuning via IýC-bus n Off-air channels, S-cable channels and Hyperband n World standardized mechanical dimensions and world standard pinning n Compact size n Complies to CENELEC EN55020 and EN55013 PINNING 1. Gain control voltage (AGC) 2. Tuning voltage 3. I²C-bus address select 4. I²C-bus serial clock 5. I²C-bus serial data 6. Not connected 7. PLL supply voltage 8. ADC input 9. Tuner supply voltage 10.Symmetrical IF output 1 11. Symmetrical IF output 2 PIN VALUE : 4.0V, Max:4.5V : Max:5.5V : Min:-0.3V, Max:5.5V : Min:-0.3V, Max:5.5V : 5.0V, Min:4.75V, Max:5.5V : 33V, Min:30V, Max:35V
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General description of UV1336:
UV1336 series is developed for reception of channels broadcast in accordance with the M, N standard. The tuning is available through built-in digitally controlled IýC bus (PLL). Features of UV1336: n Global standard pinning n Integrated Mixer-Oscillator&PLL function n Conforms to CISPR 13, FCC and DOC (Canada) regulations n Low power consumption n Both Phono connector and F connector are available PINNING 1. Gain control voltage 2. Tuning voltage 3. Address select 4. Serial clock 5. Serial data 6. Not connected 7. Supply voltage 8. ADC input (optional) 9. Tuning supply voltage 10.Ground 11. IF output PIN VALUE : 4.0V, Max:4.5V : Max:5.5V : Min:-0.3V, Max:5.5V : Min:-0.3V, Max:5.5V : 5.0V, Min:4.75V, Max:5.5V : 33V, Min:30V, Max:35V
SDA 9362 :
General Description: The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled line and standard or doubled field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All adjustable output parameters are I²C-BUS controlled. Inputs are HSYNC, VSYNC and the line locked clock CLL. Features: n I²C-Bus alignment of all deflection parameters n All EW- , V- and H- functions n PW EHT compensations n PH EHT compensations n Compensation of H-phase deviation (e.g. caused by white bar) n Upper / lover EW-corner correction separately adjustable n V-angle correction : Vertical frequent linear modulation of H-phase n V-bow correction : Vertical frequent parabolic modulation of H-phase n There reduced V-scan modes (75%, 66%, 50% V-size) selectable n H-and V-blanking time adjustable n Partial overscan adjustable to hide the cut off control measuring lines in the reduced scan modes n Stop / start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without annoying overscan n Dynamic PH EHT-compensation (white bar) n Self adaptation of V-frequency / number of lines per field between 192 and 680 for each possible line frequency n Protection againt EHT run away (X-rays protection) n Protection againt missing V-deflection (CRT-protection) n Two digital outputs for general purpose, controlled by I²C-Bus n Selectable softsart of the H-output stage n P-MQFP-44 package n 5 V supply voltage PINNING 1. Clock inputs 2. Reference oscillator input, Crystal 3. Reference oscillator input, Crystal 4. I²C-Bus data 5. I²C-Bus clock 6. H-sync input 7. Vertical blanking output 8. Blanking signal with H-and color burst component (V-component selectable by I²C-Bus) 9. Digital supply 10.Digital ground 11.Watching external V-output stage (Input is the V-sawtooth from feedback resistor)
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12.Watching EHT (input is e.g. H-flyback) 13.Analog supply 14.Output of an I²C-Bus controled switch (registor 00, bit D5) 15.Input for a beam current dependent signal for stabilization of width, height and H-phase 16.Analog ground 17.Reference voltage for IBEAM ADC, HPROT / VPROD theeshholds 18.Like VREFN 19.Analog supply 20.Control signal output for East-West raster correction 21.Control signal outout for DC coupled V-output stage 22.Like VD+ 23.Analog ground 24.Reference voltages for E / W-DAC, V-DAC 25.Like VREFL 26.Line flyback for H-delay compensation 27.Output of an I²C-Bus controlled switch (register 00, bit D3) 28.V-sync input 29.Control signal output for H driver stage 30.Switching normal operation (TEST=l) and test mode (TEST=H; pin 34 isa an additional test pin) 31.Test pin, to be grounded 32.Test pin, to be grounded 33.Defines the default value of HDE 34.Disables soft start (H) 35.Test pin, to be grounded 36.Test pin, dont connect 37.Test pin, dont connect 38.Digital supply 39.Digital ground 40.Test pin, dont connect 41.Analog ground 42.PLL loop filter 43.Analog supply 44.Reset input. active Low
MSP3410D
General Description: The MSP3410D is designed as a single-chip Multistandard Sound Procwssor for aplications in analog and digital TV sets, satellite receivers, video recorders, and PC-cards. As the successor of the MSP3410B and MSP3410C, the MSP 3410D combines all features of the two and adds several newfeatures. The MSP 3410D, again, improves function integration : The full TV sound prosessing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. It covers all European TV-Standards. The IC is produced in submicron CMOS technology, combined with high performance digital signal processing. The MSP3410D is available in PLCC68, PSDIP64, and in PSDIP52 package. Features: n 5-band graphic equalizer (as in MSP3400C) n Enhanced spatial affect (pseudostereo/basewidth enlargement as in MSP3400C) n Headphone channel with balance, bass treble, loudness n Balance for laudspeaker and headphone channels in dB units (optional) n Additional pair of D/A converters for SCART2 out n improved oversampling filters (as in MSP 3400C) n Additional SCART input n Full SCART in/out matrix without restrictions n Scart volume in dB units (optional) n Additional I²S input (as in MSP 3400C) n New FM-identification (as in MSP 3400C) n Demodulator short programming n Autodetection for terrestrial TV-sound standards n Precise bit-error rate indication n Automatic switch from NICAM to FM/AM or vice versa n Improved NICAM synchronization algorithm n Improved carrier mute algorithm n Improved AM-demoduþation n ADR together with DRP 3510A n Dolby Pro Logic together with DPL 35xx A n Reduction of necassary controlling n Less extemal components n Significant reduction of radiation 15
PINNING 1. ADR wordsttrobe 2. Not connected 3. ADR data output 4. I²S 1 data input 5. I²S data output 6. I²S wordstrobe 7. I²S clock 8. I²S data 9. I²S clock 10.Not connected 11. Standby (low-active) 12.I²C Bus address select 13.Digital control output 0 14.Digital control output 1 15.Not connected 16.Not connected 17.Not connected 18.Audio clock output 19.Not connected 20.Crystal oscillator 21.Crystal oscillator 22.Test Pin 23.IF input 2 (if ANA_IN1+is used only, connect to AVSS with 50 pF capacitor) 24.IF common 25.IF input 1 26.Analog power supply +5V 27.Analog ground 28.Mono input 29.Reference voltage IF A/D converter 30.Scart input 1 in, right 31.Scart input 1 in, left 32.Analog Shield Ground 2 33.Scart input 2 in, right 34.Scart input 2 in, left
35. Analog Sield Ground 1 36. Scart input 3 in right 37. Scart input 3 in left 38. Analog Shield Ground 4 39. Scart input 4 in, right 40. Scart input 4 in, left 41. Not connected 42. Analog reference voltage high voltage part 43. Analog ground 44. Volume capacitor MAIN 45. Analog power supply 8.0V 46. Volume capacitor AUX 47. Scart output 1, left 48. Scart output 1, right 49. Reference ground 1 high voltage part 50. Scart output 2, left 51. Scart output 2, right 52. Analog Shield Ground 3 53. Not connected 54. Not connected 55. Not connected 56. Analog output MAIN, left 57. Analog output MAIN, right 58. Reference ground 2 high voltage part 59. Analog output AUX, left 60. Analog output AUX, right 61. Power-on-reset 62. Not connected 63. Not connected 64. Not connected 65. I²S2-data input 66. Digital ground 67. Digital power supply +5V 68. ADR clock
TMS37600
General Description: The main function of the TEA6415 is to switch 8 video input sources on the 6 outputs. Each output can be switched to only one of the inputs whereas but any same input may be connected to several outputs. All switching possibilities are controlled through the I²C-bus. Features: n 20 MHz Bandwith
TEA6415:
General Description: The main function of the TEA6415 is to switch 8 video input sources on the 6 outputs. Each output can be switched to only one of the inputs whereas but any same input may be connected to several outputs. All switching possibilities are controlled through the I²C-bus. Features: n 20 MHz Bandwith n Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage) n 8 inputs (CVBS, RGB, Mac, CHROMA, ) n 6 Outputs n Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge n Bus controlled n 6.5dB gain between any input and output n -55dB crosstaljk at 5MHz n Fully ESD protected
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PINNING 1. Input 2. Data 3. Input 4. Clock 5. Input 6. Input 7. Prog 8. Input 9. Vcc 10.Input 11. Input 12.Ground 13.Output 14.Output 15.Output 16.Output 17.Output 18.Output 19.Ground 20.Input
PIN VALUE : Max : Low level : Max : Low level : Max : Max : : : : : : : : : : Max 12V Max Max 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp,
: 2Vpp, Input Current : -0.3V Max:1.5V, High level : 2Vpp, Input Current : -0.3V Max:1.5V, High level : 2Vpp, Input Current : 2Vpp, Input Current : 2Vpp, Input Current : 2Vpp, Input Current : 2Vpp, Input Current Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp
: 1mA, : 3.0V : 1mA, : 3.0V : 1mA, : 1mA, : 1mA, : 1mA, : 1mA,
Max Max Max Max Max Max
: 3mA : Vcc+0.5V : 3mA : Vcc+0.5V : 3mA : 3mA
Max : 3mA Max : 3mA Max : 3mA
: Max : 2Vpp, Input Current
: 1mA,
Max : 3mA
TEA 6420
General Description: The TEA 6420 switches 5 stereo audio inputs on 4 stereo outputs. All the switchingh possibilities are changen through the I²C-bus. Features: n 5 Stereo inputs n 4 Stereo outputs n Gain control 0/2/4/6dB mute for each output n Cascadable (2 different addresses) n Serial bus controlled n Very low noise n Very low distorsion
TDA1308
Features: n Wide temperature range n No switch ON/OFF clicks n Excellent power supply ripple rejection n Low power consumption n Short-circuit resistant n High performance - high signal-to-noise ratio - high slew rate - low distortion n Large output voltage swing PINNING 1. Output A (Voltage swing) 2. Inverting input A 3. Non-inverting input A 4. Ground 5. Non-inverting input B 6. Inverting input B 7. Output B (Voltage swing) 8. Positive supply : : : : : : : : PIN VALUE Min : 0.75V, Max : 4.25V Vo(clip) : Min : 1400mVrms 2.5V 0V 2.5V Vo(clip) : Min : 1400mVrms Min : 0.75V, Max : 4.25V 5V, Min : 3.0V, Max : 7.0V
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TDA6111Q
General Description: The TDA6111Q is a video output amplifier with 16MHz bandwidth. The device is contained in a single in-line 9-pin medium power (DBS9MPF) package, using high-voltage DMOS technology, intended to drive the cathode of a colour CRT. Features: n High bandwidth and slew rate n Black-current measurement output for Automatic Black-current Stabilization (ABS) n Two cathode outputs; one for DC currents, and one for transient currents n A feedback output seperated from the cathode outputs n Internal protection against positive appearing Cathode-Ray Tube (CRT) flashover discharges n ESD protection n Simple application with a variety of colour decoders n Differention input with a designed maximum common mode input capacitance of 3 pF, a maximum differential mode input capacitance of 0.5 pF and a differential input voltage temparature drift of 50 uV/K n Defined switch-off behaviour. PINNING 1. Non-inverting voltage input 2. Supply voltage LOW 3. I