27c512.pdf part of Holtek 27C512 27c512.rar, HT27C512 CMOS 64K8-Bit OTP EPROM text manual preview

Text preview for : 27c512.pdf part of Holtek 27C512 HT27C512 CMOS 64K8-Bit OTP EPROM

Back to : 27c512.rar | Home

HT27C512 CMOS 64K´8-Bit OTP EPROM
Features
· Operating voltage: +5.0V · Programming voltage - VPP=12.2V±0.2V - VCC=5.8V±0.2V · High-reliability CMOS technology · Latch-up immunity to 100mA from -1.0V to · 64K´8-bit organization · Fast read access time: 70ns · Fast programming algorithm · Programming time 75ms typ. · Two line control (OE & CE) · Standard product identification code · Commercial temperature range (0°C to +70°C) · 28-pin DIP/SOP, 32-pin PLCC package

VCC+1.0V
· CMOS and TTL compatible I/O · Low power consumption - Active: 30mA max. - Standby: 1mA typ.

General Description
The HT27C512 chip family is a low-power, 512K bit, +5V electrically one-time programmable (OTP) read-only memories (EPROM). Organized into 64K words with 8 bits per word, it features a fast single address location programming, typically at 75ms per byte. Any byte can be accessed in less than 70ns with respect to Spec. This eliminates the need for WAIT states in high-performance microprocessor systems. The HT27C512 has separate Output Enable (OE) and Chip Enable (CE) controls which eliminate bus contention issues.

Block Diagram

R o w A d d re s s C o lu m n A d d re s s C E O E /V P P

X -D e c o d e r

C e ll A r r a y V C C

Y -D e c o d e r

Y - G a tin g

V S S

C E & O E & P G M & T E S T C o n tr o l L o g ic

S A C K T & O u tp u t B u ffe r

D Q 0 ~ D Q 7

Rev. 1.40

1

December 8, 2003

HT27C512
Pin Assignment
A 1 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 A 1 2 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 D Q 0 D Q 1 D Q 2 V S S 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 V C C A 1 4 A 1 3 A 8 A 9 A 1 1 O E /V P P A 1 0 C E D Q 7 D Q 6 D Q 5 D Q 4 D Q 3
A 6 A 5 A 4 A 3 A 2 A 1 A 0 N C D Q 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 8 7 6 5 N C N C V C C A 1 3 A 1 4 V C C A 1 2 N C N C A 1 5 N A 1 A 1 A C 5 2 7 3 0 3 1 3 2 3 0 3 1 3 2 4 3 2 1 4 N C V S S D Q 2 D Q 1 3 2 1

2 9 2 8 2 7

A 8 A 9 A 1 1 N C O E /V P P A 1 0 C E D Q 7 D Q 6

A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 D Q 0 9 8 7 6

5

2 9 2 8 2 7

A 1 4 A 1 3 A 8 A 9 A 1 1 O E /V P P A 1 0 C E D Q 7

H T 2 7 C 5 1 2 3 2 P L C C -A

2 6 2 5 2 4 2 3 2 2 2 1

1 0 1 1 1 2 1 3 1 4

H T 2 7 C 5 1 2 3 2 P L C C -B

2 6 2 5 2 4 2 3 2 2 2 1

1 5

1 6

1 7

1 8

1 9 D Q 5

2 0 D Q 6

D Q 4 D Q 3 V S S D Q 2 D Q 1

D Q 5 D Q 4 D Q 3

H T 2 7 C 5 1 2 2 8 D IP -A /S O P -A

Pin Description
Pin Name A0~A15 DQ0~DQ7 CE OE/VPP NC VCC VSS I/O/P I I/O I I/P ¾ ¾ ¾ Address inputs Data inputs/outputs Chip enable Output enable/program voltage supply No connection Positive power supply Negative power supply, ground Description

Absolute Maximum Ratings
Operation Temperature Commercial ..........................................................................................................0°C to +70°C Storage Temperature.............................................................................................................................-65°C to 125 °C Applied VCC Voltage with Respect to VSS ................................................................................................-0.6V to 7.0V Applied Voltage on Input Pin with Respect to VSS .....................................................................................-0.6V to 7.0V Applied Voltage on Output Pin with Respect to VSS ......................................................................... -0.6V to VCC+0.5V Applied Voltage on A9 Pin with Respect to VSS ...................................................................................... -0.6V to 13.5V Applied VPP Voltage with Respect to VSS...............................................................................................-0.6V to 13.5V Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+4.5V to +5.5V Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.40

2

December 8, 2003

HT27C512
D.C. Characteristics
Symbol Read operation VOH VOL VIH VIL ILI ILO ICC ISB1 ISB2 IPP Output High Level Output Low Level Input High Level Input Low Level Input Leakage Current Output Leakage Current VCC Active Current Standby Current (CMOS) Standby Current (TTL) VPP Read/Standby Current 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V IOH=-0.4mA IOL=2.1mA ¾ ¾ VIN=0 to 5.5V VOUT=0 to 5.5V CE=VIL, f=5MHz, IOUT=0mA CE=VCC±0.3V CE=VIH CE=OE=VIL, VPP=VCC 2.4 ¾ 2.0 -0.3 -5 -10 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.0 ¾ ¾ ¾ 0.45 VCC+0.5 0.8 5 10 30 10 1.0 100 V V V V mA mA mA mA mA mA Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit

Programming operation VOH VOL VIH VIL ILI VH ICC IPP Output High Level Output Low Level Input High Level Input Low Level Input Load Current A9 Product ID Voltage VCC Supply Current VPP Supply Current 5.8V IOH=-0.4mA 5.8V IOL=2.1mA 5.8V 5.8V 5.8V VIN=VIL, VIH 5.8V 5.8V 5.8V CE=VIL ¾ ¾ ¾ ¾ 2.4 ¾ 0.7VCC -0.5 ¾ 11.5 ¾ ¾ ¾ ¾ ¾ ¾ ¾ -- ¾ ¾ ¾ 0.45 VCC+0.5 0.8 5.0 12.5 40 10 V V V V mA V mA mA

Capacitance CIN COUT CVPP Input Capacitance Output Capacitance VPP Capacitance 5V 5V 5V VIN=0V VOUT=0V VPP=0V ¾ ¾ ¾ 8 8 18 12 12 25 pF pF pF

Rev. 1.40

3

December 8, 2003

HT27C512
A.C. Characteristics
Symbol Read Operation tACC tCE tOE tDF tOH Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay CE or OE High to Output Float, Whichever Occurred First Output Hold from Address, CE or OE, Whichever Occurred First 5V 5V 5V 5V 5V CE=OE=VIL OE=VIL CE=VIL ¾ ¾ ¾ ¾ ¾ ¾ 0 ¾ ¾ ¾ ¾ ¾ 70 70 30 25 ¾ ns ns ns ns ns Parameter Test Conditions VCC Conditions Min. Typ. Ta=25°C±5°C Max. Unit

Programming Operation tAS tOES tOEH tDS tAH tDH tDFP tPW tVCS tDV tVR Address Setup Time CE/VPP Setup Time OE/VPP Hold Time Data Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay PGM Program Pulse Width VCC Setup Time Data Valid From CE OE/VPP Recovery Time 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V 5.8V ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Output Test Load
1 .3 V (1 N 9 1 4 ) 3 .3 k W O u tp u t P in C
L

2 2 2 2 0 2 0 30 2 ¾ 2

¾ ¾ ¾ ¾ ¾ ¾ ¾ 75 ¾ ¾ ¾

¾ ¾ ¾ ¾ ¾ ¾ 130 105 ¾ 150 ¾

ms ms ms ms ms ms ns ms ms ns ms

Test Waveforms and Measurements
2 .4 V A C D r iv in g L e v e ls 0 .4 5 V 2 .0 V 0 .8 V A C

M e a s u re m e n t L e v e l

tR, tF< 20ns (10% to 90%)

Note: CL=100pF including jig capacitance.

Rev. 1.40

4

December 8, 2003

HT27C512
Functional Description
Programming of the HT27C512 When the HT27C512 is delivered, the chip has all 512K bits in the ²ONE² or HIGH state. ²ZEROs² are loaded into the HT27C512 through the procedure of programming. The programming mode is entered when 12.2±0.2V is applied to the OE/VPP pin and CE is at VIL. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. The programming flowchart in Figure 3. shows the fast interactive programming algorithm. The interactive algorithm reduces programming time by using 30ms to 105ms programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached. This process is repeated while sequencing through each address of the HT27C512. This part of the programming algorithm is carried at VCC=5.8V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the final address is completed, the entire EPROM memory is read at VCC=VPP=5.25±0.25V to verify the entire memory. Program Inhibit Mode Programming of multiple HT27C512 in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE, all like inputs of the parallel HT27C512 may be common. A TTL low-level program pulse applied to an HT27C512 CE input with OE/VPP=12.2±0.2V will program that HT27C512. A high-level CE input inhibits the other HT27C512 from being programmed. Program Verify Mode Verification should be performed on the programmed bits to determine whether they were correctly programmed. The verification should be performed with OE/VPP and CE at VIL. Data should be verified at tDV after the falling edge of CE. Auto Product Identification The Auto Product Identification mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by the programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C±5°C ambient temperature range that is required when programming the HT27C512. To activate this mode, the programming equipment must force 12.0±0.5V on the address line A9 of the HT27C512. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH, when A1=VIH. All other address lines must be held at VIH during Auto Product Identification mode. Byte 0 (A0=VIL) represents the manufacturer code, and byte 1 (A0=VIH), the device code. For HT27C512, these two identifier bytes are shown in the Operation mode truth table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. When A1=VIL, the HT27C512 will read out the binary code of 7F, continuation code, to signify the unavailability of manufacturer ID codes. Read Mode The HT27C512 has two control functions, both of which must be logically satisfied in order to obtain data at outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time () is equal to the delay from CE to output (tCE). Data is available at the outputs (tOE) after the falling edge of OE, assuming the CE has been LOW and addresses have been stable for at least tACC-tOE. Standby Mode The HT27C512 has CMOS standby mode which reduces the maximum VCC current to 10mA. It is placed in CMOS standby when CE is at V C C ± 0.3V. The HT27C512 also has a TTL-standby mode which reduces the maximum VCC current to 1.0mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Two-line Output Control Function To accommodate multiple memory connections, a two-line control function is provided to allow for:
· Low memory power consumption · Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the primary device-selection function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.

Rev. 1.40

5

December 8, 2003

HT27C512
System Considerations During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1mF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Operation Mode Truth Table All the operation modes are shown in the table following. Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Product Inhibit Manufacturer Code (3) Device Type Code (3) CE VIL VIL VIH VCC± 0.3V VIL VIL VIH VIL VIL OE/VPP VIL VIH X X VPP VIL VPP VIL VIL A0 X (2) X X X X X X VIL VIH A9 X X X X X X X VH (1) VH (1) Output Dout High Z High Z High Z DIN DOUT High Z 1C 83 VCC and VPP to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7mF bulk electrolytic capacitor should be used between VCC and VPP for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

Notes: (1) VH=12.0V ± 0.5V (2) X=Either VIH or VIL (3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F

Product Identification Code
Code Manufacturer Device Type Continuation 1 0 0 1 1 1 1 1 1 1 7F Pins A0 0 1 0 A1 1 1 0 DQ7 0 1 0 DQ6 0 0 1 DQ5 0 0 1 DQ4 1 0 1 DQ3 1 0 1 DQ2 1 0 1 DQ1 0 1 1 DQ0 0 1 1 Hex Data 1C 83 7F

A d d re s s C E tC
E

A d d r e s s V a lid

tD
.

O E tA O u tp u t H IG H Z
C C

tO
E

tO
H

O u tp u t V a lid

Figure 1. A.C. Waveforms for Read Operation

Rev. 1.40

6

December 8, 2003

HT27C512
P ro g ra m A d d re s s V V V V 5 .8 V 5 .0 V tV O E /V P P 1 2 .2 V V
IL C S E S IH IL

R e a d ( V e r ify )

A d d r e s s S ta b le tA
S

tD
V

tA
H

D a ta

IH IL

D a ta In tD
S

D a ta O u t V a lid tD
H

V C C

tD

. P

tO

tO tP
R T

E H

C E

V V

IH IL

tV
R

tP
W

Figure 2. Programming Waveforms

S T A R T

A d d r e s s = . ir s t L o c a tio n

V

V

C C P P

= 5 .8 V = 1 2 .2 V

X = 0

In te r a c tiv e S e c tio n

P ro g ra m

O n e 7 5 m s P u ls e

In c re m e n t X

X = 2 5 ? N o . a il V e r ify B y te ? P a s s In c re m e n t A d d re s s N o L a s t A d d re s s Y e s V V e r ify S e c tio n
C C

Y e s

. a il

= 5 .2 5 V

V e r ify a ll B y te s ? P a s s D e v ic e P a s s e d

. a il

D e v ic e . a ile d

N o te : E ith e r 1 0 5 m s o r 3 0 m s p u ls e .

Figure 3. Fast Programming Flowchart Rev. 1.40 7 December 8, 2003

HT27C512
Package Information
28-pin DIP (600mil) Outline Dimensions
A 2 8 B 1 1 4 1 5

H C D E . G

a
I

Symbol A B C D E F G H I a

Dimensions in mil Min. 1445 535 145 125 16 50 ¾ 595 635 0° Nom. ¾ ¾ ¾ ¾ ¾ ¾ 100 ¾ ¾ ¾ Max. 1465 555 155 145 20 70 ¾ 615 670 15°

Rev. 1.40

8

December 8, 2003

HT27C512
28-pin SOP (300mil) Outline Dimensions

2 8 A

1 5 B

1

1 4

C C ' G H D E .

a

Symbol A B C C¢ D E F G H a

Dimensions in mil Min. 394 290 14 697 92 ¾ 4 32 4 0° Nom. ¾ ¾ ¾ ¾ ¾ 50 ¾ ¾ ¾ ¾ Max. 419 300 20 713 104 ¾ ¾ 38 12 10°

Rev. 1.40

9

December 8, 2003

HT27C512
32-pin PLCC Outline Dimensions

A 4 5 B 1 3 2 3 0 2 9

D C

1 3 1 4 2 0

2 1 K

E H I J G

.

Symbol A B C D E F G H I J K a

Dimensions in mil Min. 485 445 585 545 105 ¾ 15 ¾ 16 24 8 0° Nom. ¾ ¾ ¾ ¾ ¾ ¾ ¾ 50 ¾ ¾ ¾ ¾ Max. 495 455 595 555 115 140 ¾ ¾ 22 32 12 10°

Rev. 1.40

10

December 8, 2003

HT27C512
Product Tape and Reel Specifications
Reel Dimensions
T 2 D

A

B

C

T 1

SOP 28W (300mil) Symbol A B C D T1 T2 PLCC 32 Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330±1.0 62±1.5 13.0+0.5 -0.2 2.0±0.5 24.8+0.3 -0.2 30.2±0.2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330±1.0 62±1.5 13.0+0.5 -0.2 2.0±0.5 24.8+0.3 -0.2 30.2±0.2

Rev. 1.40

11

December 8, 2003

HT27C512
Carrier Tape Dimensions
D
E . W C

P 0

P 1
t

B 0

D 1

P

K 0 A 0

SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C PLCC 32 Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0±0.3 18.0±0.1 1.75±0.1 11.5±0.1 1.5+0.1 1.55+1.0 -0.05 4.0±0.1 2.0±0.1 13.1±0.1 15.5±0.1 3.9±0.1 0.30±0.05 21.3 Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0±0.3 12.0±0.1 1.75±0.1 11.5±0.1 1.5+0.1 1.5+0.25 4.0±0.1 2.0±0.1 10.85±0.1 18.34±0.1 2.97±0.1 0.35±0.01 21.3

Rev. 1.40

12

December 8, 2003

HT27C512

Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

Rev. 1.40

13

December 8, 2003