C1 COU R9 R1 R7 R3 R5 R 11 R 13 R 15 R 21 R 17 R 19 R 23 R 25 R 27 R 33 R 29 R31 R 37 R 39 R 35 R 41 R 43 R 45 R 47 TSR1 +19.2V (R49) C 3 COL C4 CEL ID1 ( R50)
3. Circuit Description 3.1 Main B'D 3.1.1 GENERAL DESCRIPTION Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-in RISC Processor Core : ARM7TDMI), system memory part, Image control part (CHORUS-2) controlling input of image received from media and conversion. The following nomenclatures by section is the same as those listed in the circuit diagram.
3.1.2 MEMORY MAP The entire Addressing area provided by MAIN CONTROLLER(S3C46Q0X) is 256MBytes from 0x00000000 to 0x10000000, and the Max. Address Range for each External Chip Select is 32M Byte or Half word from 0x000000 to 0x01FFFFFF and embodied with Big-Endian Bus interface. MEMORY area is divided into EXTERNAL ROM and RAM areas(See (Figure 1)), and the areas actually used are 2M/8M BYTES SDRAM and 1M BYTES ROM(FLASH MEMORY). In case of SDRAM0, it uses 0x0000000h ~ 0x01BFFFFFFh area.
CIRCUIT DESCRIPTION
3.1.3.1 BLOCK DIAGRAM and MAIN CONTROLLER description <1> General description MAIN CONTROLLER(S3C46Q0X,U12) consists of this system consists of CPU(ARM7TDMI RISC PROCESSOR), 8K BYTES CACHE, DATA and ADDRESS BUS, PLL deriding input frequency and CLOCK CONTROL part, SERIAL COMMUNICATION part supporting UART, PRINT HEAD control part, PARALLEL PORT INTERFACE part, USB INTERFACE part, Internal Image Processor Part, External DMA part MEMORY and EXTERNAL BANK control part, SYNCHRONOUS SERIAL INTERFACE control part for interfacing Quarter_Horse, and TX Motor drive control and general purpose I/O control parts.(See Figure 2 )
3.1.3.2 S3C46Q0X FUNCTION DESCRIPTION <1> SYSTEM CLOCK There are two ways of Clock input method. One is the method to make Master Clock(MCLK) at the internal PLL by connecting X-tal and Capacitor to the outside, and another method is to use MCLK(When inputting 40MHz) directly, which supplies maximum 40MHz Clock to the EXTCLK terminal(PIN65). The range of frequency being input in case of using X-tal is limited to 4MHz~10MHz. For making the MCLK, the Clock is supplied to the EXTCLK Terminal of the ASIC by sending output power (32.256MHz) of the MODEM (FM214 or FM214-VS, U16) XCLK via the RC Filter. The inner side of the ASIC takes the Clock, and it goes to the MPLL circuit to create a basic operating frequency (66MHz MCLK signal). Also the Clock goes to the UPLL circuit to make the operating frequency of the USB Controller (48MHz).
<2> DATA and ADDRESS BUS CONTROL 1. _RD & _WR _RD & _WR SIGNAL are synchronized with the inside MCLK(66MHZ) and becomes active to Low. These signal are Strobe Signal used to Read or Write data when each Chip Select becomes active connected to SDRAM, ROM(Flash), _WR PIN, _RD of Modem.
2. CHIP SELECT (_ROMCS, _IP_CS,_MED_CS,_SCS0,_SCS1) · _ROMCS : FLASH MEMORY(U7) CHIP SELECT (LOW ACTIVE) · _MODEM_CS : MODEM(U16) CHIP SELECT (LOW ACTIVE) · _SCSO : SDRAM (BASIC 16MBIT(U9), TAD 64MBIT(U8), CHIP SELECT (LOW ACTIVE) In case each Chip Select is low, it may Read or Write data. 3. D0 ~ D15 · 16BIT DATA BUS 4. A0 ~ A24 · ADDRESS BUS (A23 ~ A24 RESERVED)
<3> EXTERNAL DMA part This system does not use External DMA part.
<6> PARALLEL PORT INTERFACE division This system does not use Parallel Port Interface Division.
<4> DRAM control part Since S3C46Q0X has the DRAM CONTROLLER build-in, it may be used by connecting DRAM with external memory. The Control mode of DRAM CONTROLLER provided by S3C46Q0X is available for EARLY WRITE, NORMAL READ, PAGE MODE, and BYTE_HALF WORD ACCESS, and is supported even by EDO DRAM,and SDRAM as well as, Fast page DRAM. This system uses SDRAM, and the signal used for READ_WRITE uses _RD,_WR signal used for SYSTEM BUS CONTROL. It is supported with auto REFRESH and also by the Self-refresh mode for DRAM BACK UP. It consists of 2 Banks connected to common _SCSO, _SCAS, _SRAS, _SCLK, _SCKE, _DQM[1:0], each of them may use up to 2M ~ 32M HALF WORD. In this system, Basic 2MB (TAD 8MB) is applied as system memory. The area of DRAM is specified in the DRAM MEMORY MAP of Fig. 1, while the related TIMING DIAGRAM in Fig. 5, 6, 7, 8, 9.
<7> USB INTERFACE PART 1. USB function description As the mode of implementing low cost express PC Interface, USB was applied. At USB, PC plays the role of route hub simultaneously by existing in the highest level as the host. That is, the device supporting each USB is connected centering on PC. The device is available for Interface for the maximum of 127. USB cable is composed of total of a set of twisted pair and 2 power lines. The part for implementing USB function is included in S3C46Q0X. For Interface of USB, pull-up of 15K is interfaced to the data line of high level instruments, and, among data lines of lower level instruments, pull-up resistance of 1.5K is interfaced to any one. At this time, DP line is pulled up for Full Speed device, and, for Low Speed device, DMline is pulled up. For upper level instruments(Host, HUB) speed of device is classified interfaced to low level by detecting any one among DP and DM. If both lines are in the level of GND at the same time, device is judged that low device is not interfaced. In the transmission mode of USB, there are (1) Control transmission, (2) Interrupt transmission, (3) Bulk transmission, isochronous transmission. Control transmission is for Host to find out configuration information from USB device. This is conducted when device is interfaced. Interrupt transmission is used when small quantity of data is sent periodically. Interval value may be known from device in the case of initial setting. Bulk transmission is valid in case of trying to transmit data in large quantities or in case of transmitting them accurately. Isochronous transmission should be assured of bandwidth, and is used when transmitting large quantities of information. Data in voice is used where delay is not allowed but small error is allowed. At USB coding mode and bit supping are being conducted. First, in case original data is 1, bit shall not change, and only when original data is 001, it shall be inverted. Only while data is 1, 1 and 0 shall be repeated. Also, in case 1, original data, is continued in 6 bit, 0 shall be inserted, Also, in the 1st phase of packet, data in the synchronized pattern shall be sent. About more detailed information regarding USB, see http//:www.usb.org.
<5> RTC (REAL TIME CLOCK) part S3C46Q0X real time clock (RTC) operates by the super capacitor although the system power turns off. In case of the Basic, the backup is operated with the primary battery (CR2032), and in case of the TAD, the backup is operated with the secondary battery (Super-cap). The RTC has the time data that is stored as the 8 bit BCD (binary coded decimal) format. The data include second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 kHz crystal and also can perform the alarm function and round reset function.
CIRCUIT DESCRIPTION
2. operation description This system, when Host and USB cables are connected, and when +5V is detected in power detector inside chip and Vbus, 3.3V comes out through Pull-uP terminal. This is also connected to DP in pattern of hardware and supports Full-speed. Utilizing Configuration Endpoint, EPO, in USB controller, Plug & Play function is operated. Exchange of information between PCs is accomplished through DP and DM erminals. This terminal decides transmission speed depending on connection of regulator output in USB controller, and decides size of signal following USB and SPFC. Signal of general DP and DM terminals are same as Figure 10-3.
< Figure 10-3. USB Signal Line DIAGRAM >
<8> HEAD Control Part 1. General Information It drives the Inkjet Head, and it controls the HA[3:0] and _STB[5:0], which control the Six-Shooter. The Six-shooter creates the signal to drive 48 Nozzle of the HEAD. The Stubby Head in the system is the Bubble type head, and has 48 nozzle for the Mono and Color(Printer only). 48 Nozzle Head of the mono and color head receives the data by 6 bytes per1 slice. The data from the HDMA goes to the CDE (Consecutive Dot Eliminator), DITH, and Data Out Block, and the data and address, controlled by the Fire signal and the Fire Window Time of the CRCON_CRFIRE Block, are outputted to the head Driver (Six-Shooter). The head consists of the 4 firing groups. Each group has 12~14 nozzles, and only one nozzle is firing per a Fire in each group. It means that one Fire can make 4 nozzles firing.
< Figure 12. Print48(HP) Firing Timing >
CIRCUIT DESCRIPTION
2. HEAD DATA OUTPUT FORMAT The 1 slice data [47:0] from the HDMA is outputted with the PHADR in order as below.
<9> SYNCHRONOUS SERIAL INTERFACE PART It interfaces with Quarter-horse ASIC and consists of SMIC, SMID, PWM, and _RST. The Quarter-horse is the Motor Driver IC. The Quarter-horse interface Logic makes the data as a serial for transmitting the data to the Quarter-horse, and transmits the serial to the Quarter-horse IC by controlling it with the arranged Protocol. The Quarter-horse uses two signals, SMIC (clock) and SMID (data) to transmit the data. It transmits 3 bytes at once, and the 3 bytes mean the Device Address, Data 1, and Data 2. It is transmitted from MSB to LSB. The Quarterhorse sends the ACK signal at the end of the each byte to confirm the transmitted data. In case of no receiving ACK signal, the Quarter-horse_interface Logic sends the 3 bytes again. Depending on the level of the SMIC and SMID signals, the different messages are shown.
If it is high (SMIC) and high (SMID), it means the IDLE condition which means no data is received, if it is high (SMIC) and high-to-low-transition (SMID), it means the data transfer is started, and if it is high (SMIC) and low-tohigh-transition (SMID), it means the last data transfer.
CIRCUIT DESCRIPTION
While transferring the motor phase, if there is NAK, the data transfer is automatically stopped and being in the IDLE condition. In the case, The S/W makes new value to transfer the data, or if the NAK Enable of the Control Register is set, automatically the same value is transferred for data transfer after for a while.Quarter-horse controls two Stepper motors (Line Feeder and Service Station) and one DC Motor (Carriage Motor).
<10> MOTOR Control Part S3C46Q0X supports two Step Motors and one DC Motor, but only TX Scan Motor is used in the system. The Quarter-horse supports LF, SS, and CR MOTOR.
<11> S3C46QOX General Purpose I/O Port. 1. 1 Chorus-2 Assigned GCS Ports for RHINE
CIRCUIT DESCRIPTION
2. Chorus-2 Assigned GPO Ports for RHINE
CIRCUIT DESCRIPTION
3. Chorus-2 Assigned GPI Ports for RHINE
4. Chorus-2 Assigned GPIO Ports for RHINE
CIRCUIT DESCRIPTION
5. HP IMPORTANT ASIC Ports for RHINE
CIRCUIT DESCRIPTION
3.1.3.3 RESET circuit This system is configured with PRIMARY RESET(_RST) of Power Reset, Reset by WATCH DOG TIMER, external PRIMARY RESET, and SECOND RESET(__F_POR) which was done AND. PRIMARY RESET SYSTEM is used for resetting MAIN CONTROLLER(U12) when System Power is authorized, and SECOND RESET resets FLASH MEMORY(U7). Figure below is BLOCK DIAGRAM related to the reset of entire system. When +5V reaches +4.75V so that system may operate, POWER MONITOR(U2) moves to High(+5V) after maintaining low(OV) in the degree of 50mS-200mS output while monitoring it. This Reset signal is input into MFP CONTROLLER(S3C46Q0X, U12) right away, and MFP CONTROLLER becomes awake. And it releases _F_POR after MCLK 1 clock. The Quarter-horse needs +24V to be operated, but +5.0V is supplied by the Buck Regulator circuit. If +5.0V is incompletely supplied such as +4.75V, it is checked as the Power Failure. The _RST output becomes low (0V), and the S3C46Q0X (U12) confirms it to make it RESET (LOW ACTIVE). When the S3C46Q0X is released from RESET, the _F_POR of the S3C46Q0X and FLASH MEMORY are reset.
<1> WATCH DOG OUTPUT (_F_POR) Since WATCH DOG TIMER, which is Programmable Counter in (S3C46Q0X, U12) is set as disable for INITIAL STATE, it shall be set as Disable so that it won't operate, and after it is initialized for operation, it shall be reused by setting it Enable. When Watch Dog Reset occurs, it is about 10mS depending on the value set at the initial stage. And Counter value of Watch Dog Timer is changed by the program. Reset signal (_F_POR,U12-94) shall be generated, and entire system shall be Reset and initialized.
_RST
< Figure 13. POWER RESET BLOCK DIAGRAM >
CIRCUIT DESCRIPTION
3.1.4 MEMORY 3.1.4.1 General description MEMORY applied in this system are FLASH MEMORY(U7) of 1Mbyte, SDRAM (SF-330/331P:U9 ; 2Mbyte ,/ SF-335T : U8 ; 8Mbyte)
3.1.4.2 MEMORY configuration By each CHIP SELECT ( ROM_CS, _SCS0, _SD_RAS ,_SD_CAS ), FLASH MEMORY and SDRAM are selected, and DATA is accessed by HALF WORD unit.
3.1.5 Image Processing Part 3.1.5.1 General description The image processor, built-in to Chorus-2 is consisted of Scanner Interface, Motor control, Shading Acquisition _ Shading Correction, Gamma Correction, Vertical Decimation, Horizontal Enlargement/Decimation and Binarization. (See Figure 16)
3.1.5.2 Features & Functions · 0.18µm CMOS process, 208-pin QFP, std 130 library · Frequency : 66MHz(15ns) · Image Sensor I/F : 200/300/600dpi CIS or CCD · Scanning Function - Color Gray Image : each 8 bits / RGB - Mono Gray Image : 8 bits / pixel
· Ideal MSLT (Minimum Scan Line Time) - Grey mode(Color) : 3(RGB) X 5KB X 15nsec X 16clock =3.69 msec - Grey mode(mono) : 1 - Grey mode(Color) : 1 X 5KB X 15nsec X 16clock =1.23 msec X 5KB X 15nsec X 16clock =1.23 msec
· A/D conversion depth : 10 bits
CIRCUIT DESCRIPTION
3.1.5.3 Block Diagram
CIRCUIT DESCRIPTION
3.1.6 QUARTERHORSE ASIC 3.1.6.1 General Information The Quarter-horse ASIC consists of the Serial Interface port which interfaces with the main controller, Linear Pre-regulator Circuit, Power On Reset Generation Circuit, and Motor Drive part.
<1> SERIAL INTERFACE It interfaces with the Main Controller (S3C46Q0X), and consists of SMIC, SMID, PWM, and _RST. Please, refer to the picture 17 for the timing.
< Figure 17. SERIAL INTERFACE INPUT timing diagram>
CIRCUIT DESCRIPTION
<2> SERIAL INTERFACE PIN NAME preg Vin DCMA DCMB DCPWM nPA nPnA nPB nPnB +12V nSA nSnA nSB nSnB DATA SCLK GATE1 SOURCE1 Vfb COMP1 SWITCH COMP5 +5V Vdd CP1 CP2 Ground nRESET Enable CT SPWMA SPWMB Vp GND (11) DESCRIPTION Pre-regulator control DC motor driver and 5V regulator input supply voltage DC motor drive half bridge A DC motor drive half bridge B PWM input signal Paper motor phase A drive Paper motor phase nA drive Paper motor phase B drive Paper motor phase nB drive +12V EEPROM programming voltage Service station motor phase A drive Service station motor phase nA drive Service station motor phase B drive Service station motor phase nB drive Serial Data Input (and ACK output) Serial Clock Input V1 gate drive V1 source voltage return V1 return to close loop V1 compensation pin +5V switching output +5V compensation pin +5V input for logic and to close loop Input Voltage Bootstrap capacitor pin 1 Bootstrap capacitor pin 2 Ground Active low totem pole reset output Chip Enable Reset timing delay capacitor Stepper motor pwm phase A/nA Stepper motor pwm phase B/nB Boost voltage output for high side FETs Used both as ground and as heatsinking DIRECTION / TYPE analog/output power/input power/bidirectional power/bidirectional CMOS/input power/open drain power/open-drain power/open drain power/open drain output power/open drain power/open drain power/open drain power/open drain CMOS/input CMOS/input power/output analog/input analog/input analog power/output analog analog/input power/input analog analog analog CMOS/output CMOS/input analog CMOS/input CMOS/input power/output analog
CIRCUIT DESCRIPTION
3.1.6.2 QUARTERHORSE FUNCTION <1> PEN / MOTOR SUPPLY VOLTAGE REGULATOR It receives the inputted power of +24V, and the power flows to the buck type regulator, which consists of the external N-channel FET and SCHOTTKY diode, to make +19.2V. The power uses as the main power of the ink head, CR, and LF, SS MOTOR.
<2> +5V REGULATOR The +24V (inputted power) is supplied, and it becomes +5V of the logic power by using the internal switching FET Buck type regulator. It becomes +3.3V to support the main power of the CPU by using external +3.3V Regulator, and the +3.3V becomes +1.8V to support the internal power of the CPU by using +1.8 Regulator.
<3> RESET CIRCUIT The Reset of the Quarter-horse starts to work when the +5V is going down under +4.75V. It has the 1.5~5 usec of Sensitivity Timing Margin for preventing the minute shakiness of the power by ESD. Also, the Time Delay of the Reset can be controlled from 1ms to 1s by the Capacitor when power on.
<4> MOTOR DRIVERS The Quarter-horse drives one DC Motor and two stepping motors. The DC Motor drives +19.2V as the FULL H-BRIDGE, and the direction information goes to the CPU via the Serial Interface port. Also, it is inputted the PWM Modulator from CPU. The Stepping Motor is driven by the UNIPOLAR, and the phase information is transmitted to the CPU via the Serial Interface port.
1. DC MOTOR TRUTH TABLE DCA 0 0 0 1 1 1 DCB 0 1 1 0 0 1 PWM X 0 1 0 1 X A high side off on off on on on A low side on off on off off off B high side off on on on off on B low side on off off off on off
CIRCUIT DESCRIPTION
2. STEPPER MOTOR TRUTH TABLES Inputs Whinny Register Bits PPWM 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 pa (pb) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 pna (pnb) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin 38 (37) SPWMA (SPWMB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputs Pin 35(31) nPA (nPB) off off off off on on off off off off on off off on off off Pin 33(29) nPnA (nPnB) off off on on off off off off off off off on on off off off
Inputs Whinny Register Bits PPWM 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 sa (sb) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 sna (snb) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin 38 (37) SPWMA (SPWMB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputs Pin 36(32) nSA (nSB) off off on off off on off off off off off off on on off off Pin 34(30) nSnA (nSnB) off off off on on off off off off off on on off off off off
CIRCUIT DESCRIPTION
<5> Quarterhorse Block Diagram
CIRCUIT DESCRIPTION
3.1.6 SIXSHOOTOR ASIC 3.1.6.1 General Information The Six-shooter ASIC exists for operating the Ballast Resistor and TIJ 2.0 Inkjet Head, and it has 4 head address HA [3-0], input of the 6 strobe nSTB [5-0], and output of the 48 nozzle control.
3.1.6.2 OPERATE TIMING AND INTERNAL BLOCK DIAGRAM
CIRCUIT DESCRIPTION
3.1.6.3 Decoder Logic Truth Table nCS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HA3 X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X X X 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 HA2 X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X HA1 X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 HA0 X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 nSTRB5 nSTRB4 X X 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X nSTRB3 X 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X nSTRB2 nSTRB1 X X 1 1 X X X X X X X X X X X X X X X X X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X nSTRB0 X 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X nRx None None R26 R4 R6 R8 R10 R12 R14 R16 R36 R38 R40 R42 R44 R46 R48 R2 R24 R30 R32 R34 R18 R20 R22 R28 R25 R3 R5 R7 R9 R11 R13 R15 R35 R37 R39 R41 R43 R45 R47 R1 R27 R33 R19 R29 R21 R31 R17 R23
CIRCUIT DESCRIPTION
3.1.6.4 Power Driver Output Loading Schematic
CIRCUIT DESCRIPTION
3.1.7 ERTE ASIC 3.1.7.1 General Information The ERTE ASIC is driven by 19.2V, and consists of three functional blocks, such as the Head, the Pen ID which find out the kind of head by checking temperature and resistance difference when firing, and the Resistor Test which checks the possibility of the head firing.
3.1.7.2 ERTE Block Diagram
CIRCUIT DESCRIPTION
3.1.8 FAX SENDING/RECEIVING PART 3.1.8.1 General Information The circuit is for managing the transmitting signals of Modem and between the LIU part and Modem.
3.1.8.2 MODEM There are two models, FM214 for the Basic model and FM 214-VS for the TAD model, which supports the Digital TAD and Speaker Phone. The Main PCB is designed for joint use in the Rhine. The modem has the single chip fax modem function and DTMF detection/DTMF signal generation function. The principal ports of the FM214 modem are as follows when using TAD Model. The LineOut (PIN69) is a port of the sending output from the modem, and the LineIn (PIN60) is a receiving input port. The Modem_RST (PIN115) is the signal from the CPU for initializing modem without system power off.D0~D7 are Data Bus, and RS0~RS4 is the signal for internal Register Selection of modem to decide mode. _MCS (PIN 91) is a signal of the Modem Chip, and _RD (PIN 92) and _WR (PIN 90) are control signals for a reading and writing. IRQ (PIN 108) is a signal for the Modem Interrupt Output. The transmitting speed of the FM214 is Maximum 14.4k bps.
3.1.8.3 SENDING PART The circuit manages the sending output, which is analog signal of the modem.The output signal by each mode comes out from the modem lineout (PIN69), and it is sent out to PSTN telephone line via the Matching Transformer (600:600) of the LIU B'd.
3.1.8.4 RECEIVING PART The analog signal from the Matching Transformer (600:600) of the LIU B'd is amplified at the LIU PBA, and the second amplification is at the main input part for inputting the signal in the LINEIN (PIN60) of receiving input part.
3.1.8.5 MIC INPUT PART (Not for the SF330 Basic Model) SF335T Model has the Speaker Phone function and Tad function. For recording OGM and supporting a Speaker phone, MIC is needed. The first amplified signal at the OPE goes to the main and makes the second amplification. After that, it is inputted in the MIC (PIN61, 35) of modem.
CIRCUIT DESCRIPTION
3.1.8.6 FM214 MODEM BLOCK DIAGRAM
3.1.8.7 FM214-VS MODEM BLOCK DIAGRAM
CIRCUIT DESCRIPTION
3.1.8.8 FM214 SERIES MODEM PIN DESCRIPTION
CIRCUIT DESCRIPTION
3.2 OPE 3.2.1 Basic Concept 3.2.1.1 Overview OPE BOARD is separated from the Main Board functionally, and operates entire Micom(HT48C5A-000Z) in the Board. OPE and Main exchange mutual information using UART(universal asynchronous receiver/transmitter) channel. Also, Resetting of OPE is designed to control at the Main. Micom in OPE performs key-scanning and LCD, LED display control, and senses document detect, Scan position and so on. When information is generated from OPE(key touch, sensor level change, etc.), it sends specific code coping with the situation to Main, and the Main operates system by analyzing this code. If the Main tries to display data on OPE, the Main sends data to OPE via UART line on the basis of the format specified, and OPE displays it to LCD. In the case of the TAD Model, the MIC for the Speaker Phone and OGM and the Pre-Amp part of the MIC have built-in at OPE circuit.
3.2.1.2 UART OPE and MAIN exchange information mutually by using asynchronous communication mode(UART), and in full duplex. Band rate is 9600bps, and uses 7.37MHz resonator as oscillating element. It engages in communication with 8bit data without parity bit. UART line has two lines for Tx and Rx, and the default level is in the 'high' state. For communication, the start bit(low level) is transmitted before 8bit data. When the data transmission(8bit) is completed, the high state is maintained as the stop bit(high level) is transmitted. Data is transmitted from LSB(DO), and MSB(D7) is transmitted lastly.
3.2.2 UART Operation 3.2.2.1 UART Communication <1> UART TX FORMAT Codes for change of KEY, TOUCH, SENSOR LEVEL and so on are transmitted in single code without PRE/POST DATA, and OK or Error messages to check if communication is performed properly are also transmitted in single code. Provided that, in case the Main requested a certain value(LCD, other register) particularly, data requested is transmitted followed by sending Post Data('EOH') first.
<2> UART RX FORMAT Data being received will be arranged to be received according to the following specified format to know what data they are. a) b) Type of data received Number of data (N+1) received after.
---------c) DATA(N) ---------d) D0 start bit D1 D2 D3 D4 D5 D6 D7 stop bit data 8bit (D0 ~ D7)
Check sum(1)
DATA are received in the sequence of A,B,C, and D, and the Check sum to check if the transmission is made properly will be found by doing XOR data from A to C.
CIRCUIT DESCRIPTION
3.2.2.2 UART communication DATA <1> UART transmission DATA(received by the Main side) Types key data STATUS ON OFF SCAN POSITION sensor ON OFF DOC. detector sensor ON OFF For initial use of initial OPE UART communication OK ERR LCD interface of OPE OK ERR Self initial generation of OPE Send data requested by the Main LCD data keeps status quo Data types:LCD, other(Note 3) When failed in the interface once & when succeeded first(Note 2) PORT PB-5 PORT PB3 USED PORT PORT PC0~PORT PC7 LEVEL L H H L L H After power on, generated only once (Note 2) MAGIC not applied MAGIC not applied REMARKS
1. After this, keep waiting until there is response from the Main. 2. The case of longer time(longer than 10ms) elapsed longer than waiting time required for Interface is regarded as fail. 3. After this code went out, then data requested it goes out.
CIRCUIT DESCRIPTION
<2> Received DATA(transmitted by MAIN) 1. DATA TYPE DATA types a1 H a4 H LED DATA Meaning LCD DISPLAY DATA(FULL LINE) Remarks
2. NO. OF DATA · In case DATA is N BYTE, N+1
3. DATA In case DATA TYPE is LCD DATA, it is configured with ASCII CODE to be displayed. In case DATA TYPE is LED DATA, it is 1 BYTE. · LED DATA BIT ASSIGNMENT : DATA BIT LED NO. BIT 0 LED 0 Answer LED BIT 1 LED 1 Ink Save LED BIT 2 LED 2 Silent Mode LED BIT 3 LED 3 BIT 4 LED 4 BIT 5 LED 5 not used BIT 6 LED 6 BIT 7 LED 7
4. CHECK SUM The value done XOR all of them from DATA TYPE to DATA.
CIRCUIT DESCRIPTION
3.2.3 I/O PORT configuration and use usage It has 32 I/O Ports, and 24 Ports of them are arranged to decide I/O direction with Software Control, and the rest 8 Ports are arranged to be used for Input or Output only. All of I/O Ports are classified into four Blocks according to the characteristics of I/O Control, and each Block consists of 8 Ports. Type PA X PB X PC X PD X I/O Control Byte Control Byte Control Byte Control Byte Control I/O direction I/O => Output In : 4, Out : 4 I/O => Input I/O => Output USE LED Control UART, LCD, Sensor Key Input LCD Data, Key Scan Remarks Used as LCD VCCCONTROL in MAGIC. MAGIC SENSOR not applied.
<1> Assignment of Port PAX · PA1 · PA2 · PA3 · PA4 · PA5 · PA6 · PA7 : ANSWER LED (RED) : INK_SAVE LED (GREEN) : NIGHT_MODE LED (GREEN) : RESERVED : SRESERVED : RESERVED : RESERVED * HIGH --> LED OFF LOW --> LED ON
<2> Assignment of port PBX · PB0(Output) · PB1(Output) · PB2(Output) · PB3(Input) · PB4(Input) · PB5(Input) · PB6(Output) · PB7(Input) : LCD Enable : LCD R/W : LCD RS : GND : Unused (Pull-up) : GND : UART TXD in Main UART : UART RXD from Main UART
LCD ON/OFF In case of VCC applied to LCD No. 3 PIN (BACKGROUND LEVEL), all the LCD screen will be erased. When the power is applied, MICOM PA0~7 are Default High LEVEL, so LCD will be OFF. From Jupiter3, LCD will be ON simultaneously with OPE reset. Q1, Q2 have the function of simply doing On/off only. When pressing the Power Key, actual power is not turned Off but 11.75V terminal of Thundervolt Off in the Main, while simply the LCD DISPLAY should not appear in OPE. At this point, Micom should be operated normally to recognize the Key when pressing the Power key again. [The same effect as Power save]
CIRCUIT DESCRIPTION
3.3 LIU B'd 3.3.1 GENERAL DESCRIPTION LIU ( Line interface unit ) is consist of Tel-line interface part and FAX/Speech part.
<1> TEL LINE INTERFACE PART · Surge and over voltage protection part · Remote circuit · Ring detector circuit · Ext phone detector circuit · DCR and Impedance matching circuit
1. Surge and over voltage protection circuit. · ARR1 component is the protection of lightning surge. ( Spec : 400V ± 20% , 500A ) · VAR2 is a varistor that decrease over voltage noise. ( Spec : 82V , 1250A) TIP ARR1 RING
Dode
VAR2
· Over 400V of high voltage is decreased by ARR1 and the rest voltage · (low voltage : 400V under level) is decreased by VAR2.
2. Remote circuit · C8, R13 use for DC coupling / On-hook impedance. · Over voltage is depressed by ZD component · DTMF Detector path for Local start ( SF-330/331P ) · Caller ID Signal path Trans 100-1016 ZD2 R6 30k Remote
C8 15nF, 250V Line R13 30k
C4 1nF
CIRCUIT DESCRIPTION
3. Ring detector circuit · C9 use for DC coupling and Ring impedance ( Ring impedance spec : Min 4Kohm) · R1 ( 1/ 1W )protect overvoltage into PC814. · Ring signal transfer from 1st circuit to 2nd circuit through PC814 · R2/C1 translator to recognize for ring signal.
4. Ext hook detector circuit · SF-330/331P model have Ext-phone jack to connect TAM or external phone. · VAR1 protect overvoltage into PC814. · R7 is marching component of Ext phone for detect another normal phone.
R7
5. DCR / Current limit circuit / impedance · DCR / Current limit circuit consist of R25, C13, Q2, Q3, R21, R23, R14. · Current limit circuit apply only EU nation.( Q3, R21 ) · Impedance circuit consist of T2, C26, R43, R41, C35.
<2> Fax / Speech part · Fax TX / RX circuit · Speech part ( Handset MIC / RECEIVE )
1. FAX TX / RX circuit · DTMF / OGM (335T) and Fax tone transmit from Modem tx part impedance matching part (R43, C35, R4) T1 trans tel-line. · Dial tone / ICM ( 335T ) and Fax tone transmit form tel-line T1 trans Modem rx part.