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Repair Manual
Digital Laser MFP
SCX-5315F/SCX-5115
CONTENTS
1. Block Diagram 2. Connection Diagram 3. Circuit Description 4. Schematic Diagrams
This manual is made and described centering around circuit diagram and circuit description needed in the repair center in the form of appendix.
Samsung Electronics Digital Printing CS Group
Copyright (c) 2003. 07
- This Service Manual is a property of Samsung Electronics Co.,Ltd. Any unauthorized use of Manual can be punished under applicable International and/or domestic law. -
Block Diagrams
1. Block Diagrams
T M H V DEV SUPPLY BLADE
MAIN
LCD 1 6 x 2 line
H V
SPGPm
Backup logic ARM946ES
2 4P
OPE MICOM - LCD Drive - Key Scan
5P
SMPS / HVPS
+5V/+24V/+12V/+24Vs/Fuser
SRAM Flash,Kernel
(1MB) X 2EA
CACHE(16K*2) SDRAMC ROMC DMAC PVC GEU/HCT/gCODEC
SDRAM,16MB
MOTOR DRIVER
A3977SLR
8P
MOTOR 1 MOTOR 2
PLATEN
15P D-SUB
11P 2P 3P
LSU THERMISTOR FAN DEV_ID TONER_TX TONER_RX PTL SOLENOID
PICK_UP,DUPLEX,MP
D-SUB CONN.
24P
Option
SDRAM DIMM
I/O I/F Engine Control IEEE1284/USB2.0 Extended GPIO
3P 3P 4P
FLAT MOTOR
16MB
Option
2P
ADF
MOTOR DRIVER
ADF MOTOR PAPER SENSOR
POS,DET 3P x 2EA
NETWORK KIT NETWORK I/F(NetONE)
74LCX245
2P x 3EA
74HCT273
3P x 2EA 6P x 1EA
CIP4
Image Processer
4P
PAPER SENSOR
FEED+P.EMP,EXIT,MP
COVER OPEN S/W
+24V / +5V
FAST SRAM
(1Mb it)
AFE I/F I/O PORT Motor CNTR
Option
MODEM
33.6Kbps
1
4P
TRANSFORMER
600//600 Tx:Rx
MOTOR DRIVER AFE
Network I/F CENTRONICS CABLE USB CABLE
2 2P
MODEM & EXT_PHONE SEPERATING PART
LIU
LINE1
DMAC
LIN E IN T ERF A CE
EXTERNAL PHONE INTERFACE PART
Option
CCD MODULE External Auditron
EXTERNAL PHONE
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1-1
Connection Diagrams
2. Connection Diagrams
T H M H V DEV SUPPLY BLADE
L CD 20x2line
SCA N
CN 2
2 4P
V
OPE
MI COM - LCD Drive - Key Scan
CN 1 6
CN8
SMPS / HVPS
+5V/+24V/+12V/+24Vs /Fuser
CN6
Network CARD
Fl as h DIMM PS3 (2MB) CN15(100P) SDRAM DIMM
CN 1 4 CN 3 3 CN 4 CN 7 C N1 0 CN 1 1
1 0P 8P 11P 2P 3P
5P
CENTRONICS CABLE
SCF OU T BIN F ULL PC N T
DEV MOTOR FEED MOTOR LSU THERMISTOR FAN1
36 P
CN 3 1
Plat en
15P D -SUB
8P
16MB C N15(10 0P)
CN 1 2 CN 1 9 CN 2 5
D-SUB CONN.
4P 2P
FLAT MOTOR
HYPER DEV CN T OPC
4P
MAIN PBA
3P 3P
FAN1 DEV_ID
CN 1 8
CN 1 9 CN 1 7
4P
Option
3P
CN 2 3 CN 2 1 CN 2 6 CN 2 9
2P 4P
TONER_T X
4P 2P
ADF
MOTOR DRIVER
DADF MOTOR
PAPER SENSOR
POS,DET
CN 1 3 CN 5
USB CABLE
TONER_RX PTL COVER OPEN S/W
+24V / +5V
2 2P
CN 1
CN 2 2 CN 2 0 CN 2 7 CN 3 0 CN 28 CN 3 CN 24
4P
10P
3P x 2EA
CCD MODULE
External Auditron
3P 2P 2P 2P
3P
6P 14P
TRANSFORMER
600/ / 600 Tx: R x
MODEM EXT_PHONE SEPRATING PART
LI U
LINE1
LIN E
SOLENOID
PICK_ UP,DUPL EX,MP
PAPER SEN SOR
FEED+P.EMP,EXIT,MP
IN T ERFAC E
EXTERNAL PHONE INTERFACE PART
EXTERNAL PHONE
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2-1
Circuit Description
3. Circuit Description
3-1 Main PBA
3-1-1 Summary
The main circuit that consists of CPU, MFP controller (built-in 32bit RISC processor core: ARM946ES) including various I/O device drivers, system memory, scanner, printer, motor driver, PC I/F, and FAX transceiver controls the whole system. The entire structure of the main circuit is as follows :
T H
M H V
DEV SUPPLY BLADE
LCD 20x2line
SCAN
CN2
24P
CN6
V
OPE
MICOM - LCD Drive - Key Scan
CN 1 6
CN8
SMPS / HVPS
+5V/+24V/+12V/+24Vs/Fuser
Network CARD
Flash DIMM PS3 (2MB) CN15(100P) SDRAM DIMM
CN 1 4
10P 8P 11P 2P 3P
5P
CENTRONICS CABLE
SCF OUT BIN FULL PCNT
DEV MOTOR FEED MOTOR LSU THERMISTOR FAN1
36P
CN 3 3 CN 4
CN 3 1
Platen
15P D-SUB
8P
16MB CN15(100P)
CN 7
CN 1 2
D-SUB CONN.
4P 2P
C N1 0 CN 1 1
CN 1 9 CN 2 5
FLAT MOTOR
HYPER DEV CNT OPC
4P
MAIN PBA
3P 3P
FAN1 DEV_ID
CN 1 8
CN 1 9 CN 1 7
4P
Option
3P
CN 2 3
2P 4P
TONER_TX
4P 2P
CN 2 1
ADF
MOTOR DRIVER
DADF MOTOR
PAPER SENSOR
POS,DET
CN 1 3
USB CABLE
TONER_RX PTL COVER OPEN S/W
+24V / +5V
CN 2 6
22P
CN1
CN 5
CN 2 9
CN22 CN20 CN27 CN30 CN28 CN3 CN24
4P
10P
3P x 2EA
CCD MODULE
External Auditron
3P 2P 2P 2P
3P
6P 14P
TRANSFORMER
600/ / 600 Tx: Rx
MODEM EXT_PHONE SEPRATING PART
LIU
LINE1
LINE
SOLENOID
PICK_UP,DUPLEX,MP
PAPER SENSOR
FEED+P.EMP,EXIT,MP
INT ERFACE
EXTERNAL PHONE INTERFACE PART
EXTERNAL PHONE
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3-1
Circuit Description
3-2 Circuit Operation
3-2-1 Clock
1) System Clock Device Frequency Oscillator 12MHz
· ARM946ES RISC PROCESSOR: drives PLL internally uses 120MHz and external Bus uses 60 MHz.
2) Video Clock Device Frequency Oscillator 57.0167MHz
· Fvd =((PAPER 1SCAN LINE sending time * SCAN effective late /1SCAN LINE DOT #)*4 =(600dpi*600dpi*58.208mm/s*216mm*4)/(25.4mm*25.4mm*76.1%)=28.697MHz ·PAPER 1SCAN LINE sending time=SCAN LINE interval/DOCUMENT SPEED (58.208mm/S) ·1SCAN LINE DOT #=MAZ SCAN distance(216mm)*DOT# per 1mm
3)USB Clock Device Frequency Oscillator 48MHz
3-2-2 POWER ON/OFF RESET
1) Signal Operation Input Signal Output Signal
+3.3V Power Line (VCC) ARM946ES nRESET and 29LU16ø · POWER ON/OFF DETECT VCC RISING/FALLING 4.5°4.6V 1.48~1.52ms · Td=(Ct*V sensing)/I charge (...Ct=33µF, Is=100µA)
RESET TIME (Td)
2) TIMING CHART
MCLK nRESET 20 MCLK nPWRGD HICLK reRESETn 5.461 ms RESETn 15 HCLK (65535 MCLK) CLK falling 20 MCLK 5.461 ms (65535 MCLK)
3-2
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Samsung Electronics
Circuit Description
3-2-3 RISC MICROPROCESSOR
1) RISC MICROCESSOR PIN & INTERFACE(SPGPm)
Ball No B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 G4 F2 F1 G3 G2 G1 H3 H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 N3 P1 P2 R1 P3 Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name SD15 VSS_PLL1 VDD_PLL1 DATA0 / GPI1 MCLK DATA6 / GPI7 DATA1 / GPI2 DATA5 / GPI6 VDD_RING_OSC DATA3 / GPI4 DATA9 / GPI10 GND DATA8 / GPI9 DATA7 / GPI8 DATA12 / GPI13 DATA11 / GPI12 DATA10 / GPI11 DATA4 / GPI5 DATA15 / GPI16 DATA14 / GPI15 VDD_CORE DATA19 DATA18 DATA17 DATA16 DATA22 DATA13 / GPI14 DATA20 DATA21 DATA25 DATA26 DATA23 DATA24 DATA29 DATA30 DATA27 DATA28 VDD_ARM DATA31 DATA2 / GPI3 VDD_CORE nROMCS2 I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Description SDRAM Bus Data[15] VSS for Core PLL VDD for Core PLL (1.8V) ROM Bus Data[0] / GPI[1] Core PLL Clock Input (12MHz) ROM Bus Data[6] / GPI[7] ROM Bus Data[1] / GPI[2] ROM Bus Data[5] / GPI[6] VDD for Ring Oscillator (1.8V) ROM Bus Data[3] / GPI[4] ROM Bus Data[9] / GPI[10] GROUND_RING ROM Bus Data[8] / GPI[9] ROM Bus Data[7] / GPI[8] ROM Bus Data[12] / GPI[13] ROM Bus Data[11] / GPI[12] ROM Bus Data[10] / GPI[11] ROM Bus Data[4] / GPI[5] ROM Bus Data[15] / GPI[16] ROM Bus Data[14] / GPI[15] VDD for CORE (1.8V) ROM Bus Data[19] ROM Bus Data[18] ROM Bus Data[17] ROM Bus Data[16] ROM Bus Data[22] ROM Bus Data[14] / GPI[14] ROM Bus Data[20] ROM Bus Data[21] ROM Bus Data[25] ROM Bus Data[26] ROM Bus Data[23] ROM Bus Data[24] ROM Bus Data[29] ROM Bus Data[30] ROM Bus Data[27] ROM Bus Data[28] VDD for ARM ROM Bus Data[31] ROM Bus Data[2] / GPI[3] VDD for CORE (1.8V) ROM Bank2 Select_n PAD BD8TARP_TC BD8TRP_FT TLCHT_TC BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT BD8TRP_FT B4TR_TC
Samsung Electronics
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3-3
Circuit Description
Ball No R2 T1 P4 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 W2 Y1 W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 U7 W6 Y6 V7 W7 Y7 V8 W8 Y8 U9 V9 W9 Y9 W10 3-4
Pin No 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Pin Name nRD nROMCS0 nROMCS3 / nIOCS3 / GPO1 nWR nROMCS1 ADDR12 ADDR10 ADDR13 ADDR15 ADDR11 ADDR14 ADDR16 ADDR19 ADDR17 ADDR20 nIOCS0 ADDR21 nIOCS1 ADDR22 ADDR18 ADDR7 VDD_CORE nIOCS2 / nDACK0 / GPO2 ADDR1 ADDR8 ADDR9 ADDR4 ADDR6 ADDR2 ADDR3 ADDR5 VDD_ARM VDD_CORE EINT0 / TnRST EINT1 / TCK EINT2 / nRXD2 / TMS EINT3 / nTXD2 / GPO9 nRxD0 nRxD1 / GPI17 / TDI nTxD0 TESTMODE
I/O O O O O O O O O O O O O I/O I/O I/O O I/O O I/O I/O O O O O O O O O O O O I I I I/O I I O I
Description ROM Bus Read_n ROM Bank0 Select_n ROM Bank3 Select_n / IO Bank3 Select_n / GPO[1] ROM Bus Write_n ROM Bank1 Select_n ROM Bus Addr[12] ROM Bus Addr[10] ROM Bus Addr[13] ROM Bus Addr[15] ROM Bus Addr[11] ROM Bus Addr[14] ROM Bus Addr[16] ROM Bus Addr[19] ROM Bus Addr[17] ROM Bus Addr[20] IO Bank0 Select_n ROM Bus Addr[21] IO Bank1 Select_n ROM Bus Addr[22] ROM Bus Addr[18] ROM Bus Addr[7] VDD for CORE (1.8V) IO Bank2 Select_n / DMA IO Bank0 ACK_n / GPO[2] ROM Bus Addr[1] ROM Bus Addr[8] ROM Bus Addr[9] ROM Bus Addr[4] ROM Bus Addr[6] ROM Bus Addr[2] ROM Bus Addr[3] ROM Bus Addr[5] VDD for ARM Hard Macro(1.8V) VDD for CORE (1.8V) Ext. Interrupt0 / TAP Controller Reset_n Ext. Interrupt1 / TAP Controller Clock Ext. Interrupt2 / UART RX DATA[2] / TAP Controller Mode Select Ext. Interrupt3 / UART TX Data[2] / GPO[9] UART RX Data[0] UART RX Data[1] / GPI[17] / TAP Controller Data In UART TX Data[0] TESTMODE (Nomal : 0)
PAD B4TR_TC B4TR_TC B4TR_TC B4TR_TC B4TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC BD8TRP_TC BD8TRP_TC BD8TRP_TC B4TR_TC BD8TRP_TC B4TR_TC BD8TRP_TC BD8TRP_TC B8TR_TC B4TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC B8TR_TC SCHMITT_FT SCHMITT_FT SCHMITT_FT BD4STRP_FT SCHMITT_FT SCHMITT_FT B4TR_TC SCHMITT_TC
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Circuit Description
Ball No V10 Y10 Y11 W11 V11 U11 Y12 W12 V12 U12 Y13 W13 V13 Y14 W14 Y15 V14 W15 Y16 U14 V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 Y20 W20 V19 U19 U18 T17 V20 U20 T18 T19
Pin No 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Pin Name nTxD1 / GPO10 / TDO TESTSE VDD_CORE RXERR / GPI25 GND RX_DV / GPI20 RXD0 / GPI21 nLFPHB1 / nPRINT nLFPHB0 / nCMSG nLFPHA0 / CCLK RXD1 / GPI22 VDO SPD / nDREQ3 nWAIT1 / CRS COL / EINT4 TX_EN MDIO TXD3 / GPO14 TXD2 / GPO13 MDC / GPO15 TXCLK / GPI18 TXD1 / GPO12 PD4 TXD0 / nIOCS3 RXD3 / GPI24 PD2 PD6 RXD2 PWMOUT2 VCLK RXCLK / GPI19 PD1 nINIT VSS_ADC ATEST_OUT AIN2 AIN1 AIN0 VDD_ADC VDD_CORE GND VDD_CORE
I/O O I I O O O O O I O I/O I I O I/O O O O I O I/O O I I/O I/O I O I I I/O I O I I I -
Description UART Tx Data[1] / GPO[10] / Tap Controller Data Out TESTSE (Normal : 0) VDD for CORE (1.8V) MAC RX Error / GPI[25] GROUND_RING MAC RX Data Valid / GPI[20] MAC RX Data[0] / GPI[21] Motor Out B_n / Print Start_n Motor Out B / Command Message_n Motor Out A / Communication Clock MAC RX Data[1] / GPI[22] Video Data Out DIMM Detect / DMA REQ[3]_n Wait_n / MAC Carrier Sensor MAC Collision Detect / Ext. Interrupt4 MAC TX Enable MAC Management Data Inout MAC TX Data[3] / GPO[14] MAC TX Data[2] / GPO[13] MAC Management Data Clock / GPO[15] MAC TX Clock(25MHz) / GPI[18] MAC TX Data[1] / GPO[12] Parallel Port Data[4] MAC TX Data[0] / IO Bank3 Select_n MAC RX Data[3] / GPI[24] Parallel Port Data[2] Parallel Port Data[6] MAC RX Data[2] / GPI[23] PWM Output[2] Video Reference Clock MAC RX Clock(25MHz) / GPI[19] Parallel Port Data[1] Parallel Port Initialization_n VSS for ADC ADC Test Output ADC Channel2 Input ADC Channel1 Input ADC Channel0 Input Analog power for ADC (3.3V) VDD for CORE (1.8V) GROUND_RING VDD for CORE (1.8V)
PAD B4TR_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC SCHMITT_TC B4TR_TC B4TR_TC B4TR_TC SCHMITT_TC B8TR_TC BD4SRTP_TC SCHMITT_TC SCHMITT_TC B4TR_TC BD4STRUQP_TC B4TR_TC B4TR_TC B4TR_TC SCHMITT_TC B4TR_TC BD4STRP_FT B4TR_TC SCHMITT_TC BD4STRP_FT BD4STRP_FT SCHMITT_TC B4TR_TC TLCHT_TC SCHMITT_TC BD4STRP_FT SCHMITT_FT ANA_TC ANA_TC ANA_TC ANA_TC -
Samsung Electronics
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3-5
Circuit Description
Ball No T20 R18 P17 R19 R20 P18 P19 P20 N18 N19 N20 M17 M18 M19 M20 L19 L18 L20 K20 K19 K18 K17 J20 J19 J18 J17 H20 H19 H18 G20 G19 F20 G18 F19 E20 G17 F18 E19
Pin No 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
Pin Name VDD_CORE VBUS nLREADY / nEBSY nSELECTIN LSUCLK / nCBSY / GPO11 PD7 PWMOUT1 PWMOUT0 nEMSG / nDACK3 / PWMOUT3 nFSYNC / nLFPHA1 nHSYNC nSTROBE PD5 nWAIT0 / PDE nIOCS5 / nSCS4 / GPO3 / TONEOUT PD3 nFAULT nDREQ0 / GPI0 / ADDR23 nRESET PERROR nAUTOFD nDACK2 / DQM7 / GPO5 nDREQ2 / DQM6 / GPO6 nDREQ1 / DQM4 / GPO8 VDD_CORE nSCS0 nSCS2 nCAS nSCS1 nIOCS4 / nSCS3 / GPO4 BUSY PD0 SLCT_OUT nACK nDACK1 / DQM5 / GPO7 nRSTOUT / CLKOUT / GPO0 SA7 SA9
I/O I I I O I/O O O I/O I/O I I I/O I/O O I/O O I/O I O I O I/O I/O O O O O O O I/O O O O O O O
Description VDD for CORE (1.8V) USB Detect LSU Ready_n / Engine Busy_n Parallel Port Select Input_n LSU Clock / Command Busy_n / GPO[11] Parallel Port Data[7] PWM Output[1] PWM Output[0] Engine Message_n / DMA ACK[3]_n / PWM Output[3] Frame Sync_n / Motor Out A_n Line Sync_n Parallel Port Data Strobe_n Parallel Port Data[5] Wait_n / Parallel Port Data Enable DRAM Bank4 / IO Bank5 Select_n / GPO[3] / Tone Pulse Out Parallel Port Data[3] Parallel Port Fault_n DMA REQ[0]_n / GPI[0] / ADDR[23] External Reset_n Input Parallel Port Paper Error Parallel Port Auto Feed_n DMA ACK[2]_n / DQM[7] / GPO[5] DMA REQ[2]_n / DQM[6] / GPO[6] DMA REQ[1]_n / DQM[4] / GPO[8] VDD for CORE (1.8V) SDRAM Bank0 Select_n SDRAM Bank2 Select_n SDRAM Column Address Select_n SDRAM Bank1 Select_n IO Bank4 / SDRAM Bank3 Select_n / GPO[4] Parallel Port Busy Parallel Port Data[0] Parallel Port Selection Out Parallel Port Acknowledge_n DMA ACK[1]_n / DQM[5] / GPO[7] Internal Reset_n Out / Internal System Clock Out / GPO[0] SDRAM Bus Addr[7] SDRAM Bus Addr[9]
PAD SCHMITT_FT SCHMITT_FT SCHMITT_FT B4TR_TC BD4STRP_FT B4TR_TC B4TR_TC BD4STRP_FT BD4STRP_FT SCHMITT_FT SCHMITT_FT BD4STRP_FT BD4STRP_TC BD8TARP_TC BD4STRP_FT B4TR_TC BD4STRP_TC SCHMITT_TC B4TR_TC SCHMITT_FT BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC B4TR_TC BD4STRP_FT B4TR_TC B4TR_TC BD8TARP_TC B8TR_TC BD8TARP_TC BD8TARP_TC
3-6
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Samsung Electronics
Circuit Description
Ball No D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 A19 B18 B17 C17 D16 A18 A17 C16 B16 A16 C15 D14 B15 A15 C14 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 C10 D10 A9 B9
Pin No 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
Pin Name VDD_USB SA10 SA12 BA0 nRAS DQM2 DQM1 BA1 DQM0 DQM3 RREF VSSL VDDL VSSB DMNS DPLS VDD3_USB VSSC VDDC VDDB VDD_USB UCLK VSS_PLL2 VDD_PLL2 SA11 SA6 SA5 SA8 SA3 SA2 SA4 SA0 SA1 CKE nWE SD30 SD31 SD29 SD25 SD26 SD27 SD28 SD21 SD22
I/O O O O O O O O O O I/O I/O I/O I O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description VDD for USB Hard Macro (1.8V) SDRAM Bus Addr[10] SDRAM Bus Addr[120 SDRAM Bus Bank Select Addr[0] SDRAM Row Address Select_n SDRAM Bus DQM[2] SDRAM Bus DQM[1] SDRAM Bus Bank Select Addr[1] SDRAM Bus DQM[0] SDRAM Bus DQM[3] USB PHY Register Reference VSS for Deserialisation Flip flops VDD for Deserialisation Flip flops (1.8V) VSS for buffers USB2 DATAUSB2 DATA+ VDD for USB1.1 FS compliance (3.3V) VSS for DLL and Xor tree VDD for DLL and Xor tree (1.8V) VDD for buffers (1.8V) VDD for USB Hard Macro (1.8V) USB PLL Input Clock (12MHz) VSS for USB PLL VSS for USB PLL (1.8V) SDRAM Bus Addr[11] SDRAM Bus Addr[6] SDRAM Bus Addr[5] SDRAM Bus Addr[8] SDRAM Bus Addr[3] SDRAM Bus Addr[2] SDRAM Bus Addr[4] SDRAM Bus Addr[0] SDRAM Bus Addr[1] SDRAM Clock Enable SDRAM Write Enable_n SDRAM Bus Data[30] SDRAM Bus Data[31] SDRAM Bus Data[29] SDRAM Bus Data[25] SDRAM Bus Data[26] SDRAM Bus Data[27] SDRAM Bus Data[28] SDRAM Bus Data[21] SDRAM Bus Data[22]
PAD BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC ANA_FT ANA_FT ANA_FT TLCHT_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC
Samsung Electronics
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3-7
Circuit Description
Ball No C9 D9 A8 B8 C8 A7 B7 A6 C7 B6 A5 D7 C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 A2 C3
Pin No 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231
Pin Name SD23 SD24 SD18 SDCLK0 SD20 SD14 SD19 SD11 SD16 SDCLK1 SD12 SD17 SD13 SD8 SD5 SD9 SD6 SD3 SD10 SD7 SD4 SD1 SD0 SD2
I/O I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description SDRAM Bus Data[23] SDRAM Bus Data[24] SDRAM Bus Data[18] SDRAM Clock Output0 SDRAM Bus Data[20] SDRAM Bus Data[14] SDRAM Bus Data[19] SDRAM Bus Data[11] SDRAM Bus Data[16] SDRAM Clock Output1 SDRAM Bus Data[12] SDRAM Bus Data[17] SDRAM Bus Data[13] SDRAM Bus Data[8] SDRAM Bus Data[5] SDRAM Bus Data[9] SDRAM Bus Data[6] SDRAM Bus Data[3] SDRAM Bus Data[10] SDRAM Bus Data[7] SDRAM Bus Data[4] SDRAM Bus Data[1] SDRAM Bus Data[0] SDRAM Bus Data[2]
PAD BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC BD8TARP_TC
3-8
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Samsung Electronics
Circuit Description
2) RISC MICROCESSOR PIN & INTERFACE(CIP4)
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin Name GND2 NTEST TM TEST1 GND17 TEST2 XDACK1 XDREQ1 VDD1 XDACK2 XDREQ2 XDACK3 XDREQ3 nRESET CLK_OUT GND3 XP XPOUT GNDD16 FILTER* GND1 VDDA9,VDDD9 GND24,GND33 RTC_XO RTC_XI VDD8,VDD18 IRQ nCS GND4 nRD nWR BA1 BA0 GND19 A5 A4 A3 VDD2 A2 A1 A0 GND5 D31 I/O P I I I P I I O P I O I O I O P I O P O P P P O I P O I P I I I I P I I I P I I I P B Description Vss Supply Nand Tree Test Mode Selection Global Test Mode Selection Test Mode Selection 1 Vss Supply Test Mode Selection 2 DMA Acknowledge Signal 1 DMA Request Signal 1 Vdd Supply DMA Acknowledge Signal 2 DMA Request Signal 2 DMA Acknowledge Signal 3 DMA Request Signal 3 Global Reset PLL Clock Out Vss Supply Clock Oscillation Input Clock Oscillation Output Vss Supply PLL Filter Pump Out Vss Supply Vdd Supply Vss Supply RTC Clock Oscillation Output RTC Clock Oscillation Input Vdd Supply Interrupt Request Signal CIP4 Chip Select Vss Supply CIP4 CPU Read Control CIP4 CPU Write Control Bank Address Bus [1] Bank Address Bus [0] Vss Supply CPU Address Bus [5] CPU Address Bus [4] CPU Address Bus [3] Vdd Supply CPU Address Bus [2] CPU Address Bus [1] CPU Address Bus [0] Vss Supply CPU Data Bus [31] Pad Type vss2i pticd pticd pticd vss3op pticd ptis phob4 vdd2i ptis phob4 ptis phob4 ptis phob12 vss2i phsoscm26 phsoscm26 vss2t_abb poar50_abb vbb_abb vdd2t_abb vss3t_abb poar50_abb piar50_abb vdd3t_abb phob4 ptis vss2i ptis ptis ptis ptis vss3op ptis ptis ptis vdd2i ptis ptis ptis vss2i phbst8 Current drive 4mA 4mA 4mA 12mA 10~40MHz 10~40MHz 4mA 8mA
Samsung Electronics
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3-9
Circuit Description
No 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pin Name D30 D29 D28 GND20 D27 D26 D25 VDD11 D24 D23 D22 D21 GND6 D20 D19 D18 GND21 D17 D16 D15 D14 VDD3 D13 D12 D11 GND7 D10 D9 D8 D7 GND22 D6 D5 D4 VDD12 D3 D2 D1 D0 GND8 TX_EN1 TX_EN2 TX_A TX_B GND23
I/O B B B P B B B P B B B B P B B B P B B B B P B B B P B B B B P B B B P B B B B P O O O O P
Description CPU Data Bus [30] CPU Data Bus [29] CPU Data Bus [28] Vss Supply CPU Data Bus [27] CPU Data Bus [26] CPU Data Bus [25] Vdd Supply CPU Data Bus [24] CPU Data Bus [23] CPU Data Bus [22] CPU Data Bus [21] Vss Supply CPU Data Bus [20] CPU Data Bus [19] CPU Data Bus [18] Vss Supply CPU Data Bus [17] CPU Data Bus [16] CPU Data Bus [15] CPU Data Bus [14] Vdd Supply CPU Data Bus [13] CPU Data Bus [12] CPU Data Bus [11] Vss Supply CPU Data Bus [10] CPU Data Bus [9] CPU Data Bus [8] CPU Data Bus [7] Vss Supply CPU Data Bus [6] CPU Data Bus [5] CPU Data Bus [4] Vdd Supply CPU Data Bus [3] CPU Data Bus [2] CPU Data Bus [1] CPU Data Bus [0] Vss Supply Motor Control Tx Enable 1 Motor Control Tx Enable 2 Motor Control Tx Channel A Motor Control Tx Channel B Vss Supply
Pad Type phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 vdd3op phbst8 phbst8 phbst8 phbst8 vss2i phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 phbst8 vdd2i phbst8 phbst8 phbst8 vss2i phbst8 phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 vdd3op phbst8 phbst8 phbst8 phbst8 vss2i phob4 phob4 phob4 phob4 vss3op
Current drive 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 4mA 4mA 4mA 4mA -
3-10
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Samsung Electronics
Circuit Description
No 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133
Pin Name nTX_A nTX_B MOTOR_POL VDD4 PItg1 PI1 PI2 GND9 PIrs PIcp ADC_CLK VDD13 CDS2_CLK SCLK1 SLOAD1 VDD10 SDO1 SDIO1 SDIO2 GND10 AFE_D9 AFE_D8 AFE_D7 AFE_D6 VDD5 AFE_D5 AFE_D4 AFE_D3 GND25 AFE_D2 AFE_D1 AFE_D0 GND11 SRAM_A15 SRAM_A14 SRAM_A13 SRAM_A12 VDD14 SRAM_A11 SRAM_A10 SRAM_A9 GND26 SRAM_A8 SRAM_A7 SRAM_A6
I/O O O I P O O O P O O O P O O O P O B B P I I I I P I I I P I I I P O O O O P O O O P O O O
Description Motor Control Tx Channel A Motor Control Tx Channel A Motor Polarity Vdd Supply CIS/CCD PItg1 Signal CIS/CCD PI1 Signal CIS/CCD PI2 Signal Vss Supply CIS/CCD PIrs Signal CIS/CCD PIsh Signal AFE ADC Clock Vdd Supply AFE CDS2 Clock AFE SIO Sync. Clock AFE SIO Read/Write Control Signal Vdd Supply AFE SIO Serial Output 1 AFE SIO Serial Inout/Output 1 AFE SIO Serial Inout/Output 2 Vss Supply A/D Converted Data Bus [9] A/D Converted Data Bus [8] A/D Converted Data Bus [7] A/D Converted Data Bus [6] Vdd Supply A/D Converted Data Bus [5] A/D Converted Data Bus [4] A/D Converted Data Bus [3] Vss Supply A/D Converted Data Bus [2] A/D Converted Data Bus [1] A/D Converted Data Bus [0] Vss Supply SRAM Address Bus [15] SRAM Address Bus [14] SRAM Address Bus [13] SRAM Address Bus [12] Vdd Supply SRAM Address Bus [11] SRAM Address Bus [10] SRAM Address Bus [9] Vss Supply SRAM Address Bus [9] SRAM Address Bus [9] SRAM Address Bus [9]
Pad Type phob4 phob4 ptis vdd2i phob8 phob8 phob8 vss2i phob8 phob8 phob8 vdd3op phob8 phob8 phob8 vdd3op phob8 phbst8 phbst8 vss2i ptis ptis ptis ptis vdd2i ptis ptis ptis vss3op ptis ptis ptis vss2i phob8 phob8 phob8 phob8 vdd3op phob8 phob8 phob8 vss3op phob8 phob8 phob8
Current drive 4mA 4mA 4mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA
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3-11
Circuit Description
No 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 3-12
Pin Name SRAM_A5 GND12 SRAM_A4 SRAM_A3 SRAM_A2 SRAM_A1 VDD6 SRAM_A0 SRAM_nWR SRAM_D15 SRAM_D14 GND27 SRAM_D13 SRAM_D12 SRAM_D11 GND13 SRAM_D10 SRAM_D9 SRAM_D8 SRAM_D7 VDD15 SRAM_D6 SRAM_D5 SRAM_D4 GND28 SRAM_D3 SRAM_D2 SRAM_D1 SRAM_D0 GND14 GPO7/PItg2 GPO6/RLED GPO5/GLED GPO4/BLED VDD7 GPO3/PItg3 GPO2/PIsh GPO1/ LEVEL_SHIFT GPO0 GND29 GPIO2B/AFE_D11 GPIO2A/AFE_D10 GPIO29/AFE_D9 GND30 GPIO28/AFE_D8
I/O O P O O O O P O O B B P B B B P B B B B P B B B P B B B B P O O O O P O O O O P B B B P B
Description SRAM Address Bus [9] Vss Supply SRAM Address Bus [9] SRAM Address Bus [9] SRAM Address Bus [9] SRAM Address Bus [9] Vdd Supply SRAM Address Bus [9] SRAM Write Enable Signal SRAM Data Bus [15] SRAM Data Bus [14] Vss Supply SRAM Data Bus [13] SRAM Data Bus [12] SRAM Data Bus [11] Vss Supply SRAM Data Bus [10] SRAM Data Bus [9] SRAM Data Bus [8] SRAM Data Bus [7] Vdd Supply SRAM Data Bus [6] SRAM Data Bus [5] SRAM Data Bus [4] Vss Supply SRAM Data Bus [3] SRAM Data Bus [2] SRAM Data Bus [1] SRAM Data Bus [0] Vss Supply General Purpose Output [7] General Purpose Output [6] General Purpose Output [5] General Purpose Output [4] Vdd Supply General Purpose Output [3] General Purpose Output [2] General Purpose Output [1] General Purpose Output [0] Vss Supply General Purpose Input/Output 2 [11] General Purpose Input/Output 2 [10] General Purpose Input/Output 2 [9] Vss Supply General Purpose Input/Output 2 [8]
Pad Type phob8 vss2i phob8 phob8 phob8 phob8 vdd2i phob8 phob8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 vss2i phbst8 phbst8 phbst8 phbst8 vdd3op phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 phbst8 vss2i phob8 phob8 phob8 phob8 vdd2i phob8 phob8 phob8 phob8 vss3op phbst8 phbst8 phbst8 vss3op phbst8
Current drive 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA
Samsung Electronics
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Circuit Description
No 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin Name GPIO27/AFE_D7 GPIO26/AFE_D6 GPIO25/AFE_D5 VDD16 GPIO24/AFE_D4 GPIO23/AFE_D3 GPIO22/AFE_D2 GND15 GPIO21/AFE_D1 GPIO20/AFE_D0 GPIO1F/ SRAM_D15 GPIO1E/ SRAM_D14 GND31 GPIO1D/ SRAM_D13 GPIO1C/ SRAM_D12 GPIO1B/ SRAM_D11 GPIO1A/ SRAM_D10 VDD17 GPIO19/SRAM_D9 GPIO18/SRAM_D8 GPIO17/SRAM_D7 GND32 GPIO16/SRAM_D6 GPIO15/SRAM_D5 GPIO14/SRAM_D4 GPIO13/SRAM_D3 GND18 GPIO12/SRAM_D2 GPIO11/SRAM_D1 GPIO10/SRAM_D0
I/O B B B P B B B P B B B B P B B B B P B B B P B B B B P B B B
Description General Purpose Input/Output 2 [7] General Purpose Input/Output 2 [6] General Purpose Input/Output 2 [5] Vdd Supply General Purpose Input/Output 2 [4] General Purpose Input/Output 2 [3] General Purpose Input/Output 2 [2] Vss Supply General Purpose Input/Output 2 [1] General Purpose Input/Output 2 [0] General Purpose Input/Output 1 [15] General Purpose Input/Output 1 [14] Vss Supply General Purpose Input/Output 1 [13] General Purpose Input/Output 1 [12] General Purpose Input/Output 1 [11] General Purpose Input/Output 1 [10] Vdd Supply General Purpose Input/Output 1 [9] General Purpose Input/Output 1 [8] General Purpose Input/Output 1 [7] Vss Supply General Purpose Input/Output 1 [6] General Purpose Input/Output 1 [5 General Purpose Input/Output 1 [4] General Purpose Input/Output 1 [3] Vss Supply General Purpose Input/Output 1 [2] General Purpose Input/Output 1 [1] General Purpose Input/Output 1 [0]
Pad Type phbst8 phbst8 phbst8 vdd3op phbst8 phbst8 phbst8 vss2i phbst8 phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 phbst8 vdd3op phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8 phbst8 vss3op phbst8 phbst8 phbst8
Current drive 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 4mA -
-
Samsung Electronics
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3-13
Circuit Description
3-2-4 PROGRAM ROM (FLASH MEMORY) CONTROL
1) DEVICE TYPE No. CAPACITY 2) PROGRAMMING BEFORE ASS'Y AFTER ASS'Y EPROM PROGRAMMER or PROGRAMMING at the factory DOWNLOAD from PC AM29LV160DB 4 MBYTE (1MB * 16BITS * 2)
3) OPERATING PRINCIPLE When the RCSO(ROM CHIP SELECT)signal is activated from the CPU after the POWER is ON, it activates RD SIGNAL and reads the DATA(HIGH/LOW) stored in the FLASH MEMORY to control the overall system. The FLASH MEMORY may also write. When turning the power on, press and hold the key(power switch) for 2 - 3 seconds, then the LED will scroll and the PROGRAM DOWNLOAD MODE will be activated. In this mode, you can download the program through the parallel port.
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC
Read Status Data (last two cycles)
Addresses
555h
P A
P A
P A
tAH
CE# OE#
tWP
tCH
tWHWH1
WE#
tCS
tWPH
tDS
tDH PD
tBUSY
Data
A0h
Status
DOUT
tRB
RY/BY#
tVCS
VCC
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
CE# The falling edge of the last WE# signal WE#
BYTE
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16.
BYTE# Timings for Write Operations
3-14
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Samsung Electronics
Circuit Description
3-2-5 DRAM CONTROL
1) DEVICE TYPE NO. CAPACITY K4S 16MBYTES (1M * 16BITS * 4Bank * 2)
2) OPERATING PRINCIPLE DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores data white the CPU processes data. The address to read and write the data is specified by RAS SIGNAL and CAS SIGNAL. DRAMWE*SIGNAL is activated when writing data and DRAMOE*SIGNAL, when reading. You can expand up to 64MBYTE of DRAM in this system. Start Address ~ End Address 0x00000000 ~ 0x00FFFFFF 0x01000000 ~ 0x01FFFFFF 0x02000000 ~ 0x02FFFFFF 0x03000000 ~ 0x03FFFFFF 0x04000000 ~ 0x0FFFFFFF 0x10000000 ~ 0x1FFFFFFF 0x20000000 ~ 0x20FFFFFF 0x21000000 ~ 0x21FFFFFF 0x22000000 ~ 0x22FFFFFF 0x23000000 ~ 0x23FFFFFF 0x24000000 ~ 0x24FFFFFF 0x25000000 ~ 0x25FFFFFF 0x26000000 ~ 0x26FFFFFF 0x27000000 ~ 0x27FFFFFF 0x28000000 ~ 0x28FFFFFF 0x29800000 ~ 0x29FFFFFF 0x2A000000 ~ 0x2FFFFFFF 0x30000000 ~ 0x30FFFFFF 0x31000000 ~ 0x31FFFFFF 0x32000000 ~ 0x32FFFFFF 0x33000000 ~ 0x37FFFFFF 0x38000000 ~ 0x38FFFFFF 0x39000000 ~ 0x390003FF 0x38000500 ~ 0x3FFFFFFF 0x40000000 ~ 0x4FFFFFFF 0x50000000 ~ 0x5FFFFFFF 0x60000000 ~ 0x6FFFFFFF 0x70000000 ~ 0x7FFFFFFF 0x80000000 ~ 0xBFFFFFFF 0xC0000000 ~ 0xC00007FF 0xC0000800 ~ 0xC0FFFFFF Samsung Electronics
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Contents ROM Bank0 ROM Bank1 ROM Bank2 ROM Bank3 Unused Special Function Registers I/O Bank0 I/O Bank1 I/O Bank2 I/O Bank3 I/O Bank4 I/O Bank5 DMA I/O Bank0 DMA I/O Bank1 DMA I/O Bank2 DMA I/O Bank3 Unused RSH SRAM HPVC SRAM MOTOR SRAM Unused USB CSR & FIFO USB PLUG DETECT Unused SDRAM array0 (bank 0) SDRAM array1 (bank 1) SDRAM array2 (bank 2) SDRAM array3 (bank 3) SDRAM array0~4 (Mirror) MAC Unused
3-15
Circuit Description
3-2-5-1 SDRAM read timing
Basically the Extended Data Out DRAM is similar to Fast Page Mode DRAM. For FPM, the data are valid only when the nCAS is active while reading the internal data, however, it has a latch that the data will be continuously outputted even after the nCAS is inactivated. While configuring the software, you must set the timing register of SFR considering the clock speed and the DRAM spec.
0 CLOCK CKE
*Note 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CS RAS
*Note 2
CAS ADDR BA0
RAa RBb CAa RCc CBb RDd CCc CDd
BA1
A10/AP
RAa
RBb
RCc
RDd
CL=2 DQ CL=3
QAa0 QAa1 QAa2 QBb0
QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0
QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE DQM
Row Active (A-Bank)
Read (A-Bank) Row Active (B-Bank)
Read (B-Bank) Row Acive (C-Bank)
Read (C-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
(D-Bank) Precharge (A-Bank) Precharge (B-Bank)
: Don't care
* Note : 1. CS can be don't cared when RAS, CAS and WE are hih at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
3-16
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Samsung Electronics
Circuit Description
3-2-5-2 SDRAM write timing
CLOCK CKE CS RAS CAS ADDR BA0 BA1
0
1
2
3
4
5
6
7
8
9
10 HIGH
11
12
13
14
15
16
17
18
19
RAa
RBb CAa
CBb RCc
RDd CCc
CDd
*Note 2
A10/AP DQ WE
RAa
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL
*Note 1
DQM
Row Active (A-Bank)
Write (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (C-Bank)
Row Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
: Don't care
*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst wrige by Row precharge, both the write and the prechargebanks must be the same.
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3-17
Circuit Description
3-2-6 FS781 (FREQUENCY ATTENUATOR)
This system used FS741 for the main clock for EMI SUPPRESSION. It spreads the source clock in a consistent bandwidth to disperse the energy gathered in order to attenuate the energy. The capacitor value of the loop filter(PIN 4) is set depending on the source clock used or the spread bandwidth. Refer to FS781 Spec. for detail.
3-2-7 USB (Universal Serial Bus)
NS's USBN9602 is used as the interface IC and 48MHz clock is used. When the data is received through the USB port, EIRQ1 SIGNAL is activated to send interrupt to CPU, then it directly sends the data to DRAM by IOCS4*&DRAMA(11) SIGNAL through DRAMD (24;31).
3-2-8 SRAM : 1MByte SRAM K6F1008U2C
It stores a variety of option data.
3-2-9 FAX Transceiver
3-2-9-1. GENERAL
This circuit processes transmission signals of modem and between LIU and modem.
3-2-9-2. modem (u44)
FM336 is a single ship fax modem. It has functions of DTMF detection and DTMF signal production as well as functioins of modem. TX A1, 2 is transmission output port and RX IN is received data input port. / POR signal controlled by MFP controller (U3:ARM946ES) can initialize modem (/M_RST) without turning off the system. D0-D7 are 8-bit data buses. RS0-RS4 signals to select the register in modem chips. /RS and /WR signals control READ and WRITE respectively. /IRQ is a signal for modem interrupt. Transmission speed of FM336 is supported up to 33.6k. The modem is connected to LINE through transformer directly.
< FAX TRANSCEIVER >
3-18
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Samsung Electronics
Circuit Description
3-3 Scanner
3-3-1 SUMMARY
This flat-bed type device to read manuscripts has 600dpi CCD as an image sensor. There is one optical sensor for detecting CCD home position and Scan-end position. The home position is detected by a optical sensor which is attached to the CCD Module. The Scan-end position is calculated by numer of motor step.
CCD
Charge Coupled Device improves productivity and allows a compact design. This machine uses a color CCD. · Minimum Scan Line Time for One Color : 2.5mSec · Light Source Power : +18V · Maximum Pixel frequency : 10MHz · Effective Sensor Element : 5340 X 3 · Clamp Level : 0.7~ 0.8V · Bright Output : MIN 0.8V
AIN AD C_REF T ADC _REFB
PI_TG PI1 PI2
EXT SRAM
Sen so r 12-bit A/ D converter AFE_CIP4 Interface
Shadi ng Acqu isitio n
Shadi ng C orrectio n SRAM 1 024 x 8 ( R/G/ B) Gam ma C orrectio n
Vertical D ecim ation
SRAM_A[ 15:0] SRAM_D[ 15: 0] SRAM_nRD SRAM_nWR
Imag e SRAM 8 192 x 8 ( 2l ine) Enlarge men t / Redu ction Processing Mo dule
SRAM 256 x 8
SRAM
4 09 6 x16
(2 line )
IRQ
Interrupt Contro l
Vp eak Contro l
Mo to r Con tro l D MA
TX_A, B n TX_A, B
TX_EN1, EN2
CPU I/F Mod ule
CIP4 Register
Interface SRAM 1 024 x 8
n CS
n RD
n WR
A [ 5 : 0]
D [ 15 : 0]
n XDREQ
n XDACK
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3-19
Circuit Description
3-3-2 Key Features Overview
(1) 0.5µm C-MOS process(TLM), 208-PIN QFP, STD85 library (2) Frequency : Max PLL 80 MHz (3) On-Chip oscillator (4) Method : Raster scanning method (5) Image Sauce : 300/400/600dpi CIS & CCD (6) Scanning Mode · color gray image: each 8 bits / RGB · mono gray image: 8 bits / pixel · binary image: 1 bit / pixel (for text/phoot/mixed mode) (7) Maximum scanning width : A3, 600dpi (8K effective pixels) (8) Ideal MSLT (A4, 600/300dpi) · color gray image: 3x5Kx80nsec = 1.2msec (7/28 CPM) · mono gray image: 1x5Kx80nsec = 0.4msec (21/84 CPM) · binary image: 1x5Kx80nsec = 0.4msec (21/84 CPM) (9) A/D conversion depth : 12bits
Pixel processing structure
· Minimum pixel processing time : 4 system clocks · High speed pipelined processing method (Shading correction, Gamma correction, Enlargement/Reducement, and Binarization)
Shading Correction
(1) White shading correction support for each R/G/B (2) White shading data memory : 3x8Kx12bits = 288Kbits (3) Black shading data memory : 3x8Kx12bits = 288Kbits 384Kbits (external) 384Kbits (external)
Gamma Correction
(1) Independent Gamma table for each RGB component (2) Gamma table data memory : 3x1Kx8bits = 24Kbits (internal)
Binarization (mono)
(1) 256 Gray's halftone representation for Photo document : 3x5 EDF(Error DifFusion) method proposed by Stucki. (2) LAT(Local Adaptive Thresholding) for Text document : · use of 5x5 LOCAL WINDOW (TIP ALGORITHM) · ABC(Automatic Background Control) :Tmin Automatic change (3) Mixed mode processing for text/photo mixed document (4) EDF data memory : 2x4Kx16bits = 128Kbits (internal) (5) LAT data memory : 4x4Kx16bits = 256Kbits (external)
Scaling of input image
(1) Scaling factor · Horizontal direction: 25 ~ 800% by 1% unit · Vertical direction: 25 ~ 100% by 1% unit (2) Scaling data memory : 2x8Kx8bits = 128Kbits (internal)
3-20
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Samsung Electronics
Circuit Description
Intelligent scan motor controlloer
(1) Automatic acceleration/deceleration/uniform velocity (2) Data memory : 256x16bits = 4Kbits (internal)
Auto-Run
Automatic CLK_LINE (line processing start control) and ·'TG (line scan start control) signal generation| (1)Available resynchronization of øTG signal (2) programmable øTG's period & CLK_LINE's occurrence number
Processed data output format in DTM(Data Transfer Module)
(1)DMA mode : Burst/On-demand mode (2) CDIP I/F : LINE_SYNC, PIXEL_SYSNC, PIXEL_DATA[7:0]
36 General Purpose Input/Output : 8(GPO), 28(GPIO) Black/White reversion, and Image Mirroring support
ADD R BU S
DATA MEMORY
DMA Controller (SPGPm)
1M bit SRAM
DATA BUS
CLK_LINE CLK_PIX L IN E_PERIO D IW IN
T R D M A A C K
T R D M A R E Q
Image Processor
_
_
CPU SPGPm
Scan/Motor Driver
ADC _CLK CD S2 _CLK AFE Co ntro l Sig na l
AFE
12b it ADC
12 b it (R/ G/ B) ADD R- BUS ADDR- BUS PI_TG PI1 , PI2 DAT A- BUS DAT A- BUS Tx_A, Tx_B, n Tx_A, nTx_B Ana lo g Si gn al
Scanner
CIP4
D OCU MENT IMAGE
Samsung Electronics
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3-21
Circuit Description
AIN ADC_REFT ADC_REFB
PI_TG PI1 PI2
EXT SRAM
Sen so r 12-bit A/ D converter AFE_CIP4 Interface
Shadi ng Acqu isitio n
Shadi ng Correctio n SRAM 1 024 x 8 ( R/G/ B) Gam ma Correctio n
Vertical Decimation
SRAM_A[ 15:0] SRAM_D[ 15: 0] SRAM_nRD SRAM_nWR
Imag e SRAM 8 192 x8 ( 2l ine) Enlarge men t / Redu ction Processing Mo dule
SRAM 256 x 8
SRAM
4096 x16
(2 line )
IRQ
Interrupt Contro l
Vp eak Contro l
Mo to r Con tro l DMA
TX_A, B nTX_A, B
TX_EN1, EN2
CPU I/F Mod ule
CIP4 Register
Interface SRAM 1 024 x 8
nCS
nRD nWR
A [5:0]
D [15:0]
nXDREQ
nXDACK
3-22
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Samsung Electronics
Circuit Description
3-4 HOST INTERFACE:
Referred to IEEE 1284 standard.
3-4-1. Host Interface
PARALLEL PORT INTERFACE PART ARM946ES has the Parallel Port Interface Part that enables Parallel Interface with PC. This part is connected to PC through Centronics connector. It generates major control signals that are used to actuate parallel communication. It is comprised of/ERROR, PE, BUSY, /ACK, SLCT, /INIT, /SLCTIN, /AUTOFD and /STB. This part and the PC data transmission method support the method specified in IEEE P1283 Parallel Port Standard (http://www.fapo.com/ieee1284.html). In other words, it supports both compatibility mode (basic print data transmitting method), the nibble mode (4bit data; supports data uploading to PC) and ECP (enhanced capabilities port: 8bits data - high speed two-way data transmission with PC). Compatibility mode is generally referred to as the Centronics mode and this is the protocol used by most PC to transmit data to the printer. ECP mode is an improved protocol for the communication between PC and peripherals such as printer and scanner, and it provides high speed two-way data communication. ECP mode provides two cycles in the two-way data transmission; data cycle and command cycle. The command cycle has two formats; Run-Length Count and Channel Addressing. RLE (Run-Length Count) has high compression rate (64x) and it allows real-time data compression that it is useful for the printer and scanner that need to transmit large raster image that has a series of same data. Channel Addressing was designed to address multiple devices with single structure. For example, like this system, when the fax/printer/scanner have one structure, the parallel port can be used for other purposes while the printer image is being processed.This system uses RLE for high speed data transmission. PC control signals and data send/receive tasks such as PC data printing, high speed uploading of scanned data to PC, upload/download of the fax data to send or receive and monitoring the system control signal and overall system from PC are all processed through this part.
PPD( 7: 0)
DATA
BUSY
nSTROBE
nACK
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Circuit Description
1 nSTROBE
2
3
4
5
6
BUSY
PPD( 7: 0)
BYTE0
BYTE1
nAUTOFD
DATA BYTE
COMMAND BYTE
1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD 2. Host asserts nSTROBE low to indicate valid data 3. Peripheral acknowledhes host by setting BUSY high 4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral 5. Peripheral sets BUSY low to indicate that it is ready for the next byte 6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low
1 2 nACK
3
4
5 6
7
8
nAUTOFD
PPD( 7: 0)
BYTE0
BYTE1
BUSY
DATA BYTE
C M OM AND BYTE
nINI T
PE
1. The host request a reverse channel transfer by setting nINIT low 2. The peripheral signals that it is OK to proceed by setting PE low 3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high 4. Peripheral asserts nACK low to indicate valid data 5. Host acknow ledges by setting nAUTOFD high 6. Peipheral sets nACK high. This is the edge that should be used to clock the data into the host 7. Host sets nAUTOFD low to indicate that it is ready for the next byte 8. The cycle repeats, but this time it is a command cycle because BUSY is low
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Circuit Description
3-4-2 USB INTERFACE
CS RD VVR A0/ALE D[7:0]/AD[7:0] INTR MODE[1:0] RESET Vcc GND
Microcontroller Interface
Endpoint/Contol FIFOs Control Status
48 MHz Oscillator
XIN XOUT
RX TX
Clock Generator
CLKOUT
SIE Media Access Controller[MAC] Physical Layer interface[PHY] Clock Recovery USB Event Detect V3.3 Trans ceiver VReg AGND
D+
D-
Upstream Port
3-4-2-1 Features
· Full-Speed USB Node Device · USB transceiver · 3.3V signal voltage regulator · 48 MHz oscillator circuit · Programmable clock generator · Serial Interface Engine consisting of Physical Layer In-terface (PHY) and Media · Access Controller (MAC), USB Specification 1.0 compliant · Control/Status Register File · USB Function Controller with seven FIFO-based End-points : · One bidirectional Control Endpoint 0 (8bytes) - Three Transmit Endpoints (2*32 and 1*64 bytes) · Three Receive Endpoints (2*32 and 1*64 bytes) · 8-bit parallel interface with two selectable modes : - non-multoplexed · multiplexed (Intel compatible) · DMA support for parallel interface · MICROWIRE/PLUS Interface · 28-pin SO package
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Circuit Description
CS A0 VVR RD
DATA_IN DATA_IN
0x00
DATA_OUT DATA_OUT
D[7:0] ADDR ADDRESS 0x3F REGISTERFILE
cs
A0 RD
VVR
D[7:0]
input
out
out
vvrte Address
Read Data
Burst Read Data
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Circuit Description
3-5 Engine Controller
3-5-1. Fuser Control / Thermistor Circuit
This circuit controls the heat lamp temperature to fix the transferred toner on the paper. It is comprised of the thermistor that has the negative resistance against the temperature and LM393 (voltage comparator) and transistor for switching. The thermistor has the resistance value reverse proportional to the heat lamp surface temperature. The voltage value is read by #60 pin(AVIN2) of CPU refering to the parallel combined resistance with the resistor(R43) connected parallel to it and the voltage distribution of R29. The voltage read activates (inactivates) `fuser' signal to high (or low) referring to the set temperature and when the `fuseron' signal turns down(high) to low(high) by Q3 switching, the S21ME4 inside SMPS (PC3) turns on(off) and this eventually turns two-way thyristor(SY1) on(off) to allow(shut) AC voltage to the heat lamp. LM393 is a H/W designed to protect the system when the software heat lamp control does not run normal. When the thermistor temperature goes up to 210°C, #1 pin's level (LM393) will turn low to turn the `fuseron' signal to high. (forcefully shuts off Q3)In other words LM393 shuts off the heat lamp forcefully.
3-5-2. Paper Sensing Circuit
1) Cover Open Sensing Cover Open Sensor is located on the right rear side of the printer. In case the right cover is open, it shuts +5V (LSU laser unit) and +24V(main motor, polygon motor of fixer LSU and HVPS) that are supplied to each unit. It detects the cover opening through CPU. In this case, the red LED of the OP Panel LED will turn on. 2) Paper Empty Sensing The paper empty sensor (photo interruptor), located inside bottom of the bin cassette detects paper with the actuator connected to it and informs the CPU of whether there is paper. When there is no paper in the cassette, the red LED of the OP panel LED will turn on to tell the user to fill the cassette with papers. 3) Paper Feeding When the paper is fed into the set and passes through the actuator of the feed sensor unit, transistor inside the photo interrupter will turn on, `nFEED' signal will turn low and inform CPU that the paper is currently fed into the system. CPU detects this signal and sprays video data after certain time (related to paper adjustment). If the paper does not hit the feed sensor within certain time, CPU detects this and informs as "Paper Jam0" (red LED on the OP panel will turn on). 4) Paper Exit Sensing The system detects the paper going out of the set with the exit sensor assembled to the actuator attached to the frame. If CPU does not turn back high a while after the paper hits the exit sensor, CPU detects this and inform as "Paper Jam2" (red LEDs on the OP panel will turn on).
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Circuit Description
3-5-3. LSU Circuit
1) Polygon Motor Unit (actuated by +24V) The polygon motor inside LSU rotates by the `PMOTOR' signal. When it reaches the motor constant velocity section through the initial transient (transient response) section, it sends the `nLREADY' signal to the CPU. The `clock' pin is the pin that receives clock of the required frequency when LSU uses external CLK as the motor rotational frequency. Currently the external clock circuit is located in the HVPS and 1686Hz = 6.9083MHz (crystal frequency)÷212(74HC4060N IC), is used as the rotational frequency of the polygon motor. 2) Laser Unit (actuated by +5V) After laser is turned on by `nLD_ON' signal, it is reflected by 6 mirrors (polygon mirror) attached to the polygon motor and performs scan in horizontal way.When the laser beam hits the corner of the polygon mirror, it generates `nHSYNC' signal (pulse) and the CPU forms the left margin of the image using this signal (horizontal synchronous signal).
3-5-4. Fan/Solenoid Actuation Circuit
The fan actuation circuit its power using NPN TR. When it receives `FAN' signal from the CPU. The TR will turn on to make the voltage supplied to the fan to 24V in order to actuate the fan. The solenoid is actuated in the same way. When it receives control signal from the CPU, the solenoid for paper feeding is actuated by switching circuit. D29(1N4003) diode is applied to the both ends of the output terminal to protect Q22(KSC1008-Y) from noise pulse induced while the solenoid is de-energized.
3-5-5. PTL Actuation Circuit
PTL actuation circuit switches its power using NPN TR.
3-5-6. Motor Actuation Circuit
Motor actuation circuit is determined while selecting the initial driver IC (provided by the vendor). This system uses TEA3718(U57, U58), A2918(U59)'s motor driver IC. However, the sensing resistance (R273, R274, R292, R293) and reference resistance (R284, R289, R294, R295) can vary depending on the motor actuation current value. It receives motor enable signal (2 phase) from CPU and generates bipolar pulse (constant-current) and sends its output to stepping motor input.
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Circuit Description
3-5-7. High Voltage Power Supply
3-5-7-1. Summary
It is the high voltage power supply that has DC+24V/DC+5V (used for the image forming device in OA digital picture developing method) as the rated inputs. It supplies electrifying voltage (MHV), supply voltage (SUPPLY), developing voltage (DEV), blade voltage(BLADE) and transferring voltage (THV). Each high voltage supply shows the voltage required in each digital picture process.
3-5-7-2. Digital Picture Process
Digital picture developing method is widely used by copy machine, laser beam printer and fax paper. The process is comprised of electrification, exposure, develop, transfer and fixing.
BLADE SUPPLY DEV
LSU MHV
SUPPLY ROLLER
DEVELOPER ROLLER HEAT ROLLER ELECTRIFICATION ROLLER DIRECTION OF PAPER
THV
PRESSURE ROLLER
TRANSFER ROLLER
First, in the electrification process, retain constant charge at approx. -900V for the electric potential on the OPC surface by electrifying OPC drum at approx. -1.4KV through the electrification roller. The electrified surface of OPC is exposed responding to the video data by the LSU that received print command due to rotation. The unexposed non-video section will retain the original electric potential of -900V, but the electric potential of the image area exposed by LSU will be approx. -180V that it will form the electrostatic latent image. The surface of the photo-conductive drum where the electrostatic latent image is formed reaches the developer as the drum rotates. Then the electrostatic latent image formed on the OPC drum is developed by the toner supplied to the developing roller by supplying roller and it is transformed into visible image. It is the process to change the afterimage on the OPC drum surface formed by LSU into visible image by the toner particles. While the supply roller energized with -450V by HVPS and the developer roller energized with -300V rotate in the same direction, it keeps the toner particles between two rollers supplied to OPC drum in negative state by the friction between two rollers. The toner supplied to the developer roller is biased to bias electric potential by the developer roller and transferred to the developing area. After (-) toner is attached to the developer roller, it will move to the exposed high electric potential surface (-180V) rather than to the unexposed low electric potential surface (-900V) of the developer roller and OPC drum. Eventually the toner will not settle in the low electric potential surface to form the visible image. Later, the OPC drum continues to rotate and reaches to transfer location in order to accomplish the transfer process. This process transfers the (-)toner on the transfer roller to the printing paper by the transfer roller. The ()toner attached to the OPC drum will be energized to hundreds to thousands of the (+)transfer voltage by HVPS. The (+)electrostatic force of the transfer roller generated has higher adhesiveness than the (-)toner OPC drum and thus it moves to the surface of the paper passing through the transfer roller. The toner transferred to the paper with weak electrostatic force is fixed to the paper by the pressure and heat of the fixer composed of pressure roller and heat roller. The toner attached to the paper is melted by applying the heat (approx. 180°C) from the heat roller and the pressure (approx. 4kg) from the pressure roller. After the fixing process, the paper is sent out of the set to finish the printing process.
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Circuit Description
3-5-7-3. Organization of the Device
HVPS is comprised of electrification output unit, bias output unit and transfer output unit. 1) Input Unit 2) Electrification Output (Enable) Unit: MHV (Main High Voltage) 3) Bias Output (Enable) Unit: DEV (Development Voltage)/Supply(Supply Voltage)/BLADE(Blade Voltage) 4) Transfer `+' Output (Enable) Unit: THV(+)(Transfer High Voltage(+)) 5) Transfer `-' Output (Enable) Unit: THV(-)(Transfer High Voltage(-)) 6) Switching Unit 7) Feedback Unit 8) Regulation Unit 9) Output Unit
SWITCHING CONTROL UNIT
TRANS
REGULATION CIRCUIT
OUTPUT CIRCUIT
MHV
MHV-PWM
THVPWM
PWM CONTROL UNIT SWITCHING CONTROL UNIT TRANS REGULATION CIRCUIT
THV
FE E DBACK
THVEA
SWITCHING CONTROL UNIT
TRANS
REGULATION CIRCUIT
THVREAD
THV ENVIRONMENT RECOGNITION CIRCUIT FEED BACK
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Circuit Description
MHV-PWM
PWM CONTROL UNIT
SWITCHING CONTROL UNIT
TRANS
REGULATION CIRCUIT
MHV
OPC
FEEDBACK
BIAS-PWM BLADE
PWM CONTROL UNIT SWITCHING CONTROL UNIT TRANS REGULATION CIRCUIT
SUPPLY
FEEDBACK
DEV
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Circuit Description
3-5-7-4 MHV (Electrification Output Enable)
Electrification Output Enable is the electrification output control signal 'PWM-LOW ACTIVE'. When MHV-PWM LOW signal is received, Q401 turns on and the steady voltage will be accepted to the noninverting terminal of OP-AMP 324. As the voltage higher than the inverting reference voltage of OP-AMP, which is set to R405 and R406, OP-AMP output turns high. This output sends IB to the TRANS auxiliary wire through current-restricting resistance Q402 via R408 and C403 and Q402 turns on. When the current is accepted to Q402, Ic increases to the current proportional to time through the T401 primary coil, and when it reaches the Hfe limit of Q402, it will not retain the "on" state, but will turn to "off". As Q402 turns 'off', TRANS N1 will have counter-electromotive force, discharge energy to the secondary unit, sends current to the load and outputs MHV voltage through the high voltage output enable, which is comprised of Regulation circuit.
T401 24VS 18V C404 3K/471 MHV OUTPUT
D402 4KV U103 7407 R412 2.2K Q401 A708 R405 220K 24VS Q402 D526
C406 3K/471 R416 15M R413 12M OPC
MHV-PWM
R403 130K R404 27K C407 104
+
R408 47K
R409 390
R417 15M ZD401 150V
R402 82K R411 2K
_
KA324 C403 333
R406 2.2K
3-5-7-5 BIAS (supply/dev/blade output unit)
BIAS (Electrification Output Enable)Electrification Output Enable is the electrification output control signal `PWM-LOW ACTIVE'.When BIAS-PWM LOW signal is received, Q501 turns on and the steady voltage will be accepted to the non-inverting terminal of OP-AMP 324. As the voltage higher than the inverting reference voltage of OP-AMP, which is set to R506 and R507, OP-AMP output turns high. This output sends IB to the TRANS auxiliary wire through current-restricting resistance Q502 via R509 and C504 and Q502 turns on. When the current is accepted to Q502, Ic increases to the current proportional to time through the T201 primary coil, and when it reaches the Hfe limit of Q502, it will not retain the "on" state, but will turn to "off". As Q502 turns `off', TRANS N1 will have counter-electromotive force, discharge energy to the secondary unit, sends current to the load and outputs DEV voltage through the high voltage output enable, which is comprised of Regulation-circuit.
24VS T201 KAB-007
1
D502 4KV
7
R514 MGR1/2W 50K BLADE
5V C503 104 R508 47K Q502 D526-Y
5 6
R520 26K BIAS-PWM CON03-#24 2
R501 100
Q501 A708-Y
R506 86.6KF
2
C505 2KV 680
C506 3KV 471
ZD501 100V
R515 MGR1/2W 50K SUPPLY
5
_ U1 + U101-B KA324
U103-A R519 7407 2.2K R503 100KF R502 2K C501 R504 56.6KF 104 C502 222 R507 12KF
7 R509 47K R510 430 C504 333 R511 1W 3
4
ZD501 100V
6
R512 MGR1/2W 12MF
DEV R516 MGR1/2W 50K
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Circuit Description
3-5-7-6. THV(THV(+)/THV(-) Output Unit)
Transfer(+) output unit is the transfer output control signal 'PWM-LOW ACTIVE'. When THV-PWM LOW signal is received, Q203 turns on and the steady voltage will be accepted to the noninverting terminal of OP-AMP 324. As the voltage is higher than the inverting reference voltage of OP-AMP, OP-AMP output turns high. The 24V power adjusts the electric potential to ZD201 and ZD202, sends IB to TRANS auxiliary wire through current-restricting resistance R215 via R212 and C204, and eventually Q204 will turn on. When the current is accepted to Q402, Ic increases to the current proportional to time through the T201 primary coil, and when it reaches the Hfe limit of Q204, it will not retain the "on" state, but will turn to "off". As Q402 turns 'off', TRANS N1 will have counter-electromotive force, discharge energy to the secondary coil, sends current to the load and outputs THV voltage through the high voltage output enable, which is comprised of Regulation circuit. The output voltage is determined by the DUTY width. Q203 switches with PWM DUTY cycle to fluctuate the output by fluctuating the OP-AMP non-inverting end VREF electric potential, and the maximum is output at 0% and the minimum, at 100%.Transfer(-) output unit is THV-EA 'L' enable. When THV-EA is 'L', Q302 turns on and the VCE electric potential of Q302 will be formed and sends IB to TRANS auxiliary wire through R311, C305 and VR302 via current-restricting resistance R314, and eventually Q303 will turn on. When the current is accepted to Q303, Q303's Ic increases to the current proportional to time through the T301 primary coil, and when it reaches the Hfe limit of Q303, it will not retain the "on" state, but will turn to "off". As Q303 turns 'off', TRANS N1 will have counter-electromotive force, discharge energy to the secondary coil, send current to load and output THV(-) voltage through the high voltage output enable, which is comprised of Regulation circuit.
5V 18V R201 10K #7 TEV-PWM 1 U2 2 3 U2 R206 100 Q203 A708Y R208 30K R209 100KF VR201 50K + C101 35V47UF R212 680K C203 472 D203 1N4148 ZD201 ZD202 5.65V 705V R214 2.2K C204 333Z R215 390 C201 103 C202 121 R210 845KF D202 1N4148 R211 1MF 24VS T201 KAB-007 1 R205 1.8K D201 1N4148 5 + U1 6 _ 11 KA324 7 R213 2.2K Q204 D526 5 2 7 C205 2KV68pF D204 6KV C206 6KV470pF C208 6KV D206 6KV C209 6KV
D205 6KV
D207 6KV
6 C207 3KV470pF
24VS
R207 2K
R216 SBR306
R218 MGR1/2W100KF
4
R217 SBR207
#17 #19
5V
5V
D301 1N4148
18V
R309 202K #5 TEV-EA 5 7 6 U2 7407 R307 33K 18V D-GND C4 103 R310 2.2K R308 33K R302 33K R303 100KF C302 102 D302 1N4148 C303 103 R304 389KF R306 26.1KF Q302 A708Y Q301 A708Y
R312 1W56
KAB-006 T301 1 6
C307 3KW470pF
D304 4KV
24VS
R313 1W56
C306 2KV68pF 5 Q303 D526 2 7
D303 4KV
C308 3KV470pF
R315 SBR306
#24
TEV-READ
8
+ 10 U1 _ 9
VR302 2K R311 100KF C305 333Z 4 R314 1.7K
KA324
R301 470K
R305 10KF C304 500V103Z
VR301 5K C301 222
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Circuit Description
3-5-7-7. Environment Recognition
THV voltage recognizes changes in transfer roller environment and allows the voltage suitable for the environment in order to realize optimum image output. The analog input is converted to digital output by the comparator that recognizes the environmental changes of the transfer roller. It is to allow the right transfer voltage to perform appropriate environmental response considering the environment and the type of paper depending on this digital output by the programs that can be input to the engine controller ROM. This environment recognition setting is organized as follows: First, set the THV(+) standard voltage. Allow 200M load to transfer output, enable output and set the standard voltage 800V using VR201. Then set 56 (CPU's recognition index value) as the standard using VR302. This standard value with CPU makes sure that the current feedback is 4µA when output voltage is 800V and load is 200M. If the load shows different resistance value when 800V is output, the current feedback will also be different and thus the index value will also be different. according to the index value read by CPU, the transfer voltage output will differ according to the preset transfer table. The changes in transfer output required by each load is controlled by PWM-DUTY.
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Circuit Description
3-6 OPE PBA
3-6-1 SUMMARY
OPE Board is separated functionally from the main board and operated by the micom(HT48R50) in the board. OPE and the main use UART (universal asynchronous receiver/transmitter) channel to exchange information. OPE reset can be controlled by the main. OPE micom controls key-scanning and LCD and LED display. If there occurs an event in OPE (such as key touch), it sends specific codes to the main to respond to the situation and the main analyzes these codes and operates the system. For example, it the main is to display messages in OPE, the main transmits data through UART line to OPE according to the designated format and OPE displays this on LCD, LED. OPE's sensing is also transmitted to the main through UART line and then the main drives necessary operation. OPE PBA consists of U1(MICOM, HT48R50),LCD, key matrix, LED indicators. Refer to OPE Schematic Diagram and Wiring Diagram sections of this manual. · Signals from the key matrix are delivered to U1 input pin group (D1~D6) · U1 pin 48 (TX DATA) is the UART code sent to MAIN PBA. · Display from the controller is received at U1 pin 5(RX DATA). · LCD drive signals are sent from U1 P2-x pin group, P3-4~P3-6 pins. · Machine status LED drive signals are sent from U1 LED0~LED7.
RESONATOR 7.37 MHz
UART
Connector
11
LCD 16 2line
Reset
MICOM HT48R50
7 X Y 8
Key Matrix
LEDs
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Circuit Description
3-7 LIU PBA
3-7-1. SUMMARY
LIU WIRE CONNECTS Main B'D's MODEM AND LINE PARTS, AND IMPEDANCE MATCHING (AC, DC), RING DETECTION PART and LINE SEIZURE (DIALER).
3-7-2. DC MATCHING PART
Normal movement range of LIU is 12mA ~ 9mA. Adapting CTR21 standard, the regulation limits to 60mA CURRENT flow through the terminal. Therefore, select (*:for EU PIT) Option to connect necessary items then the current through LIU will not exceed 60mA. · CTR21 Standard(Europe) : 12mA~60mA · OTHER Standard (U.S.) : 12mA~90mA DC has a character to pass through the LINE. And with Q1 (VN2410) GATE section's LINE INPUT corrent and Q1 Source connection to R20, can be decided as follows : · -VDCR = VL1 + ILINE X R20 (VDCR : Tip-Ring CD Voltage, ILINE : Current flow)VL1:Line Input Voltage, VL1=VBD1+VCE(Q2)+VDS(Q1)
3-7-3. AC MATCHING PART
Basic LIU's AC IMPEDANCE is 600 and uses R47. 48. C36 to possibly control combined IMPEDANCE. · U.S. Usage : A terminal IMPEDANCE Æ 600W(±30%) · CTR21 : A Terminal IMPEDANCE Æ 270+750W//150nF
3-7-4. DIALER PART
*MF DIAL DTMF Dialing is controlled by MODEM and should be selected by appropriate LEVEL and On-off Time output based on each countries' own National specification. · Freq. Tolerance : ±1.5% High Group : 1209, 1336, 1477, 1633Hz Low Group : 697, 770, 852, 941 Hz U.S. Usage High F