Text preview for : VIZIO GV46L HDTV & (10A)_ Samsung Panel.pdf part of Vizio GV46L HDTV & (10A) Samsung Panel GV46L HDTV & (10A) Samsung Panel
Back to : VIZIO GV46L HDTV & (10A)_ | Home
Service Manual
Model #: VIZIO GV46L HDTV VIZIO GV46L HDTV10A (For Samsung Panel)
V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099
Top
Confidential
Table of Contents
CONTENTS Sections 1. Features 2. Specifications 3. On Screen Display 4. Factory Preset Timings 5. Pin Assignment 6. Main Board I/O Connections 7. Theory of Circuit Operation 8. Waveforms 9. Trouble Shooting 10. Block Diagram 11. Spare parts list 12-1. Complete Parts List (GV46L HDTV_Samsung) 12-2. Complete Parts List (GV46L HDTV10A_Samsung) 1-1 2-1 3-1 4-1 5-1 6-1 7-1 8-1 9-1 10-1 11-1 12-1 12-2 PAGE
Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram
VIZIO GV46L_HDTV,GV46L_HDTV10A Service Manual
VINC
COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.
Service Manual
VIZIO GV46L_HDTV,GV46L_HDTV10A
IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA). No part of this document may be copied, reproduced or transmitted by any means for any purpose without prior written permission from VINC.
FCC INFORMATION This equipment has been tested and found to comply with the limits of a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that the interference will not occur in a particular installation. If this equipment does cause unacceptable interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures -- reorient or relocate the receiving antenna; increase the separation between equipment and receiver; or connect the into an outlet on a circuit different from that to which the receiver is connected. FCC WARNING To assure continued FCC compliance, the user must use a grounded power supply cord and the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized changes or modifications to Amtrak products will void the user's authority to operate this device. Thus VINC Will not be held responsible for the product and its safety. CE CERTIFICATION This device complies with the requirements of the EEC directive 89/336/EEC with regard to "Electromagnetic compatibility." SAFETY CAUTION Use a power cable that is properly grounded. Always use the AC cords as follows USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards.
VIZIO GV46L_HDTV,GV46L_HDTV10A Service Manual
Chapter 1
Features
High resolution 1366 x 768 with wide screen Built-in digital HDTV and standard TV combination TV tuner All TV formats supported (1080i, 720p, 480 p and 480i) Computer Monitor (RGB): up to1366 x 768 (H x V) Wall mounting capable with and without speakers 2.1 virtual surround sound (TruSurround XT) with 20W subwoofer Dual HDMI (High Definition Multimedia Interface) Independent Red, Green and Blue adjustment in TV, Video, HDMI and VGA for user fine tuning of color temperature with reset. Zero Bright Pixel PIP, POP, CC, V-Chip, 3D Comb Filter, Zoom, Freeze, DCDi De-Interlace, 3:2 or 2:2 Reverse Pull-down, ATSC, with 8VSB & QAM demodulation, with MPEG-2 decoding, NTSC Video decoding via RF (Antenna, Cable or Satellite) or Video (CVBS, S-Video or Component), Progressive Scan Video via Component YPbPr, VGA or HDMI, HDTV via HDMI or Component YPbPr,
CONFIDENTIAL DO NOT COPY
Page 1-1 File No. SG-0199
Chapter 2
Specification
1. General specification
Native Resolution Effective Display Size Aspect Ratio Display Color Brightness Contrast Ratio TV system PC Inputs Video Inputs 1366 (H)X768 (V) pixels, 1018.353 (H) x 572.544 (V) mm 16:9 8 bit, 16.7M 400 cd/ m2 (Min) 1,200:1 (Typical, panel spec). NTSC/ATSC/ QAM 15pins D-sub, HDMI-DVI 2 x S-Video 2 x AV inputs (CVBS; RCA type) 2 x Component (Y Pb/Pr Cb/Cr) 2 x HDMI Audio Inputs Audio Outputs 6 x Stereo RCA (R/L), 1 x PC Mini-Jack Analog - 1 x stereo RCA (R/L) 1 x headphone Digital 1 x SPDIF Optical Audio Power Input Power Consumption 10W8 X 2 + 20W8 X1
100 to 240 Vac 320W Max
CONFIDENTIAL DO NOT COPY
Page 2-1 File No. SG-0199
2. Optical characteristics
Item Display Pixels Pixel Pitch Pixel Arrangement Color Depth Active Display Area Surface treatment of Hard coating Brightness Contrast ratio (panel spec) Color coordinates Specification 1366 (H) x 768 (V) pixels 0.7455 (H) x0.2485 (V) mm*3 RGB vertical stripe 8 bit, 16.7M colors 921.6 (H) x 519.2 (V) ±0.5 mm 3H 400 cd/m2 (min) 1,200:1 (Typical, dark room) Cool (9300K):: x=0.283 ± 0.03,y=0.297 ± 0.03 Standard (6500K): x=0.313 ± 0.03, y=0.329 ± 0.03 Warm (5400K): x=0.332 ± 0.03,y=0.348 ± 0.03 User: x= 0.280± 0.03, y= 0.290± 0.03 Viewing angle øL Hor. øR øU Ver. øD 75 75 75 75 RGB RGB /VIDEO RGB RGB Note
3. Power Supply
a. Input voltage b. Input current c. Inrush current d. Power consumption e. Standby/Power-off
CONFIDENTIAL DO NOT COPY
100-240Vac, 50/60Hz 3.2A or less (at AC 100V/60Hz) 60A at Vac=120V 320 W Max 3 watts max. (at 120 Vac)
Page 2-2 File No. SG-0199
4. Environment
4.1 Operating a. Temperature b. Humidity 4.2 Non-operating a. Temperature b. Humidity 4.3 Altitude a. Operating b. Non-operating 0~14,000 ft 0~40,000 ft -20~60 0%~90% RH (No condensation) 0~35 0%~90% RH (No condensation)
5. Dimensions & Weight
A: Display Module Display Module a. Height b. Width c. Depth d. Net weight e. Gross Weight 674.8 mm 1128.3 mm 120.9 mm 30.8+/- 0.5 kgs --
B: Speaker
C: Base Display Module + speaker + Base 792.6 mm 1128.3 mm 269.3 mm 37.00 +/- 0.5 kgs 44 +/- 1 kgs
Display Module + Speaker 749.2 mm 1128.3 mm 132.9 mm 33.50+/- 0.5 kgs --
CONFIDENTIAL DO NOT COPY
Page 2-3 File No. SG-0199
6. Packaging Specification
6.1 Packaged dimensions a. Height b. Width c. Depth 6.2 Pallet Load a. Sea 6.3 Container Load a. 40' container b. 20' container 108 units (@3 x 36 pallets= 108 units) 48 units (@3 x 16 pallets= 48 units) 3 units/pallet 960+/- 20 mm 1300+/- 20mm 374 +/- 20 mm
CONFIDENTIAL DO NOT COPY
Page 2-4 File No. SG-0199
Chapter 3
On Screen Display
1. Analog Menu - RGB/AV/Component/HDMI/TV Image Settings
Mode Level 1 Level 2 Vivid, Movie, Game, Sport, Custom Level 3 Level 4
VIDEO Picture Mode VIDEO Brightness(0~100) VIDEO Contrast(O~100) VIDEO Saturation(0 100) VIDEO Hue(-50~50) VIDEO Sharpness(0~24) VIDEO Advanced VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO Custom Color* VIDEO VIDEO VIDEO PC PC PC PC PC PC PC PC PC PC PC PC PC
Noise Reduction Motion(0~16) Digital(0~64) Fleshtone Dynamic Contrast (0,1,2,3) Backlight (High, Medium, Low) Red(0~100) Green(0 100) Off, High, Medium, Low
Blue(0~100) Auto Adjustment lmage Position Phase CIocks/Line Color Temp Warm(5400K) Standard(6500K) Cool(9300K) User Red(0~100) Green(0 100)
Blue(0~100) Backlight (High, Medium, Low) Page 3-1 File No. SG-0199
CONFIDENTIAL DO NOT COPY
When "Custom" in "Picture Mode" is selected. Display Settings
Mode VIDEO Level 1 Aspect Ratio Level 2 16:9 4:3 Zoom* Level 3 Level 4
Panoramic** PC Aspect Ratio PIP PIP Mode Off, Large PIP, Small PIP, POP PIP Position Top-Left, Top-Right, Bottom-Left, Bottom-Right PIP Input *** * RGB doesn't support Zoom function ** Only AV and Component 480i/480p support Panoramic function. *** Please see 4.3 "PIP/POP Table" for PIP/POP matrix for all inputs. 16:9 4:3
Audio Settings
Mode Level 1 Bass(0~20) Treble(0~20) Balance(-10~10) SRS TS XT* (On, Off) Auto Volume(On, Off) Speakers(On, Off) Audio Out** Fixed Volume, Variable Volume * SRS TS XT doesn't support DTV/TV and line out. ** When "Speakers" is off Level 2 Level 3 Level 4
CONFIDENTIAL DO NOT COPY
Page 3-2 File No. SG-0199
Parental Controls
Mode VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO Block Unrated (No, Yes) VIDEO Change Password VIDEO Please enter new password VIDEO Please re-enter new password VIDEO Clear All (No,Yes) Movie Rating Movie G (Unblocked Movie PG(Unblocked Blocked) Blocked) Level 1 Password Settings TV Rating TV Youth (Unblocked Blocked) Level 2 Level 3 Level 4
TV Youth 7 (Unblocked Blocked) TV G (Unblocked Blocked) TV PG (Unblocked Blocked) TV 14 (Unblocked Blocked)
TV MA (Unblocked Blocked) Unblocked
Movie PG-13(Unblocked Blocked) Movie R(Unblocked Blocked) Movie NC-17(Unblocked Blocked)
Movie X(Unblocked Blocked) Unblocked
CONFIDENTIAL DO NOT COPY
Page 3-3 File No. SG-0199
Setup
Mode Level 1 Closed Caption Display CC1, CC2, CC3, CC4, TEXT1, TEXT2, TEXT3, TEXT4 Captions on mute On, Off Language English, French, Spanish Factory Reset (No,Yes) Image Cleaner TV TV TV TV DTV DTV Menu* Firmware Version * DTV menu is followed by options in the following point 2 when it is selected. TV Menu Auto Scan Set Channel Cable/Antenna Add/Skip Level 2 Level 3 Level 4
2. DTV Menu Level 1 DTV Tuner Setup Time Zone Hawaii Eastern Time Indiana Central Time Mountain Time Arizona Pacific Time Alaska Cable/Air/Auto Level 2 Level 3 Level 4 Level 5
CONFIDENTIAL DO NOT COPY
Page 3-4 File No. SG-0199
Level 1 Scan*
Level 2
Level 3
Level 4
Level 5
Manual Scan* Scan mode Add-on Mode Range Mode From Channel To Channel Channel Skip Digital Audio Out PCM OFF Dolby Digital Closed Caption Analog Closed Caption Digital Closed CAPTION Digital Closed Style As Broadcaster Custom Font Size Large Small Medium Font Color Black White Green Blue Red Cyan Yellow Magenta Font Opacity Solid Translucent Transparent CONFIDENTIAL DO NOT COPY Page 3-5 File No. SG-0199 Service 1~Service 6, OFF CC1~CC4 OFF
Level 1
Level 2
Level 3
Level 4 Background Color
Level 5
Black White Green Blue Red Cyan Yellow Magenta Background Opacity Solid Translucent Transparent Window Color Black White Green Blue Red Cyan Yellow Magenta Window Opacity Solid Translucent Transparent Parental control
CONFIDENTIAL DO NOT COPY
Page 3-6 File No. SG-0199
Chapter 4
Factory preset timings
This timing chart is already preset for this LCD TV. 1. RGB PC preset modes
Horizontal Sync Polarity (TTL) N N P P P N N P P P Vertical Sync Polarity (TTL) N N P P P N N P N P 25.175 31.500 40.000 49.500 56.250 65.000 75.000 78.750 85.500 108.000 Windows Windows Windows Windows Windows Windows Windows Windows Windows Windows Pixel Rate (MHz) Remark
Mode No.
Refresh Horizontal Resolution Rate (Hz) 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1366X768 1280X1024 60 75 60 75 85 60 70 75 60 60
Vertical
Frequency Frequency (KHz) 31.5 37.5 37.9 46.9 53.7 48.4 56.5 60.0 47.7 63.98 (Hz) 59.94 75.00 60.317 75 85.06 60.01 70.07 75.03 60.00 60.02
1 2 3 4 5 6 7 8 9 10
Remark: P: positive, N: negative
1024x768 @60 Hz: Primary
2. HDMI video digital preset modes
Mode No. 1 2 3 4 Resolution 480i 480p 720p 1080i
CONFIDENTIAL DO NOT COPY
Page 4-1 File No. SG-0199
3. HDMI- DVI preset modes - through HDMI interface by an optional interface cable
3.1 Video input
Mode No. 1 2 3 4 Resolution 480i 480p 720p 1080i
3.2 PC input
Horizontal Sync Polarity (TTL) N Vertical Sync Polarity (TTL) N 25.175 Windows Pixel Rate (MHz) Remark
Mode No.
Refresh Resolution Rate (Hz) 640x480 60
Horizontal Frequency (KHz) 31.5
Vertical Frequency (Hz) 59.94
1
CONFIDENTIAL DO NOT COPY
Page 4-2 File No. SG-0199
Chapter 5
1. Input
1.1
Pin Assignment
RGB PC Connector a. Type: b. Frequency: c. Signal level: d. Impedance: e. Synchronization Analog H: 30-80KHz 0.7Vp-p 75 H/V separate sync: H/V composite sync: Sync on Green TTL TTL f. Video bandwidth: g. Connector type: 135MHz 15-pin D-Sub, female V: 60-85Hz
Pin Number 1 2 3 4 5
Pin Assignment Red video input Green video input Blue video input Ground Ground
Pin Number 9 10 11 12 13
Pin Assignment +5V Ground No connection (SDA) Horizontal sync (Composite sync)
6 7 8
Red video ground Green video ground Blue video ground
14 15
Vertical sync (SCL)
CONFIDENTIAL DO NOT COPY
Page 5-1 File No. SG-0199
1.2
HDMI Connector a. Frequency: H: 15.734KHz V: 60Hz H: 31KHz V: 60Hz H: 45KHz V: 60Hz H: 33KHz V: 60Hz b. Polarity: c. Type: d. Pin Assignment: Pin 19 Pin 1 Positive or Negative Type A Please see below
Pin 2
Pin 1 3 5 7 9 11 13 15 17 19
Signal Assignment TMDS Data2+ TMDS Data2TMDS Data1 Shield TMDS Data0+ TMDS Data0TMDS Clock Shield CEC SCL DDC/CEC Ground Hot Plug Detect
Pin 2 4 6 8 10 12 14 16 18
Signal Assignment TMDS Data2 Shield TMDS Data1+ TMDS Data1TMDS Data0 Shield TMDS Clock+ TMDS ClockReserved (N.C. on device) SDA +5V Power
CONFIDENTIAL DO NOT COPY
Page 5-2 File No. SG-0199
1.3 AV/Composite Video (CVBS) Connector a. Frequency: b. Signal level: c. Impedance: d. Connector type: 1.4 AV/S-Video Connector H: 15.734KHz 1Vp-p 75 RCA jack V: 60Hz (NTSC) Sync (H+V):0.3V below Video (Y+C)
4 2
3 1
1, 2 = GND 3 = Luminance (Y) 4 = Chrominance(C)
a. Frequency: b. Signal level: c. Impedance: d. Connector type: 1.5 Component video Connector a. Frequency:
H: 15.734KHz Y: 1Vp-p 75 4-pin mini DIN
V: 60Hz (NTSC) C: 0.286Vp-p
H: 15.734KHz H: 31KHz H: 45KHz H: 33KHz
V: 60Hz (NTSC-480i) V: 60Hz (NTSC-480p) V: 60Hz (NTSC-720p) V: 60Hz (NTSC-1080i) Pr: 0.350Vp-p
b. Signal level: c. Impedance: d. Connector type:
Y: 1Vp-p Pb: 0.350Vp-p 75 RCA jack
CONFIDENTIAL DO NOT COPY
Page 5-3 File No. SG-0199
1.6
F-type TV RF connector NTSC system a. Signal level b. Frequency ATSC system a. IF-output level b. Frequency 1Vp-p minimum 57~803 MHz Analog 1Vp-p typical (45tdB~90dB) 55~801 MHz
QAM system (supporting clear QAM) a. IF-output level b. Frequency 1.7 PC Stereo audio a. Signal level: b. Impedance: c. Connector type: 1.8 Video Stereo audio a. Signal level: b. Impedance: c. Frequency response: d. Connector type: 0.7Vrms 47K 250Hz-20KHz RCA L/R 1Vrms 47K 3.5 mini jack 1Vp-p minimum 57~849 MHz
2. Output
2.1 Analog Audio out a. Signal level: b. Impedance: c. Frequency response: d. Connector type: 2.2 Digital audio out a. Peak emission wave length: b. Transmission Speed: c. Connector type: 630 690 m 13.2M pbs Optical fiber transmitter 0.7Vrms 47K 250Hz-20KHz RCA L/R:
CONFIDENTIAL DO NOT COPY
Page 5-4 File No. SG-0199
2.3 Headphone a. Signal level: b. Impedance: c. Output: d. Connector type: 1Vrms (max.) 32 50 mW Earphone mini jack
3. Acoustic
3.1 Connection 3.1.1 Left Acoustic: Speaker connector (5-pin audio din) connected to the speaker box with 2" x 5" 8 /10 W speaker 3.1.2 Right Acoustic: Speaker connector (5-pin audio din) connected to the speaker box with 2" x 5" 8 /10 W & 4" 8 /20W speakers 3.2 Acoustic performance 3.2.1 Wide Range a. Frequency response: 250Hz-20KHz ± 3 dB b. Signal/Noise rate > 60 dB c. Output Power: 10W rms THD 10% with 2" x 5" 8 /10 W speaker 3.2.2 Sub-woofer a. Frequency response: 20Hz-250Hz ± 3 dB b. Signal/Noise rate > 60 dB c. Output Power: 20W rms THD 10% with 4" 8 /20 W speaker
CONFIDENTIAL DO NOT COPY
Page 5-5 File No. SG-0199
Chapter 6
Block Diagram
System Block Diagram
LVDS BOARD
INVERTER BOARD INVERTER BOARD
POWER BOARD
AUDIO BOARD
W1
CN5
CN3 CN1
J11
J2
MAIN BOARD W2 J4
IR BOARD
AC CORE
CONFIDENTIAL DO NOT COPY
Page 6-1 File No. SG-0199
Main board System Block Diagram
ARXD ATXD U60 TS5V330 SW ATXD_HUD ARXD_HUD
VEDIO
U40 24LC128 EEPROM(8051)
UC_SCL/UC_SDA
U38 SST89C58
U20 4052 I/O SW
51_RXD/51_TXD
HY5DU56822CT-D4 U17 DDR RAM CTZ
HY5DU56822CT-D4 U16 DDR RAM HUD LED BLACKLIGHT J12
FL8532_CTZ
Frame Store DDR Interface ADATA[0:23] W8 51_RXD/51_TXD ARXD ATXD Frame Store DDR Interface CN5 KEY PAD + IR
U42 Sil 9011 HDMI RS
UART 2 Wire Controller SCL-33V / SDA-33V U25 F75373S MSTR0_SCL/MSTR0_SDA
CN12
IPCLK0/AHS/AVS/AHREF_DE HDMI1 AUDIO
CN13 IPCLK0/AHS/AVS/AHREF_DE IPCLK1/BHS/BVS/BDE GPIO 2 Wire Controller 2 Wire Controller
CN17 U37 24LC02 EEPROM HDMI1
BDATA[0:23]
U35 Sil 9011 HDMI RS
MSTR2_SCL/MSTR2_SDA IPCLK1/BHS/BVS/BDE HDMI2 AUDIO MSTR1_SCL/MSTR1_SDA
VGA_SCL / VGA_SDA
VGA_SCL / VGA_SDA ADATA[0:23] BDATA[0:23] Digital A Input Digital B Input LVDS Display Interface
W1
Display
W13
ANLOG DDC
U21 24LC02 EEPROM VGA AIR_RAW_HS_CS/AIR_RAW_VS SV4_CTZ SV2_CTZ SV3_CTZ/A1_CTZ B1_CTZ/C1_CTZ A4/B4/C4_CTZ A3/B3/C3_CTZ A2/B2/C2_CTZ
U40 24LC02 EEPROM HDMI2
VS / HS
U45 74HCT14 Inverting Schmitt Trgger
Analog input
CN16
R G B
A4/B4/C4
U22 M61323FP VEDIO SW
JTAG_BS_TCK/TDO/TMS/TDI/TRST NTSC CVBS(SV1_HUT)
JTAG Boundary Scan
OCM External SRAM
XU1 A29LV320D MEMERY_CTZ
W6 ATSC Y Pr Pb
U23 M61323FP VEDIO SW
A3/B3/C3_CTZ
MSTR1_SCL/MSTR1_SDA
2 Wire Controller JTAG Boundary Scan
NC7SB3157 U18 BUS SW
Y Pr Pb Y Pr Pb W7
U24 M61323FP VEDIO SW
A3/B3/C3_HUD
JTAG_BS_TCK/TDO/TMS/TDI/TRST
ATXD_HUD ARXD_HUD
UART
I2CCM
U11 24LC32 EEPROM HUD
A2/B2/C2 COMP1_Audio_R/L COMP2_Audio_R/L W11 AudioAV1_R/L
AIR_RAW_HS_CS/AIR_RAW_VS A4/B4/C4_HUD A3/B3/C3_HUD A2/B2/C2_HUD SV4_HUD SV2_HUD SV3_HUD/A1_HUD B1_HUD/C1_HUD
Serial ROM Interface Analog input
U12 SST25VF040 FLASH 512K HUD
IPCLK1/BHS/BVS/BDE CVBS1 CVBS2 BDATA[0:23] W14 AudioAV2_R/L NTSC CVBS(SV1_CTZ)
GPIO
LVDS Display Interface
FL8125_HUD
W10 Y1/C1 Y2/C2
U43 CS3443 HDMI1 LR DAC
AUDIO
U36 CS3443 HDMI2 LR DAC
U46 IDTQS3253 HDMI2 AUDIO SW
U42 IDTQS3253 HDMI1 AUDIO SW HDMI1_AUDIO_L/R HDMI2_AUDIO_L/R AudioAV1_R/L AudioAV1_R/L
MSTR2_SCL/MSTR2_SDA SUBWoofer
U33 PT2308 AUDIO DRIVER
W5
VGA_AUDIO_L/R
U48 TS5V330 AUDIO SW 4/2 I/O U49 TS5V330 AUDIO SW 4/2 I/O
CH4_R/L CH3_R/L
Lineout_R/L
U33 PT2308 AUDIO DRIVER
J11 Audio connect
MP7772 AUDIO_AMP MP7782 AUDIO_AMP
J3 Audio out
U32 P4450G AUDIO PROCESS
CH2_R/L CH1_R/L TUNER SIF
HLIN/HRIN
U34 PT2308 AUDIO DRIVER
W13
COMP1_Audio_R/L COMP2_Audio_R/L VGA_AUDIO_L/R ATSC Audio L/R
J4 Audio out
RCA Lineout_R/L
AUDIO L/R OUT
W12
Headphone
DTV TV
TUNER SIF NTSC CVBS
TV/DTV
TUNER FQD1236/F H-5
ATSC Audio L/R
U9 MT5112
U10 MT5351
ATSC Y Pr Pb
CONFIDENTIAL DO NOT COPY
Page 6-2 File No. SG-0199
Chapter 7 Main/ATSC Board Internal I/O Connections
MAIN Board CN1 "DC POWER INPUT'
PIN 1 2 3 4 5 6 7 8 9 10 11 12 Description PDP_+5Vsc PDP_+5Vsc PDP_+5Vsc GND GND GND PDP_+12V PDP_+12V GND GND PDP_+12V_FAN PDP_FGND
CN2
"DC POWER INPUT'
PIN 1 2 3 4 Description PDP_Audio PDP_Audio GND GND
CN3
"DC POWER INPUT/OUTPUT'
PIN 1 2 3 4 5 Description GND VS_ON RLY_ON PDP_+5Vsb BRIGHT Page 7-1 File No. SG-0199
CONFIDENTIAL DO NOT COPY
CN5
CONNECTION
"KEYPAD"
PIN 1 2 3 4 5 6 7 8 9 10 P1 P2 Description LED2_KEYPAD KEY_VCC IR ADC_IN2 NC GND +3.3V_LBADC ADC_IN1 LED1_KEYPAD_BUF GND GND GND
CN6
CONNECTION "HDMI/ATSC_UP"
PIN 1 2 3 4 Description +5V 51_TXD 51_RXD GND
CN7
CONNECTTION "ODC2BI"
PIN 1 2 3 Description VGA_SCL_CTZ VGA_SDA_CTZ GND
CONFIDENTIAL DO NOT COPY
Page 7-2 File No. SG-0199
CN12
FAN CONNECTION
PIN 1 2 3 4 Description NC FANIN1 +12V_FAN FGND
CN13
FAN CONNECTION
PIN 1 2 3 Description FANIN1 +12V_FAN FGND
J11
CONNECTION "AUDIO BOARD"
PIN 1 2 3 4 5 6 7 Description AUDIO_EXT_R GND AUDIO_EXT_L MUTE_AMP AUDIO_SUB GND GND
CONFIDENTIAL DO NOT COPY
Page 7-3 File No. SG-0199
W1
CONNECTION "LVDS"
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Description GND TXA3TXACTXA2+ TXA1+ TXA0+ GND +5V_SW +5V_SW GND NC NC TXB3VS_ON SDA_33V GND PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Description TXA3+ TXAC+ GND TXA2TXA1TXA0GND +5V_SW GND NC NC TXB3+ GND SCL_33V NC
CONFIDENTIAL DO NOT COPY
Page 7-4 File No. SG-0199
W1
CONNECTION "ATSC BOARD"
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Description GND ATSC_CLK GND ATSC_WS GND ATSC_DA GND ATSC_Y GND ATSC_Pb GND ATSC_Pr N/C +12V_SW +12V_SW +5V_SW +5V_SW +5V_SW +5V_SW +5V_SW PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Description SCL_5V SDA_5V ATSC_RST ATSC_RDY GND SV1_CTZ / SV1_HUD GND N/C GND SIF_Tuner1 GND SIF_Tuner2 N/C ATSC_Audio_L ATSC_Audio_R ATSC_TX ATSC_RX CHKTNR0 +8V +8V
J3
SELECT KEY POWER
PIN 1-2 2-3 Description +3.3V_I/O +5V Default ON OFF
ON"
ADD JUMPER
, "OFF" NO JUMPER
CONFIDENTIAL DO NOT COPY
Page 7-5 File No. SG-0199
ATSC Board W1 CONNECTION "MAIN BOARD"
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Description GND A01MICLK/A01BLK GND A01LRCK GND A01SDATA0 GND MAIN-YOUT GND MAIN-PbOUT GND MAIN_PrOUT HDMI-SPDIF +12V_SW +12V_SW N/C N/C N/C N/C N/C PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Description Tuner-SCL2 Tuner-SDA2 ORESET READY GND NTSC-CVB1 GND N/C GND NTSC-SIF GND N/C SPDIF-Ctrl Audio_LCHOUT Audio_RCHOUT U2TX U2RX Tuner SW N/C N/C
J10
CONNECTION "ATSC POWER"
PIN 1-3 4-5 Description GND +12V
CONFIDENTIAL DO NOT COPY
Page 7-6 File No. SG-0199
AUDIO Board J1 CONNECTION "MAIN BOARD"
PIN 1 2 3 4 5 6 7 Description AUDIO_EXT_R GND AUDIO_EXT_L MUTE_AMP AUDIO_SUB GND GND
J4
CONNECTION "POWER BOARD"
PIN 1 2 3 4 Description 24V 24V GND GND
J3
CONNECTION "SPEAKER L"
PIN 1 2 Description LOUT GND
CONFIDENTIAL DO NOT COPY
Page 7-7 File No. SG-0199
J1
CONNECTION "SPEAKER R"
PIN 1 2 3 4 5 6 Description ROUT GND SWOUT SWOUT SWOUT SWOUT
CONFIDENTIAL DO NOT COPY
Page 7-8 File No. SG-0199
Chapter 8
Theory of Circuit Operation
The operation of User Interface
The following diagram provides a brief overview of the user-interactive components of the firmware.
Figure 8-1 User Interface Block Diagram
The operation of keypad
There are 7 keys to control and select the function of SHD-3010 and also have two LED to indicate the status of operation. They are "Power , Menu , Ch+/ , Ch-/ , Vol+/ , Vol-/ , Input" keys and LED. 1.The power key controls video processor FLI8532, FLI8532 will receive a low signal to turn on or off system while press the power key. 2.The other seven keys are on high state because the pull up resistor but will transit to low state dependent on which key pressed, and the state will be reader by FLI8532 through internal ADC to act corresponding function. 3.The LED is constructed with two color LED which color is White and Orange. The FLI8532 direct control the LED's when FLI8532 (VPCON) is low the LED is Orange (Close power) when FLI8532 (VPCON) is high the LED is White (Open power).
CONFIDENTIAL DO NOT COPY
Page 8-1 File No. SG-0199
The operation of Video Processor FLI8532
The Genesis Microchip FLI8532 includes an integrated 3-D Digital Video Decoder with Faroudja DCDi CinemaTM video format conversion, video enhancement, and noise reduction. The auto-detection and Faroudja DCDi CinemaTM technology allow the FLI8532 to detect, process, and enhance any video or PC graphic format. The FLI8532 supports many worldwide VBI standards for applications of Teletext, Closed Captioning, V-Chip, and other VBI technologies.
Figure 8-2 FLI8532 Block Diagram
Clock Generation:
The FLI8532 features six clock inputs. All additional clocks are internal clocks derived from one or more of these: 1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. A 19.6608 MHz TV crystal is recommended for best noise immunity with the 3D decoder. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin (leave XTAL as N/C in this case). If an external crystal is being used, connect a 10K pull-up to OCMADDR_19. See Figure 9. 2.Digital Input Video/Graphics Clocks (IPCLK0, IPCLK1, IPCLK2 and IPCLK3) 3.Audio Delay Clock (AVS_CLK) The FLI8532 TCLK oscillator circuitry is a custom designed circuit to support the use of an external oscillator or a crystal resonator to generate a reference frequency source for the FLI8532device.
CONFIDENTIAL DO NOT COPY Page 8-2 File No. SG-0199
Analog Input Port (AFE):
The FLI8532 chip has a sophisticated Analog Front End with 16 reconfigurable inputs through and analog multiplexer to anti-alias filters before the Analog to Digital Converters (ADCs). These integrated features eliminate the need for any devices between the input connector and the pin of the FLI8532.
Figure 8-3
Analog Front End
The figure above depicts the data-path for the AFE and Decoder blocks with connections to the input multiplexer that selects whether the data follows the Main Video Channel or PIP video channel. The analog front end of FLI8532 provides the capability to capture 16 analog video inputs which can be a combination of Composite (CVBS), S-Video (SY, SC), YPrPb (Y, Pr, Pb) or RGB (R,G, B).
Digital Input Port (DFE):
The Digital Input Port is a 48bit data input with flexible configuration to support a wide range of digital sources. It consists of two 24bit ports (PORTA and PORTB), two sets of control signals (VS, HS, ODD, etc.), and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these inputs are 8bit CCIR656.
CONFIDENTIAL DO NOT COPY
Page 8-3 File No. SG-0199
PORTA also includes optional signals (DIP_EXT_CLAMP, DIP_EXT_COAST, DIP_CLEAN_HS_OUT) for interfacing to external ADC/PLL devices. These signals are not present on PORTB. Bits 7 to 0 of PORTA can be configured as a bidirectional interface for media card applications. Inputs to the digital input port are TTL compatible with a maximum clock speed of 135MHz. Sync and clock polarity is programmable. Due to pin sharing, PORTB is not available when using 48bit double wide TTL output to the panel. The following digital video formats are supported by FLI8532 digital video graphic port: · ITU-BT-656 · 8-bit 4:2:2 YCbCr or YPbPr · 16-bit 4:2:2 YCbCr or YPbPr · 24-bit 4:4:4 YCbCr or YPbPr · 24-bit RGB
Digital Input Port Configuration:
The Digital Input Port offers flexible mapping of the input buses for PORTA and PORTB and allows individual Bus Flipping (MSB to LSB) for each group of 8bit inputs. The purpose of this flexible mapping is to ease the circuit board design when interfacing to other devices. This table below shows how the input DATA buses can be arbitrarily assigned through host registers.
Figure 8-4 Digital Input DATA bus assignment
CONFIDENTIAL DO NOT COPY
Page 8-4 File No. SG-0199
LVDS Transmitter:
Two LVDS channels (A and B) are available on the output of the FLI8532 to transmit data and timing information to the display device. The following diagram shows the available LVDS mapping for 30-bit LVDS output which is applying to PDP panel spec:
30-bit LVDS Output Stream
To Configure for 30-bit LVDS with this data mapping: LVDS_POWER (0x8726) = 0x3F LVDS_DIGITAL_CTRL (0x8728) = 0bUU00UU00, where U is user options. DISPLAY_CONTROL(0x862C)[11] = 1 For 30-bit LVDS, the following bus remappings are supported: Swap LVDS serial stream (6:0) (0:6) with register 0x8728[7]
Swap LVDS positive and negative differential outputs with register 0x8728[3] Swap LVDS bus data CH0_EVEN C3_ODD and CH1_EVEN 0x8728[2] Note: OSD OVL data bit is enabled with register 0x8500[9] with polarity controlled by 0x8500[10]. If 0x8500[9] = 0, then OSD OVL LVDS bit is clamped to 0.
CONFIDENTIAL DO NOT COPY Page 8-5 File No. SG-0199
C3_EVEN with register
On Chip Microcontroller:
The FLI8532 on-chip micro-controller (OCM) serves as the system micro-controller. It programs the FLI8532 and manages other devices in the system such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a 22-bit address space to utilize 4 MB external ROM
Figure 8-5 FLI8532 OCM block diagram The OCM executes a firmware program running from external ROM, as well as driver-level (or Application Programming Interface API) functions residing in internal ROM. This is illustrated above. A parallel port with separate address and data busses is available for this purpose. This port connects directly to standard, commercially available ROM or programmable Flash ROM devices in either 8 or 16-bit configurations. External Flash-ROM memory requirements range from 512Kbytes to 4Mbytes depending on the application. Both firmware and OSD content must be compiled into a HEX file and then loaded onto the external ROM. The OSD content is generated using Genesis Workbench. Genesis Workbench is a GUI based tool for defining OSD menus, navigation, and functionality.
FLI8532 I2C Master Serial Protocol :
The two-wire protocol consists of a serial clock MSTR_SCL and bi-directional serial data line MSTR_SDA. The FLI8532 acts as bus master and drives MSTR_SCL and either the master or slave can drive the MSTR_SDA line (open drain) depending on whether a read or write operation is being performed. There are three isolated Master Serial busses, all driven by a common Master Serial Controller. These busses can be independently taken "off-line" or pulled up to different voltages without affecting the other busses.
CONFIDENTIAL DO NOT COPY Page 8-6 File No. SG-0199
The two-wire protocol requires each slave device to be addressable by a 7-bit identification number. A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to-high transition on MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).
Figure 8-6 Two-Wire Protocol Data Transfer Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. bytes). The number of bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the most significant bit (MSB) first. After the eight data bits, the master releases the MSTR_SDA line and the receiver asserts the MSTR_SDA line low to acknowledge receipt of the data. The master device generates the MSTR_SCL pulse during the acknowledge cycle. The addressed receiver is obliged to acknowledge each byte that has been received.
The operation of Video Processor FLI8125
FLI8125 is another video processor designed by Genesis. In this product, we use FLI8125 to process most of PIP source input and then output digital video signal to FLI8532.
Figure 8-7 FLI8125 System Block Diagram
CONFIDENTIAL DO NOT COPY Page 8-7 File No. SG-0199
Clock Generation
The FLI8125 accepts the following input sources: 1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. Alternatively, a single ended TTL/CMOS clock input can be driven into the XTAL pin (leave TCLK as n/c in this case). 2.External Clocks on various GPIOs for test purposes 3.Host Interface Transfer Clock (SCL), I2C slave SCL for DDC2Bi and another SCL for Serial Inter-Processor Communication (SIPC) 4.Video Port VCLK 5.Second Video port clock. This is shared with ROM Address line 11. This is available only when parallel ROM interface is not used.
Clock Synthesis
Additional synthesized clocks using PLLs: 1.Main Timing Clock (T_CLK) is the output of the chip internal crystal oscillator. T_CLK is derived from the TCLK/XTAL pad input. 2.Reference Clock (R_CLK) synthesized by RCLK PLL using T_CLK or EXTCLK as the reference. 3.Input Source Clock (SCLK) synthesized by SDDS PLL using input HS as the reference. In case of analog composite video input this runs in open loop. The SDDS also uses the R_CLK to drive internal digital logic. 4.Display Clock (DCLK) synthesized by DDDS PLL using IP_CLK as the reference. The DDDS also uses the R_CLK to drive internal digital logic. 5.Fixed Frequency Clock (FCLK) synthesized by FDDS. Used as OCM_CLK domain driver. 6.Extended Clock (ECLK) synthesized by EDDS. Used by the decoder. 7.A fixed frequency clock created by LDDS (LCLK). Used by the expander in case of panoramic scaling.
CONFIDENTIAL DO NOT COPY
Page 8-8 File No. SG-0199
Figure 8-8 FLI8125 Internally Synthesized Clocks
Analog Front End
The Analog Front End is responsible for selecting and capturing the desired analog input video stream. Overall application cost is reduced by providing analog switching capabilities for 16 separate analog signals. These signals are re-configurable as different combinations of composite, S-Video, YPrPb and RGB video streams depending upon the end application. The Analog Front End directs inputs through an analog multiplexer to anti-alias filters before the Analog to Digital Converters (ADCs). These integrated features eliminate the need for any devices between the input connector and the AFE pin connection. The following figure depicts the data-path for the AFE and Decoder blocks with connections to the input multiplexer .
CONFIDENTIAL DO NOT COPY
Page 8-9 File No. SG-0199
Figure 8-9 Analog Input Port The Analog Front End provides the capability to capture 16 analog video inputs which can be a combination of Composite (CVBS), S-Video (SY, SC), YPrPb (Y, Pr, Pb) or RGB (R, G, B). The Analog Source Selectors are responsible for switching the desired analog inputs to the ADCs for digitization. There are two types of switching required: Channel Selection, Fast Blank Switching.
Digital Front End (Digital Processing after AFE)
The DFE consists of 3 channels that can support the following Fixed-position formats: Channels 1, 2 and 3 can be either R,G,B, or Y,U,V or 2 channels of Y and C or one channel of CVBS. The DFE performs Digital Clamp Loop Control for each channel, AGC Control, Color Conversion, Chroma Downscaling and 4fSC re-sampling. The Input to the DFE is 10 bit 40MHz Data. The Output is 4fsc Sampled CVBS, Y, C or YUV or just 10 bit CVBS.
CONFIDENTIAL DO NOT COPY
Page 8-10 File No. SG-0199
Figure 8-10
Digital Datapath
Digital Input Port
The Digital Input Port is 24-bit input bus that can be connected to external DVI receivers, video decoders, etc. and is able to accept either 8-bit CCIR656 data, 16-bit 4:2:2 YUV data or 24-bit RGB data. For RGB input data, a selectable color space converter is used to transform RGB video input data from a DVI Rx to internal 16-bit 4:2:2 YUV. This allows the input data to be processed by the Horizontal Enhancment Module (HEM), ACC, and ACM in the image processing block. Other RGB input data streams, such as computer inputs, remain in the RGB space and are processed as such. The 24-bit Digital Input Port provides control signals to simplify signal detection. CCIR656 data streams embedd all timing markers, for the 24-bit and 16-bit inputs the following signals are provided: CLK1 Input pixel clock for 24-bit, 16-bit or CCIR656 inputs HS/CSYNC Horizontal sync or composite sync signal VS/SOG Vertical sync input or SOG input DV/CLAMP Data valid input indicator NOTE: Unused pins of the Digital Input Port can be reprogrammed as GPIOs to increase the total number of GPIOs available. Inputs to the digital input port are TTL compatible with a maximum clock speed of 135MHz. Sync and clock polarity is programmable.
CONFIDENTIAL DO NOT COPY Page 8-11 File No. SG-0199
Input Capture
The Input Capture block is responsible for extracting valid data from the input data stream and creating the required synchronization signals required by the data pipeline. This block also provides stable timing when no stable input timing exists. The selected input data stream is cropped using a programmable input capture window. Only data within the programmable window is allowed through the data pipeline for subsequent processing. Data that lies outside of the window is ignored.
Figure 8-11
Input Capture Window
Input cropping is required in a video system since video signals are normally over scanned. For a flat panel TV, in order to over scan the image, a smaller portion of the input image needs to be selected and then expanded to fill the entire screen. Input data streams originating from CCIR656 sources are cropped with reference to the start and end of active video flags encoded into the data stream. For all other inputs, the Input Capture Window is referenced with respect to Horizontal and Vertical Sync.
CONFIDENTIAL DO NOT COPY
Page 8-12 File No. SG-0199
Image Processing
The following figure shows the various image processing blocks that operate on the captured video data stream. Each block is individually selectable and can be removed from the processing chain via a selectable bypass path. When a processing block is bypassed, it automatically enters a low power mode to help reduce overall power consumption.
Figure 8-12
Imange Processing Block Diagram
Faroudja DCDi Edge Processing
Faroudja DCDi Edge processing is used to reduced/eliminate objectionable stair stepping that occurs on interlaced diagonal lines. DCDi Edge processing is optimized for a memory architecture that is unified with the memory used for scaling. This block can process 24-bit RGB, 16-bit 4:2:2 YUV or 16-bit 4:2:2 YPrPb data streams.
Scaling Engine
The Scaling Engine accepts both 16-bit 4:2:2 YUV and 24-bit RGB inputs. It is capable of scaling the input by a factor of 0.05 to 5.0. A flexible tap structure is used so that the number of taps can be increased based on the number of pixels per line and whether the input is 4:2:2 YUV or 4:4:4 RGB. To reduce the amount of memory required for the vertical scaling process, horizontal shrink is performed prior to vertical scaling and horizontal expansion happens after vertical scaling. The maximum number of pixels per line supported by the vertical scalar is 1366.
CONFIDENTIAL DO NOT COPY
Page 8-13 File No. SG-0199
Display Output Interface
The Display Output Port provides data and control signals that permit the connection to a variety of flat panel devices using a 24-bit TTL or LVDS interface. The output interface is configurable for single or dual wide LVDS in 18 or 24-bit RGB pixels format. All display data and timing signals are synchronous with the DCLK display clock. The integrated LVDS transmitter is programmable to allow the data and control signals to be mapped into any sequence depending on the specified receiver format. DC balanced operation is supported as described in the Open LDI standard. Output timing is fully programmable via the host interface register set enabling this device to be used as a display controller of a PIP processor for other Genesis Microchip devices. The following display synchronization modes are supported: standard operation. Frame Sync Mode: The
display frame rate is synchronized to the input frame or field rate. This mode is used for Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display timing is determined only by the values programmed into the display window and timing registers.
Display Timing Programming
Horizontal values are programmed in single-pixel increments relative to the leading edge of the horizontal sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical sync signal.
CONFIDENTIAL DO NOT COPY
Page 8-14 File No. SG-0199
Figure 8-13 Display Windows and Timing
Data captured by the Input Capture Window and processed by the various image manipulation blocks is output in the Display Active Window. This window is always in the foreground and lies on top of all other output windows, except OSD overlay windows. Typically the Display Active Window is set to the same size as the output of the Scaling Engine. If the Display Active Window is set too small, then the bottom and right hand edges of the image data are cropped. If the Display Active Window is set too large, then the extra space to the left and bottom of the Display Active Window is forced to the Background Window color. Output Dithering The CLUT outputs a 10-bit value for each color channel. This value is
dithered down to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels. In this way it is possible to display 16.7 million colors on a LCD panel with 6-bit column drivers.
CONFIDENTIAL DO NOT COPY
Page 8-15 File No. SG-0199
The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image free of contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both spatially and temporally. Two dithering algorithms are available: random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel. All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).
Dual Channel LVDS Transmitter
An integrated LVDS transmitter with programmable input to output configuration is provided to enable drive of all known panels. The LVDS transmitter can support the following: Single pixel mode 24-bit panel mapping to the LVDS channels 18-bit panel mapping to the LVDS channels Programmable channel swapping (the clocks are fixed) Programmable channel polarity swapping Supports up to SXGA 75Hz output
On-Chip Microcontroller (OCM)
The on-chip microcontroller (OCM) is a 16-bit x86 100MHz processor capable of acting as either the overall system controller or a slave controller, receiving commands from an external controller. The OCM executes firmware running from external ROM, as well as driver-level (or Application Programming Interface API) functions residing in internal ROM. A parallel port with separate address and data busses is available for this purpose. This port connects directly to standard, commercially available ROM or programmable FLASH ROM devices. A serial FLASH ROM may be used with the serial peripheral interface (SPI) and cache controller inside the Genesis device. Both firmware and OSD content must be compiled into a HEX file and then loaded onto the external ROM. The OSD content is generated using Genesis Workbench. Genesis Workbench is a GUI based tool for defining OSD menus, navigation, and functionality.
CONFIDENTIAL DO NOT COPY
Page 8-16 File No. SG-0199
Figure 8-14
FLI8125 OCM Programming
The operation of HDMI Sil9011
The SiI 9011 provides one HDMI input port. The SiI 9011 video output goes to a video processor while the audio output goes to an audio DAC.
CONFIDENTIAL DO NOT COPY
Page 8-17 File No. SG-0199
Figure 8-15 HDMI 9011 Block Diagram
TMDS Digital Core
The core performs 10-to-8-bit TMDS decoding on the audio and video data received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link clock rates to 165MHz, including CE modes to 720p/1080i/1080p and PC modes to XGA, SXGA and UXGA.
Active Port Detection
The PanelLink core detects an active TMDS clock and detects an actively toggling DE signal. These states are accessible in register bits, useful for monitoring the status of the HDMI input or for automatically powering down the receiver. The +5V supply from the HDMI connector is used as a cable detect indicator. The SiI 9011 can monitor the presence of this +5V supply and, if and when necessary, provide a fast audio mute without pops when it senses the HDMI cable pulled. The microcontroller can also poll registers in the SiI9011 to check whether an HDMI cable is connected.
CONFIDENTIAL DO NOT COPY
Page 8-18 File No. SG-0199
Data Input and Conversion Mode Control Logic
The mode control logic determines if the decrypted data is video, audio or auxiliary information, and directs it to the appropriate logic block.
Video Data Conversion and Video Output
The SiI 9011 can output video in many different formats (see examples in Table 2). The receiver can also process the video data before it is output, as shown in Figure 5. Each of the processing blocks may be bypassed by setting the appropriate register bits. (See page 38 for a more detailed path diagram.)
Figure 8-16
HDMI Video Processing Path
Color Range Scaling
The color range depends on the video format, according to the CEA-861B specification. In some applications the 8-bit input range uses the entire span of 0x00 (0) to 0xFF (255) values. In other applications the range is scaled narrower. The receiver cannot detect the incoming video data range, and there is no required range specification in the HDMI AVI packet. Therefore the receiver's firmware will have to program the scaling depending on the detected video format. Refer to the SiI 9011 Programmer's Reference (SiI-PR-0006) for more details. When the receiver outputs embedded syncs (SAV/EAV codes), it also limits the YCbCr output values to 1 to 254.
Figure 8-17
CONFIDENTIAL DO NOT COPY
Digital Video Output Formats
Page 8-19 File No. SG-0199
The operation of TV route
TV signal is processes to the tuner and output toMTK8205 the MTK8205 generates the vertical and horizontal timing signals for display device. Audio is processes to the tuner output to SIF circuit and output to 4450.
The operation of DTV route
DTV signal is processes to the tuner and output to MT5112 who handle ATSC input to match MPEG-2 package, then transfer to MT5351. After passing through decoder, the signal will be with the YPbPr. The signal by way of Switch to chip FL8532-LF
CONFIDENTIAL DO NOT COPY
Page 8-20 File No. SG-0199
Chapter 9
1. Ripple Voltage
Waveforms
(1) PDP_+5Vsc (CN1.1)
(2) PDP_+12V (CN1.7)
CONFIDENTIAL DO NOT COPY
Page 9-1 File No. SG-0199
(3) PDP_+5Vsb (CN3.4)
(4) FLI8125 (U10) +3.3V_I/O_HUD
CONFIDENTIAL DO NOT COPY
Page 9-2 File No. SG-0199
+3.3V_ADC_HUD
+1.8V_ADC_HUD
CONFIDENTIAL DO NOT COPY
Page 9-3 File No. SG-0199
(5) FLI8532 (U13) +3.3V_I/O
+1.8V_ADC
CONFIDENTIAL DO NOT COPY
Page 9-4 File No. SG-0199
+2.5V_DDR
+1.8V_CORE
CONFIDENTIAL DO NOT COPY
Page 9-5 File No. SG-0199
(6) NT5DS16M16CS-5T (U16, U17)
(7) Am29LV320DT90-ED (XU1)
CONFIDENTIAL DO NOT COPY
Page 9-6 File No. SG-0199
(8) LM2660 (-5V_N of the U29)
CONFIDENTIAL DO NOT COPY
Page 9-7 File No. SG-0199
2. Clock Timing (1) NT5DS16M16CS-5T DDR clock (pin 45 of the U16 or U17)
(2) FLI8125 Crystal clock (pin 15 of the U10)
CONFIDENTIAL DO NOT COPY
Page 9-8 File No. SG-0199
Hudson output clock
(3) FLI8532 Crystal clock (pin B26 of the U13 or pin 1 of the C155) Cortze output clock
CONFIDENTIAL DO NOT COPY
Page 9-9 File No. SG-0199
(4) MSP4450G crystal clock (pin 55 of the U32)
CONFIDENTIAL DO NOT COPY
Page 9-10 File No. SG-0199
(5) SiI9011CLU crystal clock (pin 84 of the U35 and U42)
(6) IC SM5964C40J crystal clock (pin 20 of the U38)
CONFIDENTIAL DO NOT COPY
Page 9-11 File No. SG-0199
3. Horizontal and Vertical sync. Timing (1) VGA input (1024x768x60Hz) H-sync
CONFIDENTIAL DO NOT COPY
Page 9-12 File No. SG-0199
V-sync
CONFIDENTIAL DO NOT COPY
Page 9-13 File No. SG-0199
(2) SiI9011CLU (U35 and U42) CLK
BHS-sync
CONFIDENTIAL DO NOT COPY
Page 9-14 File No. SG-0199
BVS-sync
CONFIDENTIAL DO NOT COPY
Page 9-15 File No. SG-0199
CONFIDENTIAL DO NOT COPY
Page 9-16 File No. SG-0199
ATSC Board
1. Voltage Measurement (1) 12V (+12V, C4)
(2) 5V (+5V, C239)
CONFIDENTIAL DO NOT COPY
Page 9-17 File No. SG-0199
(3) 3.3V (DV33, C11)
(4) 2.5V (DV25, C185)
CONFIDENTIAL DO NOT COPY
Page 9-18 File No. SG-0199
(5) 1.8V (DV18, C64)
(6) 1.25V (+1V25_DDR, C148)
CONFIDENTIAL DO NOT COPY
Page 9-19 File No. SG-0199
(7) 1.2V (DV12, C26)
CONFIDENTIAL DO NOT COPY
Page 9-20 File No. SG-0199
2. Clock Timing
(1) MT5351 Clock Timing (U10 B2-OXTALI)
(2) MT5112 Clock Timing (U9 97-XTAL1 / 96-XTAL2) Ch1 XTAL1 / Ch2 XTAL2
CONFIDENTIAL DO NOT COPY
Page 9-21 File No. SG-0199
(3) Memory Clock Timing (U13-45, MEM_CLKA)
(4) Memory Clock Timing (U12-45, MEM_CLKA)
CONFIDENTIAL DO NOT COPY
Page 9-22 File No. SG-0199
Chapter 10 Trouble Shooting
A. SYSTEM OVERVIEW
Iverter board Power supply board Iverter board
AUDIO board
Main board
Display board
IR board ATSC Board
CONFIDENTIAL DO NOT COPY
Page10-1 File No. SG-0199
B. PCB PARTS NAME/NUMBER AND FUNCTION DESCRIPTION
PART NAME POWER SUPPLY BOARD PART NUMBER FUNCTION DESCRIPTION PROVIDE ALL THE POWER FOR TV SET
MAIN BOARD
364600120150
CONNECTING TO TRANSFER DISPLY SIGNAL TO PDP SET, AMPLIFIER THE AUDIO SIGNAL TO THE SPEAKER
IR BOARD
364600120189 364600120156 364600120190 364600120137
RECEIVE THE REMOTE CONTROLER AND DISPLAY SYSTEM STATUS LED
DISPLAY BOARD ATSC BOARD AUDIO BOARD
KEYPAD FUNCTION FOR MANUAL OPERATE TV
DTV/TV MODLE
C. BOARD PICTURE
MAIN BOARD
CONFIDENTIAL DO NOT COPY
Page10-2 File No. SG-0199
DISPLAY BOARD
IR BOARD
CONFIDENTIAL DO NOT COPY
Page10-3 File No. SG-0199
ATSC BOARD
AUDIO BOARD
CONFIDENTIAL DO NOT COPY
Page10-4 File No. SG-0199
PDP DISPLAY NOTHING
1. Main board & ATSC board block diagram
ARXD ATXD U60 TS5V330 SW ATXD_HUD ARXD_HUD
VEDIO
U40 24LC128 EEPROM(8051)
UC_SCL/UC_SDA
U38 SST89C58
U20 4052 I/O SW
51_RXD/51_TXD
HY5DU56822CT-D4 U17 DDR RAM CTZ
HY5DU56822CT-D4 U16 DDR RAM HUD LED BLACKLIGHT J12
FL8532_CTZ
Frame Store DDR Interface ADATA[0:23] W8 51_RXD/51_TXD ARXD ATXD Frame Store DDR Interface CN5 KEY PAD + IR
U42 Sil 9011 HDMI RS
UART 2 Wire Controller SCL-33V / SDA-33V U25 F75373S MSTR0_SCL/MSTR0_SDA
CN12
IPCLK0/AHS/AVS/AHREF_DE HDMI1 AUDIO
CN13 IPCLK0/AHS/AVS/AHREF_DE IPCLK1/BHS/BVS/BDE GPIO 2 Wire Controller 2 Wire Controller
CN17 U37 24LC02 EEPROM HDMI1
BDATA[0:23]
U35 Sil 9011 HDMI RS
MSTR2_SCL/MSTR2_SDA IPCLK1/BHS/BVS/BDE HDMI2 AUDIO MSTR1_SCL/MSTR1_SDA
VGA_SCL / VGA_SDA
VGA_SCL / VGA_SDA ADATA[0:23] BDATA[0:23] Digital A Input Digital B Input LVDS Display Interface
W1
Display
W13
ANLOG DDC
U21 24LC02 EEPROM VGA AIR_RAW_HS_CS/AIR_RAW_VS SV4_CTZ SV2_CTZ SV3_CTZ/A1_CTZ B1_CTZ/C1_CTZ A4/B4/C4_CTZ A3/B3/C3_CTZ A2/B2/C2_CTZ A4/B4/C4
U40 24LC02 EEPROM HDMI2
VS / HS
U45 74HCT14 Inverting Schmitt Trgger
Analog input
CN16
R G B
U22 M61323FP VEDIO SW
JTAG_BS_TCK/TDO/TMS/TDI/TRST NTSC CVBS(SV1_HUT)
JTAG Boundary Scan
OCM External SRAM
XU1 A29LV320D MEMERY_CTZ
W6 ATSC Y Pr Pb
U23 M61323FP VEDIO SW
A3/B3/C3_CTZ
MSTR1_SCL/MSTR1_SDA
2 Wire Controller JTAG Boundary Scan
NC7SB3157 U18 BUS SW
Y Pr Pb Y Pr Pb W7
U24 M61323FP VEDIO SW
A3/B3/C3_HUD
JTAG_BS_TCK/TDO/TMS/TDI/TRST
ATXD_HUD ARXD_HUD
UART
I2CCM
U11 24LC32 EEPROM HUD
A2/B2/C2 COMP1_Audio_R/L COMP2_Audio_R/L W11 AudioAV1_R/L
AIR_RAW_HS_CS/AIR_RAW_VS A4/B4/C4_HUD A3/B3/C3_HUD A2/B2/C2_HUD SV4_HUD SV2_HUD SV3_HUD/A1_HUD B1_HUD/C1_HUD
Serial ROM Interface Analog input
U12 SST25VF040 FLASH 512K HUD
IPCLK1/BHS/BVS/BDE CVBS1 CVBS2 BDATA[0:23] W14 AudioAV2_R/L NTSC CVBS(SV1_CTZ)
GPIO
LVDS Display Interface
FL8125_HUD
W10 Y1/C1 Y2/C2
U43 CS3443 HDMI1 LR DAC
AUDIO
U36 CS3443 HDMI2 LR DAC
U46 IDTQS3253 HDMI2 AUDIO SW
U42 IDTQS3253 HDMI1 AUDIO SW HDMI1_AUDIO_L/R HDMI2_AUDIO_L/R AudioAV1_R/L AudioAV1_R/L
MSTR2_SCL/MSTR2_SDA SUBWoofer
U33 PT2308 AUDIO DRIVER
W5
VGA_AUDIO_L/R
U48 TS5V330 AUDIO SW 4/2 I/O U49 TS5V330 AUDIO SW 4/2 I/O
CH4_R/L CH3_R/L
Lineout_R/L
U33 PT2308 AUDIO DRIVER
J11 Audio connect
MP7772 AUDIO_AMP MP7782 AUDIO_AMP
J3 Audio out
U32 P4450G AUDIO PROCESS
CH2_R/L CH1_R/L TUNER SIF
HLIN/HRIN
U34 PT2308 AUDIO DRIVER
W13
COMP1_Audio_R/L COMP2_Audio_R/L VGA_AUDIO_L/R ATSC Audio L/R
J4 Audio out
RCA Lineout_R/L
AUDIO L/R OUT
W12
Headphone
DTV TV
TUNER SIF NTSC CVBS
TV/DTV
TUNER FQD1236/F H-5
ATSC Audio L/R
U9 MT5112
U10 MT5351
ATSC Y Pr Pb
CONFIDENTIAL DO NOT COPY
Page10-5 File No. SG-0199
LCD DISPLAY NOTHING(Analog HD1/AC on/off default) PDP
Start
No Power LED is lighting? Check AC power cord
Yes
No Power LED is lighting? Press Meun or Info. Is there any OSD's logo No
Yes Check input source
No Check internal cable? 1.LVDS cable. Check W1 pin 27 is high? (Display_ON)
No
Remove R87. Check U13 pin AD14. Is AD14 high?
No U13 fail
Yes No No Power LED is lighting? Check internal cable? 1.CN1's cable 2.CN3's cable Check main board CN3 pin 4 studyby +5V Check CN3 pin 3 RLY_ON(high) Check CN3 pin 2 VS_ON(high) Yse Check CN1 pin 1,2,3 = +5V pin 7,8 = +12V
No Yes Check Fuse open? (F2,F3,F4) Panel power fail
No
No
Fuse fail
Yes D10,D11 LED is lighting? Yes Check U8 1.8V Yes Yes Check U9 2.5V No Yes U13 fail Check U3.4 3.3V
No U3 fail No U8 fail
No U9 fail
No If power_off high U2,U5 ON Check +3.3V_SW ,+5V_SW,+12V_SW (pin 5,6 and pin 7,8) U2,U5 fail
PDP LCD DISPLAY NOTHING(Analog HD1 without Y signal)
No Is picture on screen? Check component 1 (Y signal) C252 Is there sync? No Trace componect 1 from Input To U13 circuit Check R190,R191
Block 1
Yes
1
No Use GProbe connect from main to PC. Does scaler detect the signal? U13 fail
CONFIDENTIAL DO NOT COPY
Page10-6 File No. SG-0199
PDP LCD DISPLAY NOTHING(Analog HD1 without Pb signal)
BLOCK 1
No Is picture on screen?
Check component 1 (Pb signal) C259 Is there sync?
No
Trace componect 1 from Input To U13 circuit Check R196,R198
Yes
No Use GProbe connect from main to PC. Does scaler detect the signal?
U13 fail
LCD DISPLAY NOTHING(Analog HD1 without Pr signal) PDP
BLOCK 1
No Is picture on screen?
Check component 1 (Pr signal) C264 Is there sync?
No
Trace componect 1 from Input To U13 circuit Check R204,R201
Yes
No Use GProbe connect from main to PC. Does scaler detect the signal?
U13 fail
PDP LCD DISPLAY NOTHING(Analog HD1 on PIP mode without Y signal)
BLOCK 1
No Is picture on screen?
Check component 1 (Y signal) =>C255 Is there sync?
No
Trace componect 1 from Input To U10 circuit Check R193,R191
Yes
No Use GProbe connect from main to PC. Does scaler detect the signal?
U10 fail
2
CONFIDENTIAL DO NOT COPY
Page10-7 File No. SG-0199
PDP LCD DISPLAY NOTHING(Analog HD1 on PIP mode without Pb signal)
BLOCK 1
No Is picture on screen?
Check component 1 (Pb signal) C255 Is there sync?
No
Trace componect 1 from Input To U10 circuit Check R200,R198
Yes
No Use GProbe connect from main to PC. Does scaler detect the signal?
U10 fail
PDP LCD DISPLAY NOTHING(Analog HD1 on PIP mode without Pr signal)
BLOCK 1
No Is picture on screen?
Check component 1 (Pr signal) C255 Is there sync?
No
Trace componect 1 from Input To U10 circuit Check R205,R204
Yes
No Use GProbe connect from main to PC. Does scaler detect the signal?
U10 fail
LCD DISPLAY NOTHING(Analog HD2 without Y signal) PDP
BLOCK 1
No Is picture on screen?
Check component 2 (Y signal) C258,R195 Is there sync?
No
Yes
Check U23 outnput pin 31 Input pin 13 Input clamp voltage pin 3(+5V) Output clamp voltage pin 32(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U23 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U13 fail
Check before U23's circuit 1.C263,C265(AC coupled) 2.R209 3.R216(75ohm)
No Input source fail
3
CONFIDENTIAL DO NOT COPY
Page10-8 File No. SG-0199
PDP LCD DISPLAY NOTHING(Analog HD2 without Pb signal)
BLOCK 1
No Is no blue color on screen?
Check component 2 (Pb signal) C260,R197 Is there sync?
No
Yes
Check U23 outnput pin 28 Input pin 15 Input clamp voltage pin 5(+5V) Output clamp voltage pin 29(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U23 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U13 fail
Check before U23's circuit 1.C268,C269(AC coupled) 2.R211 3.R217(75ohm)
No Input source fail
LCD DISPLAY NOTHING(Analog HD2 without Pr signal) PDP
BLOCK 1
No Is no red color on screen?
Check component 2 (Pr signal) C254,R192 Is there signal?
No
Yes
Check U23 outnput pin 34 Input pin 11 Input clamp voltage pin 1(+5V) Output clamp voltage pin 35(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U23 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U13 fail
Check before U23's circuit 1.C256,C261(AC coupled) 2.R215 3.R218(75ohm)
No Input source fail
LCD DISPLAY NOTHING(Analog HD2 on PIP mode without Y signal) PDP
BLOCK 1
No Is picture on screen?
Check component 2 (Y signal) C287,R212 Is there sync?
No
Yes
Check U24 outnput pin 31 Input pin 13 Input clamp voltage pin 3(+5V) Output clamp voltage pin 32(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U24 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U10 fail
Check before U24's circuit 1.C282,C285(AC coupled) 2.R209 3.R216(75ohm)
No Input source fail
4
CONFIDENTIAL DO NOT COPY
Page10-9 File No. SG-0199
LCD DISPLAY NOTHING(Analog HD2 on PIP mode without Pb signal) PDP
BLOCK 1
No Is no blue color on screen?
Check component 2 (Pb signal) C288,R213 Is there sync?
No
Yes
Check U24 outnput pin 28 Input pin 15 Input clamp voltage pin 5(+5V) Output clamp voltage pin 29(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U24 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U10 fail
Check before U24's circuit 1.C289,C290(AC coupled) 2.R211 3.R217(75ohm)
No Input source fail
LCD DISPLAY NOTHING(Analog HD2 on PIP mode without Pr signal) PDP
BLOCK 1
No Is no red color on screen?
Check component 2 (Pr signal) C284,R210 Is there signal?
No
Yes
Check U24 outnput pin 34 Input pin 11 Input clamp voltage pin 1(+5V) Output clamp voltage pin 35(+5V) VCC3 pin 22,23(+5V) Input_switch_select high(+5V)
No U24 fail
No Use GProbe connect from main to PC. Does scaler detect the signal?
Yes U10 fail
Check before U24's circuit 1.C276,C281(AC coupled) 2.R215 3.R218(75ohm)
No Input source fail
LCD DISPLAY NOTHING(RGB) PDP
BLOCK 1
No Is picture on screen?
Check U45 H sync output U45 pin4,R181 V sync output U45 pin8,R184 Is there signal?
No
Check U45 H sync input U45 pin1,R185 V sync input U45 pin5,R187
Yes Check U45 pin 14 +3.3V Yes
No Yes Check input source
U45 fail
Check U22's signal output R signal C238,R180,R169,U22.34 G signal C237,R177,R171,U22.31 B signal C235,R174,R176,U22.28
No R G B
Check U22 input signal pin 2, C239;C241(AC coupled),R186,R172(75ohm) Pin 4,C234;C236(AC coupled),R166,R175(75ohm) Pin 6,C221;C224(AC coupled),R164,R173(75ohm) Yes Check U22 Input clamp voltage pin 1(+5V_V1) Output clamp voltage pin 35(+5V) VCC3 pin 22,23(+5V) Input_switch_select low (0V) No U22 fail
5
CONFIDENTIAL DO NOT COPY
Page10-10 File No. SG-0199
PDP LCD DISPLAY NOTHING(RGB on PIP mode without screen)
BLOCK 1
No Is picture on screen?
Check U45 H sync output U45 pin4,R181 V sync output U45 pin8,R184 Is there signal?
No
Check U45 H sync input U45 pin1,R185 V sync input U45 pin5,R187
Yes Check U45 pin 14 +3.3V Yes
No Yes Check input source
U45 fail
Check U22's signal output R signal C233,R180,R169,U22.34 G signal C232,R177,R171,U22.31 B signal C231,R174,R176,U22.28
No R G B
Check U22 input signal pin 2, C239;C241(AC coupled),R186,R172(75ohm) Pin 4,C234;C236(AC coupled),R166,R175(75ohm) Pin 6,C221;C224(AC coupled),R164,R173(75ohm) Yes Check U22 Input clamp voltage pin 1(+5V_V1) Output clamp voltage pin 35(+5V) VCC3 pin 22,23(+5V) Input_switch_select low (0V) No U22 fail
6
CONFIDENTIAL DO NOT COPY
Page10-11 File No. SG-0199
LCD DISPLAY NOTHING(Composite 1 without screen) PDP
BLOCK 1
No Is picture on screen? Check C310,R275,R274 Is there signal?
No Check Q28's emitter. Is there signal?
No
Check Q28's Base. Is there signal? Check collector voltage(+5V).
No Q28 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q13 fail
Yes
Check: 1.C309 (signal AC coupled) 2.R276 3.R279(75ohm impedance) Is there signal?
No Check input source
LCD DISPLAY NOTHING(Composite 1 on PIP without screen) PDP
BLOCK 1
No Is picture on screen? Check C308,R273,R274 Is there signal?
No Check Q28's emitter. Is there signal?
No
Check Q28's Base. Is there signal? Check collector voltage(+5V).
No Q28 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q10 fail
Yes
Check: 1.C309 (signal AC coupled) 2.R276 3.R279(75ohm impedance) Is there signal?
No Check input source
7
CONFIDENTIAL DO NOT COPY
Page10-12 File No. SG-0199
LCD DISPLAY NOTHING(Composite 2 without screen) PDP
BLOCK 1
No Is picture on screen? Check C316,R286,R285 Is there signal?
No Check Q29's emitter. Is there signal?
No
Check Q29's Base. Is there signal? Check collector voltage(+5V).
No Q29 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q13 fail
Yes
Check: 1.C315 (signal AC coupled) 2.R282 3.R283(75ohm impedance) Is there signal?
No Check input source
LCD DISPLAY NOTHING(Composite 2 on PIP without screen) PDP
BLOCK 1
No Is picture on screen? Check C316,R284,R285 Is there signal?
No Check Q29's emitter. Is there signal?
No
Check Q29's Base. Is there signal? Check collector voltage(+5V).
No Q29 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q10 fail
Yes
Check: 1.C315 (signal AC coupled) 2.R282 3.R283(75ohm impedance) Is there signal?
No Check input source
8
CONFIDENTIAL DO NOT COPY
Page10-13 File No. SG-0199
LCD DISPLAY NOTHING(S-VIDEO 1 without screen) PDP
BLOCK 1
No Is picture on screen? Check C320,R293,R292 Is there signal?
No Check Q30's emitter. Is there signal?
No
Check Q30's Base. Is there signal? Check collector voltage(+5V).
No Q30 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q13 fail
Yes
Check: 1.C319 (signal AC coupled) 2.R297 3.R299(75ohm impedance) Is there signal?
No Check input source
No Is picture color ok? Check C328,R308,R307 Is there signal?
No Check Q31's emitter. Is there signal?
No
Check Q31's Base. Is there signal? Check collector voltage(+5V).
No Q31 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q13 fail
Yes
Check: 1.C327 (signal AC coupled) 2.R296 3.R298(75ohm impedance) Is there signal?
No Check input source
9
CONFIDENTIAL DO NOT COPY
Page10-14 File No. SG-0199
PDP LCD DISPLAY NOTHING(S-VIDEO 1 on PIP mode without screen)
BLOCK 1
No Is picture on screen? Check C318,R291,R292 Is there signal?
No Check Q30's emitter. Is there signal?
No
Check Q30's Base. Is there signal? Check collector voltage(+5V).
No Q30 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q10 fail
Yes
Check: 1.C319 (signal AC coupled) 2.R297 3.R299(75ohm impedance) Is there signal?
No Check input source
No Is picture color ok? Check C326,R306,R307 Is there signal?
No Check Q31's emitter. Is there signal?
No
Check Q31's Base. Is there signal? Check collector voltage(+5V).
No Q31 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No Q10 fail
Yes
Check: 1.C327 (signal AC coupled) 2.R296 3.R298(75ohm impedance) Is there signal?
No Check input source
10
CONFIDENTIAL DO NOT COPY
Page10-15 File No. SG-0199
LCD DISPLAY NOTHING(S-VIDEO 2 without screen) PDP
BLOCK 1
No Is picture on screen? Check C332,R316,R320 Is there signal?
No Check Q33's emitter. Is there signal?
No
Check Q33's Base. Is there signal? Check collector voltage(+5V).
No Q33 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No U13 fail
Yes
Check: 1.C335 (signal AC coupled) 2.R300 3.R302(75ohm impedance) Is there signal?
No Check input source
No Is picture color ok? Check C336,R319,R318 Is there signal?
No Check Q32's emitter. Is there signal?
No
Check Q32's Base. Is there signal? Check collector voltage(+5V).
No Q32 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No U13 fail
Yes
Check: 1.C333 (signal AC coupled) 2.R301 3.R303(75ohm impedance) Is there signal?
No Check input source
11
CONFIDENTIAL DO NOT COPY
Page10-16 File No. SG-0199
PDP LCD DISPLAY NOTHING(S-VIDEO 2 on PIP mode without screen)
BLOCK 1
No Is picture on screen? Check C331,R313,R320 Is there signal?
No Check Q33's emitter. Is there signal?
No
Check Q33's Base. Is there signal? Check collector voltage(+5V).
No Q33 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No U10 fail
Yes
Check: 1.C335 (signal AC coupled) 2.R300 3.R302(75ohm impedance) Is there signal?
No Check input source
No Is picture color ok? Check C334,R317,R318 Is there signal?
No Check Q32's emitter. Is there signal?
No
Check Q32's Base. Is there signal? Check collector voltage(+5V).
No Q32 fail
Yes
Use GProbe connect from main to PC. Does scaler detect the signal?
No U10 fail
Yes
Check: 1.C333 (signal AC coupled) 2.R301 3.R303(75ohm impedance) Is there signal?
No Check input source
12
CONFIDENTIAL DO NOT COPY
Page10-17 File No. SG-0199
PDP LCD DISPLAY NOTHING(Digital 2 U35 with PORT B without screen)
BLOCK 1
No Is picture on screen? Check input source?
Yes
Check U37 I2C bus SCL Pin 6 SDA pin 5
No Check U37 power 5V Pin 8
No Check D66 and D65 Are there 5V output?
No
D66 fail or D65 fail
No Is picture on screen?
Check U35 pin 90 high V sync R419 H sync R420 clock R421
No
Check +3.3V_SW FB19,FB20,FB21,FB22 U41 +1.8V_HDMI1
Yes Check crystal Y2=28.322MHz
Yes
No Check Q44 source high(3.3V)
Check Q44 Gata high(5V)
No Q44 fail
Yes Check U35 I2C bus CSDA pin 39 CSCL pin 40 Yes Yes Check U35 all power U35 fail No I2C addr. R424 No Check Block 2
No Is picture color ok?
Check U35's RGB data bus B RP10,RP11 G RP12,RP14 R