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6-Ch Audio Selector
PT2323
DESCRIPTION
PT2323 is a 6-Channel Audio Selector utilizing CMOS Technology specially designed for Home Theater System. It provides a built-in 2-Channel to 6-Channel Translator, which can directly mix traditional stereo channel to simulate a 6-Channel audio output. Single power supply (9V), I2C Bus Interface as well as very low Total Harmonic Distortion (THD < 0.005%) and other features are incorporated into a single chip thereby providing very high performance. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages.
FEATURES
· · · · · · · · Supply Voltage: 9V 4 Stereo Inputs One 6-Channel Input Maximum Input Voltage: 3.75Vrms (1KHz, THD<1%) Low Total Harmonic Distortion, THD<0.005% (1KHz, 0.2Vrms) Low Noise: No<4µVrms I2C Bus Interface Available in 28 Pins, DIP or SOP
APPLICATIONS
· · · · AV System Mini Compo Car Stereo Multi-Media Audio Systems
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
BLOCK DIAGRAM
6CH IN
FL CT SL
FR
S UB
SR
L1 L2 L3 L4 2CH 6CH Converter R1 R2 R3 R4 FL FR 2CH (Stereo) IN CT SU B SL SR 6CH Switch
MUTE
FL
MUTE
FR
MUTE
CT 6CH OUT
MUTE
SU B
MUTE
SL
MUTE
SR SD A SC L
RE F
M IXO LP F I LP F O
Control Unit
I C B US
2
+ VC C GND
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
PIN CONFIGURATION
L1 L2 L3 L4 FLI FRI CTI SUBI SLI MIXO REF
1 2 3 4 5 6 7 8 9 28 27 26 25 24 23
R1 R2 R3 R4 LPF_I LPF_O FLO FRO CTO SUBO SLO SRO SCL SDA
P T2 3 23
22 21 20 19 18 17 16 15
SRI 1 0
11
VCC 1 2
13
GND 1 4
PT2323 V1.3
-3-
October, 2005
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6-Ch Audio Selector
PT2323
PIN DESCRIPTION
Pin Name L1 L2 L3 L4 FLI FRI CTI SUBI SLI SRI MIXO VCC REF GND SDA SCL SRO SLO SUBO CTO FRO FLO LPF_O LPF_I R4 R3 R2 R1 I/O I I I I I I I I I I O O I I O O O O O O O I I I I I Description Left Channel Input Pin No. 1 Left Channel Input Pin No. 2 Left Channel Input Pin No. 3 Left Channel Input Pin No. 4 6-Ch Front Left Channel Input Pin 6-Ch Front Right Channel Input Pin 6-Ch Center Channel Input Pin 6-Ch Subwoofer Channel Input Pin 6-Ch Rear Left Channel Input Pin 6-Ch Rear Right Channel Input Pin L+R Mixed Output Pins Positive Power Supply Reference Voltage (1/2 Vcc) Ground Pin I2C Control Data Input Pin I2C Control Bus Clock Input Pin 6-Ch Rear Right Channel Output Pin 6-Ch Rear Left Channel Output Pin 6-Ch Subwoofer Channel Output Pin 6-Ch Center Channel Output Pin 6-Ch Front Right Channel Output Pin 6-Ch Front Left Channel Output Pin Low Pass Filter Output Pin Low Pass Filter Input Pin Right Channel Input Pin No. 4 Right Channel Input Pin No. 3 Right Channel Input Pin No. 2 Right Channel Input Pin No. 1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
FUNCTION DESCRIPTION
BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2323 via the SDA and SCL. The SDA and SCL make up the BUS Interface. It should be noted that the pull-up resistors must be connected to the positive supply voltage.
DATA VALIDITY
A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW States of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below.
SD A
SC L D a t a Lin e S ta b le , D a t a Va lid D a ta C h a ng e A llo w e d
START AND STOP CONDITIONS
A Start Condition is activated when 1. the SCL is set to HIGH and 2. SDA shifts from HIGH to LOW State. The Stop Condition is activated when 1. SCL is set to HIGH and 2. SDA shifts from LOW to HIGH State. Please refer to the timing diagram below.
SC L
SD A
Start
Stop
BYTE FORMAT
Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bit. The MSB is transmitted first.
PT2323 V1.3 -5October, 2005
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6-Ch Audio Selector
PT2323
ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the SDA Line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge Clock Pulse so that the SDA Line is in a Stable Low State during this Clock Pulse. Please refer to the diagram below.
CLK 1 2 3 4 7 8 9
DATA Start
MSB A cknowledgm ent from R eceiver
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this case, the master transmitter can generate the STOP Information in order to abort the transfer.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you want to avoid the acknowledge detection of the audio processor, a simpler µP transmission may be used. Wait one clock and does not check the slave acknowledge of this same clock then send the new data. If you use this approach, there are greater chances of faulty operation as well as decrease in noise immunity.
INTERFACE PROTOCOL
The interface protocol consists of the following: A Start Condition A Chip Address Byte = 10010100 ACK = Acknowledge Bit A Data Byte A Stop Condition Please refer to the diagram below: PT2323 Address
MSB First Byte LSB MSB LSB MSB LSB
START
1 0 0 1 0 1 0 0 ACK
DATA
ACK
DATA
ACK STOP
DATA TRANSMITTED (N-BYTES+ACKNOWLEDGE)
Note: ACK = Acknowledge Bit Maximum Clock Speed = 100k bits / second
PT2323 V1.3 -6October, 2005
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6-Ch Audio Selector
PT2323
SOFTWARE SPECIFICATION
PT2323 ADDRESS
PT2323 Address is shown below. MSB 1 0 0 1 0 1 0 LSB 0
I2C BUS START-UP TIMING
After Power is turned ON, PT2323 needs to wait for a short time in order to insure stability. This waiting period is relative to the value of Cref. As the Cref value becomes bigger, the waiting time period for PT2323 to be able to send I2C Bus Signal effectively becomes longer. For example, if Cref = 10µF, after power is turned ON, the waiting time period for PT2323 to send I2C Bus Signal is at least 300 ms. If the waiting time period is less than 300 ms, I2C Control may fail. Please refer to the diagram below.
V
POWER ON 90% VDD
VDD at least 300ms
SDA/SCL
PT2323 V1.3
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6-Ch Audio Selector Data Bytes
MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 C3 0 0 0 0 1 1 1 C2 0 0 1 1 0 0 1 C1 0 1 0 1 0 1 1 LSB C0 M M M M M M M Function Input Switch FL Mute FR Mute CT Mute SUB Mute SL Mute SR Mute All CH Mute
PT2323
Notes: 1. M = 1 (Mute Function Enabled) 2. M=0 (Mute Function Disabled) C3 1 1 1 1 0 C2 0 0 0 0 1 C1 0 0 1 1 1 C0 0 1 0 1 1 Function Input Stereo Group 4 Input Stereo Group 3 Input Stereo Group 2 Input Stereo Group 1 6-Ch Input
Notes: 1. Stereo Group 1 consists of L1 and R1. 2. Stereo Group 2 consist of L2, R2. 3. Stereo Group 3 consists of L3, R3. 4. Stereo Group 4 consists of L4, R4.
Add-On Feature
MSB 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 1 0 1 Function Enhanced Surround Function Active Enhanced Surround Function Disabled Mixed Channel (0dB) Setup Mixed Channel (+6dB) Setup
2-Ch to 6-Ch Translation
PT2323 has a built-in 2-Ch to 6-Ch Translator. Any one of the stereo inputs -- L1/R1, L2/R2, L3/R3, L4/R4 may be selected and converted to a 6-channel output. If the 6-Channel Input is selected, the audio signal just directly flows through the 6-channel output, it is not internally processed by PT2323. During a 2-Ch to 6-Ch translation processes, the original Left and Right signals are also directly outputted and only the Center (CT), Subwoofer (SUB), Rear Right (SR) and the Rear Left (SL) signals are processed by the PT2323. PT2323 provides individual mute functions which prevent output signals from unused stereo input sources from being heard.
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector Surround Enhance Function
PT2323
When the 2-Ch to 6-Ch Translation is enabled, and the Enhanced Surround Function is turned ON, then the Surround Function is enhanced. However, it is suggested that the enhanced surround function be turned OFF when using a stereo input/output channel in order to ensure better crosstalk or stereo separation. Under the 6-Ch Input, this function is not active. The signals from the 6-Ch input just directly flow through.
Mixed Channel
The Mixed channels consist of the CT and the SUB channels. These 2 channels (CT and SUB) are mixed via the L and R signals. The Mixed Channel is set to 0dB output and includes a +6dB amplifier. 2 The I C may be used to turn on the mixed channel.
Subwoofer
PT2323 provides an internal OP AMP for the Subwoofer Crossover. An external RC Sallen Key Type Low Pass Filter may be added. Please refer to the diagram below.
C1 F r om M IXO
R
R
C2
(P in 24) LP F _I + -
(P in 25) LP F _O To SU B
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
Subwoofer Crossover Frequency Response Curve
+5 +0 -5 -10 -15 d B V -20 -25 -30 -35 -40 -45 -50 20
50
100
200
500 Hz
1k
2k
5k
10k 20k
Note: 1. R=24K (where R is the resistor in the Subwoofer Cross-Over Circuit) 2. : Cross-Over Frequency=280Hz, C1=0.047µf, C2=0.018µf 3. : Cross-Over Frequency=200Hz, C1=0.068µf, C2=0.027µf 4. : Cross-Over Frequency=120Hz, C1=0.1µf, C2=0.047µf 5. C1, C2=Low Pass Filter Capacitor
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
ABSOLUTE MAXIMUM RATING
Parameter Operating Voltage Operating Temperature Storage Temperature Symbol Vs Topr Tstg Rating 12 -40 ~ 85 -65 ~ +150 Unit V
ELECTRICAL PARAMETERS
(Unless otherwise statedTa=25, Vcc=9V, RL=100K, f=1KHz) Parameter Symbol Condition Min. VCC 4.5 Supply Voltage IS Supply Current Input=0.2Vrms Total Harmonic Distortion THD 0.001 A-Weighting RIS=600 NO Output Noise A-Weighting 0dB=1Vrms Signal to Noise Ratio SN A-Weighting RL=50K, 1KHz VIMAX Maximum Input Voltage THD=1% Voltage Gain GN F=1KHz -1 RON Internal Switch Impedance Cross Talk CT Vin=1Vrms Channel Separation CS Vin=1Vrms Vin=1Vrms Mute Function MUTE A-Weighting VIH 0.7VDD I2C Bus High Level Input Voltage 2 VIL I C Bus Low Level Input Voltage 2 TINIT CREF=10µf I C Bus Initial Time Typ. 9 4 0.005 4 100 3.75 0 200 90 90 95 300 Max. 110 +1 0.3VDD Unit V mA % µV dB Vrms dB dB dB dB V V ms
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
10 µ F 100K +
APPLICATION CIRCUIT
Lch1 Lch2 Lch3 Lch4 100K 10 µ F +
1 2 3 4 5 6 7 8 9 10 11
L1 L2 L3 L4 FLI FRI CTI PT2323 SUBI SLI SRI MIXO VCC REF GND
R1 R2 R3 R4 LPF_I LPF_O FLO FRO CTO SUBO SLO SRO SCL SDA
28
+
Rch1 Rch2 Rch3 Rch4
+ + + + + +
27
+
26
+
25 24
C2
From MIXO <<
23
C1 100K
22 270 (NOTE) 10 µ F + 21 270 (NOTE) + 20 270 (NOTE) + 19 270 (NOTE) 18 270 (NOTE) 17 270 (NOTE) 16 15
+ + +
6CH IN
+ + +
6CH OUT
<< 9V
12 13
47 µ F 0.1 +
+
10 µ F
14
I 2C BUS
Note: * = An external resistor (R=270) must be connected in series to each of the output pins (FLO, FRO, CTO, SUBO, SLO, SRO) and must be as close as possible to the PT2323 chip.
PT2323 V1.3
- 12 -
October, 2005
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6-Ch Audio Selector
PT2323
ORDER INFORMATION
Valid Part Number PT2323 PT2323-S PT2323 (L) PT2323-S (L) Package Type 28 Pins, DIP, 600mil 28 Pins, SOP, 300mil 28 Pins, DIP, 600mil 28 Pins, SOP, 300mil Top Code PT2323 PT2323-S PT2323 PT2323-S
Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the date code.
PT2323 V1.3
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6-Ch Audio Selector
PT2323
PACKAGE INFORMATION
28 PINS, DIP, 600MIL
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
Symbol A A1 A2 B B1 C D D1 E E1 e eA eB L Min. 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 2.93 Nom. -2.54 BSC. 15.24 BSC. Max. 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 17.78 5.08
PT2323
Note: 1. Controlling dimensionMILLIMETER 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimensions A, A1 and L are measured with the package seated in JEDEC Seating Plane Gauge GS-3. 4. "D" & "E1" dimensions, for ceramic packages, include allowance for glass overrun and meniscus and lid to base mismatch. 5. "D" & "E1" dimensions for plastic package, do not includes mold flash or protrusion. Mold flash or protrusions shall Not exceed 0.01 inch. (0.25mm). 6. "E" and "eA" measured with the leads constrained to be perpendicular to plane T. 7. "eB" and "eC" are measured at the lead tips with the loads un-constrained. "eC" must be zero or greater. 8. "N" is the maximum quantity of lead positions. (N=28) 9. Corner leads (1, N, N/2, and N/2+1) may be configured as shown in Figure 2. 10. Pointed our rounded leads tips are preferred to ease insertion. 11. For automatic insertion, any rained irregularity on the top surface (step, mess, etc.) shall b symmetrical about the lateral and longitudinal package centerlines. 12. Refer JEDEC MS-011 Variation AB. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
28 PINS, SOP, 300MIL
Symbol A A1 B C D E e H h L
Min. 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 0°
Nom.
Max. 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8°
1.27 BSC.
PT2323 V1.3
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October, 2005
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6-Ch Audio Selector
PT2323
Note: 1. Dimensioning and tolerancing per ANSI Y14.5-1982. 2. Dimension "D" does not include mold flash , protrusions or gate burrs. Mold Flash, protrusion or gate burrs shall not exceed 0.15mm (0.006 in) per side. 3. Dimension "E" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. The chamfer on the body is optional. It is not present, a visual index feature must be located within the crosshatched area. 5. "L" is the length of the terminal for soldering to a substrate. 6. "N" is the number of terminal positions. (N=28) 7. The lead width "B" as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.24 in). 8. Controlling dimension: MILLIMETER. 9. Refer to JEDEC MS-013 Variation AE JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2323 V1.3
- 17 -
October, 2005