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Colour Television
Chassis
MG5.1E
AA
Contents
1 2 3 4 5 6 7 8 9 10 11 MG99 Light path Introduction Overall blockdiagram Power supply Scan circuits Small signal panel CRT drive circuit Interface panel SIDE JACK panel Audio signal part Digital convergence circuit
Page
2 8 9 11 24 29 69 72 74 75 80
©
Copyright reserved 1999 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips. Printed in the Netherlands Subject to modification 5 3122 785 10053
Published by LM 9972 Service PaCE
2
1. MG99 Light path
MG5.1E
1.
MG99 Light path
MIRROR
R+G+B
RED GREEN BLUE FRESNAL LENS LENTICULAR SCREEN
CL 96532100_078.eps 121199
Figure 1-1
The MG99 Projection TV uses three single color tubes, Red, Green, and Blue. (Figure 1-1) The output of each tube is projected onto a mirror where it is then reflected onto a viewing screen. The Tubes are converged so the light from each tube strikes the same spot on the Fresnel Lens. The Fresnel Lens equalizes and concentrates the light to provide equal light uniformity across the screen. The Mirror is a first surface mirror type which has the reflective coating on the outside of the mirror. To prevent scratching of this surface, always use a soft cotton cloth to clean it.
Personal notes
MG5.1E
1. MG99 Light path
3
BLACK STRIPING OUTPUT
LIGHT
CL 96532100_079.eps 111199
Figure 1-2
The Lenticular Lens Screen calumniates the light from the Fresnel Lens. (Figure 1-2) The Lenticular Lens increases contrast by reducing the ambient light by the use of Black Striping. The Prismatic formation of the screen allows for nearly 3X light output as compared to a flat screen. Caution should be used when working with the screen. Damage can easily occur in the form of scratching, or by using certain chemical screen cleaners which can strip the black striping from the screen. To clean the screen, use one drop of dish washing detergent in a small bowl of water. (approximately 2 liters) Wipe the screen with a soft cotton cloth in the direction of the stripes.
Personal notes
4
1. MG99 Light path
MG5.1E
C ELEMENT LENS
CRT
OUTPUT LENS
LIQUID COOLANT
CL 96532100_080.eps 111199
Figure 1-3
The Three CRT's are driven by 30KV of high voltage and 15KV of focus voltage. (Figure 1-3) The Tube produces a highly concentrated light output of color. A liquid coolant of Glycol is used to transfer heat from the face of the tube to the surrounding mechanical assembly. The C-element lens seals the Coupling fluid within the coupler. The C-element lens and Coupling fluid are part of the light path and contribute to the properties of the optical system.
Personal notes
MG5.1E
1. MG99 Light path 1.1 MG99 LIGHT PATH PROBLEMS
5
1.1
MG99 LIGHT PATH PROBLEMS
CL 96532100_107.eps 021299
Figure 1-4
Look at the edges of the screen. They may be bowed inward. PROBLEM - BOTTOM CORNERS DARK PROBLEM - BOTTOM CORNERS COLORED There is no problem with the set. The viewing angle is too high.
Personal notes
6
1. MG99 Light path 1.1 MG99 LIGHT PATH PROBLEMS
MG5.1E
CL 96532100_109.eps 151199
Figure 1-5
Fresnel may be reversed. Carefully remove the fresnel and point the grooves toward the viewer. PROBLEM - BRIGTH AND DARK LINES ON A WHITE FIELD
Personal notes
MG5.1E
1. MG99 Light path 1.1 MG99 LIGHT PATH PROBLEMS
7
CL 96532100_110.eps 151199
Figure 1-6
The Fresnel offset is pointing down. The center of the Fresnel should be toward the top of the screen. PROBLEM- UPPER CORNERS OF THE SCREEN DARK
Personal notes
8
2. Introduction
MG5.1E
The 1999 MG99 PTV chassis is designed for the European market. It is available in a 46 inch (117 cm) and a 55 inch (140 cm) 16 by 9 aspect ratio screen sizes. Selected Video can be displayed in either a 4 by 3, 14 by 9, or 16 by 9 aspect ratios. The set has a viewing angle of 160 degrees. The MG99 PTV is capable of receiving signal from PAL B/G, PAL B/G 6OHz, PAL B/H, PAL D/K, PAL 1, PAL M, PAL N, PAL plus, SECAM B/G, SECAM D/K, SECAM L, AND SECAM Li TV systems. There are four composite video inputs which include three SCART connectors, and a Side Jack panel. The systems that can be applied to these inputs are NTSC 3.58, NTSC 4.43, NTSC Play Back, PAL 4.43, PAL, B/G Play Back, SECAM, and SECAM Play Back. The set is equipped with a Frame and Line doubler to produce a horizontal resolution greater than 800 lines. The picture display is driven by three seven inch Red, Green, and Blue tubes. The Sound system is driven by a 2 times 20 watt power amplifier. A switch in the rear of the set allows the sets internal speakers to be driven by an external amplifier. The following sets will be sold in Europe: 46PP9501/05U.K. and Ireland 55PP9501/05U.K. and Ireland 46PP9501/12Western Europe 55PP9501/12Western Europe 46PP9501/58Eastern Europe 55PP9501/58Eastern Europe These units will be distributed from Philips Bundling Center in Bruges, Belgium.
2. Introduction
Personal notes
9
3. Overall blockdiagram
MG5.1E
3.
Overall blockdiagram
Y_CVBS SIDE JACK PANEL C L R DELAY SVM MODULE
BLUE CRT MG99 SMALL SIGNAL PANEL Y
R G B
CRT DRIVE CIRCUIT
R G B GREEN CRT RED CRT
LEFT AUDIO AUDIO AMPLIFIER SPEAKER SWITCH
RIGHT AUDIO
CONV R, G, B, FB INTENSITY CONTROL CONV R, G, B, FB LINE SYNC FRAME SYNC LINE DRIVE INTERFACE PANEL LINE SYNC FRAME SYNC +5V STBY +15V STBY +130V POWER SUPPLY +38V -38V +33V +15V -15V AC SWITCH PANEL -7V7 +8V6 +5V2 HV CIRCUIT FOCUS FRAME DRIVE CONVERGENCE PANEL CONV YOKES
FOCUS/G2 BLOCK
G2
HV/SCAN PANEL
CL 96532100_081.eps 191199
Figure 3-1
10
3. Overall blockdiagram
MG5.1E
There are eleven PC boards in the MG99 chassis. (Figure 3-1) They are the Small Signal panel, Side Jack panel, Power Supply panel, Interface panel, SVM module, Blue CRT panel, Green CRT panel, Red CRT panel, High Voltage Scan panel, and Convergence panel. Whenever AC power is applied to the set and the Mains switch is turned On, the Power Supply panel produces a 5 and a 15 volt standby supplies. When the set is turned On by the channel up button on the Front Keyboard or the Remote Control, the 130 volt, 38 volt, -38 volt, 33 volt, 15 volt, -15 volt, -7.7 volt, 8.6 volt, and 5.2 volt supplies are switched On. Frame and Line drive from the Small Signal panel is routed through the Interface Panel to the Frame Drive and Line Drive circuits on the High voltage Scan panel. The High Voltage scan panel produces the High Voltage and Sync to the Convergence panel. Focus voltage from the High Voltage circuit is fed to a Focus/G2 block which provides Focus and G2 voltage to the three CRT'S. During the Convergence adjustment mode, Red, Green, Blue, and Fast Blanking from the Convergence Panel is fed to the Small Signal panel to generate the adjustment grid. The Small Signal panel selects video from the Antenna input, one of the three Scart connectors, or the Side Jack panel. The Small Signal panel outputs Red, Green, and Blue drive to the CRT drive circuit located on the Interface Panel. The CRT drive circuit then provides drive for the three CRT panels. Left and Right channel audio from the Small Signal panel is routed through the Interface Panel to the Audio Amplifier panel. The Audio Amplifier panel has its own separate Switch Mode power supply. The output of the Audio Amplifier is then fed to the Speaker Switch panel which selects between the Audio Amplifier or External Audio from a separate amplifier. Luminance or Y from the Small Signal panel is fed to a Delay circuit on the Interface panel before being applied to the SVM panel. The Scan Velocity Module speeds up the beam during light to dark transitions in the picture to provide a sharper image.
Personal notes
11
4. Power supply
MG5.1E
4.
Power supply
AC INPUT CIRCUIT
AC SWITCH PANEL
POWER FACTOR CORRECTION CIRCUIT
STBY POWER SUPPLY
+5V STBY
+15V STBY
+130V MAIN SMPS POWER SUPPLY ON/OFF +33V +35V -35V +15V -15V
+15V
5V2 REG
+5V2
+15V
8V6 REG
+8V6
-15V
-7V7 REG
-7V7
CL 96532100_082.eps 121199
Figure 4-1
AC power is applied to the set on the Power Supply panel. (Figure 4-1) It is then fed to the Mains switch on the AC switch panel located on the front of the set. It is then fed back to the Power Supply panel and to the Power Factor Correction circuit. If the AC mains is 240 volts, the output of the Power Factor correction circuit is approximately 329 volts DC in standby and 350 volts DC when the set is turned On. The Power Factor correction circuit is turned Off during standby. This is a "HOT" chassis. When troubleshooting this or any power supply, always use an isolation transformer. The Standby Power supply produces a 5 and a 15 volt supplies. It also provides operating voltage for the Power Factor Correction and the Audio Amplifier power supply. The Power Factor correction circuit is turned Off when the set is in the Standby mode. The Main Switch Mode Power supply produces a 130 volt, a 33 volt, a 35 volt, a -35 volt, a 15 volt, and a -15 volt supply. The Main SMPS and the Power Factor Correction Circuit is switched On by a Low from the Small Signal panel.
Personal notes
MG5.1E
4. Power supply
12
TO AC SW BD 1221 1000 5A 2000 680n 3011 1 4
5001
3004 3.3M 3005 3.3M 7000
+5VSTBY 3007 6.8K 50_60HZ 3008 10K
CL 96532100_083.eps 121199
3006 470K
Figure 4-2
The applied AC voltage is fed to a 5 amp fuse and then to the Mains switch on the AC switch panel. (Figure 4-2) The AC voltage is fed to transistor 7000 and then to the Small Signal panel for clock synchronization. The Standby Supply produces the 5 volt and 15 volt standby supplies. (Figure 4-3) The output of the Power Factor correction circuit PFCOUT is applied to Pin 5 of 7211 through Pins 2 and 4 of the switching transformer 5202. When the supply voltage is first applied, voltage through the internal startup resistor Rs is applied to capacitor 2283 via Pin 4. When the capacitor charges to 5.7 volts, the internal oscillator switches On driving the internal FET switch. When the voltage across capacitor 2283 drops below 4.7 volts, the IC turns Off. This cycle repeats until the 5 volt standby supply turns Shunt Regulator 6205 On. The supply voltage for the IC is then supplied to Pin 4 through 7213. Operating voltage to Pin 5 of 7213, the Audio Amplifier power supply, and the Power Factor correction circuit is supplied by Pin 5 of 5202. During normal operation, the 5 volt standby source is monitored by the Shunt Regulator 6205. If the 5 volt supply should increase, the Shut Regulator will cause more current to flow through the LED inside the opto-isolator 7213. This will reduce the resistance of the transistor inside 7213. As a result, more current will flow through the Sensing resistor inside 7211, which will reduce the On time of the FET inside the IC. This will reduce the output voltage to the correct level. This supply operates at approximately 100 KHz.
Personal notes
MG5.1E
+5VSTBY 5214 CONTROL 7204 5211 5233 PFC 2209 100uF GND_C 1 5 3213 10K 4 GND_C 3241 6K8 3215 1K
7206 2 7205
+5VSTBY
3289 10K
7214
3212 10K
ON_OFF
3288 10K
2284 10n
3214 100K
PFCOUT 2228 100 GND_C 5 6207 2 +15VSTBY 6204 2270 100uF 6231 5 +5VSTBY 3223 47 1 5 7213 4 3287 470 2 3244 33K 2226 22n 2208 100 2213 1000uF 3222 1K5 6200 6236 9 4 8 10 GND_C
R S
3216 10 5202 1 7 6235 2269 100 2211 .1 6201 8.2V 7208 7209 RESET 3240 39K 2210 22uF 3245 1K RESET 3230 1K5
4. Power supply
Figure 4-3
INTERNAL SUPPLY
2206 220uF
7211
5234 +5VSTBY SOURCE 2282 1uF
4
5.7V
5.7V 4.7V
-
RS
PWM
3239 2K4
3246 2K4
3247 180
1,2,3,7,8 GND_C
CL 96532100_084.eps 011299
2283 47uF
6205 SHUT REGULATOR
GND_C
13
14
4. Power supply
MG5.1E
To troubleshoot the Standby Supply, first check the supply voltage on Pin 5 of 7211. If there is no secondary voltage and 7211 is working correctly, startup pulses should be seen at Pin 5 of the IC. If the IC is pulsing and there is no secondary voltage, there is a problem with the outputs of 5202 or with the feedback circuit. If 7211 is not pulsing, either the IC or capacitor 2283 is defective. When the set is turned On, transistor 7214 will turn Off turning 7205 On. This will turn the Optoisolator 7206 On turning transistor 7204 On, switching the operating voltage to the Power Factor Correction circuit. It also switches the operating voltage to the power supply on the Audio Amplifier panel on the line labeled "CONTROL".
Personal notes
MG5.1E
4. Power supply 4.1 European power factor correction circuit
15
4.1
European power factor correction circuit
AC IN
BRIDGE CAP LOAD
AC CURRENT
CAPACITOR CHARGE
VOLTAGE
A
B
CL 96532100_085.eps 121199
Figure 4-4
The input to most switching power supplies consists of a bridge rectifier and a large electrolytic capacitor. (Figure 4-4) When AC power is applied, the Capacitor will charge to approximately 1.4 times the RMS value of the applied AC voltage. This type of supply does not draw current from the AC power source through out the entire AC cycle. When the capacitor charge falls to point "A", the instantaneous value of the AC voltage exceeds the charge of the capacitor. The bridge diodes are then forward biased, causing current to flow from the AC source. Current will continue to flow from the AC line until the AC sinusoidal voltage reaches its peak at Point "B". At this point, the charge on the capacitor will exceed the AC line voltage reversing the bridge diodes. This results in an AC current waveform that is narrow and distorted compared to the AC voltage waveform. Non sinusoidal waveforms have a high harmonic content, with excessive peaks which results in a low power factor of 0.5 to 0.6. Power Factor is a ratio of real power divided by apparent power. Excessive harmonics and peak currents reduce the efficiency of the power distribution system. The MG5.1 Projection TV without Power Factor correction has a high harmonic content of 85 percent, creating a Power Factor of 0.5. Current spikes of 7 amps will also be created in the AC supply. With the Power Factor correction circuit, the peak current is limited to 1.58 amps, with the harmonic content being reduced to 4.5 percent. The Power Factor is increased to 0.99. The ideal Power Factor is one, which occurs when the current is sinusoidal and in phase with the voltage. The European standard IEC1000 limits the current harmonic content of equipment supplied by the AC Mains.
Personal notes
16
4. Power supply 4.1 European power factor correction circuit
MG5.1E
5109 AC INPUT BRIDGE 5 3
6103 350V DC OUT 2110
CURRENT SENSE
REGULATOR DRIVE 7102
7104
CL 96532100_086.eps 121199
Figure 4-5
The MG5.1 Power Factor correction circuit uses a Boost regulator to smooth out the current draw from the AC line improving the Power Factor to 0.99, which is accomplished by drawing current from the AC source throughout the entire AC cycle making the current waveform sinusoidal. (figure 4-5) Input to the module is connected to the AC Mains. The output supplies are approximately 350 volts DC to the Main and Standby Switched mode Power Supply circuit. The Boost Regulator circuit produces a higher output voltage than the input voltage. The regulator drive circuit compares 6103's output voltage, the input voltage from the bridge, and the voltage across the current sensing resistors to control the On time of 7104. This will maintain the output voltage at 350 volts DC and limit the input current to acceptable levels. When 7104 is On, current flow through 5109 stores energy in the choke. When 7104 turns Off, 5109 reverses polarity and charges 2110. Using this type of regulation, current is drawn from the AC source throughout the entire cycle, keeping the current waveform sinusoidal. When the AC cycle is at its low point, 7104 is on for a longer period of time. When the AC voltage is at its peak, 7104 is on for a shorter time to store the same amount of energy in 5109 to maintain the output voltage at 350 volts.
If the Boost regulator circuit should become inoperative, due to a loss of regulator drive, operating voltage is still applied to the set. The supply voltage to the switching supplies will drop from 350 volt to approximately 329 volts depending on the Mains voltage. Since the customer would not detect a failure, the operation of this circuit should be checked after any repair of the set.
4.2 Full power factor correction circuit
MG5.1E
5006 3010 2R2 2105 470p 3105 6R8
5003
1222-1 5109 6000 15 13 5107 GND_B 2110 470uF 2107 1n STARTUP VOLTAGE FOR FULL POWER SECTION 5 3 5105 6103 5103
5005
5106 PFCOUT 350V DC OUT (329V)
FROM AC SW BOARD
5004
1222-4
5007 0.36V MAX 7104 3117 10K GND_B GND_B PFC 2120 220p 3132 0R1 3133 0R1
GND_C GND_B
3130 0R1
3131 0R1
GND_HA
GND_B
R491 330K R490 1M 3115 47 GND_B 3111 1M 3121 33K 2114 1n5 19V (25V) 5108 16 19 VCC 17 18 2113 100uF
R493 33K
C486 .22
C485 .22
INST LINE VOLTAGE
4 OSCILLATOR OUTPUT 20 S + + COMPARATOR + R 15 1.28 LATCH LOGIC Q
7102 3114 47 6104
4. Power supply
+
-
Figure 4-6
CURRENT AMPLIFIER IPK V REF OVP 5.11 V 8 3127 18K 3128 1K8 GND_B 2116 2n2 3120 5K6 5 5.45V 0.23V 11 2 9 3 4.3V 3109 47K GND_B 3123 1K8 3118 390 2118 1uF
1.5-5.5V
7
5.11V
6
GILBERTS MULTIPLIER
5.11V
14 5.11V
13
5.45V
3124 330K
3108 3M3
3134 470K
2115 .33
3110 39K GND_B
3119 3M3
3126 47K 3125 1K
CL 96532100_087.eps 191199
GND_B
17
18
4. Power supply 4.2 Full power factor correction circuit
MG5.1E
An explanation of the full Power Factor Correction circuit is now given. (Figure 4-6) The Power Factor Correction circuit is a fixed-frequency Pulse-Width modulated boost regulator power supply. Operating frequency is approximately 60 kilohertz. Due to the low power consumption of the set during the standby mode, the Power Factor Correction circuit is turned Off. The operating voltage, PFC, on Pin 19 of 7102 is turned Off. When the set is turned On, the operating voltage is switched to Pin 19 of 7102. Once the circuit is in operation, a 5.11 volt internal reference voltage on Pin 11 is applied to Pin 6 of the IC. Output of the bridge rectifier is fed to the IC on Pins 4 and 7. Feedback from the output circuit is fed to Pin 14 where it is multiplied with the Bridge output. Inputs to the Gilberts Multiplier produce an error signal that is fed to the current amplifier. The Gilberts Multiplier multiplies the bridge output voltage with the output voltage on D438. The 5.11 volt reference is used to provide a clamping reference for the other inputs. Input current is sampled by resistors 3130, 3131, 3132, and 3133. This sample is added to the error signal from the Multiplier going into Pin 8. The error signal is amplified and then compared to the oscillator ramp to determine the reset point for the latch. When the oscillator goes low, the latch is set making output "Q" High. With the other inputs to the AND gate High, Pin 20 then goes High, turning 7104 On. By comparing the input and output voltage, the On time of 7104 is increased when the AC voltage is at its low point to maintain the 350 volt DC output. When the AC input voltage is at its peak, 7104 is On for a shorter period. The IPK circuit connected to Pin 2 is an overcurrent protection circuit which resets the latch if there is excessive current through the return resistors. This will reduce the On time of 7104. In a like manner, the OVP, Over Voltage Protection, circuit will reset the latch removing drive to Pin 20 is the output voltage exceeds 392 volts. To check the operation of this circuit when the set is operating correctly, check the PFCOUT voltage. This voltage should be approximately 350 volts. If the output voltage is approximately 329 volts, this circuit is not working. Check the operating voltage on Pin 19 of 7102. Then check the output drive on Pin 20 and at the gate of 7104. There are three grounds on the Hot side of the supply. Ground HA is connected directly to the bridge 6000. Ground "B" is the ground for the Power Factor Correction circuit. If the current sensing resistors 3130 through 3133 should open, this would remove the ground for all the switching supplies and make the set inoperative. Ground "C" is the ground for the switching supplies. When ground "B" passes through the choke 5106, it becomes ground "C". Startup up voltage for the Full Power supply is taken from the neutral side of the AC mains.
Personal notes
4.3 Full power supply
MG5.1E
2312 470P 4 14 2350 470P 12 6315 3345 470R 8 5306 6306 3346 470R 6305 5304 5305
3330 22K 3331 22K
+33V
PFOUT 6 3446 10 3321 8K2 3320 8K2 15 6 2 17 3 19 GND_C 2307 6302 6303 GND_C GND_C GND_C 3308 0R1 3309 0R47 11 21 22 3317 15K 3447 2.7K GND_C 14 2323 470p 2.5V 11 10 GND_C GND_C VCC 3318 150K SYNC FROM STBY 9 12 3319 15K 3316 1K GND_C 3315 15K OSCILLATOR
+
+130V 2313 470uF 2314 22uF
5307 +35V 2316 1000u 2317 1000u 2318 100n
GND-C 5302 5308 3306 10R 3305 10K 6304 7301 18
3307 33R 16 2315 470p 6307
8 A S B
1V +
DEMAG 4 7 3310 330R 10 2311 1N Q
VCC
OVERVOLTAGE 17V
-35V 2321 1000uF 2319 470p 2321 1000u 2322 100n
VCC
FLIP FLOP R 2308 SOFT START 13
VCC
20
6309
5313
1302 4A 2330 470u 2319 470p 6308 5310 1301 4A
5314 2331 100n 2332 100n
2346 100N
-15V
1
UNDER VOLTAGE LOCKOUT 9.4/14.5 7302 FB 5
18V
2325 100n
5312 +15V 2324 2m2 5312 2327 470u 2326 100n
4. Power supply
Figure 4-7
STANDBY C 2442 1N 2303 100uF GND_C 3461 27K
-
REFERENCE SECTION
16
15
VCC 5 2302 6301 STARTUP 3300 22K 7303 1
3328 100R
3329 330R
3313 10K
2443 1uF
3326 4K7 4 2
2328 1u
3327 100R 2333 7303 +5VSTBY +5VSTBY 1305 7300 3304 1K 3303 100K 6313
3325 10K 2334
+130V 3324 150K 3323 2K7
7309
3344 10K ON_OFF 3343 10K 2349
CL 96532100_088.eps 011299
3322 470R 130V ADJ
19
20
4. Power supply 4.3 Full power supply
MG5.1E
When the set is turned On, the Main Switch Mode power supply is turned On. (Figure 4-7) This supply produces the +130 volt, +33 volt, +35 volt, -35 volt, -15 volt, and +15 volt supplies. When the On/Off line goes Low, transistor 7309 is turned Off, turning transistor 7300 On. This switches relay 1305 On. Startup voltage from the neutral side of the AC mains will charge capacitor 2303 to 14.5 volts which will overcome the undervoltage lockout of IC 7302. After the Soft Start capacitor 2443 charges, the oscillator inside the IC will turn On. Each cycle of the oscillator will set the flip-flop which will cause Pin 3 to go High. This will turn the FET switch 7301 On. Voltage is applied to the Drain of 7301 through Pins 4 and 8 of 5300 from the Power Factor Correction circuit. Current through sensing resistors 3308 and 3309 will develop a voltage which is applied to comparator "B" connected to Pin 7. When the voltage on Pin 7 reaches the reference voltage on the inverting input, the FlipFlop will be reset. The voltage on the inverting side of comparator "B" is limited to 1 volt. Therefore, the ramp voltage on Pin 7 will not exceed 1 volt. The circuit will continue to operate until the charge on capacitor 2303 falls below 9.4 volts shutting the IC Off. Each time 7301 is turned On, energy is stored in transformer 5300. Voltage from the Hot secondary on Pin 10 is rectified by 6301. When the output of this circuit has sufficient energy to maintain 2303 above 9.4 volts, the IC then operates in steady state. When IC 7302 develops a normal steady state operation, the 130 volt supply is sampled by resistors 3324, 3323, and 3322. This sample voltage is then sent to Shunt regulator 7303 which drives the feedback optoisolator 7303. The feedback voltage on Pin 14 is then compared with an internal 2.5 volt reference by comparator "C". Comparator "C" then sets the reference voltage on the inverting side of comparator "B" to control the On time of the drive at Pin 3. If the voltage on Pin 14 increases due to the 130 volt supply increasing, the On time of the pulse on Pin 3 will be reduced. If the 130 volt supply decreases, the voltage on Pln 14 would decrease, causing the On time of the pulse on Pin 3 to increase. This is used to keep the 130 volt supply at the correct voltage. Variable resistor 3322 is used to adjust the 130 volt supply to the correct level. The overvoltage protection circuit of the IC will shut the IC down if the VCC level on Pin 1 exceeds 17 volts. To troubleshoot this circuit, first check the On/Off line from the Small Signal Panel to ensure that it is going Low. Then check for the presence of startup voltage on Pin 1 of the regulator IC 7302. If the IC is working correctly, this voltage will be changing from 9.4 to 14.5 volts. If the startup voltage is not present, check the startup resistor 3300 and the bridge rectifier. If the voltage on Pin 1 is changing, check the drive signal on Pin3. Then check for signal on the gate and drain of 7301. An excessive load on the secondary, a short on the 130 volt line for example, would cause the supply to pulse with little or no voltage on the secondary.
Personal notes
MG5.1E
TO INTERFACE PANEL
+130V
130V RTN +15V
+8V6 5V
SS GND SSGND -7V7 8 9
1
2
3
4
5
6
7
+5V STBY
10 STBY RTN 11 50/60 HZ
1202 1 SS GND 1 2 1203 3 4 2 3 4 1210 5 6 7 8 9 POWER SUPPLY PANEL 1 2 3 4 5 1276 6 7 8 9 1222 6 5 1221 1212 4 3 2 1 +15V +15V RTN +5V STBY STBY RTN ON/OFF NC TO SCAN HIGH VOLTAGE PANEL 4 +130V 3 +130V 1205 1220 2 +130V RTN 1 +130V RTN
CL 96532100_052.eps 191199
160V DC NC 160V RTN CONTROL
SS GND +5V2 +5V2 5V STBY +8V6 +33V ON/OFF +15V
TO AUDIO AMPLIFIER
+15V -35V -35V RTN RTN +35V +35V -15V 15V RTN 10 +15V TO CONVERGENCE PANEL
TO MG99 SMALL SIGNAL PANEL
4. Power supply
Figure 4-8
AC SW BOARD
21
22
4. Power supply 4.3 Full power supply
MG5.1E
The Power Factor Correction, Standby, and Full Power circuits are all located on the Power Supply panel. (Figure 4-8) The Standby supply feeds the 5 volt standby supply to the Small Signal panel via Pin 5 of connector 121 0. The Standby voltage is present whenever power is applied to the set and the Mains switch is On. The On/Off Command from the Small Signal panel is fed to the Power Supply on Pin 8 of connector 121 0. This Pin will measure 5 volts when the set is in the standby mode and 0 volts when the set is turned On. The +33, +15, +8.6, and +5.2 volt supplies to the Small Signal panel are developed after the set is turned On. The +130, +15, +8.6, -7.7, and 5 volt standby voltages are fed to the Interface panel on connector 1202. The 50/60 Hz signal is a sync signal from the AC power mains which is used to provide sync to the clock circuit on the Small Signal panel. 350 volts from the Power Factor Correction circuit is fed to the Audio Amplifier on connector 1203. The Control line on Pin 4 of 1203 provides the operating voltage for the switching power supply on the Audio Amplifier panel. This Control voltage is switched Off when the set is in the Standby mode. Connector 1276 routes power to the Convergence panel while connectors 1212 and 1211 feeds power to the Scan High Voltage panel.
Personal notes
MG5.1E
4. Power supply 4.3 Full power supply
23
5109 AC INPUT BRIDGE 5 3
6103 350V DC OUT 2110
CURRENT SENSE
REGULATOR DRIVE 7102
7104
CL 96532100_086.eps 121199
Figure 4-9
The +15 volt source is fed to transistor 7308. (Figure 4-9) This is a Buck Switch regulator circuit which produces the 5.2 volt source. Transistor 7308 is turned On and Off by the Switching regulator IC 7307. To maintain the 5.2 volt source at the correct voltage, the output is sampled and fed to Pin 5 of the IC. The voltage on Pin 5 is then compared with an internal reference. This drives the Pulse Width Modulator which controls the On time of 7308. The -15 volt source is fed to linear regulator 7305 to produce the -7.7 volt source. The +15 volt source is also fed to the 8.6 volt regulator 7306 to develop the 8.6 volt source.
Personal notes
5.
24
SCAN CIRCUITS5.1Line Drive
10 +240V +130V 2815 680p 7 13 3815 0R27 6 14 6803 2850 470p 3 A 1 16 15 3867 1R +28V 6850 2851 100u 2899 4n7 3821 470R 2818 820p 2822 430n RED YOKE +130V 5 470p 3819 1R -13V 2826 1000u 2824 3828 68K 6801 2814 68u 2816 68K 3825 68K +130V 2809 100n 2810 330u 3810 2K2 3811 2K2 2898 220U 7802 1 2 7801 6808 2819 27n 5800 5805 3814 33R 6806 3 3813 1R 2811 330p 2817 3n3 4 2806 1n 3808 2K2 2807 100n 3807 330R 3809 330R 3823 68K +13V 2827 1000u 3865 0R47 8 12 6802 3818 1R FIL 9 2825 470p
5801
3829 15R
7803
1509-1 HDRV LINE DRIVE 3681 2K2 +15V 3840 1M 3457 2K2 E_W 3802 68K 3458 2K2 3571 2K2 3591 2K2 7553 7551 3456 100R A HPUL 3835 3K3 2837 10u 3836 270R +28V 2804 10u 3837 12K 2838 1n 3812 100K 6830 2839 10n 3839 330K 7830 3834 1R 2836 1n 5802 4 8 1 6 3801 27K 3866 18K 3590 100K 2573 2n2 7552
3830 470R
5804
2834 430n 5803 3452 4R7 2452 2u2 3453 4R7 3454 4R7 3455 4R7 2820 4u7 2805 100n 3805 100R
GREEN YOKE
+15V
5. SCAN CIRCUITS
Figure 5-1
2801 100n 3806 1K
+28V
BLUE YOKE
3803 100R
2800 1u
7800
1507-4 H_PUL
1511-1 HFB
3890 100R
3800 1K5
3817 470R
1509-7 FBSO
+15V
3833 100R
3832 3K3
HPUL_BLNK
7804
3831 68K
CL 96532100_089.eps 121199
LV
MG5.1E
MG5.1E
5. SCAN CIRCUITS 5.1 Line Drive
25
Line Drive from the Small Signal panel is fed to connector 1509 Pin 1 and then to buffer transistor 7803. (Figure 5-1) Transistor 7803 then drives the Line driver transistor 7801. Line drive is then fed to the Line output transistor 7802. Transistor 7802 drives the three Line Yokes and the Scan transformer 5801. The Scan transformer produces a 240 volt supply for the CRT drive circuits, a Filament drive for the CRT'S, a plus and minus 13 volt supply for the Frame drive circuit. It also produces a 28 volt supply for the beam limiter circuit in the High Voltage circuit. The output of the Line Output transistor 7802 is also fed to buffer transistors 7800 and 7804 to produce a Line Sync pulse (HPUL) and Line feedback pulses to the Small Signal panel (HPUL and HFB). The output of transistor 7804 also produces a Line Blanking pulse (HPUL-BLNK). Drive for geometry correction from the Small Signal panel on the E-W line drives transistors 7553, 7551, and 7552. This circuit drives the return side of the Line Yokes to provide Horizontal corrections to the geometry. Geometry correction drive, E-W, is also fed to transistor 7830 which produces drive for the Dynamic Focus, LV. The Line component to the Dynamic Focus is added in transformer 5802. The Line Sync (HPUL) is used to synchronize the High Voltage drive. If this pulse is missing, the High Voltage circuit will shut down. A loss of drive to the Line Yokes will cause the High Voltage to shut down.
Personal notes
26
5. SCAN CIRCUITS 5.2 Frame Drive circuit
Frame Drive circuit
MG5.1E
5.2
6550 VPUL 3554 100R 2511 100n 1 VERT DRIVER 3572 100R 2567 470p 1509-7 VDRV 2564 470p 3551 1K8 8 FB GEN DRIVER 7 3565 220R 3562 4R7 2565 100n 3595 33K 7590 2557 100uF 3592 330R +13V 2557 100uF +15V
-13V
3594 100R 3593 1K 1511 VFB
4 3 2 VERT OUT VERT OUT 5
VDRVP 1509-5
2822 220R 3550 1K8 3583 1R 9 3585 10K -13V 6 2559 100n 3563 220R 2558 68n 3824 220R 3826 220R
RED YOKE GREEN YOKE BLUE YOKE
2570 470p
3573 100R
2571 470p
CL 96532100_090.eps 121199
Figure 5-2
Frame Drive from the Small Signal panel (FDRVP and VDRV) is fed to the Frame Output IC 7550. (Figure 14) This circuit is powered by a +13 volt supply connected to Pin 8 and a -13 volt supply connected to Pin 6 which are supplied by the Line Drive circuit. Pin 5 of 7550 provides drive for the the three Frame yokes. Frame drive feedback from the return side of the yokes is fed back to Pin 2 of 7550. Frame sync (VPUL) for the High Voltage shutdown circuit is output on Pin 4 of the IC. Output from Pin 7 is buffered by transistor 7590 to produce a Frame Sync pulse (VFB) for the Small Signal panel. A failure in this circuit would cause the High Voltage to shut down. A problem in this circuit could be caused by a loss of drive from the Small Signal panel or a failure in the Line Sweep circuit. An open Yoke connection would also cause the Frame drive from the IC to shut down.
Personal notes
5.3 High Voltage circuit
MG5.1E
+15V 3902 12K 3901 10K +130V 2900 220uF 6 2929 330P 5900 6910 6902 1 EHT 2924 820P 2924 820P DAG GND FB 2914 330uF 3900 220R
3905 120K
3995 12K
2902 1n
3906 1K5
HD DIV
2903 1uF 7 OSCILLATOR REGULATOR +15V 7900 6905 5901 3934 0R27 5902 +130V 3922 1K5 +15V 3912 10K +15V 7909 3917 1K 3945 3999 6915 3949 56R 6916 +15V 8 3948 1K COMPARATOR CIRCUIT 1 3941 56K 3994 47K 7907 3969 47K 2918 2u2 7902 2 LATCH 2921 4.7uF 4 6 3909 180R 3996 1K 3511 47K 3918 15K 3919 1K5 +15V +15V 7901 7903 3508 4K7 6900 3954 39K +15V 3968 22K 3955 33K 3967 470R 6950 6V8 6951 ABL 3943 2K2 3963 2K2 3939 2K2 3920 1K 3932 5K6 2923 1n 3924 180R 3933 1M 3951 10K 7 7908 3975 100R ON/OFF -13V 3959 1K 3971 100K 3981 7K5 3982 7K5 +28V 6914 +5VSTBY 680K 2922 470uF 3916 1K +15V 3957 1K5 2916 6N8 3950 33R 3962 10R 3961 68R 1 7952 3962 100R 2 8 3990 1K8 3928 1K8 2905 100n 2907 15N 2933 330P 3913 4K7 3915 820R 2909 2N2 2910 1uF 3923 15K 6909 7906 HV OUT 2913 1000uF 3930 10K 3937 33K 3980 4K7
+15V 5 3 4 PHASE DETECTOR PRE-DRIVER
2908 10n
3908 1K5
2904 10n
7905
HPUL
3914 10K
3907 5K6
2915 3n9 3938 30R 3 FOCUS
3910 10K
2906 10n
3911 15R
10 6
3998 15R
5 +28V
+15V
+15V
150K +15VSTBY
5. SCAN CIRCUITS
Figure 5-3
6904 3 3946 15K 3991 1K 7501 3501 10K 6500 +15V +15V +15V 3500 4K7 2920 4u7 3993 120R 3944 120R
6502
2503 680p
3503 120K
3507 3K3
6501 3506 120K
3940 14K
+15V
+15V
6552 6V8
2501 470N
3510 470K
6906 -13V 2927 1u
2917 100n
VPUL
3505 220R
6502
3503 120K
6501
7953
+15V
+15V
+15V
+15V
7904
3927 10K
6505
3514 10K
3513 39K
3512 10K
3926 100R
3931 1M 3964 10R 3942 100K 3973 82K 3989 680R 3965 1M 2919 150n 2931 470n 3947 620R 6907
2911 4u7
7502
3921 18K
CL 96532100_091.eps 121199
BLANKING
27
28
5. SCAN CIRCUITS 5.3 High Voltage circuit
MG5.1E
Line Drive (HPUL) from the Line Drive circuit is applied to transistor 7905 and then to Pin 3 of IC 7900. This Pulse is used to phase lock the oscillator for the High Voltage drive. This circuit will default to a frequency 31.25 KHz if no signal is applied. The Sync signal will have a frequency of 31.25 KHz if a PAL or SECAM signal is applied to the set. If an NTSC signal is applied to the set, the frequency will be approximately 31.5 KHz. Drive for the High Voltage output transistor is output on Pin 1 of the IC. This signal drives transistor 7952, pre driver, and the High Voltage Output transistor 7906. The High Voltage transformer 5900 outputs 30 KV to the High Voltage Distribution block. Feedback from the Block is fed to the Shunt Regulator 7901 where it is compared with an internal 2.5 volt reference. The output of the Shunt Regulator drives transistor 7903 which drives Pin 8 of 7900. The voltage on Pin 8 of 7900 determines the On time of the signal at Pin 1 of the IC. The width of this pulse determines the On time of the High Voltage output transistor 7906. The On time of 7906 determines the amount of energy stored in 5900 which sets the level of the High Voltage. The voltage on Pin 8 of 7900 has an operating range of 4.5 to 4.8 volts. Beam Current is monitored from the bottom of the diode stack in the High Voltage Transformer and fed to transistors 7907 and 7908. Increases in Beam Current will lower the output voltage of the these transistors. This voltage is applied to Pin 8 of 7900 to make minor corrections to the High Voltage. It is also fed back to the Video Circuits on the Small Signal panel via the ABL line to make minor changes in the Picture level to compensate for changes in Beam Current. This voltage is also fed to Pin 1 of 7902 where it is compared with an internal 3.5 volt reference. Excessive beam current would cause this voltage to drop below 3.5 volts which would set the internal latch of 7902. Pin 6 of the IC would go Low which would turn transistor 7909 On. This would keep transistor 7952, High Voltage driver, On. The High Voltage would be shut Off. A High applied to Pin 7 of 7902 by turning the set Off would reset the latch. The High Voltage is shut down if it increase beyond the designed safety limits. Pin 6 of the High voltage transformer is rectified by 6904 and is fed to Pin 3 of 7902 where it is compared with an internal reference. The normal voltage at this Pin is approximately 25 volts DC. If the voltage on Pin 3 goes above 28 volts for more than 800 ms, the Latch inside 7902 will be set, shutting the High Voltage Off. To prevent damage to the, CRT's in the event of a failure in the Frame or Line drive circuits, the High voltage is shut down. The Line Drive pulse (HPUL) is rectified by diode 6502 and is applied to the base of transistor 7953. The Frame drive pulse (VPUL) is rectified by 6502 and is also applied to the base of 7953. As long as Frame and Line drive is present, the voltage at the Base of 7953 will keep the transistor turned Off. Transistor 7501 will turn On through resistor 3501 and zener diode 6500. This will turn 7503 On, turning 7502 Off, which turns 7904 Off - If the Frame or Line drive should fail, transistor 7953 turns On, turning 7501 Off, turning 7503 Off, turning 7502 On, which turns 7904 On. This turns 7903 On hard which causes the voltage on Pin 8 of 7900 to go above 4.8 volts. The pulse width of the drive on Pin 1 of 7900 will then decrease to
the point where it is not usable. The High Voltage will then be shut down. When 7501 turns On it applies a High on the Blanking line. This is applied to the CRT drive circuit on the Interface panel to blank the CRT drive signal. The focus voltage from 5900 is fed to the Focus/G2 block mounted on the TV chassis. Therefore, an easy way to determine if the High Voltage has failed would be to measure the the G2 voltage on one of the CRT panels. If High Voltage has failed, check the voltage on the anode of 6901. If this voltage is approximately 0.7 volts, the High Voltage has shut down due to a loss of Frame or Line drive. If this voltage is approximately 15 volts, the Frame and Line drive circuits are working correctly. Next, check the voltage on Pin 6 of IC 7902. If this voltage is zero, the problem was caused by an overvoltage or overcurrent condition. Before attempting any component level repair on this circuit, the CRT panels should be unplugged from the CRT'S. This is to prevent damage to the Phosphors of the CRT's is case drive is applied to the CRT's while Frame or Line drive is missing.
Personal notes
MG5.1E
6. SMALL SIGNAL PANEL 6.1 Block diagram
29
6.
SMALL SIGNAL PANEL6.1Block diagram
UV13XX
TDA9320H SAA4978
TOPIC TDA9178
HA/VA HD/VD
TDA933XH
ROTATION
SAA5800
CL 86532047_001.eps 140798
Figure 6-1
Chassis name The 'MG' chassis is the successor of the MD1, MD2, GFLchassis. The MG architecture is global and can be produced all over the world. Explanation chassis name MGX.YZ X depends on specification Y depends on introduction-timing Z region e.g. E(urope); A(sia Pacific); U(SA) This manual deals with the MG5.1E. A small signal panel (SSP) is used and a large signal panel (LSP). On the LSP there are only a few SMD's, but the SSP is further integrated. There are no modules anymore; the FBX (feature-box) is integrated on the chassis. Due to the fact that all features are flat on one board, repair down to component level is an absolute must. For this reason there is a lot of diagnostic support built-in in the chassis: · customer service mode (CSM) as used in the MD2.2chassis. It decreases the number of nuisance calls. · service default mode (SDM). Predefined state of the set. · service alignment mode (SAM) to do all kind of alignments, select test patterns, display error codes,.... · full support of the dealer service tool (DST).
New tools and service features A lot of additional service "features" are built in the MG5.1E. These "features" can be addressed with a new tool called ComPair (Computer Aided Repair). This is an interface that can receive the error codes and can send RC5 and RC6-codes. To this interface belongs also software and a CD-ROM with the service manual, circuit descriptions and fault finding trees. In this way searching for components on the PCB and schematics is history. Explanation Small Signal (fig 6.1). The tuner type UV1316 is a PLL tuner and delivers the IF-signal to the HIP (High-end Input Processor (TDA9320H)). The HIP has the following functions: · IF-part · video source select and record select · colour decoder (PAL/SECAM/NTSC) · synchronisation Three scart connectors can be used. Scart 1 and 2 are full scart and scart 3 is only cvbs. Scart 2 is meant for VCR, thus on this scartpin 10 is used for Easylink and there is possibility for y/c in/ out. The cvbs-out on pin 19 can be used for WYSIWYR (= what you see is what you record). A digital combfilter can be used to have Y/C separation. The HIP delivers the signal to the PICNIC (SAA4978). The PICNIC takes care of: · ADC (9 bits) (was FRONTIC) · DAC (was ECOBENDIC) · 100 Hz (was ECOBENDIC) · Panorama mode (super zoom) (was PANIC)
30
6. SMALL SIGNAL PANEL 6.1 Block diagram
Noise reduction (was LIMERIC) Dynamic contrast (was SMARTIC)
MG5.1E
· ·
Personal notes
For digital scan the PROZONIC (SAA4990) is required, that can be connected to the PICNIC. The PROZONIC was already used in the GFL- and MD2-chassis. For natural motion the MELZONIC can be used. These two ICs are mentioned in the blockdiagram as 2fh-features. For sets with PAL+ the same concept is used as in the MD2chassis and this is also connected to the PICNIC. From the PICNIC the signal is fed to the TOPIC (The most Outstanding Picture Improvement IC) TDA9178. This IC handles various picture improvements, e.g. sharpness. This IC works together with the PICNIC to handle auto-DNR. If there is noise in the videosignal then the DNR has to be high, but the sharpness must be low. So also the other possibility if the signal is perfect then the DNR is not necessary (DNR low) and the sharpness can be higher. (First introduced sets will not have Topic-ICs and also not a light sensor.)
noisy signal good signal high low low high
The customer can select AUTO TV for a very high performance. Auto TV contains algorithms for contrast-improvement, sharpness, noise reduction and better colour behaviour. Via a light sensor the influence of the ambient light can be used for optimal contrast/brightness control. After the TOPIC the YUV-signals are fed to the HOP (High-end Output Processor (TDA933X)). In the HOP is the video control part and geometry integrated. The RGB-signals from TXT/OSD are inserted via the HOP. This IC has all functions from a videoprocessor and geometry control (like the DDP in MD2).The cut-off control is a little different: via the service menu there is an indication that the VG2-setting is correct (later in the first sets). The geometry part delivers the H-drive, V-drive and also a drivesignal for rotation. Blue mute is possible for: · HOP · OTC · PICNIC For the MG5.1E blue mute is made via the PICNIC and perhaps in future sets from the OTC. The soundpart is built up around the MSP3410D (all versions have NICAM) for IF sound detection, sound controls, source select. The sound for the subwoofer is derived from L and R. To the MSP3410 a new IC can be added: called SEDSP (Sound Effects Digital Sound Processing IC (SAA7712H)). This IC takes care of Dolby prologic decoding and some other features like virtual DOLBY, incredible surround, DBE, equaliser, ...
MG5.1E
6. SMALL SIGNAL PANEL 6.1 Block diagram
31
1010 degaussing +t Rs +t Rp 7020
~ 220V
+5V Standby
+140 (Vbat)
7213 start 7020 7020 7808 +8V6
3517/3520 7212 +5V Standby DCDC convertor IC7520 3 MC44603 10 14 IC7556 1 M34063A 5V2
TL431 Blockdiagram supply-part
CL 86532047_002.eps 140798
Figure 6-2
I2C bus. In MG5.1E three different I2C busses are used: 1. Slow I2C bus (SCL/SDA-S); speed 100 kHz used for various IC's 2. Fast I2C bus (SCL/SDA-F); speed 400 kHz. (In the OTC there is only one hardware I2C bus. The two busses are made by a very fast switch.) 3. I2C bus for NVM (SCL/SDA-NVM). This short I2C-bus is used to avoid data corruption in the Non Volatile Memory. Microprocessor = OTC2.5 (On screen display, Teletext and Control, level 2.5 Txt) with integrated teletext (SAA5800). This IC takes care of the analogue Input- and Output-processing. The OTC, ROM and RAM are supplied with 3.3V. This voltage is derived from the +5V Standby.
Personal notes
32
6. SMALL SIGNAL PANEL 6.1 Block diagram
MG5.1E
+140V (Vbat)
+13
+13
+5V2 Hdefl 7421 2432/2434
HOP
Hdrive
east/west modulator
Vdrive+ Vdrive-
7600 TDA8177 +13V
-15V Vdefl Blockdiagram deflection
CL 86532047_003.eps 140798
Figure 6-3
Explanation Large Signal (fig 6.2 + 6.3). In MG5.1E there is a separate Standby supply that is used to reduce the Standby power. The main power supply is completely switched off via a relay and only the Standby supply is operational in Standby. A second relay (no triac) is used for switching off the degaussing circuitry. The degaussing is not switched from Standby to on. The power supply is a Fixed Frequency Supply with an operating frequency of 40 kHz. For the control part the MC44603 is used (also known from a lot of other chassis). Secondary a DCDC-converter (MC34063A) is used for stabilisation of the 5V2 for various circuitry. The Standbycommand is also fed to the FFS to ensure quick switch-off of the power supply. In fig 6-3 the blockdiagram is drawn for the line output stage. There is no seriesswitch as in MD2- and GFL-chassis, because this function is now integrated in the HOP. In case of a flash or protection the line output stage is switched off by the HOP. The complete geometrycontrol is integrated in the HOP. The V-drive is also coming from the HOP and the amplifier is realised with TDA8177.
Personal notes
MG5.1E
6. SMALL SIGNAL PANEL 6.2 Service Modes / ComPair
33
6.2
Service Modes / ComPair
Service Modes In the MG the following service modes are available: · SAM (service alignment mode) · SDM (service default mode) · CSM (customer service mode) This looks very much alike the MD2.2. (For details see service manual.) The DST tool can still be used, but an upgrade version of this is the ComPair tool (a PC-based diagnosis system). Difference related to previous sets: With an 12C bus error, the set will not be placed in protection anymore. ComPair (tool) ComPair (Computer Aided Repair) is a new tool for repairing the new TV-sets and the new high-end video-recorders. With the help of ComPair, repairing a set will be more time effective even without much knowledge of the set. By guiding the technician with the help of self-diagnostics and documents with text and oscilloscope waveforms on the screen of the PC, repair-time will decrease as well in the SSPas in the LSP part of the set. ComPair consists of an electronic interface connected to the computer, to make via infra-red communications a link to the upmarket TV-sets and via a wired I2C a link to Basic TV-sets and high-end video recorders, and a Windows based computer program. ComPair is running on a 486 PC with Windows 3.1 onwards. Infra-red commands, received from the ComPair interface, are converted into I2C commands towards devices connected to the I2C bus. In this all registers from ICs can be read to make a good diagnose. Step-wise start-up/step-wise shutdown (feature of ComPair) With ComPair it will also be possible to start-up the set step by step. In this way it is possible to distinguish which part of the start-up routine (hence with circuitry) is causing the problem (see also chapter 17). The repairman will be guided by ComPair by means of fault-finding instructions with text and oscilloscope waveforms. By going a step downwards a certain protection can be de-activated again, and measurements can be performed.
Personal notes
34
6. SMALL SIGNAL PANEL
MG5.1E
6.3
Control and TXT
+5VSTBY 7012 3059 3054 G 3V3 470E TLUV 5300 SERVICE SEND LED IR receiver 100 R MAINS-SWITCH PANEL
ON/OFF
470
90
+5V STBY
7009 3V3
3V STBY
113 111
8V6
5VSTBY
SAA 5800 OTC 2.5
7006 7007 POR 104 74 R G B FADING 100E 5V2 3V3 108 H V KEYBOARD 107 93 83 84 109 115 96 103 106 AFC tuner HIP HSEL (OPTIONAL) STATUS 3 I/O CNTR - BUS OUT I/O I/O CNTR - BUS IN I/O FRONT DETECT 16/9 DETECT 90 94 95 5 16 6Mc 3V3 3209 STBY RAM_CS RAM_DE 3206 17 18 73 I2C-0 I2C-1 I2C-SLOW I2C-FAST HIP I C-3
2
470
STANDBY
77 8V6 3V3 105 OSD/TXT 78 79 80
+ 10R
HOP IC
SELECT CL/VL RESET AUDIO SOUND EN ABLE CVBS for txt PEAKING PEAKING FILTER TUNER FBX VIDEO SEL AUDIO SELECT
7
RAM_DE CASHN CASL RaSN WE
HOP
ROM CE ROM CS 23 11 ROM 16Mbit (2Mbyte)
40 43 42 41 12 14 FLASH RAM EPG
WE
MSP 3410
TOPIC
41 71 73 69 70
RAM TXT CONTROL
NVM 32 Kbit
AO
A19
AO
A17
AO
A8
CL 86532047_004.eps 051098
Figure 6-4
MG5.1E
6. SMALL SIGNAL PANEL 6.3 Control and TXT
35
Control part Remote Control In MG5.1E a new remote control is introduced which uses RC6, because new commands are used like cursor control in 8 directions. There are two mode buttons on the side of the remote control: One for VCR and the other for DVD/SAT (digital source). OTC The SAA5800 (IC7003) is called the OTC (OSD, TXT and CONTROL). In this IC the microprocessor and the TXTdecoder are integrated. The SAA5800 is also called the OTC2.5 because also TXT-level 2.5 is supported. The OTC has also : · RGB outputs for blending. The contrast (for blending) is software controlled. · OTC 2.5 has various I/O ports for I2C, RC5, LED, .... The software for MG can be 2 MB (Megabyte). For sets with nexTView (also called EPG) a 512 KB flash-RAM IC7013 is used to store the Electronic Program Guide. For TXT-data 440 pages can be stored in a RAM IC7001. This is a DRAM of 4 Mbit and this IC is also used to store data of a working set. The Non Volatile Memory IC7008 is a 32 kbit version M24C32W6. All ICs in this part are supplied with 3V3. For this voltage a 3V3 stabiliser is used (IC7009). At start-up the POR is generated with TS7006/7007. During a reset all I/O pins are high. When a POR is generated the TV-set is in Standby mode. Via pins 105 and 106 the 8V6 and the 5V2 are sensed. If one of them is not present, the FFS-supply is switched off. The OTC will generate an error code to indicate what was wrong. The horizontal and vertical flyback pulses are also fed to the OTC for stable OSD and TXT. To create good stable pulses the HFB(H) and VFB(V) are inverted and fed to the OTC. The RGBoutputs (77/78/79) together with fading (pin 80) is fed to the HOP. The fading pin has in fact a double function: · Make transparent menu · Fast-blanking for TXT In MG5.1E there are three I2C-busses used: · Slow I2C bus for tuner, fbx, video- and audio-selection · Fast I2C bus for the HIP, HOP, MSP3410 and the TOPIC · NVM- I2C bus for the Non Volatile Memory to prevent data corruption (=I2C3) The OTC has also a connection with mains switch/led panel: · Driving the "ON" and "Standby"-leds . The green led gives a quick indication that the 8V6 is present.<----- Service tip · MG5.1E has an IR-send led connected to pin 90 for communication with DST or ComPair. · The remote control signal comes in on pin 100. This can be RC5 or RC6 commands. TXT The TXT-decoder in the OTC gets two video signals: Direct to pin 5 and via the peaking filter (for Scandinavian countries) to pin 7. The input is selected via country selection in the installation menu. The RGB-outputs are available on pins 77/ 78/79. Fast blanking is realised via pen 80, but TS7017 and TS7018 are added to create a nice fast blanking signal that is needed in the TXT-mixed mode. These transistors are driven
by an extra fast-blanking signal from pin 81. In future sets this circuitry will be deleted. In the previous chassis there was separate memory to store the TXT information. In MG the RAM (IC7001) of the microprocessor is also used for the TXTdecoder. NexTView NexTView allows the user to display a program guide on the TV screen which contains extensive information for each program. This information can be displayed in a number of different summaries: DAY: The daily summary shows, from the current moment, the program schedule for several stations for a short time ahead. CHANNEL: The channel summary shows the program schedule for one station. THEME: The theme summary shows, for each theme, the program schedule of the various stations. These themes consist of sport, film, culture, etc. and is determined from the station side. NexTView does not have to restrict itself to information about the station which is being viewed, but also offers information about other stations. In the various summaries 3 different commands can be given for the various program overviews. These commands appear as follows: WATCH: The set immediately switches over to the station concerned. REMINDER: The start time and date and the station of the program concerned is stored in the TV reminder list. The TV will give an OSD-message with the program information, or switch on the set at the correct moment (provided the set is in Standby) and tune to the station concerned. RECORD: The timer of the video recorder with `Easylink Plus' is programmed with the data of the program concerned. There has to be a video recorder (with Easylink Plus) connected to SCART2 otherwise the `RECORD' function will not be highlighted. The connection is via pin 10 from SCART. This means that it has to be a full SCART or at least pin 10 has to be wired. In order to be able to realise nexTView, two teletext type data flows, Datastream 1 and 2, are transmitted with various subcode pages of information. This data flow can transport limited information (max. 40 pages). Datastream 1 is quick repeating with a repetition time of approximately 20 to 30 seconds. However, Datastream 2 has a much longer repetition time of approximately half an hour and has a large transport capacity. Datastream 1 contains information of the station which is being viewed. Datastream 2 contains up to one week of advance information from various stations which are covered by the provider.
36
6. SMALL SIGNAL PANEL 6.3 Control and TXT
MG5.1E
Realisation of nexTView in MG5.1E MG5.1E knows two executions of nexTView called "This Channel EPG" and "Multi Channel Composite EPG". "Multi Channel Composite EPG" makes use of both Datastream 1 and Datastream 2. Due to the size, in particular of Datastream 2 and the pass time which is coupled with that, a number of additional provisions have to be made in the set. Therefore, an extra Flash Memory is used in order to retain the information. Both the interpretation and storage of Datastream 2 require calculating capacity of the microprocessor. This all can not be performed during normal operation. Datastream 2 is then also stored at the moment that the set is in Standby. For this the set will go into Semi-standby (also see Power Supply chapter). The Semistandby mode can be recognised by both the Standby and the "On"-LED illuminating. In the Semi-standby mode the entire small signal is switched on and it will be tuned to the nexTView provider which has been assigned during installation. The microprocessor can now use its full calculating capacity in order to load the Flash Memory. After the Datastream 2 has been completely stored the set will switch to Standby. This takes place after approximately half an hour. After this the set will check every 12 hours whether the information in Datastream 2 has changed. To do this the set again switches to Semi-standby and the Flash Memory is erased and re-loaded when the information in Dataflow 2 has changed. Every morning at 5:40 the nexTView information will also be re-loaded because then information for the previous day can be deleted from the Flash Memory. "This Channel EPG" makes use of Datastream 1only. This data is loaded in the RAM as soon as the set is switched on. Only data of the current and next day is loaded and this is only data of the station watched. No Flash Memory is used. As soon as the set is put in standby after watching, the set will go to semi-standby for updating the so called CNI numbers. For this the set tunes to all pre-installed presets and tries to detect the CNI number of the broadcaster. A CNI number is an unique identification number assigned to a broadcaster and is available in TXT package 8/30. This CNI number will be stored in the EAROM as part of the preset information. As more then one broadcasters can be available on a certain preset more then one CNI number can be registered under one preset. These CNI numbers are used to identify the right broadcatser when EPG features like Watch, Record and Remind are used. If no nexTView provider is available the set will show a nexTView alike screen including a TXT page as soon as the nexTView feature is activated. This TXT page can be set to the TXT program guide if available. Some of the nexTView features as record can still be used in this case.
Personal notes
MG5.1E
6. SMALL SIGNAL PANEL
37
SAA5800 pin description
pin nr.
1 2 3 4 5 6 7 8 9 10 11
pin name
IREF_DEC IREF REF+ CVBS0_R CVBS0 CVBS1_R CVBS1 STN/BLACK VDDA VSSA TEST0
Description
Iref decouple Current reference input ADC voltage reference decoupling Reference for video signal 0 Composite video signal 0
I/O Level
I I I I I analogue analogue analogue analogue analogue analogue analogue analogue 3V3 gnd gnd
pin nr.
61 62 63 64 65 66 67 68 69 70 71
pin name
A7 A8 A17 A19 A18 A20 A21 A22 RASn WEn CASHn
Description
Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit DRAM Row address strobe Write enable DRAM Column address strobe high byte DRAM Column address strobe low byte External rom access Reset Digital power 2 Digital ground 2 Red Green Blue Blending Data indicator Frame indicator Horizontal display sync Vertical display sync SCL Slow I2C bus SDA Slow I2C bus SCL Fast I2C bus SDA Fast I2C bus Reserved for switching SCAVEM IR Led for Service SDA EAROM SCL EAROM Status SCART 4 Reset audio Sound mute Switch to service default mode Easy link out Fixed Beam Current Switch Off (FBCSO) IR receiver Digital power 3 Digital ground 3
I/O Level
O O O O O O O O O O O digital digital digital digital digital digital digital digital active low active low active low
I Reference for video signal 1 Composite video signal 1 I ADC current reference decoupling Analogue power Analogue ground Ground I I I I
12
TEST1
Ground
I
gnd
72
CASLn
O
active low
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TEST2 TEST3 TEST4 OSCOUT OSCIN OSCGND VDDN1 VDD1 VSSD1 D11 D4 D3 D12 D10 D5 D2 D13 D9 D6 D1 D14 D8 D7 D0 D15 VDDP1 VSSP1 ROM_OEn RAM_OEn RAM_CSn ROM_CSn
Ground Ground Ground 6 MHz Oscillator out 6 MHz Oscillator in Oscillator local ground reference Digital power (connect to VDDD1) Digital power 1 Digital ground 1 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Periphery power 1 Periphery ground 1 ROM output enable RAM output enable SRAM chip select (FLASH RAM) ROM chip select
I I I O I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O O O
gnd gnd gnd analogue analogue gnd 3V3 3V3 gnd digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital 3V3 gnd active low active low active low active low
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
EAn RESET VDDD2 VSSD2 R G B FADING DATA/VIDEOn FRAME HSYNC VSYNC P0.0|SCL0 P0.1|SDA0 P0.2|SCL1 P0.3|SDA1 P0.4|RXD P0.5|TXD P0.6|COR P0.7 P1.0|T0 P1.1|T1 P1.2|T2 P1.3|INT0 P1.4|INT1 P1.5|INT2 P1.6|INT3 P1.6|RC5 VDDD3 VSSD3 P2.0|PWM0
I I I I O O O
active low active low 3V3 gnd analogue analogue analogue
O analogue O high active O high active I active low I active low I/0 digital I/O digital I/O digital I/O digital O active low O I/O O I O O I I I I I I digital digital digital active low active low active low active low digital active low active low 3v3 gnd active high
Front detect: Signal I present on front connector Standby PROTECTION +8V6 PROTECTION +5V2 KEYBOARD Status SCART 3 Periphery power 3 Periphery ground 3 Stand-by LED Beam Current protection (BC-PROT) DC protection (DC-PROT) Service mode input Easy link out O I I I I I I O I I I O
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A16 A0 A15 A1 A14 VDDP2 VSSP2 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9
Address bit Address bit Address bit Address bit Address bit Periphery power 2 Periphery ground 2 Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit
O O O O O I I O O O O O O O O O O
digital digital digital digital digital 3v3 gnd digital digital digital digital digital digital digital digital digital digital
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
P2.1|PWM1 P2.2|ADC1 P2.3|PROTECTION +5V2 P2.4|KEYBOARD P2.5|AGC P2.6|STATUS3 P2.7 VDDP3 VSSP3 P3.0|LED0 P3.1|LED1 P3.2 P3.3 P3.4 P3.5 P3.6|SERVICE MODE P3.7|P50_OUT
active high active high active high analogue active low 3V3 gnd low: LED on active high active high low active digital
cl96532100_116.eps 021299
38
6. SMALL SIGNAL PANEL 6.4 Tuner & IF
Tuner & IF
MG5.1E
6.4
HIP
TUNER SAW VIDEO 2/3 IC7501 TDA9320H CVBS 13 HA/VA 60/61 I2C SAW SOUND 63/64 SOUND IF 5 49 50 R OTC G B LMN I2C BG 36/41 37/42 38/43 22 19 51 LF AM 5 V U V
CL 86532047_014.eps 051098
Figure 6-5
Tuner A new tuner is introduced for MG5.1E: UV1316 Mk2. The tuner is I2C-controlled and has three bands: low/mid/high (see table).
Tuner Low Mid High UV1316 Mk2 44 - 155.9375 MHz 156 - 440.9375 MHz 441 - 865.25 MHz
received. One extra filter (5103) (40.4 MHz) is necessary for L/ L' sets with 6.5 MHz sound to suppress the neighbour channel. Two SAW filters are used: One for filtering picture-IF and the second-one for sound-IF. The output of the tuner is controlled via an IF-amplifier with AGC-control. This is a voltage feedback from pin 62 of the HIP to pin 1 of the tuner. AGC take-over point is adjusted via the service alignment mode 'Tuner AGC'. If there is too much noise in the picture, then it could be that the AGC setting is wrong. The AGC-setting could also be mis-aligned if the picture deforms with perfect signal. The IF-amplifier amplifies too much. The video IF-signal is fed to pins 2/3 of the PLL-controlled IFdemodulator. The voltage controlled oscillator of the PLL is adjusted via the service menu `IF AFC'. If the alignment is correct then the displayed frequency in the installation menu is the same as the applied frequency from a generator. The external coil L5108 connected between pins 7/8 is used as reference. The demodulated IF-video signal is available at pin 10 of the HIP. In this videosignal there is a rest of soundcarrier, which is filtered by the sound traps 1106/1107. Then the signal is again fed into the HIP on pin 12 where the group delay can be corrected, dependent on the norm which is received. On pin 13 the CVBS-signal becomes available which is used for further processing in the television. Via TS7502 the signal is supplied to external 1 and back into the HIP on pin 14 to the source/ record selection. (See chapter 6.6 for further description.) In short: Video signal on pin 10, back-in on pin 12, out again pin 13, back-in on 14. So there are various pins where the video
SYSTEM IF PC-SC FREQUENCY distance MHz Mhz sc1 B/G L L' I D/K 38.9 38.9 33.95 38.9 38.9 5.5 6.5 6.5 6 6.5 sc2 5.74 dig 5.85 5.85 5.85 6.55 6.24/ 5.85 6.74
DESTINATION
WEST EUROPE WEST EUROPE (only France) WEST EUROPE (UK) EASTERN EUROPE
`sc1/sc2' are the analogue sound carriers and `dig' stands for the NICAM (digital) sound carrier. The IF-filter is integrated in one SAW (Surface Acoustic Wave) filter. The type of this filter is different, dependent of the standard(s) that has to be
MG5.1E
6. SMALL SIGNAL PANEL 6.4 Tuner & IF
39
signal can be checked. To realise quasi split sound the IFsignal is fed to the HIP on pin 63/64 via SAW-filters 1104/1105. The FM (or AM for L-norm) -modulated signal is available on pin 5 and is fed to the audio demodulator MSP3410 (see chapter 6.5).
Personal notes
40
6. SMALL SIGNAL PANEL
MG5.1E
Search command
Start search
Y
1 Tuned to TV transmitter?
N
N
3 System L'?
2 System L'?
N
Y
L'frequencies covered
Y
Y
6 Step 5 MHz in 62.5 kHz sub-steps
4 Step to next L' frequency?
N
5 Step 250 kHz in 62.5 kHz sub-steps
7
Y
8
N Y
Video recognition?
System L'?
N
9 Video recognition?
N
Y
10 12 Find frequency
Y
13
Y
AFC crossing?
Video recognition?
N
14
Y
Frequency found?
N (Bad AFC crossing detected)
11 Step 62.5 kHz
N
(No more video identification)
CL 86532047_015.eps 140798
Figure 6-6
MG5.1E
6. SMALL SIGNAL PANEL 6.4 Tuner & IF
41
For search tuning two inputs are used: 1. Is there video recognition (sync detection (phi-1 lock) in the HIP) 2. Is there a carrier (AFC crossing; PLL-lock) The complete tuning procedure is illustrated in fig 6.6, but this is all inside the HIP. There is also automatic switching for the different videosystems.
Personal notes
42
6. SMALL SIGNAL PANEL 6.5 Sound MG5.1E
Sound MG5.1E
MG5.1E
6.5
+5V
+5V
7770 SEDSP *ONLY DOLBY 16 SSL 12 SSR 4800 A SUBWOOFER