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RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Data Sheet January 2002
70A, 60V, 0.014 Ohm, N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA78440.
Features
· 70A, 60V · rDS(on) = 0.014 · Temperature Compensated PSPICE® Model · Peak Current vs Pulse Width Curve · UIS Rating Curve (Single Pulse) · 175oC Operating Temperature · Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFG70N06 RFP70N06 RF1S70N06 RF1S70N06SM PACKAGE TO-247 TO-220AB TO-262AA TO-263AB BRAND RFG70N06 RFP70N06 F1S70N06 F1S70N06
Symbol
D
G
S
NOTE: When ordering use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) GATE SOURCE DRAIN (FLANGE)
JEDEC TO-263AB
JEDEC TO-220AB
SOURCE DRAIN GATE
JEDEC TO-262AA
SOURCE DRAIN GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFG70N06, RFP70N06 RF1S70N06, RF1S70N06SM 60 60 70 Refer to Peak Current Curve ±20 Refer to UIS Curve 150 1.0 -55 to 175 300 260 UNITS V V A V A W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJC RJA TO-220 and TO-263 TO-247 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 48V, ID = 70A, RL = 0.68 Ig(REF) = 2.2mA (Figure 13) TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 11) VGS = VDS, ID = 250µA (Figure 10) VDS = 60V, VGS = 0V VDS = 0.8 x Rated BVDSS, TC = 150oC VGS = ±20V ID = 70A, VGS = 10V (Figure 9) VDD = 30V, ID 70A, RL = 0.43, VGS = 10V, RGS = 2.5 (Figure 13) MIN 60 2 TYP 12 50 40 15 185 100 5.5 3000 900 300 MAX 4 1 25 ±100 0.014 125 125 215 115 6.5 1.0 62 30 UNITS V V µA µA nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time NOTES: 2. Pulse test: pulse width 300ms, duty cycle 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 70A ISD = 70A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 60 50 40 30 20 10 0 25 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175
TC = 25oC, Unless Otherwise Specified
80 70
50
75 100 125 TC, CASE TEMPERATURE (oC)
150
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
1 0.5 THERMAL IMPEDANCE ZJC, NORMALIZED
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 PDM
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 100 101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
1000
100
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100µs
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 T C I = I 25 ---------------------- 150 VGS = 10V
10
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
1ms 10ms
100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
1
100
50 10-5
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Typical Performance Curves
300 IAS, AVALANCHE CURRENT (A)
TC = 25oC, Unless Otherwise Specified (Continued)
200 VGS = 20V ID, DRAIN CURRENT (A) 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 6V VGS = 5V VGS = 4.5V VGS = 10V VGS = 8V VGS = 7V
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS-VDD) +1] STARTING TJ = 25oC
100
120
80
STARTING TJ = 150oC 10 0.01
40
1 0.1 tAV, TIME IN AVALANCHE (ms)
10
0
0
1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V)
5
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
200
160
-55oC
25oC 175oC
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V
2.5
2
PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 70A
120
1.5
80
1
40
0.5
0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
0 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0
VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
2.0 ID = 250µA
NORMALIZED GATE THRESHOLD VOLTAGE
1.5
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
0 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Typical Performance Curves
5000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS VDS, DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC, Unless Otherwise Specified (Continued)
60 10 VGS, GATE TO SOURCE VOLTAGE (V)
4000 C, CAPACITANCE (pF) CISS 3000
VDD = BVDSS 45 RL = 0.86 IG(REF) = 2.2mA VGS = 10V 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS
VDD = BVDSS
7.5
30
5
2000 COSS 1000 CRSS 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25
15
2.5
0 I 20 G(REF) IG(ACT) t, TIME (µs) I 80 G(REF) IG(ACT)
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Test Circuits and Waveforms
VDS RL VDD VDS VGS = 20V VGS
+
(Continued)
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM PSPICE Electrical Model
.SUBCKT RFG70N06 2 1 3 ;
CA 12 8 5.56e-9 CB 15 14 5.30e-9 CIN 6 8 2.63e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.18 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 4.66e-3 RLDRAIN 2 5 10 RGATE 9 20 1.21 RLGATE 1 9 31 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RLSOURCE 3 7 18.2 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 LGATE
rev 3/20/92
RLDRAIN DPLCAP 10 LDRAIN RSCL2 5 51 RSCL1 + 51 ESCL 50 6 8 + RLGATE 9 20 + EVTO 18 8 RDRAIN 16 11 EBREAK 17 18 MOS2 DBODY + DBREAK 5 2 DRAIN
ESG VTO
6
+ 21 MOS1
-
RGATE
RIN
CIN 8 RSOURCE 7
RLSOURCE 3 SOURCE LSOURCE
S1A 12 S1B CA + EGS 6 8 13 8 14 13
S2A 15 17 S2B 13 CB + EDS 14 5 8 IT
RBREAK 18 RVTO 19 VBAT +
-
-
VBAT 8 19 DC 1 VTO 21 6 0.605
.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8) .MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7) .MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6) .MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C
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Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4
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