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AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
Document No.: AX796-17 / V1.7 / Jan. 25 '02

Features
· · · · · · · · · · Highly integrated with embedded 10/100Mbps MAC, PHY and Transceiver Embedded 8K * 16 bit SRAM Compliant with IEEE 802.3/802.3u 100BASE-TX/FX specification NE2000 register level compatible instruction Single chip local CPU bus 10/100Mbps Fast Ethernet MAC Controller Support both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series and MC68K series CPU Support both 10Mbps and 100Mbps data rate Support both full-duplex or half-duplex operation Provides an extra MII port for supporting other media. For example, Home LAN application Support EEPROM interface to store MAC address · · · · · · External and internal loop-back capability Support Standard Print Port for printer server application Support upto 3/1 General Purpose In/Out pins 128-pin LQFP low profile package Low Power Consumption, typical under 100mA 0.25 Micron low power CMOS process. 25MHz Operation, Pure 3.3V operation with 5V I/O tolerance. *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders.

Product description
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface, Home LAN PHY type media can be supported. As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins

System Block Diagram
AD BUS

Optional Print Port Or General I/O Ports Addr L Optional Home LAN PHY AX88796 With 10/100 Mbps PHY/TxRx RJ45

LATCH

RJ11

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

ASIX ELECTRONICS CORPORATION

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558

8051 CPU

Addr H

Ctl BUS

Always contact ASIX for possible updates before starting a design.

First Released Date : July/31/2000
http://www.asix.com.tw

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller CONTENTS

1.0 INTRODUCTION .............................................................................................................................................. 5 1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5 1.2 AX88796 BLOCK DIAGRAM: .............................................................................................................................. 5 1.3A AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6 1.3B AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION ........................................................................ 7 1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode................................................................................ 8 1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9 1.3.3 AX88796 Pin Connection Diagram for MC68K Mode .............................................................................. 10 1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11 2.0 SIGNAL DESCRIPTION ................................................................................................................................. 12 2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ................................................................................................... 12 2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ......................................................................................... 13 2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..................................................................................................... 13 2.4 EEPROM SIGNALS GROUP .............................................................................................................................. 14 2.5 MII INTERFACE SIGNALS GROUP(OPTIONAL) ..................................................................................................... 14 2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL)................................................................ 15

2.7 GENERAL PURPOSE I/O PINS GROUP ........................................................................................... 15
2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 16

2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ..................... 17
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18 3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 18 3.2 I/O MAPPING ................................................................................................................................................... 18 3.3 SRAM MEMORY MAPPING .............................................................................................................................. 18 4.0 BASIC OPERATION ...................................................................................................................................... 19 4.1 RECEIVER FILTERING ....................................................................................................................................... 19 4.1.1 Unicast Address Match Filter................................................................................................................... 19 4.1.2 Multicast Address Match Filter ................................................................................................................ 19 4.1.3 Broadcast Address Match Filter............................................................................................................... 20 4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20 4.2 BUFFER MANAGEMENT OPERATION .................................................................................................................. 22 4.2.1 Packet Reception ..................................................................................................................................... 22 4.2.2 Packet Transmision.................................................................................................................................. 25 4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) .................................................................... 27 4.2.4 Removing Packets from the Ring (Host read data from memory) .............................................................. 28 4.2.5 Other Useful Operations .......................................................................................................................... 31 5.0 REGISTERS OPERATION ............................................................................................................................. 32 5.1 MAC CORE REGISTERS.................................................................................................................................... 32 5.1.1 Command Register (CR) Offset 00H (Read/Write) ................................................................................... 34 5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 34 5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35 5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 35 5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35 5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36 5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36 5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36 5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37 5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 37 5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 37 5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37 2 ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.1.13 Test Register (TR) Offset 15H (Write).................................................................................................... 37 5.1.14 Test Register (TR) Offset 15H (Read) .................................................................................................... 38 5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)...................................................................... 38 5.1.16 GPO and Control (GPOC) Offset 17H (Write)....................................................................................... 38 5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) ............................................................... 39 5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read)........................................................................ 39 5.1.19 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)....................................................... 39 5.2 THE EMBEDDED PHY REGISTERS ..................................................................................................................... 40 5.2.1 MR0 -- Control Register Bit Descriptions................................................................................................. 41 5.2.2 MR1 -- Status Register Bit Descriptions ................................................................................................... 42 5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions.............................................................. 43 5.2.4 MR4 Autonegotiation Advertisement Registers Bit Descriptions............................................................ 43 5.2.5 MR5 Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 43 5.2.6 MR5 Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit Descriptions ............................. 44 5.2.7 MR6 Autonegotiation Expansion Register Bit Descriptions ................................................................... 44 5.2.8 MR7 Next Page Transmit Register Bit Descriptions ............................................................................... 45 5.2.9 MR16 PCS Control Register Bit Descriptions........................................................................................ 45 5.2.10 MR17 Autonegotiation Register A Bit Descriptions .............................................................................. 46 5.2.11 MR18 Autonegotiation Register B Bit Descriptions .............................................................................. 46 5.2.12 MR20 User Defined Register Bit Descriptions...................................................................................... 46 5.2.13 MR21 RXER Counter Register Bit Descriptions ................................................................................... 47 5.2.14 MR28 Device-Specific Register 1 (Status Register) Bit Descriptions..................................................... 47 5.2.15 MR29 Device-Specific Register 2 (100Mbps Control) Bit Descriptions................................................. 48 5.2.16 MR30 Device-Specific Register 3 (10Mbps Control) Bit Descriptions................................................... 49 5.2.17 MR31 Device-Specific Register 4 (Quick Status) Bit Descriptions ........................................................ 50 6.0 CPU I/O READ AND WRITE FUNCTIONS ................................................................................................. 51 6.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 51 6.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 51 6.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 52 6.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .................................................................................................... 52 6.5 CPU ACCESS MII STATION MANAGEMENT FUNCTIONS. .................................................................................... 53 7.0 ELECTRICAL SPECIFICATION AND TIMINGS....................................................................................... 54 7.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 54 7.2 GENERAL OPERATION CONDITIONS................................................................................................................... 54 7.3 DC CHARACTERISTICS ..................................................................................................................................... 54 7.4 A.C. TIMING CHARACTERISTICS ....................................................................................................................... 55 7.4.1 XTAL / CLOCK........................................................................................................................................ 55 7.4.2 Reset Timing ............................................................................................................................................ 55 7.4.3 ISA Bus Access Timing............................................................................................................................. 57 7.4.4 80186 Type I/O Access Timing ................................................................................................................. 58 7.4.5 68K Type I/O Access Timing .................................................................................................................... 59 7.4.6 8051 Bus Access Timing........................................................................................................................... 60 7.4.7 MII Timing............................................................................................................................................... 61 8.0 PACKAGE INFORMATION........................................................................................................................... 62 APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 63

A.1 USING CRYSTAL 25MHZ ................................................................................................................ 63 A.2 USING OSCILLATOR 25MHZ ......................................................................................................... 63
APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 64 ERRATA OF AX88796 .......................................................................................................................................... 65 DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY .............................. 66

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

FIGURES
FIG - 1 AX88796 BLOCK DIAGRAM ............................................................................................................................. 5 FIG - 2 AX88796 PIN CONNECTION DIAGRAM .............................................................................................................. 6 FIG - 3 AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION......................................................................... 7 FIG - 4 AX88796 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ............................................................................... 8 FIG - 5 AX88796 PIN CONNECTION DIAGRAM FOR 80X86 MODE .................................................................................. 9 FIG - 6 AX88796 PIN CONNECTION DIAGRAM FOR MC68K MODE.............................................................................. 10 FIG - 7 AX88796 PIN CONNECTION DIAGRAM FOR MCS-51 MODE ............................................................................. 11 FIG - 8 RECEIVE BUFFER RING.................................................................................................................................... 22 FIG - 9 RECEIVE BUFFER RING AT INITIALIZATION ...................................................................................................... 23

TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP .................................................................................................. 12 TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP ..................................................................................... 13 TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .................................................................................................. 13 TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP ..................................................................................................... 14 TAB - 5 MII INTERFACE SIGNALS GROUP ..................................................................................................................... 14 TAB - 6 STANDARD PRINTER PORT INTERFACE PINS GROUP ......................................................................................... 15 TAB - 7 GENERAL PURPOSES I/O PINS GROUP .............................................................................................................. 15 TAB - 8 MISCELLANEOUS PINS GROUP ......................................................................................................................... 17 TAB - 9 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 17 TAB - 10 I/O ADDRESS MAPPING ............................................................................................................................... 18 TAB - 11 LOCAL MEMORY MAPPING .......................................................................................................................... 18 TAB - 12 PAGE 0 OF MAC CORE REGISTERS MAPPING ................................................................................................ 32 TAB - 13 PAGE 1 OF MAC CORE REGISTERS MAPPING ................................................................................................ 33 TAB - 14 THE EMBEDDED PHY REGISTERS ................................................................................................................. 40 TAB - 15 MII MANAGEMENT FRAME FORMAT ............................................................................................................ 53 TAB - 16 MII MANAGEMENT FRAMES- FIELD DESCRIPTION......................................................................................... 53

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ASIX ELECTRONICS CORPORATION

AX88796 L
1.0 Introduction

3-in-1 Local Bus Fast Ethernet Controller

1.1 General Description:
The AX88796 provides industrial standard NE2000 registers level compatible instruction set. Various drivers are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded systems with no pain and tears The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface, Home LAN PHY type media can be supported. As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins The main difference between AX88796 and AX88195 are : 1) Embedded packet buffer memory 2) Built-in 10/100Mbps PHY/Transceiver 3) Replace memory I/F with PHY/Transceiver I/F. 4) Canceling SAX address decoding. 5) Fix interrupt status can't always clean up problem of AX88195. 6) Add upto 3/1 general Purpose In/Out pins. AX88796 use 128-pin LQFP low profile package, 25MHz operation, and single 3.3V operation with 5V I/O tolerance. The ultra low power consumption is an outstanding feature and enlarges the application field. It is suitable for some power consumption sensitive product like small size embedded products, PDA (Personal Digital Assistant) and Palm size computer ...etc.

1.2 AX88796 Block Diagram:
SMDC SMDIO EECS EECK EEDI EEDO SPP / GPIO 8K* 16 SRAM and Memory Arbiter SEEPROM I/F NE2000 Registers STA TPI, TPO

Remote DMA FIFOs

MAC Core & PHY+ Tranceiver

MII I/F

Print Port or General I/O

Host Interface

Ctl BUS Fig - 1 AX88796 Block Diagram

SA[9:0]

SD[15:0]

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3a AX88796 Pin Connection Diagram
The AX88796 is housed in the 128-pin plastic light quad flat pack. Fig - 2 shows the AX88796 pin connection diagram.
RX_DV COL CRS RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 GPI[0]/LINK VDD VSS GPI[1]/DPX TX_CLK TX_EN TXD[0] TXD[1] TXD[2] TXD[3] GPI[2]/SPD VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC /IOCS16 NC NC VDD VSS /CS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE MAC Controller

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 2 AX88796 Pin Connection Diagram

AEN/PSEN RDY/DTACK RESET /LDS SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] IRQ /IRQ NC R/W /IOWR /IORD NC NC /UDS /BHE SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3b AX88796 Pin Connection Diagram with SPP Port Option
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 SLCT VDD VSS PE /ACK BUSY /STRB /ATFD /INIT /SLIN /ERR VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC /IOCS16 NC NC VDD VSS /CS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE MAC Controller (With SPP Port)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 3 AX88796 Pin Connection Diagram with SPP Port Option

AEN/PSEN RDY/DTACK RESET /LDS SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] IRQ /IRQ NC R/W /IOWR /IORD NC NC /UDS /BHE SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3]

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode
RX_DV COL CRS RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 GPI[0]/LINK VDD VSS GPI[1]/DPX TX_CLK TX_EN TXD[0] TXD[1] TXD[2] TXD[3] GPI[2]/SPD VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC /IOCS16 NC NC VDD VSS /CS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for ISA Bus I/F)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 4 AX88796 Pin Connection Diagram for ISA Bus Mode

AEN RDY RESET SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] IRQ NC /IOWR /IORD NC NC /BHE SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3]

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode
RX_DV COL CRS RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

GPI[0]/LINK VDD VSS GPI[1]/DPX TX_CLK TX_EN TXD[0] TXD[1] TXD[2] TXD[3] GPI[2]/SPD VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC NC NC NC VDD VSS /CS

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for x86 Interface)
NC RDY RESET SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] IRQ NC /IOWR /IORD NC NC /BHE SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 5 AX88796 Pin Connection Diagram for 80x86 Mode

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3.3 AX88796 Pin Connection Diagram for MC68K Mode
RX_DV COL CRS RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 GPI[0]/LINK VDD VSS GPI[1]/DPX TX_CLK TX_EN TXD[0] TXD[1] TXD[2] TXD[3] GPI[2]/SPD VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC NC NC NC VDD VSS /CS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for 68K Interface)
NC /DTACK RESET /LDS SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] /IRQ NC R/W NC NC NC /UDS SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 6 AX88796 Pin Connection Diagram for MC68K Mode

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode
RX_DV COL CRS RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] VSS VSSM ZVREG VDDO VSSO VSSO TPOP TPON VSSO VSSA REXT10 REXT100 VDDA VSSPD XTALOUT LCLK/XTALIN VDDPD VSSM VDDM VSSA REXTBS VDDA VSSA TPIN TPIP VDDA VSSA MDC MDIO TEST1 GPI[0]/LINK VDD VSS GPI[1]/DPX TX_CLK TX_EN TXD[0] TXD[1] TXD[2] TXD[3] GPI[2]/SPD VDD VSS I_OP IO_BASE[0] IO_BASE[1] IO_BASE[2] GPO[0] NC NC NC NC NC VDD VSS /CS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for 8051 Interface)
/PSEN NC RESET SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] VDD VSS SA[9] /IRQ NC /IOWR /IORD NC NC NC SD[15] SD[14] SD[13] SD[12] VDD VSS SD[11] SD[10] SD[9] SD[8] SD[7] VSS SD[6] SD[5] SD[4] SD[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

NC VSS I_ACT I_SPEED I_LINK CPU[1] CPU[0] VDD VDDA VSSA VSS VDD VSS EECS EECK EEDI EEDO TEST2 IDDQ BIST CLKO25M VSS SD[0] SD[1] VDD SD[2]

Fig - 7 AX88796 Pin Connection Diagram for MCS-51 Mode

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ASIX ELECTRONICS CORPORATION

AX88796 L
2.0 Signal Description

3-in-1 Local Bus Fast Ethernet Controller

The following terms describe the AX88796 pin-out: All pin names with the "/" suffix are asserted low. The following abbreviations are used in following Tables. I O I/O OD Input Output Input/Output Open Drain PU PD P Pull Up Pull Down Power Pin

2.1 Local CPU Bus Interface Signals Group
SIGNAL SA[9:1], SA[0]/LDS /BHE or /UDS SD[15:0] TYPE I PIN NO. 15, 12 4 22 DESCRIPTION System Address : Signals SA[9:0] are address bus input lines, which lower I/O spaces on chip. SA[0] also means Lower Data Strobe (/LDS) active low signal in 68K application mode. Bus High Enable or Upper Data Strobe : Bus High Enable is active low signal in some 16-bit application mode, which enable high bus (SD[15:8]) active. The signal also name as Upper Data Strobe (/UDS) for 68K application mode. System Data Bus : Signals SD[15:0] constitute the bi-directional data bus.

I/PU

I/O/PD

IREQ/IREQ

O

23 26, 29 33, 35 39, 41 42 16

RDY/DTACK

OD

2

/CS /IORD /IOWR or R/W /OCS16

I/PU I/PU I/PU

128 19 18

OD

123

AEN or /PSEN

I/PD

1

Interrupt Request : When ISA BUS or 80186 CPU mode is select. IREQ is asserted high to indicate the host system that the chip requires host software service. When MC68K or MCS-51 CPU mode is select. /IREQ is asserted low to indicate the host system that the chip requires host software service. Ready : This signal is set low to insert wait states during Remote DMA transfer. /Dtack : When Motorola CPU type is selected, the pin is active low inform CPU that data is accepted. Chip Select When the /CS signal is asserted, the chip is selected. I/O Read :The host asserts /IORD to read data from AX88796 I/O space. When Motorola CPU type is select , the pin is useless. I/O Write :The host asserts /IOWR to write data into AX88796 I/O space. When Motorola CPU type is select, the pin is active high for read operation at the same time. I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the range corresponds to an I/O address to which the chip responds, and the I/O port addressed is capable of 16-bit access. Address Enable : The signal is asserted when the address bus is available for DMA cycle. When negated (low), AX88796 an I/O slave device may respond to addresses and I/O command. PSEN : This signal is active low for 8051 program access. For I/O device, AX88796, this signal is active high to access the chip. This signal is for 8051 bus application only.

Tab - 1 Local CPU bus interface signals group

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

2.2 10/100Mbps Twisted-Pair Interface pins group
SIGNAL TPI+ TYPE I PIN NO. 70 DESCRIPTION Received Data. Positive differential received 125M baud MLT3 or 10M baud Manchester data from magnetic.

TPI-

I

71

Received Data. Negative differential received 125M baud MLT3 or 10M baud Manchester data from magnetic.

TPO+

O

88

Transmit Data. Positive differential transmit 125M baud MLT3 or 10M baud Manchester data to magnetic.

TPO-

O

87

Transmit Data. Negative differential transmit 125M baud MLT3 or 10M baud Manchester data to magnetic.

REXT10

I

84

REXT100

I

83

REXTBS

I

74

Current Setting 10Mbits/s. An external resistor 20k ohm is placed from this signal to ground to set the 10Mbits/s TP driver transmit output level. Current Setting 100Mbits/s. An external resistor 2.49k ohm is placed from this signal to ground to set the 100Mbits/s TP driver transmit output level. External Bias Resistor. Band Gap Reference for the Receive Channel. Connect this signal to a 24.9k ohm +/- 1 percent resistor to ground. The parasitic load capacitance should be less than 15 pF.

Tab - 2 10/100Mbps Twisted-Pair Interfaces pins group

2.3 Built-in PHY LED indicator pins group
SIGNAL I_ACT or I_FULL/COL TYPE O PIN NO. 62 DESCRIPTION Active Status : When I_OP is logic 1. If there is activity, transmit or receive, on the line occurred, the output will be driven low for 0.67 sec and then driven high at least 0.67 sec. Full-Duplex/Collision Status. When I_OP is logic 0. If this signal is low, it indicates full-duplex link established, and if it is high, then the link is in half-duplex mode. When in half-duplex and collision occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. (Current sink capacity is 6mA) Speed Status : If this signal is low, it indicates 100Mbps, and if it is high, then the speed is 10Mbps. (Current sink capacity is 6mA) Link Status : When I_OP is logic 1. If this signal is low, it indicates link, and if it is high, then the link is fail. Link Status/Active : When I_OP is logic 0. If this signal is low, it indicates link, and if it is high, then the link is fail. When in link status and line activity occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. (Current sink capacity is 6mA)

I_SPEED I_LINK Or I_LK/ACT

O O

61 60

Tab - 3 Built-in PHY LED indicator pins group

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AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 2.4 EEPROM Signals Group
SIGNAL EECS EECK EEDI EEDO TYPE O O/PD O I/PU PIN NO. 51 50 49 48 DESCRIPTION EEPROM Chip Select : EEPROM chip select signal. EEPROM Clock : Signal connected to EEPROM clock pin. EEPROM Data In : Signal connected to EEPROM data input pin. EEPROM Data Out : Signal connected to EEPROM data output pin.

Tab - 4 EEPROM bus interface signals group

2.5 MII interface signals group(Optional)
SIGNAL RXD[3:0] CRS RX_DV TYPE I/PU I/PD I/PD DESCRIPTION Receive Data : RXD[3:0] is driven by the PHY synchronously with respect to RX_CLK. 100 Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. 102 Receive Data Valid : RX_DV is driven by the PHY synchronously with respect to RX_CLK. Asserted high when valid data is present on RXD [3:0]. No Support Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is asserted for one or more RX_CLK periods to indicate to the port that an error has detected. 99 Receive Clock : RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from the PHY to the MII port of the repeater. 101 Collision : this signal is driven by PHY when collision is detected. 108 Transmit Enable : TX_EN is transition synchronously with respect to the rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles on TXD [3:0] for transmission. 112 109 Transmit Data : TXD[3:0] is transition synchronously with respect to the rising edge of TX_CLK. For each TX_CLK period in which TX_EN is asserted, TXD[3:0] are accepted for transmission by the PHY. 107 Transmit Clock : TX_CLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals from the MII port to the PHY. 67 Station Management Data Clock : The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. The signal output reflects MDC register value. About MDC register, please refer to MII/EEPROM Management register bit 0. MDC clock frequency is a 2.5MHz maximum accourding to IEEE 802.3u MII specification. Acturely, many PHYs are designed to accept higher frequency than 2.5MHz. 66 Station Management Data Input/Output :Serial data input/output transfers from/to the PHYs . The transfer protocol has to meet the IEEE 802.3u MII specification. For more information, please refer to section 6.5 CPU Access MII Station Management functions. PIN NO. 98 95

RX_ER

(Omit)

RX_CLK

I/PU

COL TX_EN

I/PD O

TXD[3:0]

O

TX_CLK

I/PU

MDC

O/PU

MDIO

I/O/PU

Tab - 5 MII interface signals group

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3-in-1 Local Bus Fast Ethernet Controller

2.6 Standard Printer Port (SPP) Interface pins group (Optional)
SIGNAL PD[7:5] PD[4:0] BUSY /ACK PE SLCT /ERR /SLCTIN /INIT /ATFD /STRB TYPE I/O/PD I/O/PU I/PU I/PU I/PU I/PU I/PU O O O O PIN NO. 102 100 99 - 95 108 107 106 103 113 112 111 110 109 DESCRIPTION Parallel Data :The bi-directional parallel data bus is used to transfer information between CPU and peripherals. Default serve as input, using /DOE bit of register offset x1Ah to set the direction. Busy : This is a status input from the printer, high indicating that the printer is not ready to receive new data. Acknowledge : A low active input from the printer indicating that it has received the data and is ready to accept new data. Paper Empty : A status input from the printer, high indicating that the printer is out of paper. Slect: This high active input from the printer indicating that it has power on. Error : A low active input from the printer indicating that there is an error condition at the printer. Slect In: This active low output selects the printer. Init: This signal is used to initiate the printer when low. Auto Feed :This output goes low to cause the printer to automatically feed one line after each line is printed. Strobe : A low active pulse on this output is used to strobe the print data into the printer.

Tab - 6 Standard Printer Port Interface pins group

2.7 General Purpose I/O pins group
Signal Name
GPI[2]/SPD GPI[1]/DPX

Type
I/PU I/PU

Pin No.
113 106

Description
Read register offset 17h bit 6 value reflects this input value. When MII port is selected. Read register offset 17h bit 5 value reflects this input value. When SPP port is selected. The pin is defined as PE. When MII port is selected. Read register offset 17h bit 4 value reflects this input value. When SPP port is selected. The pin is defined as SLCT. Default "1". The pin reflects write register offset 17h bit 0 inverted value.

GPI[0]/LINK

I/PU

103

GPO[0]

O

120

Tab - 7 General Purposes I/O pins group

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

2.8 Miscellaneous pins group
SIGNAL LCLK/XTALIN TYPE I DESCRIPTION CMOS Local Clock : A 25Mhz clock, +/- 100 PPM, 40%-60% duty cycle. The signal not supports 5 Volts tolerance. Crystal Oscillator Input : A 25Mhz crystal, +/- 25 PPM can be connected across XTALIN and XTALOUT. 80 Crystal Oscillator Output : A 25Mhz crystal, +/- 25 PPM can be connected across XTALIN and XTALOUT. If a single-ended external clock (LCLK) is connected to XTALIN, the crystal output pin should be left floating. 44 Clock Output : This clock is source from LCLK/XTALIN. 3 Reset : Reset is active high then place AX88796 into reset mode immediately. During the falling edge the AX88796 loads the power on setting data. 59, 58 CPU type selection: CPU[1] CPU[0] CPU TYPE 0 0 ISA BUS 0 1 80186 1 0 MC68K 1 1 MCS-51 (805X) 119, 118, I/O Base Address Selection: 117 IO_BASE[2] IO_BASE[1] IO_BASE[0] IO_BASE 0 0 0 300h 0 0 1 320h 0 1 0 340h 0 1 1 360h 1 0 0 380h 1 0 1 3A0h 1 1 0 200h(default) 1 1 1 220h 116 LED Indicator Option : Selection of LED display mode. I_OP = 0: I_LK/ACT, I_SPEED and I_FULL/COL LED display mode. I_OP = 1: I_LINK, I_SPEED and I_ACT LED display mode. (default) 47, 65 Test Pins : Active high These pins are just for test mode setting purpose only. Must be pull down or keep no connection when normal operation. 46 For test only. Must be pulled down at normal operation. 45 For test only. Must be pulled down or keep no connection when normal operation. 92 This sets the common mode voltage for 10Base-T and 100Base-TX modes. It should be connected to the center tap of the transmit side of the transformer 17, 20, 21, No Connection : for manufacturing test only. 64, 122, 124, 125 13, 27, 40, Power Supply : +3.3V DC. 53, 57, 104, 114, 126 14, 28, 34, Power Supply : +0V DC or Ground Power. 43, 52, 54, 63, 94, 105,115, 127 56, 69, Power Supply for Analog Circuit: +3.3V DC. 16 ASIX ELECTRONICS CORPORATION PIN NO. 79

XTALOUT

O

CLKO25M RESET

O I/PU

CPU[1:0]

I/PU

IO_BASE[2:1] IO_BASE[0]

I/PU I/PD

I_OP

I/PU

TEST[2:1]

I/PD

IDDQ BIST ZVREG

I I/PD O

NC

N/A

VDD

P

VSS

P

VDDA

P

AX88796 L
VSSA VDDM VSSM VDDPD VSSPD VDDO VSSO P P P P P P P

3-in-1 Local Bus Fast Ethernet Controller
73, 82 55, 68, Power Supply for Analog Circuit: +0V DC or Ground Power. 72, 75, 85, 76 Powers the analog block around the transmit/receive area. This should be connected to VDDA: +3.3V DC. 77, 93 Powers the analog block around the transmit/receive area. This should be connected to VSSA: +0V DC or Ground Power. 78 The Phase Detector (or PLL) power. This should be isolated with other power: +3.3V DC. 81 The Phase Detector (or PLL) power. This should be isolated with other power: +0V DC or Ground. 91 Power Supply for Transceiver Output Driver: +3.3V DC. 86, 89, 90 Power Supply for Transceiver Output Driver: +0V DC or Ground.

Tab - 8 Miscellaneous pins group

2.9 Power on configuration setup signals cross reference table
Signal Name
/SPP_SET

Share with
MDC

Description
Standard Printer Port Selection: /SPP_SET = 0 : Standard Printer Port or GPIO is selected /SPP_SET = 1 : MII port is selected (default) PPD_SET = 0 : Internal PHY in normal mode. (default) PPD_SET = 1 : Internal PHY in power down mode.

PPD_SET

EECK

Tab - 9 Power on Configuration Setup Table

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AX88796 L
3.0 Memory and I/O Mapping

3-in-1 Local Bus Fast Ethernet Controller

There are three memories or I/O mapping used in AX88796. 1. 2. 3. EEPROM Memory Mapping I/O Mapping Local Memory Mapping

3.1 EEPROM Memory Mapping
User can define by them and can access via I/O address offset 14H MII/EEPROM registers. The contants of EEPROM will not be loading to any registers automaticlly.

3.2 I/O Mapping
SYSTEM I/O OFFSET 0000H 001FH Tab - 10 I/O Address Mapping FUNCTION MAC CORE REGISTER

3.3 SRAM Memory Mapping
OFFSET 0000H 3FFFH 4000H 7FFF 8000H FFFFH Tab - 11 Local Memory Mapping FUNCTION RESERVED NE2000 COMPATABLE MODE 8K X 16 SRAM BUFFER RESERVED

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AX88796 L
4.0 Basic Operation

3-in-1 Local Bus Fast Ethernet Controller

4.1 Receiver Filtering
The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is rejected by the Protocol Control Logic. Each destination address is also checked for all 1's which is the reserved broadcast address.

4.1.1 Unicast Address Match Filter
The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet. D7 DA7 DA15 DA23 DA31 DA39 DA47 D6 DA6 DA14 DA22 DA30 DA38 DA46 D5 DA5 DA13 DA21 DA29 DA37 DA45 D4 DA4 DA12 DA20 DA28 DA36 DA44 D3 DA3 DA11 DA19 DA27 DA35 DA43 D2 DA2 DA10 DA18 DA26 DA34 DA42 D1 DA1 DA9 DA17 DA25 DA33 DA41 D0 DA0 DA8 DA16 DA24 DA32 DA40

PAR0 PAR1 PAR2 PAR3 PAR4 PAR5

Note: The bit sequence of the received packet is DA0, DA1, ... DA7, DA8 ....

4.1.2 Multicast Address Match Filter
The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones.

MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7

D7 FB7 FB15 FB23 FB31 FB39 FB47 FB55 FB63

D6 FB6 FB14 FB22 FB30 FB38 FB46 FB54 FB62

D5 FB5 FB13 FB21 FB29 FB37 FB45 FB53 FB61

D4 FB4 FB12 FB20 FB28 FB36 FB44 FB52 FB60

D3 FB3 FB11 FB19 FB27 FB35 FB43 FB51 FB59

D2 FB2 FB10 FB18 FB26 FB34 FB42 FB50 FB58

D1 FB1 FB9 FB17 FB25 FB33 FB41 FB49 FB57

D0 FB0 FB8 FB16 FB24 FB32 FB40 FB48 FB56

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

32-bit CRC Generator X=31 to X=26 Clock Latch

1 of 64 bit decoder

Filter bit array

Selected bit 0 = reject, 1= accept

If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1''. This will cause the AX88796 to accept any multicast packet with the address Y. Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64 logical address filteres if these addresses are chosen to map into unique locations in the multicast filter.

Note: The first bit of received packet sequence is 1's stands by Multicast Address.

4.1.3 Broadcast Address Match Filter
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1's, that is the values are "FF FF FF FF FF FF FF" in Hex format. If any bit of the six bytes does not equal to 1's, the Protocol Control Logic rejects the packet.

4.1.4 Aggregate Address Filter with Receive Configuration Setup
The final address filter decision depands on the destination address types, identified by the above 3 address match filters, and the setup of parameters of Receive Configuration Register. Definitions of address match filter result are as following: Signal Value Description Phy =1 Unicast Address Match =0 Unicast Address not Match Mul =1 Multicast Address Match =0 Multicast Address not Match Bro =1 Brocast Address Match =0 Brocast Address not Match AGG =1 Aggregate Address Match =0 Aggregate Address not Match The meaning of AB, AM and PRO signals, please refer to "Receive Configuration Register"

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AX88796 L
Aggregate Address Filter function will be:

3-in-1 Local Bus Fast Ethernet Controller

Bro AND Logic AB

/Bro /Mul PRO OR Logic /Bro Mul AM AND Logic AGG AND Logic

Phy

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

4.2 Buffer Management Operation
There are four buffer memory access types used in AX88796. 1. Packet Reception (Write data to memory from MAC) 2. Packet Transmision (Read data from memory to MAC) 3. Filling Packets to Transmit Buffer (Host fill data to memory) 4. Removing Packets from the Receive Buffer Ring (Host read data from memory) The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write operation and type 4 does Remote DMA read operation.

4.2.1 Packet Reception
The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256 byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum packet size (64 bytes) to maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage of back-to-back packets in loaded networks. The assignment of buffers for storing packets is controlled by Buffer Management Logic in the AX88796. The Buffer Management Logic provides three basic functions: linking receive buffers for long packets, recovery of buffers when a packet is rejected, and recirculation of buffer pages that have been read by the host. At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring. Two eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define the physical boundaries of where the buffers reside. The AX88796 treats the list of buffers as a logical ring; whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.
4000h

... n-2
Page Start

4 3

Page Stop

Buffer #1 Buffer #2 Buffer #3 ... ... ... ... Buffer #n
Physical Memory Map

n-1 n
8000h Logic Receive Buffer Ring

2 1

Fig - 8 Receive Buffer Ring

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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

INITIALIZATION OF THE BUFFER RING Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the DMA for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a CRC, or Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the host. If the local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A simple analogy to remember the function of these registers is that the Current Page Register acts as a Write Pointer and the Boundary Pointer acts as a Read Pointer.

4000h

... n-2
Page Start Boundary Page Current Page

4 3

Page Stop

Buffer #1 Buffer #2 Buffer #3 ... ... ... ... Buffer #n
Physical Memory Map

n-1 n
8000h Logic Receive Buffer Ring

2 1

Fig - 9 Receive Buffer Ring At Initialization
BEGINNING OF RECEPTION When the first packet begins arriving the AX88796 and begins storing the packet at the location pointed to by the Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receive status corresponding to this packet. LINKING RECEIVE BUFFER PAGES If the length of the packet exhausts the first 256 bytes buffer, the DMA performs a forward link to the next buffer to store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the entire packet. Buffers cannot be skipped when linking, a packet will always be stored in contiguous buffers. Before the next buffer can be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for equality between the DMA address of the next buffer and the contents of the Page Stop Register. If the buffer address equals the Page Stop Register, the buffer management logic will restore the DMA to the first buffer in the Receive Buffer Ring value programmed in the Page Start Address Register. The second comparison test for equality between the DMA address of the next buffer address and the contents of the Boundary Pointer Register. If the two values are equal the reception is aborted. The Boundary Pointer Register can be used to protect against overwriting any area in the receive buffer ring that has not yet been read. When linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the
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AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is performed. LINKING BUFFERS Before the DMA can enter the next contiguous 256 bytes buffer, the address is checked for equality to PSTOP and to the Boundary Pointer. If neither are reached, the DMA is allowed to use the next buffer. BUFFER RING OVERFLOW If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the incoming packet will be aborted by the AX88796. Thus, the packets previously received and still contained in the Ring will not be destroyed. In a heavily loaded network environment the local DMA may be disabled, preventing the AX88796 from buffering packets from the network. To guarantee this will not happen, a software reset must be issued during all Receive Buffer Ring over flows (indicated by the OVW bit in the Interrupt Status Register). The following procedure is required to recover from a Receiver Buffer Ring Overflow. If this routine is not adhered to, the AX88796 may act in an unpredictable manner. It should also be noted that it is not permissible to service an overflow interrupt by continuing to empty packets from the receive buffer without implementing the prescribed overflow routine. Note: It is necessary to define a variable in the driver, which will be called ``Resend''. 1. Read and store the value of the TXP bit in the AX88796's Command Register. 2. Issue the STOP command to the AX88796. This is accomplished be setting the STP bit in the AX88796's Command Register. Writing 21H to the Command Register will stop the AX88796. 3. Wait for at least 1.5 ms. Since the AX88796 will complete any transmission or reception that is in progress, it is necessary to time out for the maximum possible duration of an Ethernet transmission or reception. By waiting 1.5 ms this is achieved with some guard band added. Previously, it was recommended that the RST bit of the Interrupt Status Register be polled to insure that the pending transmission or reception is completed. This bit is not a reliable indicator and subsequently should be ignored. 4. Clear the AX88796's Remote Byte Count registers (RBCR0 and RBCR1). 5. Read the stored value of the TXP bit from step 1, above. If this value is a 0, set the ``Resend'' variable to a 0 and jump to step 6. If this value is a 1, read the AX88796's Interrupt Status Register. If either the Packet Transmitted bit (PTX) or Transmit Error bit (TXE) is set to a 1, set the ``Resend'' variable to a 0 and jump to step 6. If neither of these bits is set, place a 1 in the ``Resend'' variable and jump to step 6. This step determines if there was a transmission in progress when the stop command was issued in step 2. If there was a transmission in progress, the AX88796's ISR is read to determine whether or not the packet was recognized by the AX88796. If neither the PTX nor TXE bit was set, then the packet will essentially be lost and retransmitted only after a time-out takes place in the upper level software. By determining that the packet was lost at the driver level, a transmit command can be reissued to the AX88796 once the overflow routine is completed (as in step 11). Also, it is possible for the AX88796 to defer indefinitely, when it is stopped on a busy network. Step 5 also alleviates this problem. Step 5 is essential and should not be omitted from the overflow routine, in order for the AX88796 to operate correctly. 6. Place the AX88796 in mode 1 loopback. This can be accomplished by setting bits D2 and D1, of the Transmit Configuration Register to ``0,1''. 7. Issue the START command to the AX88796. This can be accomplished by writing 22H to the Command Register. This is necessary to activate the AX88796's Remote DMA channel. 8. Remove one or more packets from the receive bufferring. 9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register. 10. Take the AX88796 out of loopback. This is done by writing the Transmit Configuration Register with the value it contains during normal operation. (Bits D2 and D1 should both be programmed to 0.) 11. If the ``Resend'' variable is set to a 1, reset the ``Resend'' variable and reissue the transmit command. This is done by writing a value of 26H to the Command Register. If the ``Resend'' variable is 0, nothing needs to
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AX88796 L
bedone. END OF PACKET OPERATIONS

3-in-1 Local Bus Fast Ethernet Controller

At the end of the packet the AX88796 determines whether the received packet is to be accepted or rejected. It either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store the packet. SUCCESSFUL RECEPTION If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet (pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current Page Register is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had been previously calculated and temporarily stored in an internal scratchpad register.) BUFFER RECOVERY FOR REJECTED PACKETS If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796 is programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC is always stored in buffer memory after the last byte of received data for the packet. Error Recovery If the packet is rejected as shown, the DMA is restored by the AX88796 by reprogramming the DMA starting address pointed to by the Current Page Register.

4.2.2 Packet Transmision
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0,1). When the AX88796 receives a command to transmit the packet pointed to by these registers, buffer memory data will be moved into the FIFO as required during transmission. The AX88796 Controller will generate and append the preamble, synch and CRC fields. TRANSMIT PACKET ASSEMBLY The AX88796 requires a contiguous assembled packet with the format shown. The transmit byte count includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC. When transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The programmer is responsible for adding and stripping pad bytes. The packets are placed in the buffer RAM by the system. System programs the AX88796 Core's Remote DMA to move the data from the data port to the RAM handshaking with system transfers loading the I/O data port. The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting the CPU[1:0] pins for ISA, 80186 or MC68K mode.

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

Destination Address 6 Bytes Source Address 6 Bytes Length / Type 2 Bytes Data 46 Bytes (Pad if < 46 Bytes) Min. General Transmit Packet Format

TRANSMISSION Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set. The Transmit Status Register (TSR) is cleared and the AX88796 begins to prefetch transmit data from memory. If the Interpacket Gap (IPG) has timed out the AX88796 will begin transmission. CONDITIONS REQUIRED TO BEGIN TRANSMISSION In order to transmit a packet, the following three conditions must be met: 1. The Interpacket Gap Timer has timed out 2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started) 3. If a collision had been detected then before transmission the packet backoff time must have timed out.

COLLISION RECOVERY During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be aborted and the ABT bit in the TSR will be set. Transmit Packet Assembly Format The following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes. The various formats are selected in the Data Configuration Register and setting the CPU[1:0] pins for ISA, 80186, MC68K or MCS-51 mode. D15 D8 D7 D0 Destination Address 1 Destination Address 0 Destination Address 3 Destination Address 2 Destination Address 5 Destination Address 4 Source Address 1 Source Address 0 Source Address 3 Source Address 2 Source Address 5 Source Address 4 Type / Length 1 Type / Length 0 Data 1 Data 0 ... ... BOS = 0, WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode.

26

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

D15 D8 D7 D0 Destination Address 0 Destination Address 1 Destination Address 2 Destination Address 3 Destination Address 4 Destination Address 5 Source