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Intel 100 MHz Pentium(tm) II processor/440BX AGPset Uniprocessor Customer Reference Schematics
4
Revision 1.0
** Please note that these schematics are subject to change.
4
TITLE
COVER SHEET BLOCK DIAGRAM SLOT 1 CONNECTOR CLOCK SYNTHESIZER 82443BX
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PAGE
1 2 3,4 5 6,7,8 9,10,11 12,13 14 15 16,17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES W H A T S O EVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. *Third-party brands and names are the property of their respective owners. Copyright * Intel Corporation 1997, 1998
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DIMM SOCKETS PIIX4E ULTRA I/O AGP CONNECTOR PCI CONNECTORS ISA CONNECTORS IDE CONNECTORS USB CONNECTORS FLASH BIOS
2
PARALLEL SERIAL/FLOPPY KEYBOARD/MOUSE VRM POWER CONNECTOR GTL+ TERMINATION PCI/AGP PULLUPS/PULLDOWNS ISA PULLUPS/PULLDOWNS 82443BX DECOUPLING
2
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title Intel 100MHz Pentium(tm) II processor/440BX AGPset Uni-Processor Cover Sheet Size A Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
D
1
BULK DECOUPLING TERMINATION DECOUPLING LM79 REVISION HISTORY
A
1
Rev 1.0 1
E
Sheet
of
34
1
2
3
4
5
6
7
8
VRM VTT GEN.
PG. 25
A
P E N T I U M (tm) II PROCESSOR
(SLOT 1)
PG. 3,4
CK100 & ITP CON.
PG. 5
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER P R O DUCT. iNTEL IS NOT RESPONSIBLE FOR THE MISUSE O F THIS INFORMATION.
A
SMBus Interface
MAX1617 ME
PG. 3
DEVICE TABLE
SYSTEM BUS
ADDR ADDR CNTL
CNTL DATA
DATA
GTL TERM.
PG. 27
DEVICE TYPE
FUSES
REFERENCE DESIGNATOR
F1,F2,F3,F4
PAGE #
20,24
ITP Connector DIMM Sockets
CNTL
J2 J4,J5,J6 J12, J13 J14, J15 J16, J17 J24 J33 A,B J32 J34-37
5 9,10,11 18 19 20 25 3,4 15 16,17
B
MEMORY
3 SDRAM DIMM MODULES PG. 9-11
ISA Connectors IDE Connectors USB Connectors VRM8.2 Slot 1 Connector AGP Connector
ADDR/DATA
AGP C O N N.
ADDR CNTL
82443BX
492 BGA
CKBF
PG. 6
DATA
AGP SIDEBAND PG. 15
B
PG. 6-8
PCI Connectors
BLM31A700S
CNTL
L1-L6,L7-L13
20,24
ADD/DATA
CK100
U1 3VSB U5 A,B,C,D,E,F U6 U7 A,B,C,D,E,F U8 A,B,C,D,E,F U9 U12 A,B,C,D,E,F U13
5 13,26 14 15,26,29 21,25,26 21 25,26,29 25
PCI BUS
PG. 20 2 USB CONN. ADD/DATA
74LVC14
FDC37C932FR 74AS07 CNTL
PG. 16-17 2 PCI IDE CONNECTORS
74HCT14 E28F002BC-T(FLASH)
USB
USB
PCI CONN
PCI CONN
PCI CONN
PCI CONN
PG. 19 CNTL
74F07 74LVC3244
SECONDARY IDE
PRIMARY IDE
CNTL
82371EB
324 BGA PG. 12-13 ADDR/DATA
74ALS08 74HC10 82443BX CKBF 5VSB
U16 A,B,C,D U17 A,B,C U19-1,2,3 U20 U21 5VSB U28 A,B,C,D,E,F U23 A,B U24 U27 A,B
26,29 13,26,29 6,7,8 6 33 13,26,29 12,13 3 13
C
ADDR/DATA
C
CONTROL
ADDR
CNTL
DATA
LM79 74F07
ISA BUS
82371EB (PIIX4E) MAX1617 ME 74HC112
ADDR
P G 18 LT1585
ADDR
ADDR
CNTL
DATA
VR1 VR2
25 25
LT1575
ISA CONN
ISA CONN
FLASH BIOS PG. 21
LM79
PG. 33
DATA
X-BUS
KEYBOARD PG. 24
Crystal (14.318MHz) Crystal(32.768KHz)
Y1 Y2
5 13
ULTRA I/O
PG.14
CNTL
DATA MOUSE
D D
PG. 24 FLOPPY CONN. PG. 23 PARA. CONN. PG. 20 SER. CONN. PG .23 SER. CONN. INTEL CORPORATION
RESET, POWER CONNECTORS ISA, PCI RESISTORS DECOUPLING CAPACITORS
PG. 26
PG. 28-29
P L A T F O R M COMPONENTS DIVISION 1 9 0 0 P R A I R I E CITY RD. FM5-62 FOLSOM, CA 95630 Title
PG. 30-32 Size
I N T E L 1 0 0 M H z P e n t i u m ( t m ) I I p r ocessor/440BX AGPset Block Diagram Document Number Intel(R) 440BX AGPset T hursday, April 09, 1998
7
Custom Date:
1 2 3 4 5 6
Rev 1.0 Sheet 2
8
of
34
A
B
C
D
E
VCC2.5 * Note: This strong pullup resistor on S L P # i s n e c e s s a r y when using an LAI.
VTT VCC2.5
VCC3 VCC3
R1 330
VCCCORE J 3 3A B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73
EMI FLUSH# SMI# INIT# VCC_VTT STPCLK# TCK SLP# VCC_VTT TMS TRST# RESERVED VCC_CORE RESERVED RESERVED LINT[1] VCC_CORE PICCLK BP#[2] RESERVED 100/66# PICD[1] PRDY# BPM#[1] VCC_CORE DEP#[2] DEP#[4] DEP#[7] VCC_CORE D#[62] D#[58] D#[63] VCC_CORE D#[56] D#[50] D#[54] VCC_CORE D#[59] D#[48] D#[52] EMI D#[41] D#[47] D#[44] VCC_CORE D#[36] D#[40] D#[34] VCC_CORE D#[38] D#[32] D#[28] VCC_CORE D#[29] D#[26] D#[25] VCC_CORE D#[22] D#[19] D#[18] EMI D#[20] D#[17] D#[15] VCC_CORE D#[12] D#[7] D#[6] VCC_CORE D#[4] D#[2] D#[0] VCC_CORE VCC_VTT GND VCC_VTT IERR# A20M# GND FERR# IGNNE# TDI GND TDO PWRGOOD TESTHI1 GND THERMTRIP# RESERVED LINT[0] GND PICD[0] PREQ# BP#[3] GND BPM#[0] BINIT# DEP#[0] GND DEP#[1] DEP#[3] DEP#[5] GND DEP#[6] D#[61] D#[55] GND D#[60] D#[53] D#[57] GND D#[46] D#[49] D#[51] GND D#[42] D#[45] D#[39] GND RESERVED D#[43] D#[37] GND D#[33] D#[35] D#[31] GND D#[30] D#[27] D#[24] GND D#[23] D#[21] D#[16] GND D#[13] D#[11] D#[10] GND D#[14] D#[9] D#[8] GND D#[5] D#[3] D#[1]
VTT R3 4.7K
4
4
28 F L U S H# 13,28 PX4_SMI# 13,28 HINIT# C164 13,28 STPCLK# 5 TCK 13 SLP# 5 TMS 5 TRST# C188 2 2 00pF
R239 4 . 7K U24 15 S M B SLAVE A D D R ESS = 0011000b
0.1 uF 2
S T BY# D+ DADD1 ADD0 3 4 25,28 LINT1 5 P I C C LK 5,11 100/66# 28 P I C D1 5 , 27 P R D Y#0
6 10
MAX1617 ME
16p QSOP
6 , 9 , 1 0,11,13,28,33 S M BDATA 6 , 9 , 1 0,11,13,28,33 SMBCLK
12 14
SMBDATA SMBCLK SMB_ALERT# 11
3
1 5 9 13 16
GND
GND
R E SV R E SV R E SV R E SV R E SV
THERM# 13,28 H D # 62 H D #58 H D #63 H D # 56 H D # 50 H D # 54 H D # 59 H D # 48 H D # 52 H D # 41 H D # 47 H D # 44 H D # 36 H D # 40 H D # 34 H D # 38 H D # 32 H D # 28 H D # 29 H D # 26 H D # 25 H D # 22 H D # 19 H D # 18 H D # 20 H D # 17 H D # 15 H D # 12 HD#7 HD#6 HD#4 HD#2 HD#0
MAX1617_2
2
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73
A20M# 25,28 F E R R# 13,28 I G N N E # 2 5 ,28 TDI 5 TDO 5 P W RGOOD 2 1 ,26 T H E R MTRIP# 28 LINT0 25,28 P I C D 0 28 ITPREQ# 5
V+
3
H D # 61 H D # 55 H D # 60 H D # 53 H D # 57 H D # 46 H D # 49 H D # 51 H D # 42 H D # 45 H D # 39 H D # 43 H D # 37 H D # 33 H D # 35 H D # 31 H D # 30 H D # 27 H D # 24 H D # 23 H D # 21 H D # 16 H D # 13 H D # 11 H D # 10 H D # 14 HD#9 HD#8 HD#5 HD#3 HD#1
7
8
2
SLOT1_0.8 8 , 27 H D # [ 6 3 : 0]
SLOT 1a
1
I N T E L C O R P O RATION R4 0 R5 0 R6 0 P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title S L O T 1 (PART I) Size Document Number Custom Intel(R) 440BX AGPset D a t e : Thursday, April 09, 1998
A B C D
1
* P lease place as close to the connector as possible
Rev 1.0 3
E
Sheet
of
34
A
B
C
D
E
V C C C O RE VCC
4
VCC3 J33B
4
5 , 6,27 H R E SET#
H A # 29 H A # 26 H A # 24 H A # 28 HA#20 H A # 21 H A # 25 HA#15 HA#17 HA#11 H A # 12 HA#8 HA#7
3
HA#3 HA#6 H R E Q#0 H R E Q#1 H R E Q#4 6,27 H L O CK# 6,27 D R D Y # 6,27 RS#0 6,27 HIT# 6,27 RS#2
VID3 VID0
R219 R221
0 0
B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121
RESET# BREQ1# FRCERR# VCC_CORE A#[35] A#[32] A#[29] EMI A#[26] A#[24] A#[28] VCC_CORE A#[20] A#[21] A#[25] VCC_CORE A#[15] A#[17] A#[11] VCC_CORE A#[12] A#[8] A#[7] VCC_CORE A#[3] A#[6] EMI SLOTOCC# REQ#[0] REQ#[1] REQ#[4] VCC_CORE LOCK# DRDY# RS#[0] VCC_5 HIT# RS#[2] RESERVED VCC_3 RP# RSP# AP#[1] VCC_3 AERR# VID[3] VID[0] VCC_3
GND BCLK BREQ0# BERR# GND A#[33] A#[34] A#[30] GND A#[31] A#[27] A#[22] GND A#[23] RESERVED A#[19] GND A#[18] A#[16] A#[13] GND A#[14] A#[10] A#[5] GND A#[9] A#[4] BNR# GND BPRI# TRDY# DEFER# GND REQ#[2] REQ#[3] HITM# GND DBSY# RS#[1] RESERVED GND ADS# RESERVED AP#[0] GND VID[2] VID[1] VID[4]
A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121
CPUHCLK 5 BREQ0# 6,27
H A # 30 H A # 31 H A # 27 H A # 22 H A # 23 H A # 19 H A # 18 H A # 16 H A # 13 H A # 14 H A # 10 HA#5
3
HA#9 HA#4 B N R # 6,27 B P RI# 6,27 H T R D Y # 6 , 27 D E F ER# 6,27 H R E Q#2 H R E Q#3 HITM# 6,27 D B S Y# 6 , 27 RS#1 6 , 27 A D S# 6 , 27
R220 R222 R223
0 0 0
VID2 VID1 VID4
SLOT1_0.8
2
SLOT 1b
2
6 , 27 H A # [ 3 1 : 3] 6,27 H R E Q # [ 4 :0] 25,33 V I D[ 4 : 0] VCC JP1 VID0 2 3 1 S E L _VID0 R7 8 . 2K
* Please place as close to the connector as possible
R8 0
R9 0 VID1 2
JP2
1 3
S E L _VID1
R10 8 . 2K
VRM optional override jumpers & resistors
Jumper position 1-2 is s t u f f e d a s the default. To override, R219-223 must be removed.
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title S L O T 1 ( PART II) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E 1
JP3 VID2 2
1 3
S E L _VID2
R11 8 . 2K
1
JP4 VID3 2
1 3
S E L _VID3
R12 8 . 2K
JP5 VID4 2
1 3
S E L _VID4
R13 8 . 2K
Rev 1.0 4 of 34
A
B
C
D
A
B
C
D
E
CLOCK SYNTHESIZER
VCC3 1 L15
4
L14 2 2 FBHS01L 1
VCC2.5
VCC3 R176 200
FBHS01L CD85 CD86 CD87 0.01uF 16V CD88 100pF 16V CD89 100pF 16V CD90 1 0 0 pF 16V C168 + 22uF
4
CD91 100pF 16V
CD92 100pF 16V
CD93 0.01uF 16V
CD94 0.01uF 16V
CD95 0.01uF 16V
0.01 uF 0.01 uF 16V 16V
C169 + 22uF
9 15 19 21 33 48 V D D P C I0 VDDPCI1 VDDCORE0 V D D 4 8 M HZ V D D C O RE1 VDDQREF
U1
V D D A P IC VDDCPU0 VDDCPU1
46 41 37
VCC3 C1 10pF R18 8.2K R19 8.2K R20 8.2K C2 10pF 4
CPUCLK0 CPUCLK1 CPUCLK2 CPUCLK3 PCICLK_F PCICLK_1 PCICLK_2 PCICLK_3 PCICLK_4 PCICLK_5 PCICLK_6 PCICLK_7 48MHZ_0 48MHZ_1 APICCLK_0 APICCLK_1
40 39 36 35 7 8 10 11 13 14 16 17 22 23 45 44 1 2 47
R27 R14 R15 R16 R17 R22 R23 R24 R25
22 22 22 22 22 22 22 22 22
I T P C LK B X H C LK 6 CPUHCLK 4 P X P C L K 13 PCLK1 16 PCLK2 16 PCLK3 17 PCLK4 17 B X PCLK 7
* Note * This is a stuffing option: 10-15 p F c a p s to ground may be desirable to reduce the effects of EMI.
* Note * For power managed systems, the PIIX4 must be connected to PCICLK_F of the CK100 which is a free running PCLK not affected by the assertion of PCISTOP#.
XTLI1 Y1 14.318MHz XTLO1
X T A LIN
5 42 28 27 26 25
XTALOUT RESV RESV S E L0 S E L1 S E L _ 1 0 0/66# P C I _ S TP# C P U _ S T P# PWRDWN#
CK100
R26 R177 R178 R179 R180
22 22 22 22 22
4 8 M h z_0 13
3
3
3,11 100/66# 1 3 P C I _ S TP# 13 CPU_STP# 13 SUSA# R264 0 R265 0 R266 0 R242 10K R249 R250 10K 10K
PICCLK 3 OSC1 18 OSC2 13 OSC3 14
31 30 29
VCC3
DO NOT STUFF
Stuffing option to enable the stopping of the CPUCLKs, PCICLKs, and the powerdown of the CK100. Please note that the resistors are not stuffed.
C K 1 0 0 _05
3 6 12 18 20 24 32 38 34 43
V S S REF V S S PCI0 VSSPCI1 VSSPCI2 V S S CORE0 VSS48MHZ VSSCORE1 V S S C PU0 VSSCPU1 VSSAPIC
REF0 REF1 REF2
VCC2.5 R224 0 VCC2.5 VTT
R28
2
R29 1K
R36 1K 5%
Stuffing option to enable Spread# function for possible EMI reduction.
4,6,27 H R E S E T # 2 6 D B R E S ET# 3 TCK R237 47 R238 3 TMS 47 R34 240
1K
OPTIONAL ITP TEST CONNECTOR J2
ITP_RST ITP_PON 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
R33 R30 330 330 150 R32
2
TDI 3 TDO 3 T R ST# 3 PRDY0_R# R35 240 R37 680 I T P R E Q# 3 PRDY#0 3,27
I T P C LK
ITP CONN
1
1
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title CLOCK SYNTHESIZER Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 5 of 34
A
B
C
D
E
VCC3 V21 Y21 F7 F9 F18 F20 G6 G21 J6 J21 AA7 AA9 AA18 AA20
4,27 H A # [ 3 1 : 3] U 1 9-1 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 H A # 10 H A # 11 H A # 12 H A # 13 H A # 14 H A # 15 H A # 16 H A # 17 H A # 18 H A # 19 H A # 20 H A # 21 H A # 22 H A # 23 H A # 24 H A # 25 H A # 26 H A # 27 H A # 28 H A # 29 H A # 30 H A # 31 4 , 5 ,27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4 , 27 4,27 H R E SET# ADS# BNR# B P R I# DBSY# D E F ER# DRDY# HIT# HITM# H L O CK# HTRDY# BREQ0# RS#0 RS#1 RS#2 4,27 R S # [ 2 :0] H R E Q#0 H R E Q#1 H R E Q#2 H R E Q#3 H R E Q#4 G25 H22 G23 H23 G24 F26 G26 G22 F22 F23 F24 F25 E23 E26 E25 D25 D26 B25 C26 A25 C25 A24 D24 C23 B24 C24 A23 E22 D23 B23 K21 H24 H26 L23 J26 K23 L24 L22 K22 H25 B26 K26 L26 L25 J22 J23 K24 K25 J25 HA3# HA4# HA5# HA6# HA7# HA8# HA9# H A 1 0# H A 1 1# H A 1 2# H A 1 3# H A 1 4# H A 1 5# H A 1 6# H A 1 7# H A 1 8# H A 1 9# H A 2 0# H A 2 1# H A 2 2# H A 2 3# H A 2 4# H A 2 5# H A 2 6# H A 2 7# H A 2 8# H A 2 9# H A 3 0# H A 3 1# C P U R ST# A D S# BNR# B P R I# D B S Y# D E F ER# DRDY# HIT# HITM# H L O CK# HTRDY# BREQ0# RS#0 RS#1 RS#2 H R E Q#0 H R E Q#1 H R E Q#2 H R E Q#3 H R E Q#4
M A A [ 1 3:0] 9 , 10 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAB0# MAB1# MAB2# MAB3# MAB4# MAB5# MAB6# MAB7# MAB8# MAB9# MAB10 MAB11# MAB12# MAB13 CSA0# CSA1# CSA2# CSA3# CSA4# CSA5# CKE2/CSA6# CKE3/CSA7# CSB0# CSB1# CSB2# CSB3# CSB4# CSB5# CKE4/CSB6# CKE5/CSB7# DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 DQMB1 DQMB5 CKE0/FENA CKE1/GCKE SRAS_A# SRAS_B# SCAS_A# SCAS_B# AF17 AB16 AE17 AC17 AF18 AE19 AF19 AC18 AC19 AE20 AD20 AF21 AC21 AF25 AD16 AC16 AD17 AB17 AE18 AD19 AB18 AB19 AF20 AC20 AB20 AE21 AD21 AF22 AB14 AF15 AE15 AC15 AD15 AE16 AE24 AD23 AE25 AD24 AD26 AC24 AC26 AB23 AC23 AF24 AD13 AC13 AC25 AB26 AE14 AC14 AA22 AA24 AE13 AD14 AC22 AF23 AF16 AA17 AF12 AB13 AE12 AC12 AB21 AD25 AB22 R281 22 D C L K REF DQMB1 DQMB5 C K E0 C K E1 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB#11 MAB#12 MAB13 CS_A#0 CS_A#1 CS_A#2 CS_A#3 CS_A#4 CS_A#5 CKE2 CKE3 CS_B#0 CS_B#1 CS_B#2 CS_B#3 CS_B#4 CS_B#5 CKE4 CKE5 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 DQMB1 11 DQMB5 11 CKE0 9 CKE1 9 R280 S R A S_A# S R AS_B# S C A S_A# S C AS_B# 9 , 10 11 9 , 10 11 47 38 11 25 24 1 2 47 48
4
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
4
M A B #[13:0] 11
82443BX
492 BGA
L16 2 F B H S01L 100pF C S _ A # [1:0] 9 C S _ A # [3:2] 10 C S _ A # [5:4] 11 C K E [ 3 :2] 10 . 0 1 uF C S _ B #[1:0] 9 C S _ B #[3:2] 10 . 0 1 uF C S _ B #[5:4] 11 C K E [ 5 :4] 11 . 0 1 uF D Q M A [ 7:0] 9 , 10,11 C183 2 2 uF + C184 C181 100pF C182 . 0 1 uF . 0 1 uF C175 100pF C177 100pF C179 100pF C180 C178 C176 C174 1
VCC3
3
DRAM INTERFACE
U20
23 3 7 12 16 20 29 33 37 42 46
4,27 H R E Q # [ 4 :0] 5 BXHCLK
2
VDDIIC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
SYSTEM INTERFACE
3
VCC3 R38 4.7k
D C L K [ 11:0] 9 , 10,11
N23 C R ESET# M25 M26 A3 VCC3
HCLKIN T E S TIN# CRESET# P C I RST#
25 C R ESET# 1 2 ,15,16,17 P C I RST#
OE
CKBF
BUF_IN S C LOCK S D A TA RESV RESV RESV RESV
R39 8.2K
AE22 AE23 P22
R E S VA R E SVB R E S VC
WE_A# WE_B# DCLKO DCLKWR DCLKRD
W E _ A # 9,10 W E _ B# 11
VSSIIC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17
4 5 8 9 13 14 17 18 31 32 35 36 40 41 44 45 21 28
R181 R182 R183 R184 R185 R186
0 0 0 0 0 0
D C LK9 D C LK8 D C LK5 D C LK4 D C LK0 D C LK1
**Please Note ** These clock assignments may not be optimum.
2
R187 R188 R189 R190 R191 R193 R194
0 0 0 0 0 0 0
D C LK11 D C LK10 D C LK7 D C LK6 D C LK3 D C LK2 D C L K REF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
** TESTIN# pullup may be removed after validation has been completed.
443BX_10
C162 2 0 pF
C K BF
A1 A14 A26 C5 C9 C18 C22 E3 E12 E15 E24 F6 F8 F19 F21 H6 H21 J3 J24
1
* * L o cate R280 close to CKBF and R281 close to 443BX. **Locate "T" and cap close to BX. ** Please make DCLKREF trace length equal to 2.5" more than the DCLK outputs to the DIMMs. DCLK outputs to the DIMMs should all be the same recommended length. E x a m ple: if DCLK[0-11] = 2.5" then DCLKREF = 2.5" + 2.5".
A B C D
26 6 10 15 19 22 27 30 34 39 43
slave address = 1101001b
*The unused SDRAM clocks may be disabled using the SMBus interface.
SMBCLK 3 , 9 , 1 0,11,13,28,33 S M BDATA 3 , 9 , 1 0,11,13,28,33 I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title 8 2 4 4 3 B X S Y S T E M AND DRAM INTERFACES Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E 1
Rev 1.0 6 of 34
A
B
C
D
E
VCC3
L11 L13 L14 L16 M12 M15 N11 N16 P11 P16 R12 R15 T11 T13 T14 T16 N26
1 2 ,16,17 A D [ 3 1 : 0]
4
U 1 9-2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / BE#0 C / BE#1 C / BE#2 C / BE#3 K6 K2 K4 K3 K5 J1 J2 H2 H1 J5 H3 H5 H4 G1 G2 G4 D1 D3 D2 C1 A2 C3 B3 D4 E5 A4 D5 B4 B5 A5 E6 C6 J4 G3 E4 C4 E2 F3 E1 F5 F4 G5 F1 F2 B6 D6 AE3 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 P G NT#0 P G NT#1 P G NT#2 P G NT#3 P G NT#4 A6 C7 F10 D8 D10 AD4 E7 D7 E10 E8 E9 AF3 AC4 C2 B2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / BE0# C / BE1# C / BE2# C / BE3# F R AME# DEVSEL# IRDY# TRDY# STOP# PAR S E RR# PLOCK# P H O LD# P H L D A# WSC# P R E Q0#/IOREQ# PREQ1# PREQ2# PREQ3# PREQ4# S U STAT# P G N T 0 #/IOGNT# P G NT1# P G NT2# P G NT3# P G NT4# BX-PWROK CLKRUN# R E F V C C5 P C L K IN
P1 AE1 V6 Y6
G A D [ 3 1:0] 15 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GC/BE0# GC/BE1# GC/BE2# GC/BE3# GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# GCLKOUT GCLKIN PIPE# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 RBF# ST0 ST1 ST2 GADSTB-A GADSTB-B SB-STB AGPREFV AB5 AE2 AD3 AD2 AD1 AC3 AC1 AB4 AB1 AA5 AA3 AA4 AA2 AA1 Y5 Y3 W1 V2 W2 U5 V1 U4 U3 U1 T3 T4 T2 T1 U6 R3 R4 R2 AB2 Y4 V4 U2 W3 W5 V5 W4 Y1 Y2 L5 L3 P5 N5 M3 K1 M2 M1 N2 P2 P4 P3 R1 M4 L4 L2 L1 AC2 T5 N3 N4 R175 100 1% ST0 ST1 ST2 S T [ 2 :0] 15 A D S TB-A 15,28 A D STB-B 15,28 SBSTB 15,28 R240 R241 22 S B A0 S B A1 S B A2 S B A3 S B A4 S B A5 S B A6 S B A7 PIPE# 15,28 22 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 G A D10 G A D11 G A D12 G A D13 G A D14 G A D15 G A D16 G A D17 G A D18 G A D19 G A D20 G A D21 G A D22 G A D23 G A D24 G A D25 G A D26 G A D27 G A D28 G A D29 G A D30 G A D31 GCBE#0 GCBE#1 GCBE#2 GCBE#3 GFRAME# 15,28 GDEVSEL# 15,28 G I R D Y # 15,28 G T R D Y# 1 5 ,28 GSTOP# 15,28 G P AR 15,28 GREQ# 15,28 G G NT# 1 5 ,28 G C LKOUT 15
4
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
82443BX
492 BGA
3
VDD VDD VDD VDD
P C I INTERFACE
3
12,16,17 C / B E # [ 3:0]
G C / B E # [3:0] 15
VCC3
1 2 , 16,17,28 1 2 , 16,17,28 1 2 , 16,17,28 1 2 , 16,17,28 1 2 , 16,17,28 1 2 ,16,17 1 2 , 16,17,28 1 6 ,17,28
F R AME# DEVSEL# IRDY# TRDY# STOP# PAR S E RR# PLOCK#
R196 10K
12,28 P H L D# 12,28 P H L D A# 16,17,28 P R E Q # [3:0]
AGP INTERFACE
2
13 S U STAT#
R282 0
28 PREQ#4 1 6 ,17,28 P G N T # [ 3:0]
** Note** Please make the GCLKIN trace length 3.3" more than the GCLKOUT recommended trace length. Stub to tee should be 1" MAX.
PCI ARB & PWR MGT
2
DO NOT STUFF
S t u f fing option to enable and test 28 P G NT#4 13,26 P W R O K the POS state.
13 V R E F 5V 5 BXPCLK
S B A [ 7 :0] 15 R B F# 15,28 VCC3
R174 150 1%
R255 100
443BX_10
1
N1 M5 L12 L15 M11 M13 M14 M16 M22 N12 N13 N14 N15 P12 P13 P14 P15 P26 T12 T15 R5 R11 R13 R14 R16 R22 V3 V24 W6 W21
** Place as close to 443BX as possible.
C157 0 . 0 01uF
** It is recommended that the tolerance on these resistors be 1 % i n order to meet t h e m argins of this reference voltage.
1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title 8 2 4 4 3 B X P C I A N D AGP INTERFACES Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998
A B C D
Rev 1.0 7 of 34
Sheet
E
A
B
C
D
E
VCC3 B1 N22 AF14 AF2 AE26 HD#[63:0] 3,27
9,10,11 MD[63:0] MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 9,10,11 MECC[7:0] AF4 AE4 AF5 AD6 AE6 AB7 AC7 AF7 AB8 AB9 AC9 AE9 AB10 AC10 AF10 AD11 Y24 Y25 W23 W24 W26 W25 V26 U24 U23 T22 T23 T26 R24 R25 P23 N25 AC5 AE5 AB6 AC6 AF6 AD7 AE7 AC8 AD8 AF8 AE8 AF9 AD10 AE10 AB11 AC11 Y23 Y26 W22 V22 V23 V25 U22 U25 U26 T24 T25 U21 R23 R26 P24 P25 AE11 AA10 AA23 AA26 AF11 AD12 AA25 Y22
U19-3 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 443BX_10
4
82443BX
492 BGA
3
2
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
B22 D22 E21 A22 D21 C21 A21 C20 B21 E20 A20 E19 B20 E18 D20 D19 D18 C19 B19 A18 A19 B18 C17 E17 D17 B17 C16 A17 C15 B16 D16 A16 B15 A15 D14 D15 B13 C14 E14 D13 A13 D12 B12 B14 C13 E13 D11 A12 B11 A11 B7 C12 C8 B10 A10 A9 A7 E11 D9 C11 C10 B8 A8 B9
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
VDD VDD VDD VDD VDD
4
VTT
R170 75 1%
3
GTLREF1 R171 150 1%
HOST DATA BUS
M E M O R Y D A T A BUS
C155 0.001uF
VTT
R172 75 1% GTLREF2 R173 150 1%
2
C156 0.001uF
GTLREF2 GTLREF1 M23 E16 M24 F17 INTEL CORPORATION VTT PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title 82443BX MD/HD BUS Size Custom Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
D 1
1
GTLREFA GTLREFB VTTA VTTB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB25 N24 AA6 AA8 AA19 AA21 AB3 AB12 AB15 AB24 AD5 AD9 AD18 AD22 AF1 AF13 AF26
Rev 1.0 8
E
Sheet
of
34
A
B
C
A
B
C
D
E
DIMM SOCKET 0
VCC3 VCC3 8,10,11 MD[63:0]
6 18 26 40 41 90 102 110 124
4
49 59 73 84 133 143 157 168
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13 6,10,11 DQMA[7:0] DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 VCC3
4
VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC
3
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
3
R252 0 ohm
6,10 MAA[13:0]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
CKE[1:0] CKE0 CKE1 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 MECC[7:0]
6
8,10,11
Slave address = 1010000b
SMBDATA 3,6,10,11,13,28,33 SMBCLK 3,6,10,11,13,28,33 CS_A#[1:0] CS_A#0 CS_A#1 CS_B#0 CS_B#1 CS_B#[1:0] 6 6
2
2
MAA11 MAA12
DIMM 0
DIMM 1
DIMM 2
WE_A# 6,10 SCAS_A# 6,10 SRAS_A# 6,10 DCLK8 DCLK9 DCLK10 DCLK11 DCLK[11:0] 6,10,11
MAB MAA
STRAPS
82443BX
J4 DIMM REF
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CONTROL B CONTROL A
1
INTEL CORPORATION PLATFORM COMP ONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 0 Size Custom Date:
A B C D
Block diagram for 3 DIMM MA and control connection.
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 9 of 34
A
B
C
D
E
DIMM SOCKET 1
VCC3 VCC3
8,9,11 MD[63:0]
4 4
6 18 26 40 41 90 102 110 124
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13 6,9,11 DQMA[7:0] DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 MAA11 MAA12
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
49 59 73 84 133 143 157 168
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 VCC3
VCC VCC VCC VCC VCC VCC VCC VCC VCC
3
VCC VCC VCC VCC VCC VCC VCC VCC
3
6,9 MAA[13:0]
R253 0 ohm
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
CKE[3:2] CKE2 CKE3 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 R_SA0 R42 4.7K MECC[7:0]
6 8,9,11
VCC3
2
Slave address = 1010001b
2
SMBDATA 3,6,9,11,13,28,33 SMBCLK 3,6,9,11,13,28,33 CS_A#[3:2] CS_A#2 CS_A#3 CS_B#2 CS_B#3 CS_B#[3:2] 6 6
WE_A# 6,9 SCAS_A# 6,9 SRAS_A# 6,9 DCLK4 DCLK5 DCLK6 DCLK7 DCLK[11:0] 6,9,11
J5 DIMM REF
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMP ONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 1 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 10 of 34
A
B
C
D
E
DIMM SOCKET 2
VCC3 VCC3 8,9,10 MD[63:0]
4 4
6 18 26 40 41 90 102 110 124
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB13
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
49 59 73 84 133 143 157 168
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC
3
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
VCC3
3
3,5 100/66#
R200 10K JP19 IOQ DEPTH SEL
MAB#12 6 MAB#[13:0] MAB#11
R254 0 ohm
R199 10K 6,9,10 DQMA[7:0] DQMA0 6 DQMB1
2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
CKE[5:4] 6 CKE4 CKE5 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 MECC[7:0] 8,9,10
DQMA2 DQMA3 DQMA4 DQMA6 DQMA7 MAB#11 MAB#12
VCC3
Slave address = 1010010b
R_SA1 R43 4.7K S M B D A T A 3,6,9,10,13,28,33 S M B C L K 3,6,9,10,13,28,33 CS_A#[5:4] 6 CS_A#4 CS_A#5 CS_B#4 CS_B#5 CS_B#[5:4] 6
2
6 DQMB5
MAB#11: 1 = IOQ depth of 4 (default), 0 = IOQ depth of 1
WE_B# 6 SCAS_B# 6 SRAS_B# 6 DCLK0 DCLK1 DCLK2 DCLK3 DCLK[11:0] 6,9,10
J6 DIMM REF
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 2 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 S heet
E
Rev 1.0 11 of 34
A
B
C
D
E
U23A AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 7 , 16,17 A D [ 3 1 : 0] C / BE#0 C / BE#1 C / BE#2 C / BE#3 B10 A10 D9 C9 B9 A9 D8 E8 B8 A8 D7 C7 B7 A7 D6 E6 E4 C4 B4 A4 D3 E3 C3 B3 E2 C2 B2 A2 D1 E1 C1 B1 C8 C6 D4 D2 C10 E5 A5 A3 B5 B6 A1 B12 A12 A6 D5 C5 E10 A11 B11 C11 S D A0 S D A1 S D A2 C17 B17 A18 G19 A17 F18 A16 F17 F16 G20 C16 B16 D16 G16 G18 G17 F20 E18 E20 D18 D20 C20 B20 A20 A19 B19 C19 D19 D17 E19 E17 F19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / B E#0 C / B E#1 C / B E#2 C / B E#3 C L O C K R U N# D E VSEL# F R AME# I D S EL IRDY# PAR P C I R ST# P H O LD# P H O L DA# S E R R# STOP# TRDY# REQ0# REQ1# REQ2# REQ3# S D A0 S D A1 S D A2 P D D A CK# S D D A CK# P D R EQ S D R EQ P D I O R# P D IOW# PIORDY S D I O R# S D IOW# SIORDY P D A0 P D A1 P D A2 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 P D D10 P D D11 P D D12 P D D13 P D D14 P D D15 PIIX4_15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SCS3# PCS3# SCS1# PCS1# SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 LA17 LA18 LA19 LA20 LA21 LA22 LA23 MEMCS16# MEMR# MEMW# SMEMR# SMEMW# SYSCLK BALE IOCHK# REFRESH# IOCS16# ZEROWS# SBHE# RSTDRV IOR# IOW# IOCHRDY AEN E15 B15 D14 C14 A14 C13 A13 C12 D12 B13 D13 B14 E14 A15 C15 D15 C18 H16 B18 H17 U11 T11 W11 Y11 T10 W10 U9 V9 Y9 T8 W8 U7 V7 Y7 V6 Y6 T5 W5 U4 V4 V3 W3 U2 T2 W2 Y2 T1 V1 W16 T16 Y17 V17 Y18 W18 Y19 W19 Y15 T14 W14 U13 V13 Y13 T12 Y12 V15 U15 W4 U3 T7 U10 Y1 W7 V12 Y3 W12 W1 Y5 T4 T3 Y4 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 S A [ 1 9 :0] 1 4 , 18,21,29,33 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 S D [ 1 5 :0] 1 4 ,18,29 LA17 LA18 LA19 LA20 LA21 LA22 LA23 L A [ 2 3:17] 18,29 MEMCS16# 18,29 MEMR# 18,21,29 MEMW# 18,21,29 SMEMR# 18 SMEMW# 18 S Y S CLK 18,33 BALE 18 I O C H K# 18,29 R E F R ESH# 18,29 I O CS16# 18,29 Z E R O W S # 18,29 SBHE# 18 R S T D RV 14,26 I O R# 1 4 , 18,29,33 IOW# 1 4 , 18,29,33 I O C H R D Y 1 4 ,18,29 A E N 14,18 I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S O M, CA 95630 Title 8 2 3 7 1 EB (PART I) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998
A B C D 1
4
IDE SIGNALS
S D D0 S D D1 S D D2 S D D3 S D D4 S D D5 S D D6 S D D7 S D D8 S D D9 S D D10 S D D11 S D D12 S D D13 S D D14 S D D15 S D D [ 1 5 :0] 19 SCS3# 19 PCS3# 19 SCS1# 19 PCS1# 19
4
PCI BUS INTERFACE
82371EB
3
7 , 16,17 C / B E # [ 3:0] 7 , 16,17,28 D E VSEL# 7 , 1 6,17,28 F R AME# R256 100 7 , 1 6,17,28 I R D Y # 7 , 16,17 P A R 6 , 1 5,16,17 P C I R ST# 7 , 28 P H L D# R45 7,28 P H L D A# 7 , 1 6,17,28 S E RR# 100 7 , 1 6,17,28 STOP# 7 , 1 6,17,28 T R D Y # 7 , 1 6,17,28 P R E Q #[3:0]
3
R _ AD18
A D 18
19 S D A [ 2 : 0]
2
19 19 19 19 19 19 19 19 19 19
P D D A CK# S D D A CK# P D R EQ S D R EQ P D I O R# PDIOW# PIORDY S D I O R# S D IOW# SIORDY
ISA/EIO SIGNALS
2
IDE SIGNALS
P D A0 P D A1 P D A2 P D D0 P D D1 P D D2 P D D3 P D D4 P D D5 P D D6 P D D7 P D D8 P D D9 P D D10 P D D11 P D D12 P D D13 P D D14 P D D15
19 P D A [ 2 : 0]
1
19 P D D [ 1 5:0]
Rev 1.0 12
E
Sheet
of
34
A
B
C
D
E
VCC3
VCC3
3VSB VCC3
F6 E11 F15 R6 R15
U23B 14,18 D A C K # [ 3 : 0 ] DACK#0 DACK#1 DACK#2 DACK#3 DACK#5 DACK#6 DACK#7 U14 W6 Y10 V5 T15 V16 W17 W15 U6 V2 U5 Y16 U16 U17 M1 N2 P3 N1 P2 P4 V10 J17 H18 K18 H20 J20 T9 W9 U8 V8 Y8 Y20 U1 U12 W13 T13 V14 Y14 J19 R3 R4 P5 G1 M19 K19 L17 L18 L19 P1 L20 P20 N20 M20 M18 K17 V18 DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7# DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7 REQA#/GPI2 REQB#/GPI3 REQC#/GPI4 GNTA#/GPO9 GNTB#/GPO10 GNTC#/GPO11 TC APICACK#/GPO12 APICCS#/GPO13 APICREQ#/GPI5 IRQ0/GPO14 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8/GPI6 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 SERIRQ/GPI7 PIRQA# PIRQB# PIRQC# PIRQD# CPURST FERR# IGNNE# INIT INTR A20GATE NMI SMI# RCIN# A20M# PWROK SPKR TEST#
E9 E12 E16 F5 F14 G6 R7 P15 T6
R16 N16 K5
4
18 DACK#[7:5]
USBP1+ USBP1USBP0+ USBP0OC0 OC1
F1 H2 G2 H3 J1 J2 V20 W20 V19 U18 R1 R2 K16 H19 U19 M17 U20 P16 T20 R19 N17 P18
USBP1+ 20 USBP1- 20 USBP0+ 20 USBP0- 20 OC#0 20 OC#1 20 EXTSMI# 28,33 SUSA# 5 SUSC# CPU_STP# 5 PCI_STP# 5 C3 0.01 uF
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCC VCC VCC VCC VCC
VCCSUS VCCSUS VCCUSB
5VSB
USB
4
3VSB
5VSB 14 U28A 2 1 7 2
R290 10K
JP21 CONFIG.
1-2 2-3 SAVE STATE ON POWER DOWN. PIIX4 POWERS ON SYS. AT POWER-UP.
DMA SIGNALS
POWER MANAGEMENT
14,18,29 14,18,29 14,18,29 14,18,29 18,29 18,29 18,29
DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7
EXTSMI# SUSA# GPO15/SUSB# GPO16/SUSC# GPO17/CPU_STP# GPO18/PCI_STP# GPO19/ZZ GPI8/THERM# GPI9/BATLOW# RSMRST# PWRBT# GPI10/LID SMBDATA SMBCLK GPI11/SMBALERT# GPI12/RI#A
14 1 7
U5A
74LVC14
74F07 JP21 3 2 1 JMP_3P B_SUSC 26
28 REQ#A 28 REQ#B 28 REQ#C
14,18 T C
82371EB
T H E R M # 3,28 BATLOW# 28 RSMRST# 26 PWRBT# 26 LID 26,28 S M B D A T A 3,6,9,10,11,28,33 S M B C L K 3,6,9,10,11,28,33 SMBALERT# 28 A G P _ P M E # 15,28
VCC3
**External logic shown is used to handle power loss condition.
28 APICREQ#
3
14,29 14,18,29 14,18,29 14,18,29 14,18,29 14,18,29 29 14,18,29 14,18,29 14,18,29 14,18,29 14,18,19,29 14,18,19,29 28 15,16,17,28 15,16,17,28 16,17,28 16,17,28 GPI7 PIRQ#A PIRQ#B PIRQ#C PIRQ#D
IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ#8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 PIRQ#A PIRQ#B PIRQ#C PIRQ#D
SUSCLK GPO20/SUS_STAT1# GPO21/SUS_STAT2# STPCLK# SLP#
P17 T17 T18 J18 K20
SUSTAT# 7 S T P C L K # 3,28 SLP# 3
D1 SCHOTTKY BAR43
VCC
R46 1K
3
G P O /GPI/GPIO/SCAN
SUSC# GPI[20:13] GPI21 2 3 28
3,28 25,28 3,28 25,28 14,28 25,28 3,28 3VSB 14,28 25,28 7,26 26 28 D2 SCHOTTKY BAR43
FERR# PX4_IGNNE# HINIT# PX4_INTR A20GATE PX4_NMI PX4_SMI# KBRST# P X 4 _ A 2 0 M# PWROK SPKR TEST#
74HC10 SPS2
2
GPO0 GPO8 GPO27 GPO28 GPO29 GPO30 MCCS#
N4 L4 N5 J4 N18 N3 M5 M16 R5 R17 R18 PGCS#0 PGCS#1 26 PS_POK 1 TP5 P G C S # 1 28,33 R268 1K 5VSB 16 3 1 2 8 3VSB PX4_CFG1 28 14 13 7 74LVC14 R47 8.2K C165 0.1uF R245 8.2K RTC_BAT 1 RSMRST# U5F 12 GPO8# U27A Q 5 10 VCC J CLK CL K GND Q 6 16 11 13 12 8 U27B Q 9 4 VCC J CLK K GND CL Q 7
14 XOE# 1 4 XDIR# 21 BIOSCS# RTC_BAT
VB2
R48 1K
1 3 C6 0.1 uF
JP6
2 RTCX2 RTCX1 R244 0
M4 M3 M2 L1 K2 K1 L16 R20 N19 L3 V11 D11
XOE#/GPO23 XDIR#/GPO22 BIOSCS# RTCALE/GPO25 RTCCS#/GPO24 KBCCS#/GPO26 VBAT RTCX2 RTCX1 48Mhz OSC PCICLK
PGCS0# PGCS1# N/C N/C N/C N/C N/C N/C CONFIG1 CONFIG2 VSS_USB
PR
1
G4 T19 G5 F2 F3 F4
3
3
14 U17B 3 4 5 7
R243 10K
1
R269 1.5K
PR
15
74HC112
14
IRQ SIGNALS CPU INTERFACE X-BUS
VREF
J16
VREF5V 7
+
GPI1 GPI13 GPI14 GPI15 GPI16 GPI17 GPI18 GPI19 GPI20 GPI21 P19 L2 J3 L5 K3 K4 H1 H4 H5 G3 GPI13 GPI14 GPI15 GPI16 GPI17 GPI18 GPI19 GPI20 GPI21 P C I _ P M E # 16,17,28
C4 1.0 uF
C5 0.1 uF 5VSB 5VSB SP3
5VSB
Q8 2N7002 2
WOLLID
26
6
GPO8 GPO27 GPO28
FAN_LED 26 1 1 TP3 TP4
RTC_BAT R291 8.2K R267 10K
Q6 2N7002 2
POWER-ON
26
2
10K R292
74HC112 3
D3 SCHOTTKY BAR43 CMOS_CLR R49 1K 1 VB1 2
5 48Mhz_0 5 OSC2 5 PXPCLK
JK_CLR 2
Q5 2N7002
Y2 1 32.768KHz C7 18pF C8 18pF PIIX4_15
D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
CLEAR CMOS
BT1
J5
1
JP6 CONFIG 1 -2 2-3 NORMAL CLEAR CMOS
2
INTEL CORPORATION P L A TFORM COMPONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title 82371EB (PART II) Size Custom Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
E
Rev 1.0 Sheet 13 of 34
A
B
C
D
1
2
3
4
5
6
7
8
VCC U6 121 122 124 22 68 69 70 80 90 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 72 73 74 75 76 77 78 79 89 D R Q0 D R Q1 D R Q2 D R Q3 D A C K#0 D A C K#1 D A C K#2 D A C K#3 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 I R Q 10 I R Q 11 I R Q 12 I R Q 14 I R Q 15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 1 1 1 1 1 1 1 1 S I O _PU2 TP080 TP081 TP082 TP083 TP084 TP079 TP078 TP085 82 84 86 88 81 83 85 87 67 66 65 64 63 62 61 59 58 57 56 55 54 41 42 43 44 45 46 47 48 49 50 51 52 53 27 28 29 26 23 24 25 30 31 34 33 32 92 91 94 93 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 21,33 X D [ 7:0] 13 XOE# 13 X D IR#
D
21 60 101 125 139
A
5 OSC3 1 2 ,18,29,33 I O R # 1 2 ,18,29,33 IOW# 12,18 A E N 12,26 R S T D RV 12,18,29 I O C H R D Y 12,18,29 S D [ 1 5 :0]
V B AT XTAL1 XTAL2 1 4 C LOCKI IOR# IOW# AEN R S T D RV IOCHRDY SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 TC D R Q0 D R Q1 D R Q2 D R Q3 D A C K0 D A C K1 D A C K2 D A C K3 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 I R Q8# IRQ9 I R Q10 I R Q11 I R Q12 I R Q14 I R Q15
14CLK01 14CLK02 14CLK03 16CLK 24CLK INDEX# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# SIDE1# DSKCHG# MTR0# MTR1# DRVSEL0# DRVSEL1# DRVDEN0 DRVDEN1 MEDID0 MEDID1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLIN# INIT# AFD# STB# BUSY ACK# PE SLCT ERR# RXD1 TXD1 RTS1# CTS1# DTR1# DSR1# DCD1# RI1# RXD2 TXD2 RTS2# CTS2# DTR2# DSR2# DCD2# RI2# GP10/IRQIN GP11/IRQIN GP12/IRRX GP13/IRTX GP14/RS GP15/WS GP16/JOYRS GP17/JSWS GP20/IDE2_OE GP21/EEDIN GP22/EDOUT GP23/EECLK GP24/EEEN GP25/8042_P21
37 38 39 36 35 14 9 10 11 12 15 16 17 13 18 4 7 6 5 2 3 20 19 138 137 136 135 134 133 132 131 140 141 143 144 128 129 127 126 142 145 146 148 149 150 147 152 151 155 156 158 159 160 157 154 153 96 97 98 99 100 102 103 104 105 106 107 108 109 110
VCC VCC VCC VCC VCC
TP076 TP077 TP088
1 1 1
TP7 TP8 TP9 INDEX# 23 D I R # 23 STEP# 23 W D ATA# 23 WGATE# 23 TRK0# 23 W P T# 23 R D A TA# 23 S I DE1# 23 D S K C HG# 23 MOTEA# 23 MOTEB# 23 D R V S A# 23 D R V SB# 23 R E D W C # 23 D R ATE0 23
A
Stuff for 93X only R284 1K R285 1K
13,18 TC 1 3 ,18,29 D R Q [ 7 : 0]
TP090 I R R 4_MODE P D R0 P D R1 P D R2 P D R3 P D R4 P D R5 P D R6 P D R7
1
TP10
Stuff for 93XFR R286 0
13,18 D A C K # [ 3 :0]
P D R [ 7 : 0] 22
VCC
1 3 ,18,29 I R Q [ 7 : 0]
R258 10k
B
FDC37C932FR 160 PIN QFP
13,18,29 13,18,29 13,18,29 13,18,29 1 3 , 18,19,29 1 3 , 18,19,29 1 2 , 18,21,29,33 S A [ 1 9:0]
IRQ9 I R Q 10 I R Q 11 I R Q 12 I R Q 14 I R Q 15
S L I N #R 22 INIT#R 22 A F D # R 22 STB#R 22 B U S Y 22 A C K# 22 PE 22 SLCT 22 E R R# 22 RX0 23 TX0 23
C O N F I G P O R T A D D RESS
VCC 3 7 0 I / O decode R287 10K
B
VCC
R53 8.2K
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 S A 1 2/CS S A 1 3 / HDCS2# S A 1 4 / HDCS3# S A 1 5 / IDE2_IRQ I D E 1 _IRQ IDE1_OE# H D C S 0# H D C S 1# I O ROP# IOWOP# I D E _A0 I D E _A1 I D E _A2 KCLK K D AT MSCLK MSDAT RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 ROMCS# R O M DIR# F D C 3 7 C932FR_1.3
RTS0# 23 CTS0# 23 DTR0# 23 DSR0# 23 RLSD0# 23 R I 0# 23 RX1 23 TX1 23 RTS1# 23 CTS1# 23 DTR1# 23 DSR1# 23 RLSD1# 23 R I 1# 23 TP092 TP091 I R RX IRTX TP073 TP072 TP087 TP075 R_GP21 TP071 TP070 TP069 1 1 1 1 1 1 1 1 1 TP14 TP16 TP19 TP21 TP23 TP24 KBRST# 13,28 TP25 TP26 TP27 A20GATE 13,28 R52 1K 3 F 0 I / O d e c o de(DEFAULT) VCC C9 4 7 0pF JP7
C
VCC RP1 1 2 3 4 4 . 7K 24 24 24 24 KBCLK# K B DAT# MSCLK# MSDAT# 8 7 6 5 Stuff for 93XFR
VCC
TP11 TP12 TP13 TP15 TP17 TP18 TP20 TP22
KEY
6 5 4 3 2 1 INFRARED HDR
C
R288 0
C10 470pF C12 0 . 1 uF
C11 470pF C13 0.1 uF
111 112 113 114 115 116 117 118 119 120
VCC R54 8.2K VSS VSS VSS VSS VSS VSS VSS
1 8 40 71 95 123 130
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title I / O C O N T R O L L E R ( U LTRA I/O) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet 14
8
D
Stuff for 93XFR
R289 0
ULTRA I/O
Rev 1.0 of 34
1
2
3
4
5
6
7
A
B
C
D
E
AGP CONNECTOR
VCC3 VCC3
7 SBA[7:0] 7 ST[2:0]
4
VCC3 20 AGP_OC# R56 4.7K
J32 VCC
+12V
VCC3
4
B1 B2 B3
OVRCNT# 5V 5V USB+ GND INTB# CLK REQ# VCC3.3 ST0 ST2 RBF# GND SPARE SBA0 VCC3.3 SBA2 SB_STB GND SBA4 SBA6
12V SPARE RESERVED USBGND INTA# RST# GNT# VCC3.3 ST1 RESERVED PIPE# GND SPARE SBA1 VCC3.3 SBA3 RESERVED GND SBA5 SBA7
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 SBA3 SBA1 ST1
R55 4.7K
20 USBAGP+ U7C 6 74AS07
B4 B5
USBAGP- 20 PIRQ3#A 3 U7B 4 74AS07 PIRQ#A 13,16,17,28
13,16,17,28 PIRQ#B
5
PIRQ3#B 7 GCLKOUT
B6 B7 B8 B9 ST0 ST2 B10 B11 B12 B13 B14 SBA0 B15 B16 SBA2 B17 B18 B19
PCIRST# 6,12,16,17 GGNT# 7,28
7,28 GREQ#
7,28 RBF#
PIPE# 7,28
7,28 SBSTB
3
SBA4 SBA6
B20 B21
3
SBA5 SBA7
GAD31 GAD29
B26 B27 B28
AD31 AD29 VCC3.3 AD27 AD25 GND AD_STB1 AD23 Vddq3.3 AD21 AD19 GND AD17 C/BE2# Vddq3.3 IRDY# SPARE GND SPARE VCC3.3 DEVSEL# Vddq3.3 PERR# GND SERR# C/BE1# Vddq3.3 AD14 AD12 GND AD10 AD8 Vddq3.3 AD_STB0 AD7 GND AD5 AD3 Vddq3.3 AD1 RESERVED
AD30 AD28 VCC3.3 AD26 AD24 GND RESERVED GC/BE3# Vddq3.3 AD22 AD20 GND AD18 AD16 Vddq3.3 FRAME# SPARE GND SPARE VCC3.3 TRDY# STOP# PME# GND PAR AD15 Vddq3.3 AD13 AD11 GND AD9 C/BE0# Vddq3.3 RESERVED AD6 GND AD4 AD2 Vddq3.3 AD0 RESERVED
A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
GAD30 GAD28
GAD27 GAD25
B29 B30 B31
GAD26 GAD24
7,28 ADSTB-B GAD23
B32 B33 B34 GAD21 GAD19 B35 B36 B37 GAD17 GC/BE#2 B38 B39 B40
GC/BE#3
GAD22 GAD20
GAD18 GAD16
2
7,28 GIRDY#
B41 B42 B43 B44 B45
GFRAME# 7,28
2
7,28 GDEVSEL#
B46 B47
GTRDY# 7,28 GSTOP# 7,28 AGP_PME# 13,28
28 GPERR#
B48 B49
28 GSERR# GC/BE#1
B50 B51 B52 GAD14 GAD12 B53 B54 B55 GAD10 GAD8 B56 B57 B58
GPAR 7,28 GAD15
GAD13 GAD11
GAD9 GC/BE#0
7,28 ADSTB-A GAD7
B59 B60 B61 GAD5 B62 B63 B64 GAD1 B65 B66
GAD6
GAD4 GAD2
1
1
GAD3
GAD0
INTEL CORPORATION AGP_CONN_1.3 PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title 7 GAD[31:0] GC/BE#[3:0] ACCELERATED GRAPHICS PORT (AGP) CONNECTOR Size Document Number Custom Intel(R) 440BX AGPset Date:
A B C D
Rev 1.0 15 of 34
Thursday, April 09, 1998
E
Sheet
1
2
3
4
5
6
7
8
VCC3 VCC3 -12V VCC VCC +12V
PCI CONNECTORS 1 AND 2
-12V PTRST# 17 PTMS 17 PTDI 1 7 PIRQ#A PIRQ#C 13,15,17,28 13,17,28 R59 5.6K PIRQ#C PIRQ#A PRSNT#21 PRSNT#22
VCC VCC3 VCC3 VCC VCC +12V R57 5.6K
VCC
R58 5.6K
A
J34 17 PTCK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSV PRSNT2# GND GND RSV GND CLK GND REQ# +5V AD(31) AD(29) GND AD(27) AD(25) +3.3V C/BE#3) AD(23) GND AD(21) AD(19) +3.3V AD(17) C/BE#(2) GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#(1) AD(14) GND AD(12) AD(10) GND TRST# +12V TMS TDI +5V INTA# INTC# +5V RSV +5V RSV GND GND RSV RESET# +5V GNT# GND PME# AD(30) +3.3V AD(28) AD(26) GND AD(24) IDSEL +3.3V AD(22) AD(20) GND AD(18) AD(16) +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD(15) +3.3V AD(13) AD(11) GND AD(09) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 PTCK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
J35 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSV PRSNT2# GND GND RSV GND CLK GND REQ# +5V AD(31) AD(29) GND AD(27) AD(25) +3.3V C/BE#3) AD(23) GND AD(21) AD(19) +3.3V AD(17) C/BE#(2) GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#(1) AD(14) GND AD(12) AD(10) GND TRST# +12V TMS TDI +5V INTA# INTC# +5V RSV +5V RSV GND GND RSV RESET# +5V GNT# GND PME# AD(30) +3.3V AD(28) AD(26) GND AD(24) IDSEL +3.3V AD(22) AD(20) GND AD(18) AD(16) +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD(15) +3.3V AD(13) AD(11) GND AD(09) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 PTRST# PTMS PTDI PIRQ#B PIRQ#D
A
13,15,17,28 13,17,28
PIRQ#B PIRQ#D
PRSNT#11 PRSNT#12
R60 5.6K
PCIRST#
6,12,15,17 5 PCLK2
PCIRST# P G N T # 1 7,28 PCI_PME# AD30 AD28 AD26 AD24 R_AD27 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONEP2 SBOP2 PAR AD15 AD13 AD11 AD9
B
5 PCLK1 7,28 P R E Q # 0 AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 7,12,17,28 7,12,17,28 IRDY#
P G N T # 0 7,28 PCI_PME# AD30 AD28 AD26 AD24 R_AD26 AD22 AD20 AD18 AD16 F R A M E # 7,12,17,28 TRDY# 7,12,17,28 7,28 P R E Q # 1 AD31 AD29 AD27 A_D25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 IRDY# DEVSEL# PLOCK# PERR# SERR# AD15 AD13 AD11 AD9 P A R 7,12,17 C/BE#1 AD14 AD12 AD10
PCI_PME#
13,17,28
B
DEVSEL#
S T O P # 7,12,17,28 SDONEP1 SBOP1
7,17,28 P L O C K # 17,28 P E R R # 7,12,17,28 SERR# C/BE#1 AD14 AD12 AD10
AD8 AD7 AD5 AD3 AD1 PU1_REQ64#
C
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
KEY
AD(8) AD(7) +3.3V AD(5) AD(3) GND AD(1) +5V ACK64# +5V +5V PCI_CONN C/BE#(0) +3.3V AD(06) AD(04) GND AD(02) AD(00) +5V REQ64# +5V +5V
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C/BE#0 AD6 AD4 AD2 AD0 PU1_ACK64#
AD8 AD7 AD5 AD3 AD1 PU2_REQ64#
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
KEY
AD(8) AD(7) +3.3V AD(5) AD(3) GND AD(1) +5V ACK64# +5V +5V PCI_CONN C/BE#(0) +3.3V AD(06) AD(04) GND AD(02) AD(00) +5V REQ64# +5V +5V
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C/BE#0 AD6 AD4 AD2 AD0 PU2_ACK64#
C
7,12,17
C/BE#[3:0]
7,12,17 AD[31:0]
C14 PRSNT#11 VCC VCC RP2 SDONEP1 SDONEP2 SBOP1 SBOP2 1 2 3 4 5.6K
D
0.1 uF C15 PRSNT#12 PU1_ACK64# 0.1 uF PU1_REQ64# C16 PRSNT#21 PU2_ACK64# 0.1 uF R66 C17 PRSNT#22 2.7K 0.1 uF INTEL CORPORATION P L A T F O R M COMPONENTS DIVISION 1 9 0 0 P R A I R I E CITY RD. FM5-62 FOLSOM, CA 95630 Title P C I CONNECTORS 1 & 2 Size Custom Date: Document Number Intel(R) 440BX AGPset T hursday, April 09, 1998
7
R61 AD26 R63 2.7K
R62 R_AD26 100 R64
8 7 6 5
2.7K
R65
AD27 100
R_AD27
2.7K
D
PU2_REQ64#
Rev 1.0 Sheet 16
8
of
34
1
2
3
4
5
6
1
2
3
4
5
6
7
8
VCC3 VCC3 -12V VCC +12V VCC
A
PCI CONNECTORS 3 AND 4
PTRST# 16 PTMS 16 PTDI 1 6 PIRQ#C PIRQ#A 13,16,28 13,15,16,28
VCC3 VCC3 -12V VCC +12V VCC J37
A
J36 16 PTCK PTCK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSV PRSNT2# GND GND RSV GND CLK GND REQ# +5V AD(31) AD(29) GND AD(27) AD(25) +3.3V C/BE#3) AD(23) GND AD(21) AD(19) +3.3V AD(17) C/BE#(2) GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#(1) AD(14) GND AD(12) AD(10) GND TRST# +12V TMS TDI +5V INTA# INTC# +5V RSV +5V RSV GND GND RSV RESET# +5V GNT# GND PME# AD(30) +3.3V AD(28) AD(26) GND AD(24) IDSEL +3.3V AD(22) AD(20) GND AD(18) AD(16) +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD(15) +3.3V AD(13) AD(11) GND AD(09) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 PTCK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
13,16,28 13,15,16,28
PIRQ#D PIRQ#B
PRSNT#31 PRSNT#32
PIRQ#A PIRQ#C PRSNT#41 PRSNT#42
PCIRST#
6,12,15,16 5 PCLK4
5 PCLK3 7,28 P R E Q # 2 AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 7,12,16,28 7,12,16,28 IRDY#
P G N T # 2 7,28 PCI_PME# AD30 AD28 AD26 AD24 R_AD29 AD22 AD20 AD18 AD16 FRAME# TRDY# 7,12,16,28 7,12,16,28 7,28 P R E Q # 3 AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 IRDY# DEVSEL# PLOCK# PERR# SERR# AD15 AD13 AD11 AD9 P A R 7,12,16 C/BE#1 AD14 AD12 AD10
B
DEVSEL#
S T O P # 7,12,16,28 SDONEP3 SBOP3
7,16,28 P L O C K # 16,28 P E R R # 7,12,16,28 SERR# C/BE#1 AD14 AD12 AD10
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSV PRSNT2# GND GND RSV GND CLK GND REQ# +5V AD(31) AD(29) GND AD(27) AD(25) +3.3V C/BE#3) AD(23) GND AD(21) AD(19) +3.3V AD(17) C/BE#(2) GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#(1) AD(14) GND AD(12) AD(10) GND
TRST# +12V TMS TDI +5V INTA# INTC# +5V RSV +5V RSV GND GND RSV RESET# +5V GNT# GND PME# AD(30) +3.3V AD(28) AD(26) GND AD(24) IDSEL +3.3V AD(22) AD(20) GND AD(18) AD(16) +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD(15) +3.3V AD(13) AD(11) GND AD(09)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
PTRST# PTMS PTDI PIRQ#D PIRQ#B
PCIRST# P G N T # 3 7,28 PCI_PME# AD30 AD28 AD26 AD24 R_AD31 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONEP4 SBOP4 PAR AD15 AD13 AD11 AD9
B
P C I _ P M E # 13,16,28
AD8 AD7 AD5 AD3 AD1 PU3_REQ64#
C
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
KEY
AD(8) AD(7) +3.3V AD(5) AD(3) GND AD(1) +5V ACK64# +5V +5V PCI_CONN C/BE#(0) +3.3V AD(06) AD(04) GND AD(02) AD(00) +5V REQ64# +5V +5V
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C/BE#0 AD6 AD4 AD2 AD0 PU3_ACK64#
AD8 AD7 AD5 AD3 AD1 PU4_REQ64#
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
KEY
AD(8) AD(7) +3.3V AD(5) AD(3) GND AD(1) +5V ACK64# +5V +5V PCI_CONN C/BE#(0) +3.3V AD(06) AD(04) GND AD(02) AD(00) +5V REQ64# +5V +5V
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C/BE#0 AD6 AD4 AD2 AD0 PU4_ACK64#
C
7,12,16
C/BE#[3:0]
7,12,16
AD[31:0]
C18 PRSNT#31 VCC 0.1 uF VCC C19 RP3 SDONEP3 SDONEP4 SBOP3 SBOP4 1 2 3 4 5.6K
D
R67 PU3_ACK64# AD29 R69 PU3_REQ64# 2.7K 100 2.7K PU4_ACK64# R70 AD31 R72 2.7K 100
D
PRSNT#32 8 7 6 5 0.1 uF C20 PRSNT#41 0.1 uF C21 PRSNT#42 0.1 uF
R68 R_AD29
R71 R_AD31
PU4_REQ64# 2.7K INTEL CORPORATION P L A T F O R M COMPONENTS DIVISION 1 9 0 0 P R A I R I E CITY RD. FM5-62 FOLSOM, CA 95630 Title P C I CONNECTORS 3 & 4 Size Custom Date: Document Number Intel(R) 440BX AGPset T hursday, April 09, 1998
7
Rev 1.0 Sheet 17
8
of
34
1
2
3
4
5
6
1
2
3
4
5
6
7
8
ISA SLOTS
VCC
A
R73 1K VCC R74 1K VCC
A
VCC J12 26 B R S T D R V 13,14,29 IRQ9 13,14,29 D R Q 2 12,29 Z E R O W S # 12 S M E M W# 12 S M E M R# 12,14,29,33 IOW# 12,14,29,33 IOR# 13,14 DACK#3 13,14,29 D R Q 3 13,14 DACK#1 13,14,29 D R Q 1 12,29 R E F R E S H # 12,33 S Y S C L K 13,14,29 IRQ7 13,14,29 IRQ6 13,14,29 IRQ5 13,14,29 IRQ4 13,14,29 IRQ3 13,14 DACK#2 13,14 T C 12 BALE 5 OSC1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 GND BRSTDRV VCC IRQ9 -5V DREQ2 -12V ZEROWS# +12V GND S M E M W# S M E M R# IOW# IOR# DACK3# DREQ3# DACK1# DREQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC BALE VCC OSC GND M E M C S 1 6# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DREQ0 DACK5# DREQ5 DACK6# DREQ6 DACK7# DREQ7 VCC M A S T E R# GND CON_ISA16C C22 47pF IOCHK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 IOCHK# 12,29 S D 7 12,14,29 S D 6 12,14,29 S D 5 12,14,29 S D 4 12,14,29 S D 3 12,14,29 S D 2 12,14,29 S D 1 12,14,29 S D 0 12,14,29 I O C H R D Y 12,14,29 AEN 12,14 SA19 12,21,29 SA18 12,21,29 SA17 12,21,29 SA16 12,21,29 SA15 12,14,21,29 SA14 12,14,21,29 SA13 12,14,21,29 SA12 12,14,21,29 SA11 12,14,21,29 SA10 12,14,21,29 SA9 12,14,21,29 SA8 12,14,21,29 SA7 12,14,21,29 SA6 12,14,21,29 SA5 12,14,21,29 SA4 12,14,21,29 SA3 12,14,21,29 SA2 12,14,21,29,33 SA1 12,14,21,29,33 SA0 12,14,21,29,33 S B H E # 12 LA23 12,29 LA22 12,29 LA21 12,29 LA20 12,29 LA19 12,29 LA18 12,29 LA17 12,29 M E M R # 12,21,29 M E M W # 12,21,29 S D 8 12,29 S D 9 12,29 S D 1 0 12,29 S D 1 1 12,29 S D 1 2 12,29 S D 1 3 12,29 S D 1 4 12,29 S D 1 5 12,29 BRSTDRV -5V -12V +12V IRQ9 DRQ2 ZEROWS# S M E M W# S M E M R# IOW# IOR# DACK#3 DRQ3 DACK#1 DRQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK#2 TC BALE NS5 TBD OSC1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 J13 GND BRSTDRV VCC IRQ9 -5V DREQ2 -12V ZEROWS# +12V GND S M E M W# S M E M R# IOW# IOR# DACK3# DREQ3# DACK1# DREQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC BALE VCC OSC GND M E M C S 1 6# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DREQ0 DACK5# DREQ5 DACK6# DREQ6 DACK7# DREQ7 VCC M A S T E R# GND CON_ISA16C IOCHK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 IOCHK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 M E M R# M E M W# SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
-5V -12V +12V
B
B
C
12,29 M E M C S 1 6# 12,29 IOCS16# 13,14,29 IRQ10 13,14,29 IRQ11 13,14,29 IRQ12 13,14,19,29 IRQ15 13,14,19,29 IRQ14 13,14 DACK#0 13,14,29 D R Q 0 13 DACK#5 13,29 D R Q 5 13 DACK#6 13,29 D R Q 6 13 DACK#7 13,29 D R Q 7 29 R M A S T E R #
NOTE :
DEFAULT NO STUFF. T H IS CAP USED TO FILTER NOISE ON TC SIGNAL.
M E M C S 16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK#0 DRQ0 DACK#5 DRQ5 DACK#6 DRQ6 DACK#7 DRQ7 R M A S T E R#
C
ISA 0
ISA 1
C23 47pF
D
D
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title ISA SLOTS Size Custom Date:
1 2 3 4 5 6
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
7
Rev 1.0 18
8
S heet
of
34
1
2
3
4
5
6
7
8
A
A
IDE CONNECTORS
1 2 SDD[15:0]
1 2 PDD[15:0]
J14 R75 26 BRSTDRV# 33 DD7#1 RP4 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 1 2 3 4 5 6 7 8 33 R77 1K R79 12 PDREQ 12 PDIOW# R83 1 2 PDIOR# 33 1 2 PIORDY 47 RP8 12 P D D A C K # PDA1 PDA0 1 2 3 4 33 R89 12 PCS1# 26 IDEACTP#
C
J15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 R_PDA2 R_PCS3# R87 33 R90 33 26 IDEACTS# 1 2 SDA[2:0] PCS3# 12 12 SCS1# PDA2 PRI_PD1 R85 1 2 SIORDY 470 12 S D D A C K # SDA1 SDA0 1 2 3 4 33 R91 33 R_SCS1# RP9 47 8 7 6 5 RSDACK# 31 R_SDA1 R_SDA0 33 35 37 39 32 34 36 38 40 R_SDA2 R_SCS3# R88 33 R92 SCS3# 12 33
C
R_BRSTDRV#1
1 3 5 7 9 11 13 15 17 19
BRSTDRV# DD8#1 DD9#1 DD10#1 DD11#1 DD12#1 DD13#1 DD14#1 DD15#1 1 2 3 4 5 6 7 8 33 R78 1K R80 12 SDREQ 33 R82 33 12 SDIOW# R84 1 2 SDIOR# 33 RP5 16 15 14 13 12 11 10 9 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 1 2 3 4 5 6 7 8 VCC 33 R271 10K RP6 16 15 14 13 12 11 10 9
R76 33
R_BRSTDRV#2 DD7#2 DD6#2 DD5#2 DD4#2 DD3#2 DD2#2 DD1#2 DD0#2
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SEC_PD1 R86 470 DD8#2 DD9#2 DD10#2 DD11#2 DD12#2 DD13#2 DD14#2 DD15#2 1 2 3 4 5 6 7 8 33 RP7 16 15 14 13 12 11 10 9 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
DD6#1 16 15 14 13 12 11 10 9 R270 10K DD5#1 DD4#1 DD3#1 DD2#1 DD1#1 DD0#1
B
B
VCC
33
R_PDDREQ# R81 R_PDIOW# 33 R_PDIOR# R259
21 23 25 27 29
R_SDDREQ# R_SDIOW# R_SDIOR#
21 23 25 27 29
R260
8 7 6 5
RPDACK# 31 R_PDA1 R_PDA0 33 35 R_PCS1# 37 39
SDA2
33
1 2 PDA[2:0] R261 13,14,18,29 IRQ14 R93 5.6K 47 PRIMARY IDE CONN.
R262 13,14,18,29 IRQ15 R94 5.6K 47
SECONDARY IDE CONN.
D
D
INTEL CORPORATION P L A T F O R M COMPONENTS DIVISION 1 9 0 0 P R A I R I E CITY RD. FM5-62 FOLSOM, CA 95630 Title P C I IDE CONNECTORS Size Custom Date:
1 2 3 4 5 6
Document Number Intel(R) 440BX AGPset T hursday, April 09, 1998
7
Rev 1.0 Sheet 19
8
of
34
A
B
C
D
E
USB CONNECTORS
F1 VCC 1.5-2.0A
4
USB_PWR0 R95 470K
4
13 O C # 0 C24 0.001uF R96 560K BLM31A700S 1 L1 2 C25 68 uF (TANTALUM) J16 USBV0 USBD0C26 0.1 uF USBD0+ USBG0 2 1 2 3 4 VCC 5 DATADATA+ 6 GND USB_CON_0.0 1 L3 BLM31A700S 1 6 2 L2 BLM31A700S
5
UGND0
+
F2 VCC 1.5-2.0A
3
USB_PWR1 R97 470K
BLM31A700S 1 L4 2
C27 470 pF
+
C29 68 uF (TANTALUM) C30 0.1 uF USBV1 USBD1USBD1+ USBG1 1 2 3 4 2 J17 VCC 5 DATADATA+ 6 GND USB_CON_0.0 L6 BLM31A700S 1 1 6 2
3
13 O C # 1 VCC3
R246 0 C28 0.001uF R263 330K R247 0 R98 560K
5
UGND1
15 A G P _ O C # 13 USBP013 U S B P 0 +
DO NOT STUFF
R204 27 R203 27 R202 27 R201 27 C161 C160 C159 C158 R105 15K R106 15K R107 15K R108 15K R_USBD1+ 47pF 47pF 47pF 47pF DO NOT STUFF R_USBD1R102 R104 0 0 C31 470 pF
L5 BLM31A700S
13 USBP12
13 U S B P 1 +
2
**NOTE: PLACE R201-204 AND C158-161 AS CLOSE AS POSSIBLE TO THE PIIX4.
R109
0
U S B A G P + 15
R110
0
U S B A G P - 15 NOTE: USE PIIX4 APPLICATION NOTE FOR LAYOUT GUIDELINES
INTEL CORPORATION
1
PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title USB HEADER Size Custom Date:
A B C
1
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
D
Rev 1.0 20
E
Sheet
of
34
1
2
3
4
5
6
7
8
A
A
S Y S T E M ROM
STUFFING OPTION
VCC JP20
MODE NORMAL
U8A 1 74HCT14 SA17 3 2 B_SA17 JP8 1 2 J_SA17
JP8
1-2 2-3
RECOVERY
FLASH SOCKET
B
SA19 SA16 SA15 SA12 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 XD[7:0] 14,33 XD0 XD1 XD2
12,14,18,29,33 SA[19:0] SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 40 1 2 3 4 5 6 36 7 8 14 15 16 17 18 19 20 21 9 24 22 10
U9 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WE# OE# CE# RP# E 2 8 F 0 0 2 B C -T DU 12
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
SA18 SA17 SA14 SA13 SA8 SA9 SA11 M E M W# SA10 BIOSCS# XD7 XD6 XD5 XD4 XD3
B
Emulator Header
MODE
PROG DEV
JP9 JP10
P r o g Boot Block 1-2
(incl. boot block)
2-3
+12V
1-2 1-2 2-3 1-2 2-3 2-3
PnP
Write Protect
JP9 1 2 3,26 P W R G O O D 12,18,29 M E M W# 12,18,29 M E M R# FL2MPU 3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC NC NC NC VPP
25 26 27 28 32 33 34 35 13 29 37 38 11
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 +12V JP10 1 FL_VPP 2 3 FL1MPU
* Header provided for BIOS emulation
TSOP SOCKET
C C
C36 0.01 uF C37 0.01 uF
13 BIOSCS#
D
D
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title S Y S T E M R OM Size Custom Date:
1 2 3 4 5 6
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
7
Rev 1.0 21
8
S heet
of
34
1
2
3
4
5
6
7
8
C38 180pF
A A
C39 180pF C40 180pF VCC
C41 180pF D4 IN4148 C42 180pF
PAR5VOLTS RP10 1 4 PDR[7:0] 5 6 7 8 RP11 PDR0
B
PARALLEL HEADER
4 3 2 1 1K C43 180pF C44 180pF STB# AFD# PD0 ERR# PD1 INIT# PD2 C45 180pF RP12 SLIN# PD3 PD4 PD5 PD6 PD7 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 CONNECTOR DB25 C49 180pF C50 180pF J18
14 AFD#R 14 STB#R 1 4 INIT#R
5 6 7 8 33
4 3 2 1 C46 180pF
B
PDR3 RP13 PDR2 1 4 SLIN#R PDR1 5 6 7 8 33 4 3 2 1
5 6 7 8 1K
4 3 2 1
C47 180pF C48 180pF
ACK# BUSY PE SLCT
RP14 1 2 3 4 RP15 PDR7 PDR6 PDR5 PDR4
C
8 7 6 5 1K
5 6 7 8 33
4 3 2 1 RP16 5 6 7 8 1K 4 3 2 1 C52 180pF C51 180pF
C
14 ERR# 14 SLCT 14 P E 14 BUSY 14 ACK# RP17 1 2 3 4 1K 8 7 6 5
C53 180pF
C54 180pF
D
D
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1 9 0 0 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title PARALLEL PORT Size Custom Date:
1 2 3 4 5 6
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
7
Rev 1.0 Sheet 22
8
of
34
A
B
C
D
E
+12V U10 SP_DCD0 S P _ R XD0 SP_DSR0 S P _ D T R0 S P _TXD0 S P _ C TS0 S P _ R TS0 SP_RI0 1 2 3 4 5 6 7 8 9 10 VCC+ RA RA RA DY DY RA DY RA VCCG D 7 5 2 3 2SOP -12V VCC RY RY RY DA DA RY DA RY GND 20 19 18 17 16 15 14 13 12 11
VCC J19 SP_DCD0 S P _ RXD0 SP_TXD0 S P _ D TR0 S P _ D S R0 S P _ RTS0 S P _ CTS0 SP_RI0 1 2 3 4 5 6 7 8 9
4
RI0#
RLSD0# 14 RX0 14 DSR0# 14 DTR0# 14 TX0 1 4 C T S 0# 1 4 R T S 0# 1 4 RI0# 14
COM 0 HEADER
4
HEADER 9 C55 100pF C56 100pF C57 100pF C59 100pF C60 1 0 0 pF C61 1 0 0 pF C62 100pF C58 100pF
3
3
+12V U11 SP_DCD1 S P _ R XD1 SP_DSR1 S P _ D T R1 S P _TXD1 S P _ C TS1 S P _ R TS1 SP_RI1 1 2 3 4 5 6 7 8 9 10 VCC+ RA RA RA DY DY RA DY RA VCCG D 7 5 2 3 2SOP -12V VCC RY RY RY DA DA RY DA RY GND 20 19 18 17 16 15 14 13 12 11
VCC J20 SP_DCD1 S P _ R XD1 S P _TXD1 S P _ D T R1 SP_DSR1 S P _ R TS1 S P _ C TS1 SP_RI1 1 2 3 4 5 6 7 8 9
RI1#
RLSD1# 14 R X 1 14 D S R 1 # 14 D T R 1 # 14 TX1 14 C T S 1# 14 R T S 1# 14 RI1# 14
COM 1 HEADER
HEADER 9 C63 100pF C64 100pF C65 100pF C67 100pF C68 100pF C69 100pF C70 100pF
2
C66 100pF
2
VCC RP18 5 6 7 8 1K R112 1.0K J21 14 DSKCHG# 14 SIDE1# 14 R D A T A# 14 W P T# 1 4 T R K 0# 1 4 W G ATE# 1 4 W D A T A# 1 4 S T EP# 14 DIR# 14 M O TEB# 14 DRVSA# 14 D R V S B # 14 M O TEA# 14 INDEX# 14 D R A T E0 14 REDWC# TP28 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 4 3 2 1
FLOPPY INTERFACE HEADER
G P I 21 13
** Connected to GPI21 of the PIIX4 for BIOS detection of a floppy drive.
1
1
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title SERIAL AND FLOPPY Size Custom Date: Document Number Intel(R) 440