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CDX-C8850/C9500
SERVICE MANUAL
US Model
CDX-C8850
E Model
CDX-C9500
Photo: CDX-C9500
SPECIFICATIONS
AUDIO POWER SPECIFICATIONS (US Model) POWER OUTPUT AND TOTAL HARMONIC DISTORTION 19 watts per channel minimum continuous average power into 4 ohms, 4 channels driven from 20 Hz to 20 kHz with no more than 1% total harmonic distortion. Other Specifications CD player section
System Signal-to-noise ratio Frequency response Wow and flutter Laser Diode Properties Material GaAlAs Wavelength 780 nm Emission Duration Continuous Laser output power Less than 44.6 µW* * This output is the value measured at a distance of 200 mm from the objective lens surface on the Optical Pick-up Block. Compact disc digital audio system 98 dB 10 20,000 Hz Below measurable limit
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
CDX-C880 MG-363S-121 KSS-521A
AM Tuning range
CDX-C8850: 530 1,710 kHz CDX-C9500: AM tuning interval: 9 kHz/10 kHz switchable 531 1,602 kHz (at 9 kHz step) 530 1,710 kHz (at 10 kHz step) Antenna terminal External antenna connector Intermediate frequency 10.71 MHz/450 kHz Sensitivity 30 µV
Power amplifier section
Speaker outputs (sure seal connectors) Speaker impedance 4 8 ohms Maximum power output 45 W × 4 (at 4 ohms) Outputs
Tuner section
FM Tuning range CDX-C8850: 87.5 107.9 MHz CDX-C9500: FM tuning interval: 50 kHz/200 kHz switchable 87.5 108.0 MHz (at 50 kHz step) 87.5 107.9 MHz (at 200 kHz step) Antenna terminal External antenna connector Intermediate frequency 10.7 MHz Usable sensitivity 8 dBf Selectivity 75 dB at 400 kHz 50 dB at 200 kHz Signal-to-noise ratio 65 dB (stereo), 68 dB (mono) Harmonic distortion at 1 kHz 0.7% (stereo), 0.4% (mono) Separation 35 dB at 1 kHz Frequency response 30 15,000 Hz
Continued on next page
FM/AM COMPACT DISC PLAYER
MICROFILM
1
SECTION 4 DIAGRAMS
4-1. IC PIN DESCRIPTIONS · IC501 CXD2548R (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin Name SYSM RMUT1 LMUT2 CKOUT VDD0 SBSO EXCK SQCK SQSO SENS SCLK DATA XLAT CLOK XRST ACDT PWM1 XLON SPOA WFCK GTOP XUGF XPCK GFS RFCK C2PO XROF SCOR MNT0 MNT1 MNT3 VSS1 DOUT ATSK MIRR DFCT FOK VDD1 VPCO1 VPCO2 VCK.I V16M VCTL PCO FILO FILI AVSS4 CLTV AVDD4 RFAC BIAS I/O I O O O -- O I I O O I I I I I O I O I O O O O O O O O O O O O -- O I O O O -- O O I O I O O I -- I -- I I Pin Description System mute input (Not used.) R-ch, "0" detection output. ("H" : ON, "L" : OFF) (Not used.) L-ch, "0" detection output. ("H" : ON, "L" : OFF) (Not used.) Master clock frequency division output (Not used.) Digital power supply Serial output of sub-P to W. Clock input for SBSO read output. Clock input for SQSO read output. SubQ 80 bit, PCM peak and level data 16 bit output. SENS output. Output to CPU. Clock input for SENS real data read. Serial data input from CPU. Latch input from CPU. Latch serial data at the falling edge. Serial data transfer clock input from CPU. System reset ("L" : Reset) Not used. External control input of spindle motor. Microcomputer extension interface (Output) (Not used.) Microcomputer extension interface (Input A) (Not used.) WFCK (Write Flame Clock) output GTOP output XUGF output (Not used.) XPLCK output (Not used.) GFS output RFCK output C2PO output (Not used.) XROF output "H" output at either detection, sub code sync S0 or S1. MNT0 output (Not used.) MNT1 output (Not used.) MNT3 output (Not used.) Digital GND Digital-Out output For anti-shock. Mirror signal output (Not used.) Diffect signal output (Not used.) Focus OK signal output Digital power supply Charge pump output for wideband EFM PLL. VCO2 charge pump output for wideband EFM PLL. VCO2 oscillator input for wideband EFM PLL. VCO2 oscillator output for wideband EFM PLL. VCO2 control input for wideband EFM PLL. Charge pump output for master PLL. Filter output for master PLL (slave = digital PLL). Filter input for master PLL. Analog GND VCO control voltage input for master. Analog power supply EFM signal input Asymmetry circuit constant current input
23
Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65, 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
Pin Name ASY.I ASY.O VC FE SE TE CE RFDC RFC ADIO AVSS3 IGEN AVDD3 TES2, 3 VSS2 TEST SFDR SRDR TFDR TRDR FFDR FRDR VDD2 COUT LOCK MDS MDP SSTP FSTO FSTI XTSL C4M WDCK VDD3 LRCK LRCKI PCMD PCMDI BCK BCKI EMPH EMPHI VSS3 AVSS1 AVDD1 AOUT1 AIN1 LOUT1 AVSS1 XVDD XTAI XTAO XVSS
I/O I O I I I I I I I O -- I -- I -- I O O O O O O -- O O O O I O I I O O -- O I O I O I O I -- -- -- O I O -- -- I O --
Pin Description Asymmetry comparate voltage input EFM full-swing output ("L" : VSS, "H" : VDD) Center voltage input Focus error signal input Sled error signal input Tracking error signal input Center error signal input RF signal input Condenser connection pin for LPF time constant of RF signal. OP amplifier output (Not used.) Analog GND Current source reference resistor connection for OP amplifier. Analog power supply TEST pin (Fixed at "L".) Digital GND TEST pin (Fixed at "L".) Sled drive output Sled drive output Tracking drive output Tracking drive output Focus drive output Focus drive output Digital power supply Track number count signal output (Not used.) Not used. Servo control output of spindle motor. (Not used.) Servo control output of spindle motor. Disc most inner track detection signal input 2/3 frequency division output of pins 103 and 104. Reference clock input for digital servo. X'tal select input ("L" : 16.9344 MHz) 4.2336 MHz output D/A interface. Word clock f = 2Fs Digital power supply D/A interface. LR clock f = Fs LR clock input to DAC. (48 bit slot) (Connect to GND.) D/A interface. Serial data (2's COMP, MSB first) Audio data input to DAC. (48 bit slot) (Connect to GND.) D/A interface. Bit clock Bit clock input to DAC. (48 bit slot) (Connect to GND.) Not used. De-emphasis ON/OFF of DAC. ("H" : ON, "L" : OFF) (Connect to GND.) Digital GND L-ch, Analog GND. L-ch, Analog power supply. L-ch, Analog output. (Not used.) L-ch, OP amplifier input. (Connect to GND.) L-ch, LINE output. (Not used.) L-ch, Analog GND. Analog power supply for master clock. X'tal oscillator input of master clock (16.9344 MHz). X'tal oscillator output of master clock. (Not used.) Analog GND for master clock. (Connect to GND.)
24
Pin No. 106 107 108 109 110 111 112
Pin Name AVSS2 ROUT2 AIN2 AOUT2 AVDD2 AVSS2 VSS0
I/O -- O I O -- -- -- R-ch, Analog GND.
Pin Description R-ch, LINE output. (Not used.) R-ch, OP amplifier input. (Connect to GND.) R-ch, Analog output. (Not used.) R-ch, Analog power supply. R-ch, Analog GND. Digital GND
25
· IC5 CXP84640-050Q (CD SYSTEM CONTROL) (SERVO BOARD)
Pin No. 15 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pin Name NCO FP OPEN FP CLOSE LINKOFF DRV OE D SW NCO LM EJ LM LOD EMPH O CDMON CD ON A MUT LD ON CD RST -- PH3 TSTIN0 TSTIN1 TST CLV NCO RESET X IN X OUT GND XT OUT XT IN AVSS AVREF TEP L TEP H NCO PH2 SCLK ESPXQOK ESPSDT GRSRST GRSCOR CD XLAT TX CLK TX DATA UNISO BUS CLK BUS SI BUS SO F OK GFS SCOR SENS -- CD CKO I/O -- I O I O I -- O O O O O O O O -- I I I I -- I I O -- O I -- I I I -- I O O I O I O O O O I/O I O I I O I I O Pin Description Not used in this set. Front panel open detection input Front panel close control output Bus interface link input (Not used in this set.) Focus/tracking coil/sled motor control output Down switch input (SW4) Not used in this set. Loading motor control output Loading motor control output De-emphasis ON/OFF control output CD mechanism deck power control output CD power control output System attenuate control output Laser power ON/OFF control output CD system reset output Not used in this set. Not used in this set. Not used in this set. Not used in this set. Not used in this set. Not used in this set. System reset input ("L" = Reset) X'tal oscillator input of system clock. (10 MHz) X'tal oscillator output of system clock. (10 MHz) Analog GND Not used in this set. Not used in this set. A/D converter GND A/D converter reference voltage input Not used in this set. Not used in this set. Not used in this set. Not used in this set. CD-TEXT data read clock output XQOK signal output to DRAM controller. Serial data input from DRAM controller. Reset signal output to DRAM controller. Sub-cord sync input from DRAM controller. CD signal process serial latch output EEPROM serial clock output EEPROM serial data output Not used in this set. Bus system serial clock input/output Bus system serial interface input Bus system serial interface output Focus OK signal input GFS signal detection input Sub-cord sync output SENS signal input Fixed at "H" in this set. CD signal process serial clock output
26
Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80
Pin Name BU.IN BUSON IN SW SELF SW TX CE SCK2 SI2 CD DATA ESPXWRE ESPXRDE ESPXLT ESPXSOE VDD HIN TEXT.ON/OFF PH1 FBTBSEL CDOSEL --
I/O I I I I O O I O O O O O -- I I I I I -- Back-up power detection input Bus on control input Disc in switch input (SW1) Self switch input (SW2) EEPROM chip enable output
Pin Description
Sub Q read clock output Sub Q 80 bit, PCM peak and level data 16 bit input CD signal process serial data output Write signal output to DRAM controller. Read signal output to DRAM controller. Serial data latch output to DRAM controller. XSOE signal output to DRAM controller. Power supply Fixed at "H" in this set. Fixed at "H" in this set. Not used in this set. Not used in this set. Not used in this set. Not used in this set.
27
· IC300 CXD2727Q (DIGITAL SIGNAL PROCESSOR) (MAIN BOARD)
Pin No. 1 2 15 16 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 69 70 71 72, 73 Pin Name VSS1 TD0 13 TST0 5 JPE1 3 VDD1 AVS3 FL-OUT AVD3 RL-OUT AVD5 AVS5 AVD1 AVS1 LREF LIN AVS7 AVD7 NCO AVDX XTLO38 XTLI38 AVSX SUB-OUT AVD8 AVS8 RIN RREF AVS2 AVD2 AVS6 AVD6 RR-OUT AVD4 FR-OUT AVS4 VSS2 RST BFOT SCK REDY TRDT LAT RVDT XS24 VDD2 VSS3 SO1 3 SOUT SI1 SI2, 3 I/O -- I I I -- -- O -- O -- -- -- -- O I -- -- -- -- O I -- O -- -- I O -- -- -- -- O -- O -- -- I O I O O I I I -- -- O O I I Digital ground Test pin (Normally, fixed at "L".) Test pin (Normally, fixed at "L".) External condition jump input ("H" : condition jump) (Fixed at "L" in this set.) Digital power supply pin (+3.3 V) Analog ground (for D/A converter 1) Analog signal output for front (L-ch) output. Analog power supply pin (+3.3 V) (for D/A converter 1) Analog signal output for rear (L-ch) output. Analog power supply pin (+3.3 V) (for D/A converter 1) Analog ground (for D/A converter 1) Analog power supply pin (+3.3 V) (for A/D converter L-ch) Analog ground (for A/D converter L-ch) Pass control connection pin for A/D converter. (for L-ch) Tuner and bus audio in signal input (for L-ch) Analog ground (for D/A converter 2) Analog power supply pin (+3.3 V) (for D/A converter 2) Not used. (Open) Analog power supply pin (+3.3 V) (for master clock) System clock output (16.9344 MHz) System clock input (16.9344 MHz) Analog ground (for master clock) Analog signal output for sub woofer output. Analog power supply pin (+3.3 V) (for D/A converter 2) Analog ground (for D/A converter 2) Tuner and bus audio in signal input (for R-ch) Pass control connection pin for A/D converter. (for R-ch) Analog ground (for A/D converter R-ch) Analog power supply pin (+3.3 V) (for A/D converter R-ch) Analog ground (for D/A converter 3) Analog power supply pin (+3.3 V) (for D/A converter 3) Analog signal output for rear (R-ch) output. Analog power supply pin (+3.3 V) (for D/A converter 3) Analog signal output for front (R-ch) output. Analog ground (for D/A converter 3) Digital ground System reset signal input from system control (IC500). ("L" : reset) Master clock output for CD. Clock signal input for serial data transfer from system control (IC500). Micon interface transfer permission signal output to system control (IC500). ("L" : transfer prohibit) Serial data output to system control (IC500). Serial data latch pulse input from system control (IC500). Serial data input from system control (IC500). Serial data 24/32 bit slot select signal input from system control (IC500). ("L" : 24 bit slot, "H" : 32 bit slot) (Valid at slave mode.) Digital power supply pin (+3.3 V) Digital ground Serial data output (Not used in this set.) Serial data output (Not used in this set.) Serial data input Serial data input (Fixed at "L" in this set.) Pin Description
28
Pin No. 74 75 76 77 78 79 80 81 82 83 84 85 94 95 96 97 98 99 100
Pin Name SIN BCK LRCK XMST VDD3 AVSP PLLEN PLCLK CKSTP AVDP VSS4 TD14 23 VDD4 AVSD SCLI BIM SDRAM AVDD
I/O I I I I -- -- I O I -- -- I -- -- I I I --
Pin Description Serial data input (Fixed at "L" in this set.) Clock signal input for serial bit transfer of serial input/output data. Sampling frequency clock signal input of serial input/output data. Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select signal input from system control (IC500). ("L" : master mode, "H" : slave mode) Digital power supply pin (+3.3 V) PLL system ground PLL enable signal input (Normally, fixed at "L".) PLL clock signal output (Not used in this set.) PLL clock output control signal input from system control (IC500). PLL system power supply pin (+3.3 V) Digital ground Test pin (Normally, fixed at "L".) Digital power supply pin (+3.3 V) Ground (for D-RAM) Not used. (Normally, fixed at "L".) Not used. (Normally, fixed at "L".) Not used. (Normally, fixed at "L".) Power supply pin (+3.3 V) (for D-RAM)
29
· IC701 HD6432355A08F (DISPLAY CONTROL) (MAIN BOARD)
Pin No. 1, 2 3 4 5 69 10 11 14 15 18 19 20 23 24 27 28 29 30 31 32 33 34 35, 36 37 38 39 40 41 43 44 45 46, 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67, 68 69 70 71 72 78 79 Pin Name PG3, 4 VSS NC VCC PC0 3 VSS PC4 7 PB0 3 VSS PB4 7 PA0 3 VSS PA4/IRQ4 PA5/IRQ5 PA6/IRQ6 PA7/IRQ7 SP-LAT P66/IRQ2 VSS P65/IRQ1 BUS-ON VCC CD/MD PE1 3 VSS TIR IND PE5, 6 MD LOCK BU-IN LINK-OFF PD2 ILL-ON VSS DOOR SW NCO PD6 BOOT VCC NC TX/FL-SO/LCDDATA SP-SI RX SP-SCK LCDCLK VSS LCDINH VSS LCDCE0 LCDCE1 P63 P27 21 FL W I/O O -- -- -- O -- O O -- O O -- O O O O I O -- O I -- I O -- O O I I O O O -- I -- O I -- -- O I I I O -- O -- O O O O O Not used. (Open) Ground Not used. (Open) Power supply pin (+5 V) Not used. (Open) Ground Not used. (Open) Not used. (Open) Ground Not used. (Open) Not used. (Open) Ground Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Digital signal processor spectrum analyzer data latch input Not used. (Open) Ground Not used. (Open) SONY BUS ON input Power supply pin (+5 V) CD/MD mechanism deck setting input ("L" : CD mechanism deck) Not used. (Open) Ground TIR indicator LED drive output Not used. (Open) MD lock signal input ("L" : unlock) Back-up power supply detection input LINK OFF output (Not used in this set.) Not used. (Open) Illumination power supply control output Ground DOOR switch input ("L" : close, "H" : open) Not used. (Open) Not used. (Open) FLASH write mode detection input Power supply pin (+5 V) Not used. (Open) LCD driver serial data/FLASH rewriting serial data output Digital signal processor spectrum analyzer data input FLASH rewriting serial data input Digital signal processor spectrum analyzer data serial clock input LCD driver/serial clock output Ground LCD driver inhibit control output Ground LCD chip enable output LCD chip enable output Not used. (Open) Not used. (Open) FLASH write control output Pin Description
30
Pin No. 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99, 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 122 123 124 125 126 128
Pin Name FWE (L) RES NMI (H) STBY (H) VCC XTAL EXTAL VSS PF7 VCC PF6 0 UNI-SO UNI-SI VSS UNI-SCK P53/ADTRG AVCC VREF P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17 10 MD0 (H) MD1 (H) MD2 (H) PG0 2
I/O I I I I -- I O -- O -- O O I -- I O -- -- I I I I I I I I -- -- O I I I O FLASH write enable input Reset input Non-maskable interruption input Hardware standby input Power supply pin (+5 V)
Pin Description
Main clock crystal input (18.432 MHz) Main clock crystal output (18.432 MHz) Ground Not used. (Open) Power supply pin (+5 V) Not used. (Open) SONY BUS serial data output SONY BUS serial data input Ground SONY BUS serial clock input Not used. (Open) A/D, D/A power supply pin (+5 V) A/D, D/A reference voltage input (+5 V) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) Not used. (Connect to ground.) A/D, D/A ground Ground Not used. (Open) Operation mode setting input (Fixed at "H".) Operation mode setting input (Fixed at "H".) Operation mode setting input (Fixed at "H".) Not used. (Open)
31
· IC500 MB90574APMT-G-214-BND (SYSTEM CONTROL) (MAIN BOARD)
Pin No. 1, 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47, 48 49 50 51 52 53 54 Pin Name RE IN0, 1 TIR BUSY TIR PDOWN TIR RST SYS RST BUS ON VCC DSPSTP TIR PLAY CSV PLAY RX/FLS SI TX/FLS SO FLS WR BEEP CSV ON DSP SI DSP SO DSP CK UNI SI UNI SO UNI CK SD IN SIRCS CSV SI CSV SO CSV CK DSP RST ST/MONO DSP XMST WIDE NARROW VSS C RAM BU MUTE ASEL0 DVCC DVSS ASEL1 LCD ANG AVCC AVRH AVRL AVSS VSM KEY IN0, 1 RC IN0 DST SEL0 DST SEL1 QUALITY MPT VCC I/O I O O O O O -- O O O I O I O O I O O I O O I I I O O O I/O O O O -- -- I O O -- -- O O -- -- -- -- I I I I I I I -- Rotary encoder input Not used. (Open) Not used. (Open) Not used. (Open) Reset output for SONY BUS slave micon. SONY BUS ON output Power supply pin (+5 V) Digital signal processor master clock control output Not used. (Open) Voice guide sound/Digital signal processor sound select output FLASH write communication input FLASH write communication output FLASH write mode select input Beep output CSV control IC power supply control output Serial data input from digital signal processor. Serial data output to digital signal processor. Serial data shift clock output to digital signal processor. SONY BUS serial data input SONY BUS serial data output SONY BUS serial clock output Tuner reception signal detection input Wireless remote commander signal input CSV control IC serial data input CSV control IC serial data output CSV control IC serial clock output Digital signal processor reset output Used in conjunction with stereo input/forced monaural output. Digital signal processor master mode/slave mode select output WIDE/NARROW select output WIDE/NARROW select output Ground Stabilized capacitor connection pin RAM backup voltage detection input Mute control output of audio output. Digital signal processor analog input source select output D/A power supply pin (+5 V) D/A ground Digital signal processor analog input source select output LCD contrast alignment output D/A, A/D power supply pin (+5 V) A/D reference voltage input (+5 V) A/D reference voltage input (0 V) D/A, A/D ground Tuner S-Meter voltage input Front panel key input Rotary commander key input Destination select input ("L" : C9500, "H" : C8850) Destination select input Tuner quality voltage input Tuner multi pass voltage input Power supply pin (+5 V) Pin Description
32
Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88, 89 90 91 92 93 94 95 96 97 98 99 102 103 104 105 106 107 108 109 110 111
Pin Name VOL LOAD VOL DATA L VOL DATA R VOL CLK DSP XLAT RC IN1 ACC IN POW ON VSS BOOT PWM NCO RDS DAVN CD/MD CD/MD ON I2C SDA I2C SCL SHIFT X1A X0A NCO KEY ACK BU IN SP LAT DSP REDY TEST EMPH WAKE UP TEL MUTE TU ON ILL IN HSTX MD2 MD1, 0 RST VSS X0 X1 VCC DOOR IND DSP ON NCO AMP-STBY TIR D0 3 TIR RD TIR WR TIR CE1 TIR CE0 AD ON NCO NOSE SW CSV REQ CSV CE
I/O O O O O O I I O -- O I -- I I I I/O I/O O O I -- I I O I I I O I O I I I I I -- I O -- O O -- O O O O O O O -- I I O
Pin Description Electronic volume IC data latch output Electronic volume L-ch setting data output Electronic volume R-ch setting data output Electronic volume setting clock output Data latch output to digital signal processor. Rotary commander shift switch input Accessory signal input System power ON/OFF control output Ground Low output at display micon rewriting. PWM control input Not used. (Open) RDS IC data reception mode read input CD/MD mechanism deck setting input ("L" : CD mechanism deck) CD/MD servo B+ detection input For communication with device connected to I2C-bus. For communication with device connected to I2C-bus. Shift signal output Low speed frequency output (32.768 kHz) Low speed frequency input (32.768 kHz) Not used. (Open) Key input detection at micon sleeping. Back-up power supply detection input Spectrum analyzer data latch output Ready signal input from digital signal processor. Test input Emphasis signal input at MD/CD play. ("H" : emphasis ON) DC/DC converter power supply ON/OFF control output (Not used in this set.) Audio signal muting input ("L" : mute ON) Tuner power supply ON/OFF output Illumination signal input Hardware standby input Operation mode designation input (Fixed at "L" in this set.) Operation mode designation input (Fixed at "H" in this set.) Reset input Ground High speed frequency input (3.68 MHz) High speed frequency output (3.68 MHz) Power supply pin (+5 V) Front panel door indicator output Digital signal processor power control output Not used. (Open) Power amplifier standby signal output Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Power control output to keys. Not used. (Open) Front panel attachment detection input Data transfer request input from CSV control IC. Chip enable output to CSV control IC.
33
Pin No. 112 113 114 115 116 117 118 119 120
Pin Name CSV RST NCO FM ON DOOR SW NS MASK SEEK AF MUTE VSS SSTOP
I/O O -- O I O O O -- I
Pin Description CSV control IC initial reset output Not used. (Open) Power control output at FM reception. Door switch input Mask control output of quality input at tuner reception. Seek control output at tuner reception. Muting output of tuner audio output. Ground IF count result input of PLL IC.
34
CDX-C8850/C9500
4-6. SCHEMATIC DIAGRAM -- CD MECHANISM SECTION (1/3) -- · Refer to page 57 for IC Block Diagrams.
(Page 40)
Note: · Voltage and waveforms are dc with respect to ground under no-signal conditions. no mark : CD PLAY : Impossible to measure
39
39
(Page 41)
CDX-C8850/C9500
4-7. SCHEMATIC DIAGRAM -- CD MECHANISM SECTION (2/3) -- · Refer to page 57 for IC Block Diagrams.
(Page 39)
Note: · Voltage and waveforms are dc with respect to ground under no-signal conditions. no mark : CD PLAY : Impossible to measure
40
40
(Page 41)
CDX-C8850/C9500
4-8. SCHEMATIC DIAGRAM -- CD MECHANISM SECTION (3/3) -- · Refer to page 58 for IC Block Diagrams.
(Page 49)
(Page 40)
(Page 39)
Note: · Voltage and waveforms are dc with respect to ground under no-signal conditions. no mark : CD PLAY : Impossible to measure
41
41
CDX-C8850/C9500
4-11. SCHEMATIC DIAGRAM -- MAIN SECTION (1/5) -- · Refer to page 59 for IC Block Diagrams.
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM ( ) : AM
46
46
(Page 47)
(Page 49)
CDX-C8850/C9500
4-12. SCHEMATIC DIAGRAM -- MAIN SECTION (2/5) -- · Refer to page 59 for IC Block Diagrams.
(Page 46)
(Page 49)
(Page 50)
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
47
47
(Page 48)
CDX-C8850/C9500
4-13. SCHEMATIC DIAGRAM -- MAIN SECTION (3/5) -- · Refer to page 60 for IC Block Diagrams.
(Page 47)
(Page 49)
(Page 50) Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
48
48
CDX-C8850/C9500
4-14. SCHEMATIC DIAGRAM -- MAIN SECTION (4/5) -- · Refer to page 60 for IC Block Diagrams.
(Page 47) (Page 46) (Page 48)
(Page 41)
(Page 50)
(Page 47)
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
49
49
(Page 50)
(Page 51)
CDX-C8850/C9500
4-15. SCHEMATIC DIAGRAM -- MAIN SECTION (5/5) -- · Refer to page 59 for IC Block Diagrams.
(Page 47)
(Page 48)
(Page 49)
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
50
50
(Page 54)
CDX-C8850/C9500
4-16. SCHEMATIC DIAGRAM -- POWER SECTION -- · Refer to page 60 for IC Block Diagrams.
(Page 49)
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
51
51
CDX-C8850/C9500
4-19. SCHEMATIC DIAGRAM -- RELAY SECTION --
(Page 55)
54
54
(Page 50)
CDX-C8850/C9500
4-20. SCHEMATIC DIAGRAM -- DISPLAY SECTION --
(Page 54)
Note: · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
55
55
· IC Block Diagrams IC1 CXA1791N-T4
LD 1 VC APC PD AMP + VREF 1.25V APC LD AMP +
IC601 BA6195FP-YT2
OPIN OPIN+ NC MUTE NC GND GND NC VCC NC NC NC
25 24 23 22 21 20 THERMAL SHUT DOWN +
19 18 17 16 15 14
VCC
20 VCC 19 APC ON
PD 2
DRIVER MUTE +
IN
LEVEL SHIFT +
VC PD1 3 VC + RF IV AMP1 VC PD2 4 VC GND 5 VC F 6 VC + F IV AMP + E IV AMP VCC VC BUFFER VC VC + + RF IV AMP2 + VC + RF SUMMING AMP
18 RFI 17 RFO
+
+
16 FE 15 FE BIAS
14 TE TRACKING ERROR AMP 13 EI
IC6 LB1638MTP-T1
12 EO
E 7 VC
DROUT
GND 1
10 N.C.
IN1 2
11 NC
CONTROL LOGIC
VR 8 VC 9 NC 10 VC
9 OUT1 8 VS 7 OUT2
VCC 3 IN2 4 GND 5
6 N.C.
IC7 BA6797FP-E2
OUT4-A OUT4-B IN4 () IN4 (+) IN3(+) IN3() PREOUT4 OUT3-B OUT3-A PREOUT3 GND GND VCC VCC
28
27
26
25
24 23
22
21 20 19
18
17
16
15
VCC
VCC
VCC/2 LEVEL LEVEL VCC/2 + VCC/2 SHIFT IN +
VCC/2
VCC/2 + IN LEVEL
VCC/2
IN SHIFT
SHIFT LEVEL IN + VCC/2 SHIFT VCC/2
1
2
3
4 5
6
7
8 9 10 11
12
13
14
IN1 () IN1 (+)
BIASIN MUTE IN2 (+)
IN2 ()
PREOUT1
REGOUT
OUT1-B
PREOUT2
OUT2-B
OUT1-A
OUT2-A
REG-B
DROUT+
OPOUT NC NC BIAS DRIN' DRIN
NC NC NC NC NC
FOCUS ERROR AMP
1 2 3 4 5 6
7 8 9 10 11
12
13
+
57
IC4 MB814400C-70PFTN
26 VSS 25 DQ4 24 DQ3
IC551 LC89170M-TLM
DQ1 DQ2 WE
1 2 3 WRITE CLOCK GENERATOR DATA INPUT BUFFER DATA OUTPUT BUFFER
VDD EXCK 1 14 VDD
CPU INTERFACE
SBSO 2 32 WORD X 8 BIT DUAL PORT RAM CRC CHECKER
13 DQSY
SCOR 3
CLOCK GENERATOR 2 23 CAS 22 OE WFCK 4
12 SRDT
COLUMN SENSE AMP DECODER I/O GATE
4M BIT MEMORY CELL ROW DECODER BOARD BIAS GENERATOR
11 SCLK
MCK 5
CLOCK GENERATOR 1
XMODE 6 GND 7
TIMING & SYNCHRONIZATION SIGNAL PROTECTION
10 SW2
9 SW1
RAS
4
MODE CONTROL
PREADDRESS BUFFER DECODER
REFRESH ADDRESS COUNTER
8 TEST
A9 A0 A1 A2 A3 VCC
5 9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
IC2 CXD2522R-T6
XWRE SPSL SDTO XSOE SCK SDTI XLT XRDE OSCE VSS A5 A6 A7 A8 XOE A4
48 47 46 45 44 43 42 41
40
39
38 37 36 35 34 33
CPU I/F XEMP XWIH AM4 AM3 AM2 AM1 AM0 VDD XQOK 49 50 51 52 53 54 55 56 57
ADDRESS MONITOR DRAM I/F
WRITE BASE COUNTER READ BASE COUNTER
VWA
32 31 30 29 28 27 26 25 24 23 22 21 20
XCAS D4 D3 D0 D1 XWE XRAS A9 VDD A0 A1 A2 A3
SELECTOR GSCR SCOR NC NC NC GRST XRST 58 59 60 61 62 63 64
DATA LINKING CONTROL
TIMING GEN. DSP I/F DAC I/F DIGITAL OUT
19 C176
18 DOUT 17 LRCK
1 2 3 4 5 6
WFCK DIN C4M XROI RFCK GTOP
7 8 9 10 11
BCKI VSS DATI LRCI WDCI
12
TEST
13
XTAO
14
XTAI
15 16
BCK DATA
58
IC151 TDA7427ADTR
DOUT2 DOUT1/INLOCK
LP OUT
GND-SIG
VDD2 GND-AM AM IN FM IN NC
28
27 26 25 24 23
22
21
20 19 18 17 16 15
11 BIT PROGRAMMABLE COUNTER
SUPPLY & POWER ON RESET SWITCH SWM/DIR 5 BIT PROGRAMMABLE COUNTER PRE COUNTER FM/AM SWITCH SWITCH SWM/DIR
CONTROL SWITCH OUT 16 BIT PROGRAMMABLE COUNTER TIMER 14 BIT PROGRAMMABLE COUNTER 11 21 BIT PROGRAMMABLE COUNTER FM/AM SWITCH
INLOCK DETECTOR
CHARGE PUMP SWITCH LP1/LP2
PHASE COMPARATOR
TEST LOGIC PORT EXTENSION REFERENCE OSCILLATOR IIC BUS INTERFACE
1 2 3 LP FM LP HC LP AM
4 VREF
5 6 7 8 DOUT3 DOUT4 DOUT5 DOUT6
9 OSCIN
10 OSCOUT
11 NC
12 SCL
13 SDA
IC551 LC89170M-TLM
VDD EXCK 1 14 VDD
IC271 BA8270FV-E2
BUS ON 1
BUS ON SWITCH RESET SWITCH BATTERY SWITCH
14 VCC
CPU INTERFACE
RST 2
SBSO 2 32 WORD X 8 BIT DUAL PORT RAM CRC CHECKER 13 DQSY
SCOR 3
12 SRDT
BATT 3
13 12 11 10
RST BUS ON CLK IN BU IN
WFCK 4
11 SCLK
MCK 5
XMODE 6 GND 7
TIMING & SYNCHRONIZATION SIGNAL PROTECTION
10 SW2
CLK 4 VREF 5 DATA 6 GND 7
9 DATA IN 8 DATA OUT
9 SW1
8 TEST
IC352 TC7SET08FU (TE85L)
5 VCC 4 OUT Y
IN B 1 IN A 2 GND 3
IF AM
SSTOP IF FM 14
ADDR HFREF
VDD1
+
59
IC602, 632 LM1973XM
DATA-OUT DATA-IN VDD2 GND AC VDD1 GND3 OUT2 OUT3 VSS1 IN3
IC604, 634 NJM2160AM-TE2
VCCL 1 INL 2 BUFFER VCCL
20 19 18 17 RESISTIVE NETWORK TAP SWITCHES
16
15 14 13
12
11
16 CL+ 15 CL
SVRL 3
SWITCH DRIVE DECODE
BUFFER
LIFT AMP
REFERENCE
DECODE SWITCH DRIVE DECODE
VCCL SIGNAL AMP
14 LGND 13 OUTL
INML 4
SWITCH DRIVE LATCH
VCCR INMR 5
TAP SWITCHES RESISTIVE NETWORK TAP SWITCHES RESISTIVE NETWORK SHIFT REGISTER
12 OUTR SIGNAL AMP REFERENCE 11 RGND
1
2
3
4
5
6
7 8
9 10
GND AC
CLOCK LOAD/SHIFT
GND2
VSS2 LOGIC GND
IN2
GND1
IN1
OUT1
BUFFER SVRR 6 INR 7 VCCR 8 BUFFER
VCCR LIFT AMP 10 CR 9 CR+
IC507 RN5VD33AA-TL
CD NC
IC702 TC7W14FU (TE12R)
8 VCC 7 1Y 6 3A 5 2Y
5
4
1A 1 3Y 2 2A 3 GND 4
RESET
1
OUT
2
VDD
3
GND
IC691, 752 TC7W66FU (TE12L)
VCC CONT1 OUT/IN2 IN/OUT2
IC802 TC74VHC08FT (EL)
8 9 10 11
GND 7 6 5 4 3 2 1
8 7 6
5
1
IN/OUT1
2 3 4
OUT/IN1 CONT2 GND
12 13 14 VCC
IC804 TCTS32FU-TE85L
IN B 1 IN A 2 GND 3 5 VCC 4 OUT Y
60
IC801 RSC-164
DACOUT WRD RDD WRC RDC GND VDD P00 P01 P02 P03 P04 P05 P06 45 44 43 42 41 40 39 38 37 36 35 34 33 PORT 0 BUFFER INTERNAL ROM 32 X 8 (HIGH) INTERNAL ROM 32 X 8 (LOW) DAC ANALOG ADC CONTROL SH 49 INTERNAL BUS AIN1 AIN0 AGND BUFOUT/PWM0 TEST/PWM1 AVDD GND D7 D6 D5 D4 D3 D2 D1 D0 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ADC MUX INTERRUPT LOGIC SLEEP PON PULSE WIDTH MODULATOR PORT 1 REGISTER SPACE STACK SPACE CPU 32 P07 XML XMH 47 46
48
EXTERNAL MEMORY INTERFACE
31 30 29 28 27 26 25 24 23 22 21
P10 P11 P12 P13 P14 P15 P16 P17 VDD GND RESET
DATA BUS
POWER CONTROL
TIMING & CONTROL
TIMER
OSC
20 XI1 19 XO1
WAKEUP LOGIC (FROM PORT 0/1) 18 A0 17 A1
ADDRESS BUS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A15 A14 A13 A12 A11 A10 A9 A8 GND VDD A7 A6 A5 A4 A3 A2
IC803 MSM534001E-49TSKFDR3 (CDX-C8850) IC803 MSM534001E-50TSKFDR3 (CDX-C9500)
OE A10 CE D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 X DECODER ADDRESS BUFFER Y DECODER MULTIPLEXER MEMORY CELL MATRIX 524,288 X 8 CE/OE CONTROL OUTPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 A14 A17 A18 VCC NC A16 A15 A12 A7 A6 A5 A4
61
IC805 MBM29F800TA
A16 48 BYTE 47 8,388,608 CELL MATRIX Y GATE ADDRESS LATCH Y DECODER I/O BUFFER DATA LATCH STB STB GND 46 DQ15/A1 45 DQ7 44 DQ14 43 DQ6 42 DQ13 41 DQ5 40 DQ12 39 DQ4 38 VCC 37 DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 36 35 34 33 32 31 30 29
1 2 3 4 5 6 7 8
A15 A14 A13 A12 A11 A10 A9 A8
X DECODER
9 NC 10 NC
11 12
WE RESET
CONTROL CIRCUIT
LOW VCC DETECTOR CIRCUIT WRITE/ERASE PULSE TIMER
13 NC 14 NC RY/BY 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24
WRITE CIRCUIT RY/BY BUFFER
ERASE CIRCUIT CHIP ENABLE/ OUTPUT ENABLE CIRCUIT
OE
28
GND 27 CE 26 A0 25
IC871 TL1451ACDB-E20
DEAD TIME CONTROL2 NON-INVINPUT2
INVINPUT2
FEED BACK2
OUT2
S.C.P
REF OUT
16 VERF. +2.5V VCC REFERENCE VOLTAGE +2.5V SHORT CIRCUIT PROTECTION COMPARATOR + + VREF/2
15
14
13
12
11
10
+ ERROR AMP2 VERF VERF VERF PWM COMPARATOR2
OUTPUT2
OUTPUT1 S R LATCH R U.V.L.O PWM COMPARATOR1
TRIANGLE OSCILLATOR 1 CT 2 RT 3 NON-INVINPUT1 4 INVINPUT1
+ ERROR AMP1 GND 5 FEED BACK1 6 DEAD TIME CONTROL1 7 OUT1 8 GND
62
VCC 9