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TCL M113 Chassis Service Manual
SERVICE MANUAL FOR M113 CHASSIS
PART I. Servicing Precautions
When working, the unit is with ultra high voltage about 25KV inside. So, to avoid the risk of electric shock,
be careful to adjust the chassis!
1. Only qualified personnel should perform service procedures.
2. All specification must be met over line voltage ranger of 110V AC to 240V AC 50Hz/60Hz.
3. Do not operate in WET/DAMP conditions.
4. Portions of the power supply board are hot ground. The remaining boards are cold ground.
5. Discharge of CRT anode should be done only to CRT ground strap.
6. When fuse blow, ensure to replace a fuse with the same type and specification.
7. Keep the wires away from the components with high temperature or high voltage.
8. When replacing the resister with high power, keep it over the PCB about 10mm.
9. The CRT anode high voltage has been adjusted and set in the factory. When repairing the chassis, do
not make the high voltage exceed 27.5KV (The beam current is 0uA). Generally, the high voltage is set on
25.5KV 1.5KV (The beam current is 700uA).
* The values of parameters above are for information only.
10. Before return the fixed unit, do check all the covering of wires to ensure that not fold or not short with
any metal components. Check the entire protection units, such as control knobs, rear cabinet & front panel,
insulation resister & capacitor, mechanical insulators and so on.
11. There are some mechanical and electrical parts associating with safety (EMC) features (Generally
related to high voltage or high temperature or electric shock), these features cannot be found out from the
outside. When replace these components, perhaps the voltage and power suit the requirements, but
efficient X-ray protection may not be provided. All these components are marked with in the schematic
diagram. When replace these, you'd better look up the components listed in this manual. If the component
you replaced not has the same safety (EMC) performance, harmful X-ray may be produced.
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Part -Product Specification
1. Ambient conditions:
1.1 Ambient temperatures:
a. Operating: -10 ~ +40
b. Storage: -15 ~ +45
1.2 Humidity
a. Operation: < 80%
b. Storage: < 90%
1.3 Air pressure: 86kpa ~ 106kpa
2. M113 Chassis Specification
2.1 MCU&Chroma Decoder:TMPA8809 Super one chip IC
2.2 System
PAL DK/BG/I
SECAM DK/BG
NTSC 3.579/4.43 AV MODE
Receiving channels 48.25MHz 463.25MHz (Hyper band)
471.25MHz 855.25MHz (UHF)
Scanning lines and frequencies 525/625 lines 15.625kHz/15.75kHz 50/60Hz
Color sub-carrier 4.433MHz/3.579MHz
2.3 IF:picture 38.0MHz sound 5.5MHz/6.0MHz/6.5MHz
2.4 Power Consumption:80W
2.5 Power Supply:AC 220V 45-55Hz
2.6 Audio Output Power(7%THD):6W+6W
2.7 Aerial Input Impedance:75 Unbalanced Din Jack Ant.Input
2.8 Product EMC/EMI Requirement:CA
2.9 Product EMC/EMI Requirement:CA
3. Basic Feature of Controller
3.1 Channel Tuning Method:Voltage Synthesizer
3.2 Presettable Program:100 Programs
3.3 Tuning for VHF and UHF Bands:Auto/Manual/Fine Tuning
3.4 Picture and Sound Adjustment
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Bright,Contrast,Color and Volume Control
Tint Control(NTSC)
Trible,Bass,Balance Control
Sharpness Control
3.5 OSD
General Features(Volume, Brightness, Contrast, Color, Program, Band, AutoSearch, Manual, Tune,
Muting, AV And Sleep Timer)
Stereo Dual Language
Four Sound Effect Indicator
German Stereo Indicator
3.6 Sleep Timer:15MIN
3.7 Remote Effective Distance:8m
3.8 Construction of Front Panel
Main Power Switch
Remote Sensor
Menu Select
S.VHS Input
TV/AV Select
Standby Indicator
Program Volume UP/DOWN
RCA Socket
3.9 Construction of Rear Panel
75 Aerial Terminal
RCA Socket-Audio-R+L In/Out,Video-In/Out
Y/U/V input
Specification Scart RCA
Video input 75 1Vp-p 1Vp-p
Audio input 10k (R+L) 0.5Vrms 0.5Vrms
Video output 75 1Vp-p 1Vp-p
Audio output 1k (R+L) 0.5Vrms 0.5Vrms
RGB input 75 0.7Vp-p
Audio line output 1k 1Vp-p
Design and specifications are subject to change without prior notice for the purpose of performance
improvement.
This specification is only for your reference.
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Part -Brief Introduction on Chassis
Nicam Option
W/Nicam N/Nicam
IC602
NICAM BD
Z141 K3955K K2966 TDA8944
SIF
I2C BUS
RF IN IF Q101 Z141
TUNER IF AMP SAWFILTER
IF
X-TAL IC 101
8MHz TMPA8809 (M113)
Hi-POT
AV INPUT IC601 I2C BUS
OUTPUT NJW1136 IC301
V-OUTP UT
24C08 TDA8172
E2PROM
REMOTE RECE IVER Q411 H OUTPUT
HANDSET KEY MATRIX H DRIVE FBT
30V
T803 B+,
IC801 Q801
MC44608 BUZ91A POWER 12V,9V,5VA
TRANSISTOR 16V
5V
1.RF IF AMP
The tuner receives, selects and amplifies RF signal, frequency mixes with local oscillate source, gets
38.0MHz&38.9MHz IF signal via C107 to Q101.After Q101 amplifing about 20dB,the PIF(Picture IF) and
SIF(Sound IF) are separated. Having passed sawfilter, PIF signal sent to TMPA8809 in pin 41,42.The IF
signal pass the video detect circuit to generate CVBS signal. Then the processor deals the signal with
luminance and chroma separation. The processor also deals the chroma siganl with integrated chroma
BPFs, PAL/NTSC demodulation and deals luminance signal with integrated chroma traps, black strech,
Y-gamma, so that the resolution of picture details is improved and Y signal is well timed with chroma signal.
The processor also deals the chroma signal with chroma sub-carrier recovery, color system recognition
and color signal decoding, then output R\G\B to CRT board. Via three groups dual emitter amplifiers to
drive KR\KG\KB. On the other hand, the processor separated by video detect circuit. Having passed the
horizontal & vertical frequency dividing circuit, H&V OSC signal, which be generated by H-AFC&V-AFC,
then output H&V signal which wave is sawtooth.
2.Channel Selection
The RF signal is converted into IF signal by the tuner. Then the IF signal cross the IF amplifier circuit(IF
pre-amp) to get a gain about 15dB. By the coupling capacitance(C107) and the match resistance R107,the
input resistance of the IF pre-amplifier match with the tuner. The signals pass a parallel connection circuit
with voltage NFB, which the input and output impedance is lower, of wide dynamic rage.R106 is the NFB
resistance, which is used to adjust the gain in the pass band. Having been amplified by the IF amplifier, the
IF signal pass the IF sawfilter K3955K(and C109 is the coupling cap.).Than PIF signal been sent from pin
4,pin5 of sawfilter to pin 41,pin42 of super one chip(TMPA8809).The processor deal the PIF signal with IF
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detection, PLL demodulation, IF AGC, AFC, video peak detection, and color system recognition ect, then
output a AGC signal from pin43 to the tuner to adjust the input control IF detection.R228,C227,C226
makes up picture IF PLL circuit, which is used to control IF detection.IC101 output a TV signal from
pin30,when pin30 level is high, TV-out signal is amplified by Q202,Q204,and Q203,Q205 is system switch
which controlled by Q211,Q210.
Tuning control and band switch control circuits
The processor output a tuning control signal from pin60.The control signal will pass Q004 and R/C network
to be amplified and differential circuit, then added to VT terminal to provide all channels' tuning voltage for
the tuner to make the channel stable.
3.Vertical Output Section
TMPA8809 outputs vertical saw-tooth wave from pin 16. It come to pin1 of TDA8172 with DC coupling, and
is amplified by inner difference amplifier. Pin7 of TDA8172 is the same phase input terminal. R302 and
R303 are DC offset resistances. C304 is a filter capacitor. In application to M113, pin7 of TDA8172 is fixed
as the DC amplify ref terminal. The amplified saw tooth-wave comes out from pin5 and make the deflect
coil to generate the deflect current. R304 and C305 filtrate the inductive interference from the horizontal
deflect coil. R310 and C309 are used to eliminate spurious oscillation generated by the deflect coil and
distributed capacitance resonance. C308, R309, C307 and accessory circuit are in charge of draw AC saw
tooth wave out at the deflect coil terminal connected with R303A, and feedback to the input terminal of
TDA8172 (pin1) to correct the linearity of horizontal scan. C301 is a high frequency decoupling capacitor.
D301 and C302 make up of a voltage pump up circuit. TDA8172 output a vertical kickback impulse from
pin6 to locate the OSD characters.
4.Horizontal Output And FBT Section
The processor outputs horizontal drive impulse from pin 13(H-OUT). The drive impulse is done with
voltage division by R201 and R401, and then comes to the base of the drive triode (Q401). C401 is used
to eliminate the noise in the H drive impulse. T401 is a horizontal drive transformer. Q411 is a horizontal
output triode with a damper inside. L412 is connected with the emitter of the horizontal output diode to
eliminate the radiation and to improve the distortions at the cross of vertical and horizontal white lines.
C412 and C413 are retrace capacitors and C414 is an s-correct capacitor. L413 is horizontal linear
inductors. R441 is used to eliminate the parasitic oscillation caused by horizontal linear inductors. C421,
R421 and D421 are used to correct the M-distortion in horizontal direction.
The deflect coil and the horizontal output triode have some resistance R while they are ducting. The
resistance R will cause the non-linear distortion, which means that the right direction scanning speed of the
electron beam becomes slower, and the right of the raster is compressed to generate distortion. We use a
horizontal linear adjuster to compensate this kind of distortion. We use L414 as the H linear adjuster in
horizontal scanning section of M113 chassis. R419, which is parallel connected with L414, is a despiking
resistance for preventing the oscillation by compensating inductor and the stray capacitance. The linear
adjuster is a transductor coil with a magnetic core inside. If the current, which pass the linear adjuster coil,
increase to a certain value, the magnetic core becomes saturated to decrease the inductance of the linear
adjustment inductor. If the +B is steady, the increase speed of Iy is faster to compensate the reducing of
deflecting current by the resistance R mention above.
We can adjust the magnetic core to change the inductance of the linear compensate inductor to adjust the
H linearity.
The EW-correct signal sent from pin28 of TMPA8809,amplified with Q412,Q413 and Q414,to adjust
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horizontal output circuit.
The EHT generation circuit
The FBT supply the anode high voltage, focus voltage and screen voltage for M113 chassis. D441and
C441 are in charge of regulating the primary impulse of the transformer to output a voltage of 200V for the
video amplifiers. The ( 4 ) ~ ( 7 ) coils of the FBT supply the heater with power. To limit the beam current in
a safe range, we add a ABL(auto brightness limit) circuit in M113 chassis. When the beam current is higher
than normal,Q451 which is a emitter follower strength conductivity, the emitter gets a lower negative
voltage, so the collector of it follows a lower voltage, then gain of system brightness decreases, brightness
decrease and beam current decreases.
Also the ABL control voltage is sampled from R426 to adjust & control EW-scan.
Extension distortion and compensation
This kind of distortion is mainly caused by the structure of CRT. Due to the screen of SF CRT is not a pure
flat screen, the distances from the deflecting center to the screen are not the same. The scanning speed of
the electron beam is uniform. If the electron beam scannning the screen equally with the effect of ture
linear sawtooth current, the E-W sides of the picture are stretched. That is the extension distortion. Usually,
we add a S-correct capacitor in series with the deflecting coil to compensate this kind of distortion. The
integral character of S-correct capacitor make the current waveform S shape. So the scanning speed of
electron beam at the center of screen is faster than the one at the side. So this action can correct the
extension distortion. C414 is a S-correct capacitor. The capacitance is inverse ratio with the correcting
effection.
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PART IV. IC Pin Description
1. MC44608-High Voltage PWM Controller
Pin Name Description
The Demag pin offers 3 different functions: Zero voltage crossing detection (50mV), 24
A current detection and 120 A current detection. The 24 A level is used to detect the
1 Demag
secondary reconfiguration status and the 120 A level to detect an Over Voltage status
called Quick OVP.
The Current Sense pin senses the voltage developed on the series resistor inserted in
the source of the power MOSFET. When Isense reaches 1V, the Driver output (pin 5) is
disabled. This is known as the Over Current Protection function. A 200 A current source
is flowing out of the pin 3 during the startup phase and during the switching phase in
2 Isense
case of the Pulsed Mode of
operation. A resistor can be inserted between the sense resistor and the pin 3, thus a
programmable peak current detection can be performed during the SMPS standby
mode.
A feedback current from the secondary side of the SMPS via the optocoupler is
Control
3 injected into this pin. A resistor can be connected between this pin and GND to allow
Input
the programming of the Burst duty cycle during the Standby mode.
4 Ground This pin is the ground of the primary side of the SMPS.
5 Driver The current and slew rate capability of this pin are suited to drive Power MOSFETs.
This pin is the positive supply of the IC. The driver output gets disabled when the
voltage becomes higher than 15V and the operating range is between 6.6V and 13V.
6 VCC
An intermediate voltage level of 10V creates a disabling condition called Latched Off
phase.
7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6.
This pin can be directly connected to a 500V voltage source for startup function of the
IC. During the Startup phase a 9 mA current source is internally delivered to the VCC
8 Vi
pin 6 allowing a rapid charge of the VCC capacitor. As soon as the IC startsup, this
current source is disabled.
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OPERATING DESCRIPTION
Regulation
The pin 3 senses the feedback current provided by the opto-coupler. During the switching phase the switch S2 is
closed and the shunt regulator is accessible by the pin 3. The shunt regulator voltage is typically 5V. The dynamic
resistance of the shunt regulator represented by the zener diode is 20 .
The gain of the Control input is given on Figure 10 which shows the duty cycle as a function of the current injected
into the pin 3.
The maximum current sense threshold is fixed at 1V. The peak
A 4KHz filter network is inserted
between the shunt regulator and the
PWM comparator to cancel the high
frequency residual noise.
The switch S3 is closed in Standby
mode during the Latched Off Phase
while the switch S2 remains open. (See
section PULSED MODE DUTY
CYCLE CONTROL).
The resistor Rdpulsed (Rduty cycle
burst) has no effect on the regulation
process. This resistor is used to
determine the burst duty cycle described in the chapter "Pulsed Duty Cycle Control" on page 8.
PWM Latch
The MC44608 works in voltage mode. The ontime is controlled by the PWM comparator that compares the
oscillator sawtooth with the regulation block output.
The PWM latch is initialized by the
oscillator and is reset by the PWM
comparator or by the current sense
comparator in case of an over current.
This configuration ensures that only a
single pulse appears at the circuit
output during an oscillator cycle.
Current Sense
The inductor current is converted to a
positive voltage by inserting a ground
reference sense resistor RSense in series
with the power switch.
The maximum current sense threshold is fixed at 1V. The peak current is given by the following equation:
Ipkmax = 1/Rsense( ) (A)
In standby mode, this current can be lowered as due to the activation of a 200 A current source:
IpkMAX-STBY
The current sense input consists of a filter (6k , 4pF) and of a leading edge blanking. Thanks to that, this pin is not
sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is
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TCL M113 Chassis Service Manual
required to sense the current.
Finally, this pin is used:
as a protection against over currents (Isense > I)
as a reduction of the peak current during a Pulsed Mode switching phase.
The overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate).
This results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode
switching sequence.
Demagnetization Section
The MC44608 demagnetization
detection consists of a
comparator designed to compare
the VCC winding voltage to a
reference that is typically equal
to 50mV.
This reference is chosen low to
increase effectiveness of the
demagnetization detection even
during startup.
A latch is incorporated to turn
the demagnetization block
output into a low level as soon
as a voltage less than 50 mV is
detected, and to keep it in this
state until a new pulse is
generated on the output. This
avoids any ringing on the input
signal which may alter the
demagnetization detection.
For a higher safety, the
demagnetization block output is
also directly connected to the
output, which is disabled during the demagnetization phase.
The demagnetization pin is also used for the quick, programmable OVP. In fact, the demagnetization input current is
sensed so that the circuit output is latched off when this current is detected as higher than 120 A.
This function can be inhibited by grounding it but in this case, the quick and programmable OVP is also disabled.
Oscillator
The MC44608 contains a fixed frequency oscillator. It is built around a fixed value capacitor CT succesively charged
and discharged by two distinct current sources ICH and IDCH. The window comparator senses the CT voltage value
and activates the sources when the voltage is reaching the 2.4V/4V levels.
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The complete demagnetization status
DMG is used to inhibit the recharge of the
CT capacitor.
Thus in case of incomplete transformer
demagnetization the next switching cycle is
postpone until the DMG signal appears. The
oscillator remains at 2.4V corresponding to
the sawtooth valley voltage. In this way the
SMPS is working in the so called SOPS
mode (Self Oscillating Power Supply). In
that case the effective switching frequency is
variable and no longer depends on the
oscillator timing but on the external working
conditions (Refer to DMG signal in the
Figure 5).
The OSC and Clock signals are provided according to the Figure 5. The Clock signals correspond to the CT capacitor
discharge. The bottom curve represents the current flowing in the sense resistor Rcs. It starts from zero and stops
when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode
control.
Overvoltage Protection
The MC44608 offers two OVP functions:
a fixed function that detects when VCC is higher than 15.4V
a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120 A). Thus this OVP is quicker as it is not impacted by the VCC inertia
and is called QOVP.
In both cases, once an OVP condition is detected, the output is latched off until a new circuit
STARTUP.
Startup Management
The Vi pin 8 is directly connected to the HV DC rail Vin. This high voltage current source is
internally connected to the
VCC pin and thus is used to
charge the VCC capacitor. The
VCC capacitor charge period
corresponds to the Startup
phase. When the VCC voltage
reaches 13V, the high voltage
9mA current source is
disabled and the device starts
working. The device enters
into the switching phase.
It is to be noticed that the maximum rating of the Vi pin 8 is 700V. ESD protection circuitry is not currently added to
this pin due to size limitations and technology constraints. Protection is limited by the drainsubstrate junction in
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TCL M113 Chassis Service Manual
avalanche breakdown. To help increase the application safety against high voltage spike on that pin it is possible to
insert a small wattage 1k series resistor between the Vin rail and pin 8.
The Figure 6 shows the VCC voltage evolution in case of no external current source providing current into the VCC pin
during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding
is not present (strong overload on the SMPS output for example).
The Figure16 also depicts this working configuration.
In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%.
Mode Transition
The LW latch Figure
7 is the memory of
the working status at
the end of every
switching sequence.
Two different cases
must be considered
for the logic at the
termination of the
SWITCHING
PHASE:
1. No Over Current was observed
2. An Over Current was observed
These 2 cases are corresponding to the signal labeled NOC in case of "No Over Current" and "OC" in case of Over
Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over
current and Q=0 for over current.
This sequence is repeated during the Switching phase.
Several events can occur:
1. SMPS switch OFF
2. SMPS output overload
3. Transition from Normal to Pulsed Mode
4. Transition from Pulsed Mode to Normal Mode
1. SMPS SWITCH OFF
When the mains is switched OFF, so long as the bulk electrolithic bulk capacitor provides energy to the SMPS, the
controller remains in the switching phase. Then the peak current reaches its maximum peak value, the switching
frequency decreases and all the secondary voltages are reduced. The VCC voltage is also reduced. When VCC is equal
to 10V, the SMPS stops working.
2. Overload
In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 6):
The SWITCHING PHASE: The SMPS output is low and the regulation block reacts by increasing the ON time
(dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 7) is reset before the
VPWM signal appears. The SMPS output voltage is low. The VCC voltage cannot be maintained at a normal level as
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the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. Vout
nominal / Vout shortcircuit). Consequently the VCC voltage is reduced at an operating rate given by the combination
VCC capacitor value together with the ICC working consumption (3.2mA) according to the equation 2. When VCC
crosses 10V the WORKING PHASE gets terminated. The LW latch remains in the reset status.
The LATCHEDOFF PHASE: The VCC capacitor voltage continues to drop. When it reaches 6.5V this phase is
terminated. Its duration is governed by equation 3.
The STARTUP PHASE is reinitiated. The high voltage startup current source (ICC1 = 9mA) is activated and the
MODE latch is reset. The VCC voltage ramps up according to the equation 1. When it reaches 13V, the IC enters into
the SWITCHING PHASE.
The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) activates the
NORMAL mode of operation. Figure 2 shows that no current is injected out pin 2.
The over current sense level corresponds to 1V.
As long as the overload is present, this sequence repeats. The SWITCHING PHASE duty cycle is in the range of
10%.
3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS standby mode all the SMPS outputs are lowered except for the low voltage output that supply the
wakeup circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.
The secondary reconfiguration status can be detected on the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the Demagnetization Section). In the reconfigured status, the Laux
voltage is also reduced. The VCC selfpowering is no longer possible thus the SMPS enters in a hiccup mode similar
to the one described under the Overload condition.
In the SMPS standby mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced according to
the equation of the current sense section, page 5. The C.S. clamping level depends on the power to be delivered to the
load during the SMPS standby mode. Every switching sequence ON/OFF is terminated by an OC as long as the
secondary Zener diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated
by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW
latch stores this NOC status.
The LATCHED OFF PHASE: The MODE latch is set.
The STARTUP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The Standby signal is validated and the 200 A is sourced out of the Current Sense
pin 2.
4. Transition from Standby to Normal
The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be
achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset.
At the next WORKING PHASE a NORMAL mode status takes place.
In order to become independent of the recovery time SWITCHING PHASE constant on the secondary side of the
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SMPS an additional reset input R2 is provided on the MODE latch. The condition Idemag<24 A corresponds to the
activation of the secondary reconfiguration status. The R2 reset insures a return into the NORMAL mode following
the first corresponds to 1V. STARTUP PHASE.
Pulsed Mode Duty Cycle Control
During the sleep mode of the SMPS the switch S3 is closed and the control input pin 3 is connected to a 4.6V voltage
source thru a 500 resistor. The discharge rate of the VCC capacitor is given by ICClatch (device consumption during
the LATCHED OFF phase) in addition to the current drawn out of the pin 3. Connecting a resistor between the Pin 3
and GND (RDPULSED) a programmable current is drawn from the VCC through pin 3. The duration of the LATCHED
OFF phase is impacted by the presence of the resistor RDPULSED. The equation 3 shows the relation to the pin 3
current.
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective behavior during the PULSED MODE operation. The equations
6, 7, and 8 contain K, Y, and D factors. These factors are combinations of measured parameters. They appear in the
parameter section "K factors for pulsed mode operation" page 4. In equations 3 through 8 the pin 3 current is the
current defined in the above section "Pulsed Mode Duty Cycle Control".
2. TDA9801-Single standard VIF-PLL demodulator and FM-PLL detector
FUNCTIONAL DESCRIPTION
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SYMBOL PIN DESCRIPTION
VIF1 1 VIF differential input 1
VIF2 2 VIF differential input 2
TOP 3 tuner AGC TakeOver Point (TOP) connection
ADJ 4 phase adjust connection
MUTE 5 sound mute switch connection
TPLL 6 PLL time constant connection
CVBS 7 CVBS (positive) video output
n.c. 8 not connected
AF 9 AF output
DAF 10 AF amplifier decoupling capacitor connection
SI 11 sound intercarrier input
TAGC 12 tuner AGC output
VSO 13 video and sound intercarrier output
VI 14 buffer amplifier video input
AFC 15 AFC output
VCO1 16 VCO1 reference circuit for 2fPC
VCO2 17 VCO2 reference circuit for 2fPC
GND 18 ground supply (0 V)
AGC 19 AGC detector capacitor connection
VP 20 supply voltage (+5 V)
Stage IF amplifier
The VIF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a
feedback network controlled by emitter degeneration.
AGC detector, IF AGC and tuner AGC
The automatic control voltage to maintain the video output signal at a constant level is generated in accordance with
the transmission standard. Since the TDA9801 is suitable for negative modulation only the peak sync pulse level is
detected.
The AGC detector charges and discharges capacitor CAGC to set the IF amplifier and tuner gain. The voltage on
capacitor CAGC is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC
output current on pin TAGC (open-collector output). The tuner AGC takeover point level is set at pin TOP. This
allows the tuner to be matched to the SAW filter in order to achieve the optimum IF input level.
Frequency detector and phase detector
The VIF amplifier output signal is fed into a frequency detector and into a phase detector. During acquisition the
frequency detector produces a DC current proportional to the frequency difference between the input and the VCO
signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between
the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC
voltage via the loop filter which controls the VCO frequency.
Video demodulator
The true synchronous video demodulator is realized by a linear multiplier which is designed for low distortion and
wide bandwidth. The vision IF input signal is multiplied with the `in phase' component of the VCO output. The
demodulator output signal is fed via an integrated low-pass filter (fg = 12 MHz) for suppression of the carrier
harmonics to the video amplifier.
VCO, AFC detector and travelling wave divider
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The VCO operates with a symmetrically connected reference LC circuit, operating at the double vision carrier
frequency. Frequency control is performed by an internal variable capacitor diode.
The voltage to set the VCO frequency to the actual double vision carrier frequency is also amplified and converted
for the AFC output current.
The VCO signal is divided-by-2 with a Travelling Wave Divider (TWD) which generates two differential output
signals with a 90 degree phase difference independent of the frequency.
Video amplifier
The composite video amplifier is a wide bandwidth operational amplifier with internal feedback. A nominal positive
video signal of 1 V (p-p) is present at pin VSO.
Buffer amplifier and noise clipper
The input impedance of the 7 dB wideband CVBS buffer amplifier (with internal feedback) is suitable for ceramic
sound trap filters. Pin CVBS provides a positive video signal of 2 V (p-p). Noise clipping is provided internally.
Sound demodulation
LIMITER AMPLIFIER
The FM sound intercarrier signal is fed to pin SI and through a limiter amplifier before it is demodulated. The result
is high sensitivity and AM suppression. The limiter amplifier consists of 7 stages which areinternally AC-coupled in
order to minimizing the DC offset.
FM-PLL DETECTOR
The FM-PLL demodulator consists of an RC oscillator, loop filter and phase detector. The oscillator frequency is
locked on the FM intercarrier signal from the limiter amplifier. As a result of this locking, the RC oscillator is
frequency modulated. The modulating voltage (AF signal) is used to control the oscillator frequency. By this, the
FM-PLL operates as an FM demodulator.
AF AMPLIFIER
The audio frequency amplifier with internal feedback is designed for high gain and high common-mode rejection.
The low-level AF signal output from the FM-PLL demodulator is amplified and buffered in a low-ohmic audio
output stage. An external decoupling capacitor CDAF removes the DC voltage from the audio amplifier input.
By using the sound mute switch (pin MUTE) the AF amplifier is set in the mute state.
3. TDA9874A Digital TV sound demodulator/decoder
SYMBOL PIN DESCRIPTION
EXTIR 1 external audio input right channel
EXTIL 2 external audio input left channel
Vref2 3 analog reference voltage for DAC and operational amplifiers
P2 4 second general purpose I/O pin
OUTM 5 analog output mono
VSSA4 6 analog ground supply 4 for analog back-end circuitry
OUTL 7 analog output left
OUTR 8 analog output right
VDDA1 9 analog supply voltage 1; back-end circuitry 5 V
VSSA1 10 analog ground supply 1; back-end circuitry
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VSSD1 11 digital ground supply 1; core circuitry
VDDD1 12 digital supply voltage 1; core voltage regulator circuitry
VSSD2 13 digital ground supply 2; core circuitry
TP2 14 additional test pin 2; connected to VSSD for normal operation
NICAM 15 serial NICAM data output (at 728 kHz)
TP1 16 additional test pin 1; connected to VSSD for normal operation
PCLK 17 NICAM clock output (at 728 kHz)
ADDR1 18 first I2C-bus slave address modifier input
XTALO 19 crystal oscillator output
XTALI 20 crystal oscillator input
TEST2 21 test pin 2; connected to VSSD for normal operation
Iref 22 resistor for reference current generation; front-end circuitry
ADDR2 23 second I2C-bus slave address modifier input
VSSA2 24 analog ground supply 2; analog front-end circuitry
VDEC 25 analog front-end circuitry supply voltage decoupling
TEST1 26 test pin 1; connected to VSSD for normal operation
SIF2 27 sound IF input 2
Vref1 28 reference voltage; for analog front-end circuitry
SIF1 29 sound IF input 1
CRESET 30 capacitor for Power-on reset
VSSA3 31 digital ground supply 3; front-end circuitry
VDDA3 32 analog front-end circuitry regulator supply voltage 3 (5 V)
SCL 33 I2C-bus serial clock input
SDA 34 I2C-bus serial data input/output
SDO 35 I2S-bus serial data output
WS 36 I2S-bus word select input/output
SCK 37 I2S-bus clock input/output
SYSCLK 38 system clock output
VDDD3 39 digital supply voltage 3; digital I/O pads
VSSD3 40 digital ground supply 3; digital I/O pads
P1 41 first general purpose I/O pin
MONOIN 42 analog mono input
FUNCTIONAL DESCRIPTION
Description of the demodulator and decoder section
1. SIF INPUTS
Two inputs are provided, pin SIF1 and pin SIF2. For higher SIF signal levels the
SIF input can be attenuated with an internal switchable 10 dB resistor divider.
As no specific filters are integrated, both inputs have the same specification
giving flexibility in application. The selected signal is passed through
an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz.
2. AGC
The gain of the AGC amplifier is controlled from the ADC output by means of
a digital control loop employing hysteresis. The AGC has a fast attack behaviour
to prevent ADC overloads, and a slow decay behaviour to prevent AGC oscillations.
For AM demodulation the AGC must be switched off. When switched off, the
control loop is reset and fixed gain settings can be chosen. The AGC can be
controlled via the I2C-bus.
3. MIXER
The digitized input signal is fed to the mixers, which mix one or both input sound
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carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer
control word registers is via the I2C-bus or via Easy Standard Programming (ESP). When receiving NICAM
programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency
loop.
4.FM AND AM DEMODULATION
An FM or AM input signal is fed through a switchable band-limiting filter into a demodulator that can be used for
either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis
is available for Wegener-Panda 1 encoded satellite programs.
5. FM DECODING
A 2-carrier stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the
European and Korean stereo systems are supported.
Automatic FM dematrixing is also supported, which means that the FM sound mode identification (mono, stereo or
dual) switches the FM dematrix directly. No loop via the microcontroller is needed.
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For highly overmodulated signals, a high deviation mode for monaural audio sound single carrier demodulation can
be selected.
NICAM decoding is still possible in high deviation mode.
6. FM IDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot and
narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection
can be made via the I2C-bus for B/G, D/K and M standards, and for three different time constants that represent
different trade-offs between speed and reliability of identification. A pilot detector allows the control software to
identify an analog 2-carrier (A2) transmission within approximately 0.1 s.
Automatic FM dematrixing, depending on the identification, is possible.
7. NICAM DEMODULATION
The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbits/s. The NICAM demodulator performs
DQPSK demodulation and passes the resulting bitstream and clock signal to the NICAM decoder and, for evaluation
purposes, to various pins.
A timing loop controls the frequency of the crystal oscillator to lock the sampling instants to the symbol timing of the
NICAM data.
8. NICAM DECODING
The device performs all decoding functions in accordance with the "EBU NICAM 728 specification". After locking
to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence. The
device then synchronizes to the periodic frame flag bit C0.
The status of the NICAM decoder can be read out from the NICAM status register by the user. The OSB bit indicates
that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM
data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is
identical to the sound conveyed by the NICAM channel.
The error byte contains the number of sound sample errors (resulting from parity checking) that occurred in the past
128 ms period. The Bit Error Rate (BER) can be calculated using the following equation:
BER = bit errors / total bits error byte 1.74 10-5
9. NICAM AUTO-MUTE
This function is enabled by setting bit AMUTE to logic 0. Upper and lower error limits may be defined by writing
appropriate values to two registers in the I2C-bus section. When the number of errors in a 128 ms period exceeds the
upper error limit, the auto-mute function will switch the output sound from NICAM to whatever sound is on the first
sound carrier (FM or AM) or to the analog mono input. When the error count is smaller than the lower error limit, the
NICAM sound is restored.
The auto-mute function can be disabled by setting bit AMUTE to logic 1. In this case clicks become audible when the
error count increases. The user will hear a signal of degrading quality.
If no NICAM sound is received, the outputs are switched from the NICAM channel to the 1st sound carrier.
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A decision to enable or disable the auto-mute is taken by the microprocessor based on an interpretation of the
application control bits C1, C2, C3 and C4, and possibly any additional strategy implemented by the user in the
microcontroller software. When the AM sound in NICAM L systems is demodulated in the 1st sound IF and the
audio signal connected to the mono input of the TDA9874A, the controlling microprocessor has to ensure
switching from NICAM reception to mono input, if auto-muting is desired. This can be achieved by setting bit
AMSEL = 1 and bit AMUTE = 0.
10. CRYSTAL OSCILLATOR
The digital controlled crystal oscillator (DCXO) is fully integrated. Only an external 24.576 MHz crystal is required.
11. TEST PINS
All test pins are active HIGH. In normal operation of the device they can be left open-circuit, as they have internal
pull-down resistors. Test functions are for manufacturing tests only and are not available to customers.
12. POWER FAIL DETECTOR
The power fail detector monitors the internal power supply for the digital part of the device. If the supply has
temporarily been lower than the specified lower limit, the power failure register bit PFR in subaddress 0, will be set
to logic 1. Bit CLRPFR, slave register subaddress 1, resets the Power-on reset flip-flop to logic 0. If this is detected,
an initialization of the TDA9874A has to be performed to ensure reliable operation.
13. POWER-ON RESET
The reset is active LOW. In order to perform a reset at power-up, a simple RC circuit may be used which consists of
an integrated passive pull-up resistor and an external capacitor connected to ground.
The pull-up resistor has a nominal value of 50 k , which can easily be measured between pins CRESET and
VDDD3. Before the supply voltage has reached a certain minimum level, the state of the circuit is completely
undefined and remains in this undefined state until a reset is applied.
The reset is guaranteed to be active when:
.The power supply is within the specified limits (4.5 to
5.5 V)
.The crystal oscillator (DCXO) is functioning
.The voltage at pin CRESET is
below 0.3VDDD (1.5 V if VDDD= 5.0 V, typically
below 1.8 V).
The required capacitor value depends on the gradient of
the rising power supply voltage. The time constant of the
RC circuit should be clearly larger than the rise time of
the power supply (to make sure that the reset condition is
always satisfied), even when considering tolerance spreading. To avoid problems with a too slow discharging of the
capacitor at
power-down, it may be helpful to add a diode from pin CRESET to VDDD.
It should be noted that the internal ESD protection diode does not help here as it only conducts at higher voltages.
Under difficult power supply conditions (e.g. very slow or non-monotonic ramp-up), it is recommended to drive the
reset line from a microcontroller port or the like.
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Description of the DSP
1. LEVEL SCALING
All input channels to the digital crossbar switch are equipped with a level adjustment facility to change the signal
level in a range of ±15 dB. Adjusting the signal level is intended to compensate for the different modulation
parameters of the various TV standards. Under nominal conditions it is recommended to scale all input channels to be
15 dB below full-scale. This will create sufficient headroom to cope with overmodulation and avoids changes of the
volume impression when switching from FM to NICAM or vice versa.
2. NICAM PATH
The NICAM path has a switchable J17 de-emphasis.
3. NICAM AUTO-MUTE
If NICAM is received, the auto-mute is enabled and the signal quality becomes poor. The digital crossbar switches
automatically to FM, channel 1 or the analog mono input, as selected by bit AMSEL. This automatic switching
depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus.
4. FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator that may occur due to carrier Frequency offsets,
and supplies the FM monitor function with DC values, e.g. for the purpose of microprocessor controlled carrier
search or fine tuning functions.
An adaptive de-emphasis is available for Wegener-Panda 1 encoded satellite programs.
The de-emphasis stage offers a choice of settings for the supported TV standards.
The 2-channel decoder performs the dematrixing of 1€2(L + R), R to L and R signals of 1€2(L + R) and 1€2(L - R) to L
and R signals or of channel 1 and channel 2 to L and R signals, as demanded by the different TV standards or user
preferences.
Automatic FM dematrixing is also supported.
Using the high deviation mode, only channel 1 (mono) can be demodulated. The scaling is -6 dB compared to
2-channel decoding.
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5. MONITOR
This function provides data words from the FM demodulator outputs and FM and NICAM signals for external use,
such as carrier search or fine tuning. The peak level of these signals can also be observed. Source selection and data
read out are performed via the I2C-bus.
6. DIGITAL CROSSBAR SWITCH
The input channels are derived from the FM and NICAM paths, while the output channels comprise I2S-bus and the
audio DACs to the analog crossbar switch. It should be noted that there is no connection from the external analog
audio inputs to the digital crossbar switch.
7. DIGITAL AUDIO OUTPUT
The digital audio output interface comprises an I2S-bus output port and a system clock output. The I2S-bus port is
equipped with a level adjustment facility that can change the signal level in a ±15 dB range in 1 dB steps. Muting is
possible, too, and outputs can be disabled to improve EMC performance.
The I2S-bus output matrix provides the functions for forced mono, stereo, channel swap, channel 1 or channel 2.
Automatic selection for TV applications is possible. In this case the microcontroller program only has to provide a
user controlled sound A or sound B selection.
8. STEREO CHANNEL TO THE ANALOG CROSSBAR PATH
A level adjustment function is provided with control positions of 0 dB, +3 dB, +6 dB and +9 dB in combination with
the audio DACs. The Automatic Volume Level (AVL) function provides a constant output level of -20 dB (full-scale)
for input levels between 0 dB (full-scale) and -26 dB (full-scale).
There are some fixed decay time constants to choose from, i.e. 2, 4 or 8 seconds.
Automatic selection for TV applications is possible. In this case the microcontroller program only has to provide a
user controlled sound A or sound B selection.
9. GENERAL
The level adjustment functions can provide signal gain at multiple locations. Great care has to be taken when using
gain with large input signals, e.g., due to overmodulation, in order not to exceed the maximum possible signal swing,
which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital
crossbar switch should be 15 dB below digital full-scale (-15dB full-scale).
Description of the analog audio section
1. ANALOG CROSSBAR SWITCH AND ANALOG MATRIX
The TDA9874A has one external analog stereo input, one mono input, one 2-channel and one single-channel output
port. Analog source selector switches are employed to provide the desired analog signal routing capability, which is
done by the analog crossbar switch section.
The basic signal routing philosophy of the TDA9874A is that each switch handles two signal channels at the same
time (e.g. left and right, language A and B) directly at the source.
Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a
signal from one input channel, say language A, to both output channels or for swapping left and right channels. The
analog matrix provides the functions given in the follow table. Automatic matrixing for TV applications is also
supported.
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2
All switches and matrices are controlled via the I C-bus.
Analog matrix functions
2. EXTERNAL AND MONO INPUTS
MATRIX OUTPUT
MODE The external and mono inputs accept signal levels of up to 1.4 V
L OUTPUT R OUTPUT
1 L input R input (RMS). By adding external series resistors to provide suitable
2 R input L input attenuation, the external input could be used as a SCART input.
3 L input L input
Whenever the external or mono input is selected, the output of the
4 R input R input
DAC is muted to improve the crosstalk performance.
3. AUDIO DACS
The TDA9874A comprises a 2-channel audio DAC and an additional single-channel audio DAC for
feeding signals from the DSP section to the analog crossbar switch. These DACs have a resolution of
15 bits and employ four-times oversampling and noise shaping.
4. AUDIO OUTPUT BUFFERS
The output buffers provide a gain of 0 dB and offer a
muting possibility. The post filter capacitors of the audio
DACs are connected to the buffer outputs.
5. STANDBY MODE
Switch diagram for the analog audio section
The standby mode (see Section 7.3.3) disables most functions and reduces power dissipation of the TDA9874A. It
provides no other function.
Internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on
returning to normal operation. This can be accomplished in the same way as after a Power-on reset.
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4.NJW1136 AUDIO PROCESSOR with Subwoofer Output
GENERAL DESCRIPTION PACKAGE OUTLINE
THE NJW1136 is a sound processor with subwoofer output includes
all of functions processing audio signal for TV, such as tone control,
balance, volume, mute, and AGC function. Also the NJW1136 includes
the LPF for subwoofer output and bass boost function. The original
surround system reproduces natural surround sound and clear vocal
orientation. All of internal status and variables are controlled by IIC BUS
interface. NJW1136D
FEATURES
Operating Voltage: 8 to 13V
3ch Output(Lch, Rch, Subwoofer ch) / 2ch Output(Lch, Rch)
LPF Filter (Adjustable cut off frequency by external parts)
AGC Circuit (It reduces volume difference among input sources.)
Adjustable AGC boost level by external parts and AGC compression level by IIC BUS
NJRC O