Formenti 19-1-CHASSIS Manual De Servicio.pdf part of Formenti F19 Formenti 19-1-CHASSIS Manual De Servicio.rar, Formenti 19-1-CHASSIS Manual De Servicio text manual preview

Text preview for : Formenti 19-1-CHASSIS Manual De Servicio.pdf part of Formenti F19 Formenti 19-1-CHASSIS Manual De Servicio

Back to : Formenti 19-1-CHASSIS Man | Home

F 19 SERVICE MANUAL
THIS DOCUMENT IS A PROPERTY OF INDUSTRIE FORMENTI ITALIA NO AUTHORIZED MODIFICATIONS ARE PERMITTED.

CREATED BY E.G.

There are two different types of F19 chassis that are equipped with two different microcontroller. These microcontroller are known as ETT having a code SAA5297A and PAINTER with a code number SAA5553. From the point of view of the application on the F19 chassis the two type of microcontroller are substantially having the same performances, the same pinout , the same firmware but they are not interchangeable as the power supply are different.
In case of SAA5297A the power supply is 5 V for the SAA5553 is 3.3 V.

Even if the two devices are non interchangeable the two chassis can be interchanged as the in/out interface are exactly the same.
As the specifications of the two devices are the same and the first version of the chassis was equipped with the SAA5297A , in this document the characteristics of it are very much detailed meanwhile there is a very short description (as an addendum at the end) for the SAA5553.

F19 CHASSIS DESCRIPTION
Summary The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect ratio and dimension from 25" up to 34". As we can see from the block diagram the chassis is equipped with the most recent Integrated Circuit like the one chip TV processor TDA884x that does include all the low level signal processing including Video, Audio, synchronisation process, and chroma

decoder . (see more detail at the "TDA884x FAMILY SPECIFICATION" paragraph), and the Sound Processor TDA9875A that perform all sound function including digital decoding of NICAM signals. (see more detail at the " TDA9870A & tda9875A MAIN CHARACTERISTICS" paragraph). The above mentioned devices are driven by an Integrated Circuit that does include the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages RAM. (SAA5297A) In the F19 chassis there are, besides the stereo one, two possible module that are performing "FEATURES" like PIP (picture in picture) and / or CTI (colour transients

improvement) and 4 by 3 to 16 by 9 signal processing. One further module is dedicated to the so called "Zero Power Stand By" A 26 Key Remote Control is performing the full control for the end- used but can also be used in " SERVICE MODE" to control and adjust, without open the back cover of the TV set all the necessary functions. With the 5 "LOCAL KEY BOARD" button all the end user function can also be performed When the TV set is equipped with a PLL tuner the microcontroller recognise it and the tuning method became a frequency synthesis system if not it work as a voltage tuning system (provided all necessary components are mounted) The TV make use of a multilevel MENU (activated both by the Remote Control and Local Keyboard) using five selectable languages ( Italian, German, English, France, end Spanish) with which it is possible to control sequentially all video and sound value, to adjust several parameter like picture format, sound response, sleep timer etc., and to set others important parameter like standard, select country for automatic tuning and sort etc. Here below a list of the characteristics of the TV se

E.G.Data creazione 31/10/99 15.38

1/7

f19intro

TV SET CHARACTERISTICS (MONO & STEREO )
PICTURE TUBE SIZE : · 4 : 3 ASPECT RATIO · 16 : 9 ASPECT RATIO · STANDARD · R.F. (ANTENNA) (FOR FREQ. SYNTH.) · VIDEO (SCART & CINCH) · COLOUR (MAX. THREE STANDARDS) · SOUND STANDARD: MONO STEREO TUNING SYSTEM SELECTABLE : FREQUENCY SYTHETIZER · TOTAL AVAILABLE CHANNEL NUMBER · CHANNEL IN ONE RF STANDARD UP TO · NUMBER OF PROGRAM · DIRECT PROGRAM & CHANNEL CALL WITH · PROGRAM & CHANNEL STEP UP AND DOWN · VOLTAGE SYNTHESISER · CABLE & HYPERBAND CHANNEL · SWITCHABLE AFC · AUTOMATIC SEARCH TUNING · A S T WITH AUTO SORT 21" / 25" / 28" / 29" / 34" 28 " / 32" CCIR ( B / G/ L / L' / D / K / I ) B / G/ L / L' / D / K / I / M / N PAL / SECAM / NTSC B / G/ L / L' / D / K / I AM & FM A2 OR NICAM FACTORY OPTION 200 100 100 1, OR 2 OR 3 DIGIT YES YES YES YES YES

AUDIO SECTION
POWER · MONO · STEREO EXTERNAL CONNECTION · HEADPHONE · LOUDSPEAKERS A / V INPUT / OUTPUT · FRONT PANEL CINCH · I FULL SCART (CVBS, STEREO, RBA) · SCART (CVBS & STEREO IN / OUT) · SCART A TO SCART B LOOP THROUGH TXT · LEVEL 1 · LEVEL 1,5 (FASTEXT) FEATURES · CTI (COLOUR TRANSIENT IMPROVEMENT) · 16:9 TO 4:3 VIDEO COMPRESSION · VERTICAL ZOOM OUT · MENU DRIVEN SYSTEM · EASY TO USE REMOTE CONTROL · REMOTE CONTROL WITH "SERVICE" USE · PIP E.G.Data creazione 31/10/99 15.38 2/7 6 W RMS. 2 x 6 W RMS. STEREO SET ONLY INTERNAL L.S. SWITCHED A / V INPUT MULTIMEDIA INPUT OUTPUT VCR, HI.FI, SATELLITE, ETC FOR PROGRAMS DUBBING PANEUROPEAN CHARACTER SET 8 PAGES 7 PAGES OPTION ONLY FOR 16:9 TV SET 3 LEVEL

NOT ACCESSIBLE TO END USER OPTION f19intro

AUDIO

TD A9 87 5

AUDIO TDA1521

THIS MODULE IS PRESENT ONLY FOR STEREO SET
AUDIO AUDIO VIDEO & AUDIO

EEPROM PCF8582
TUNER

2ND SCART
A/V IN/OUT

SCART INTER.
A /V OUT A/V IN

FULL SCART
RGB

TD A 84 4X

PLL

SAW FILTER

VIDEO PROCESSOR

RGB VIDEO AMPL. RGB (OSD) TDA5112

TDA 8362A
D.L. CROMA TDA4661

IIC bus MICRO

CUT-OFF

V.

SA A 52 97 A

PCA84C841/210

SECAM TDA8395

VERTICAL TDA3654

RGB

110°

TXT

SAA5281/....

TXT & OSD RBG
H. DRIVER

E.W. GEN. TDA4950
L.O.T.
BU 508 D

H.
EHT TRAFO EAT

T.O.P. PHILIPS

BC 639
POWER SUPPLY TDA 460

140 V 26 V 15 V 12 V F16UPF19.DRW E.G. 2/02/99

5

& STH7N80F

PIP SIEMENS

PIP (RGB)

8V

F16 UPDATED F19

BLOCK DIAGRAM

AUDIO STEREO (NICAM) PROCESSOR TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)

2x7W
AUDIO POWER

F 19
EEPROM PCF8584 / ST2404CB TUNER PLL IIC bus

V I D E O A U D I O I. F.

TDA1521

THIS MODULE IS PRESENT ONLY FOR STEREO SET
I N T E R C A R R I E R AUDIO VIDEO & AUDIO

AUDIO

AUDIO SCART SWITCH HEF4053 VIDEOSCART SWITCH LA7955
A/V IN

HEADPHONE LINE OUT (OPTION)

2ND SCART
A/V IN/OUT A /V OUT

FULL SCART
A/V/ CINCH (OPTION)

RGB

IIC BUS ONE CHIP VIDEO PROCESSOR
SAW FILTER

RGB

VIDEO AMPL. TDA5112

TDA 8843 (4)
*IF VIDEO & PLL DEM *AGC & AFC, MUTE *AUDIO PLL DEM *PAL/NTSC (SECAM) DEC. *B.B CHROMA DELAY LINE *FULL SCART INTERFACE. UV *H & V SYNC PROCESSIG *FULL IIC BUS CONTROLL FOR: *AUTO CUT-OFF *ALL ANALOGUE FUCTIONS *GEOMETRY CORRECTION *FEATURES INTERFACE E-WE-W POWER BUK474200A H DRIVE

CUT-OFF
E-W LOAD COIL

RGB
VERTICAL FEEDBACK

IIC bus

LOCAL KEY BOARD

CRT
V.

ETT

4

FEATURES MODULE TDA4566 (CTI) SAA4981 (16:9 TO 4:3)

VERTICAL TDA8351

110°

SAA5297A
IIC bus MICROCONTROLLER & TELETEX 8 PAGES TXT & OSD RBG

OPTION
H. DRIVER

E-W DRIVE COIL

H.
H. DEFL. &EHT TRAFO EAT

PIP
OPTION

BC 338 I.R. INPUT PIP (RGB) POWER SUPPLY TDA 4605 & STH7N90F1

DRIVER TRAFO 150 V 26 V 12 V 8V 5V

L.O.T. BU 508 D

F19 BLOCK DIAGRAM

F19BLDIA.DRW E.G. 17 / 7 / 99

AUDIO STEREO (NICAM) PROCESSOR TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)
V I D E O A U D I O I. F.

2x7W
AUDIO POWER

TDA1521

F 19.1
EEPROM PCF8584 / ST2404CB TUNER PLL IIC bus

THIS MODULE IS PRESENT ONLY FOR STEREO SET
I N T E R C A R R I E R

AUDIO
VIDEO & AUDIO

AUDIO

AUDIO SCART SWITCH HEF4053 VIDEOSCART SWITCH LA7955
A/V IN

HEADPHONE LINE OUT (OPTION)

2ND SCART
A/V IN/OUT A /V OUT

FULL SCART
A/V/ CINCH (OPTION) RGB

IIC BUS ONE CHIP VIDEO PROCESSOR
SAW FILTER

RGB

VIDEO AMPL. TDA5112

TDA 8843 (4)
*IF VIDEO & PLL DEM *AGC & AFC, MUTE *AUDIO PLL DEM *PAL/NTSC (SECAM) DEC. *B.B CHROMA DELAY LINE *FULL SCART INTERFACE. UV 4 *H & V SYNC PROCESSIG *FULL IIC BUS CONTROLL FOR: *AUTO CUT-OFF *ALL ANALOGUE FUCTIONS *GEOMETRY CORRECTION *FEATURES INTERFACE E-WE-W POWER BUK474200A H DRIVE

CUT-OFF
E-W LOAD COIL

RGB
VERTICAL FEEDBACK

IIC bus LOCAL KEY BOARD

CRT
V.

ETT
IIC bus

FEATURES MODULE TDA4566 (CTI) SAA4981 (16:9 TO 4:3)

SAA5297A or SAA5553M3
MICROCONTROLLER & 8 PAGES TELETEXT TXT & OSD RBG

VERTICAL TDA8351

110°

H.
E-W DRIVE COIL

OPTION
H. DRIVER

PIP
OPTION

BC 338

DRIVER TRAFO 150 V

I.R. INPUT PIP (RGB) POWER SUPPLY TDA 4605 & STH7N90F1 26 V 12 V 8V 5V

L.O.T. BU 508 D

H. DEFL. &EHT TRAFO EAT

F19.1 BLOCK DIAGRAM

F19BDE&P.DRW E.G. 22/04/2000

F19

TUNING & TELETEXT

SAA529XA FAMILY MAIN CHARACTERISTICS

FEATURES

General · · · · · Single chip microcontroller with integrated teletext decoder Single +5 V power supply Single crystal oscillator for teletext decoder, display and microcontroller Teletext function can be powered-down independent of microcontroller function for reduced power consumption in standby Pin compatibility throughout family.

Microcontroller · · · · · · · · · 80C51 microcontroller core 16/32/64 kbyte mask programmed ROM 256/768/1280 bytes of microcontroller RAM Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals One 14-bit PWM for Voltage Synthesis Tuner control Four 8-bit Analog-to-Digital converters 2 high current open-drain outputs for directly driving LEDs etc. I 2 C-bus interface External ROM and RAM capability on QFP80 package version.

Teletext acquisition · · · · · · · 1 page and 10 page Teletext version Acquisition of 525-line and 625-line World System Teletext, with automatic selection Acquisition and decoding of VPS data (PDC system A) Page clearing in under 64 s (1 TV line)

Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7) Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) end Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7) Automatic detection of FASTEXT transmission 8 / 30 F19MANU.doc

E.G.Data creazione 01/11/99 17.27

SAA5297A
TO CURRENT INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD. SWITCH CTI DETECTOR 16 : 9 DETECTOR SCART1 / SCART2 SWITCH SCART 1 / TV TO SCART 2 SWITCH FRONT CINCH / SCART1 SWITCH SCART 1 INPUT DETECTOR SCART 2 INPUT DETECTOR HEAD PHONES DETECTOR STANDARD SWITCH

MICRO & TXT Block Diagram
ROM RAM TIMER

UHF SUPPLY (VOLTAGE SINTESYS ONLY) TV / AV SWITCH

MENU V - V + P -

P+

LOCAL KEY BOARD
TV ON / OFF SWITCH TUNER SUPPLY (V.S. ONLY) TUNER SUPPLY(V.S. ONLY)

CVBS FROM ANTENNA CVBS FROM SCART SAA5297A.DRW E.G . 17 / 10 / 99 DATA SLICER REF.PIN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V TUN. DSC SWT. L/L' CTI STS. 16:9 STS SWT. S1/S2 COPY SWT. SWT. CI/S1 AV1 STS. AV2 STS. H.P. STS. SYSTEM VSS M+T UHF TV / AV P0.3 P0.4 P0.5 ON / OFF VHF H VHF L VSSA CVBS0 CVBS1 BLACK IREF

P O R T 2

A/ D

P O R T 3

PWM

B U S

D TI ISP M LA IN Y G

P O R T 0

TXT INT

PAGE RAM

T X T DATA SLICER & ACQUISITION

SWT 16:9 P OSC. SWT. O MSDA R MSCL T SDA 1 1 INTO SCL 1 AM/FM 8051 VDDM CORE RESET OSCOUT OR OSCIN AT LL CI OSCGND OS VDDT VDDA VSYNC HSYNC BLK R G B RGBREF PIP STS INT. TEST FRAME

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TO CHANGE ASPECT RATIO TO SWITCH S.C. FROM 4.43 TO 3.58 MHz

MAIN IIC BUS

I.R.

IIC BUS FOR EEPROM

SOUND STANDARD SWITCH 5 V from ST-BY FROM RESESET CIRCUIT

QZ100 12 MHz 5V
VERTICAL FLYBACK HORIZONTAL FLYBACK PULSE

TO TDA884X
RGB REFERENCE

DI SP LA Y

2,5 VVOLTAGE
PIP DETECTOR NOT CONNECTED

NOT CONNECTED

SAA5553M3
TO CURRENT INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD. SWITCH CTI DETECTOR 16 : 9 DETECTOR SCART1 / SCART2 SWITCH SCART 1 / TV TO SCART 2 SWITCH FRONT CINCH / SCART1 SWITCH SCART 1 INPUT DETECTOR SCART 2 INPUT DETECTOR HEAD PHONES DETECTOR STANDARD SWITCH

MICRO & TXT Block Diagram
RAM TIMER
P O R T 1

UHF SUPPLY (VOLTAGE SINTESYS ONLY) TV / AV SWITCH

MENU V - V + P -

P+

LOCAL KEY BOARD
TV ON / OFF SWITCH TUNER SUPPLY (V.S. ONLY) TUNER SUPPLY(V.S. ONLY)

CVBS FROM ANTENNA CVBS FROM SCART DATA SLICER REF.PIN

SAA5553.DRW E.G 22/ 04 / 2000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V TUN. DSC SWT. L/L' CTI STS. 16:9 STS SWT. S1/S2 COPY SWT. SWT. CI/S1 AV1 STS. AV2 STS. H.P. STS. SYSTEM VSS M+T UHF TV / AV P0.3 P0.4 P0.5 ON / OFF VHF H VHF L VSSA CVBS0 CVBS1 BLACK IREF

ROM
P O R T 2

A/ D

P O R T 3

PWM

B U S

8051 CORE
OR AT L IL SC O

DI TI SP M LA IN Y G

P O R T 0

TXT INT

PAGE RAM

T X T DATA SLICER & ACQUISITION

SWT 16:9 OSC. SWT. MSDA MSCL SDA 1 INTO SCL 1 AM/FM VDDM RESET OSCOUT OSCIN OSCGND VDDT VDDA VSYNC HSYNC BLK R G B RGBREF PIP STS INT. TEST FRAME

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TO CHANGE ASPECT RATIO TO SWITCH S.C. FROM 4.43 TO 3.58 MHz

MAIN IIC BUS I.R.
IIC BUS FOR EEPROM

SOUND STANDARD SWITCH 5 V from ST-BY FROM RESESET CIRCUIT

QZ100 12 MHz 3V
VERTICAL FLYBACK HORIZONTAL FLYBACK PULSE

TO TDA884X
RGB REFERENCE

DI SP LA Y

2,5 V VOLTAGE
PIP DETECTOR NOT CONNECTED

NOT CONNECTED

· · ·

Real-time packet 26 engine for processing accented (and other) characters Comprehensive Teletext language coverage Video signal quality detector.

Teletext Display · · · · · · · · · 525-line and 625-line display 12 10 character matrix

Double height, width and size On-Screen Display (OSD) Definable border colour Enhanced display features including meshing and shadowing 260 characters in mask programmed ROM Automatic FRAME output control with manual override RGB push-pull output to standard decoder ICs Stable display via slave synchronisation to horizontal sync and vertical sync.

Additional features of SAA529xA devices · Wide Screen Signalling (WSS) bit decoding (line 23).

2 GENERAL DESCRIPTION The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the Philips' industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system and include an integrated teletext function. The teletext hardware has the capability of decoding and displaying both 525-line and 625line World System Teletext. The same display hardware is used both for Teletext and OnScreen Display, which means that the display features give greater flexibility to differentiate the TV set. The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes. Increasing display capability is offered from the SAA5290 to the SAA5497.

TELETEXT DECODER Data slicer E.G.Data creazione 01/11/99 17.27 9 / 30 F19MANU.doc

The data slicer extracts the digital teletext data from the incoming analog waveform. This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock. Acquisition timing The acquisition timing is generated from a logic level positive-going composite sync signal VCS. This signal is generated by a sync separator circuit which adaptively slices the sync pulses. The acquisition clocking and timing are locked to the VCS signal using a digital phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected. Teletext acquisition This family is capable of acquiring 625-line and 525-line World System Teletext see "World System Teletext and Data Broadcasting System". Teletext pages are identified by seven numbers: magazine (page hundreds), page tens, page units, hours tens, hours units, minutes tens and minutes units. The last four digits, hours and minutes, are known as the subcode, and were originally intended to be time related, hence their names. For the ten page device, each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up each page request defaults to any page, hold on and error check Mode 0. Rolling headers and time When a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found. Error checking Before teletext packets are written into the page memory they are error checked. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data the byte is not written into the memory. E.G.Data creazione 01/11/99 17.27 10 / 30 F19MANU.doc

Packet 26 processing One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. Fastext detection When a packet 27, designation code 0 is detected, whether or not it is acquired, the TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit. When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the SFR bit. THE DISPLAY Introduction The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on screen displays. The display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is displayed at the top of the screen, followed by row 0, but normally memory rows are displayed in numerical order. The teletext memory stores 8 bit character codes which correspond to a number of displayable characters and control characters, which are normally displayed as spaces. The character set of the device is described in more detail below.

E.G.Data creazione 01/11/99 17.27

11 / 30

F19MANU.doc

(OPTION BYTE 1 BIT 3 SETTED TO 0
EAST EUROPE
CHARACTER SET NATIONAL OPTION FOR:

POLISH GERMAN ESTONIAN SERBO-CROAT CZECH SLOVAKIA RUMANIAN WEST EUROPE
CHARACTER SET NATIONAL OPTION FOR:

WEST ENGLISH GERMAN SWEDISH ITALIAN FREANCH SPANISH TURKISH

EAST

D A

PL CZ H Y

R

(OPTION BYTE 1 BIT 6 SETTED TO 1

F19 E&WCS.DRW E.G. 7/11/99

Character matrix Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed, each pixel is 1 12 s wide and 1 TV line, in each field, high.

East/West selection In common with their predecessors, these devices store teletext pages as a series of 8 bit character codes which are interpreted as either control codes (to change colour, invoke flashing etc.) or displayable characters. When the control characters are excluded, this gives an addressable set of 212 characters at any given time.

National option characters The meanings of some character codes between 20H and 7FH depend on the C12 to C14 language control bits from the teletext page header. The interpretation of the C12 to C14 language control bits is dependent on the East/West bit. On-Screen Display characters Character codes 80H to 9FH are not addressed by the teletext decoding hardware. An editor is available to allow these characters to be redefined by the customer. The

alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when the `graphics' serial attribute is set. This increases the number of customer definable characters to 64. Clock generator The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator circuitry. It is operated in parallel resonance. XTALIN is the high gain amplifier input and XTALOUT is the output. To drive the device externally XTALIN is driven from an external source and XTALOUT is left open-circuit.

E.G.Data creazione 01/11/99 17.27

12 / 30

F19MANU.doc

12 V

SOUND I.F. AM SOUND FILTER F204 12V TR218

TUNUNG VOLTAGE TO PIN 2 TR500 TUNER

SAA5297A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MICRO & TXT PERIPHERALS
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
TO CTI & 16:9 MOULE TR 109 TR 208 4.43 MHz

TO X13

TR219 5V

R174

CVBS PIN 6 IC 204
TO PIN 10, 11 IC 200

TO PIN 4 IC 201 TO PIN 8 IC 201

R128 R140 R141

TR200

TR110 TR201 F575 5V TO PIN 1 IC 204 F576 TR210 TR111 TR107 TO STEREO NICAM MODULE TO SWITC INT/EX SOUND R146 TR209 FRON PIN 8 SCART 1 FROM PIN 8 SCART 2

MENU V - V + P -

P+

TO PIN 4 IC 10

TR2

TV ON / OFF

TR 502 PIN 5 CVBS FROM ANTENNA TR 501 PIN 3 TR203

T O T U N E R PIN 4

TR503

CVBS FROM SCART TR211

5V

V TUN. SWT 16:9 OSC. SWT. DSC SWT. L/L' MSDA MSCL CTI STS. SDA 1 16:9 STS SWT. S1/S2 INTO COPY SWT. SCL 1 SWT. CI/S1 AM/FM VDDM AV1 STS. AV2 STS. RESET H.P. STS. OSCOUT OSCIN SYSTEM VSS M+T OSCGND VDDT UHF VDDA TV / AV VSYNC P0.3 HSYNC P0.4 BLK P0.5 R ON / OFF G VHF H B VHF L RGBREF VSSA PIP STS CVBS0 COR CVBS1 BLACK INT. TEST FRAME IREF

TR206 IIC BUS 3.58MHz TR 205 TO PIN 35 IC 204

IRR100

IIC BUS

EEPROM IC 101
TO PIN 10 IC 102 TR 105

SOUND STDANDARD SWITCH

TR 108

5V ST-BY

QZ100 12 MHz
R 106

D 105

5V
D 102 FLYBACK PULSE FROM EHT VERTICAL BLANKING FROM PIN 8 IC 5

D 108

TR 101 TR 102 TR 103 5V R167

TO PIN 23, 24, 25 IC 204

F19MTPER.DRW E.G. 24 /10 /99 FOR VOLTAGE SISTETIZER ONLY

12 V

SOUND I.F. AM SOUND FILTER F204 12V CVBSPIN 6 IC 204 TO PIN 10, 11 IC 200 TR218

TUNUNG VOLTAGE TO PIN 2 TUNER

TR500

SAA 5553 MICRO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

& TXT PERIPHERALS
TO CTI & 16:9 MOULE TR 109 TR 208 4.43 MHz

TO X13

TR219 5V

R174

TO PIN 4 IC 201 TO PIN 8 IC 201 TR110

R128 R140 R141

TR200 TR201 F575

FRON PIN 8 SCART 1 FROM PIN 8 SCART 2 5V

TO PIN 1 IC 204 F576 TR210

R146 TR209 TR111

TR107 TO STEREO NICAM MODULE

TO SWITC INT/EX SOUND

MENU V - V + P -

P+

TO PIN 4 IC 10

TR2

TV ON / OFF

TR 502

PIN 5
T O T U N E R PIN 4 PIN 3 TR 501

CVBS FROM ANTENNA TR203

TR503

CVBS FROM SCART TR211 5V

V TUN. SWT 16:9 DSC OSC. SWT. SWT. L/L' MSDA MSCL CTI STS. SDA 1 16:9 STS SWT. S1/S2 INTO COPY SWT. SCL 1 SWT. CI/S1AM/FM AV1 STS. VDDM AV2 STS. RESET H.P. STS. OSCOUT SYSTEM OSCIN VSS M+T OSCGND VDDT UHF VSSA TV / AV VSYNC P0.3 HSYNC P0.4 BLK P0.5 R ON / OFF G VHF H B VHF L RGBREF VSSA PIP STS CVBS0 COR CVBS1 BLACK INT. TEST FRAME IREF

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TR206 IIC BUS 3.58MHz

TR 205

TO PIN 35 IC 204

IRR100

IIC BUS

EEPROM IC 101
TO PIN 10 IC 102 TR 105

SOUND STDANDARD SWITCH 3,3 V

TR 108
TR8

5V
R39 R40

QZ100 12 MHz

D 105

3,3 V 5V D 108 D 102

TR7 D5 2,5V FLYBACK FROM EHT VERTICAL BLANKING FROM PIN 8 IC 5 TO PIN 23, 24, 25 IC 204

TR 101 TR 102

TR 103
5V R167 F19PAPER.DRW E.G. 22 / 04 /2000 FOR VOLTAGE SISTETIZER ONLY

PAINTER

VIDEO SIGNAL PROCESSING

FOR VOLTAGE SINTHESIS ONLY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SIF AUDEXT NC NC PLLIF IFVIDEO OUT SCL SDA DECOUPLING CHR.IN EX.CVBS/Y IN VP1 INT CVBS IN GND AUDIO OUT DECOUPLING EX. CVBS IN BLKIN B OUT G OUT R OUT BCL/VG R IN G IN B IN RGB INSERT. Y IN Y OUT

TR500 UV 1 2 3 4 5 6 7 8 9 10 11 UHF

TDA884X
I.F. VIDEO AGC AFC DEM. IDENT

EF

EF
TR200 IIC

F 19
TO PIN 33 IC100 CVBS EF FOR TXT TR203 TO PIN 24 IC 100 (CVBS FOR TXT) TO PIN 9 IC 100 AV1 STATUS 19 8 15 11 7 16 20

TR201

MSD PAL (SECAM) NTSC

TR202

EF
VIDEO IN CINCH

SOUND PROCES. (MONO)

C.D. & RGB MATRIX VIDEO CONTROL

EF
TR204

SYNC PROCES. V. & H. TIME BASE

EXT RGB SWITCH & RGB DRIVE

SCART 1

IIC
TRANSRECEIVER

DECOUPLING DEENPHASIS AGC OUT DECOPLING I REF VERT. RAMP EHT PROTEC. IF IN 2 IF IN 1 V. DRIVE A V. DRIVE B E - W OUT GND 2 PH. 1 FILTER PH. 2 FILTER H. IN, S.C. OUT HOR. OUT DECOUPLING CVBS 1 OUT VP2 DET FILTER X TAL 2 X TAL 1 S.C. REF OUT R - Y IN B - Y IN R - Y OUT B - Y OUT

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

FROM PIN 1 IC 100 TR501 5V

TR503

IIC

VHF H VHF L TR502

FROM IC 100 PIN 14, 20, 21 BAND SWITCHING TR105

TR208 3.58MHz 8V 4.43MHz 3,57MHz FROM PIN 51 IC 100 TR205 TR206

A10
1 2 3 4 5

CTI & 4:3 TO 16 : 9

12 V TR211

EF
FROM PIN 6 IC100 AV1 / AV2 SWITCH CVBS IN TV CVBS FROM PIN 7 IC100 AV1 / TV SWITCH TO AV2 3 2 TO PIN 10 IC 100 AV2 STATUS 7 8 9 12 V 4 1 6 5 TR212 CVBS OUT

EF
5V

EF
SCART 2 8 20 19

RGB AMPLIFIER MODULE

6 7 8 9 10 11 12

1/3 0F IC201 LA7955
CVBS IN

FROM PIN 52 IC 100 4:3 TO 16:9 SWITCH

TO CRT
8V

FROM EHT

VIDEO SIGNAL PATH

F19VIDEP.DRW E.G. 14 / 11 / 99

Reset signal The externally applied RESET signal (active HIGH) is used to initialize the microcontroller core, in addition to the teletext decoder. However, the teletext decoder incorporates a separate internal reset function which is activated on the rising edge of the analog supply pin, VDDA . The purpose of this internal reset circuit is to initialize the teletext decoder when returning from the "text standby mode".

TDA884X FAMILY SPECIFICATION
FEATURES

The following features are available in all IC's: · Multi-standard vision IF circuit with an alignment-freePLL demodulator without external components · Alignment-free multi-standard FM sound demodulator(4.5 MHz to 6.5 MHz) · Audio switch · Flexible source selection with CVBS switch andY(CVBS)/C input so that a comb filter can be applied · Integrated chrominance trap circuit · Integrated luminance delay line · Asymmetrical peaking in the luminance channel with a(defeatable) noise coring function · Black stretching of non-standard CVBS or luminancesignals · Integrated chroma band-pass filter with switchablecentre frequency · Dynamic skin tone control circuit · Blue stretch circuit which offsets colours near whitetowards blue · RGB control circuit with "Continuous CathodeCalibration" and white point adjustment · Possibility to insert a "blue back" option when no videosignal is available · Horizontal synchronization with two control loops andalignment-free horizontal

oscillatoroptimised N2 application.Functionally the IC series is split up is 3 categories, viz:

E.G.Data creazione 01/11/99 17.27

13 / 30

F19MANU.doc

CVBS OUT CVBS (int) IN CVBS / Y IN (comb filter) CVBS OUTPUT CVBS (ext) IN CHROMA IN

Secam Decoupling SCL SDA

Xtal 34 35 36 33 28 29
BASE BAND CHROMA DELAY LINE

Loop filter Phase Detector

6
TUNER AGC

13

17

11
CVBS & Y/C SWITCH

10

38

7

8

54 53 48

IF & TUNER A G C

TUNER T.O.P gating calibration I.F. value IIC TRANSRECEIVER

16

BURST PHASE DETECTOR & VCXO
Subcarrier

IIC
I.F IN PLL FILTER VIDEO IF AMPLIFIER PLL DEMOD. & VCO MOD Pos./Neg. VIDEO AMPLIFIER Luma Y DELAY, C. TRAP, Y PEAKING Chroma CHROMA CLOCHE & BANDPASS

Fsc Y B-Y R-Y Y B-Y R-Y R G B F.B.
Black O Currente U Input T R P U G T I N P U T

49
Sensitivity

5
A F W AFA AFB AFC

To Sync

PAL / NTSC SECAM DECODER
GAI AUTO SYSTEM IDENT. MANAGER V. sync

30 27 31 32 23 24 25 26 18

H. SYNC
SEPARATOR

V . SYNC
SEPARATOR

SAT

MAT

TDA 8844
55
Deenphasis DEENPHASIS LINE Internal Audio EXTERNAL AUDIO SWITCH SWT MONO AUDIO OUTPUT

H. sync VIDEO IDENT. VIDEO MUTE

DSA VERTICAL DEVIDER

PHI 1
DETECTOR

R-Y & B-Y MATRIX SAT CONTR. BLACK STRETCH SKIN TINT CORR. RGB SWITCH

AVL

CON
AUDIO PRE AMPLIFIER & MUTE

2
EXTERNAL AUDIO IN

AVL
SWITCH & VOLUME Volume

LINE
OSCILL.

VERTICAL SAWTOOTH GENERATOR

A.F.
AVL Decoupling

15 (45) 1

RGB CONTROL AUTO CUT-OFF & OUTPUT BRI

19 20 21 47

B Vertical Drive Output

INTERCARRIER IN BandGap Decoupling

1 A 10 MHz B.P.F.

AUDIO LIMITER

AUDIO PLL DEM.

PHI 2 LINE OUT S.C. GENER.

E-W GEOMETRY

VERTICAL DRIVE

46

9

12
8 V Main Supply

37
8V Supply

14
Ground

56
Sound Decoupling

43

42
Phi 2 filter

41

40

51

52

45

50
EHT Overvoltage

22
V- Guard & B.C. limiter TDA8844BLDIA.DRW E.G. 17 /10 / 99

Phi 1 filter

Flyback in Line E-W Sand Pulse DRIVE Vertical Castle Out Sawtooth Reference Out

· Versions intended to be used in economy TV receiverswith all basic functions (envelope: S-DIP 56 and QFP 64) · Versions with additional features like E-W geometrycontrol, H-V zoom function and YUV interface which are intended for TV receivers with 110° picture tubes(envelope: S-DIP 56) · Versions which have in addition a second RGB inputwith saturation control and a second CVBS output (envelope: QFP 64) · Vertical count-down circuit · Vertical driver optimised for DC-coupled vertical outputstages
GENERAL DESCRIPTION

The various versions of the TDA 884X/5X series areI 2 C-bus controlled single chip TV processors which are intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers. The N2 version is pin and application compatible with the N1 version, however,a new feature has been added which makes the N2 more attractive. The IF PLL demodulator has been replaced byan alignment-free IF PLL demodulator with internal VCO (no tuned circuit required). The setting of the variousfrequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz) can be made via the I 2 C-bus. Because of this difference the N2 version is compatiblewith the N1, however, N1 devices cannot be used in an optimized N2 application Functionally the IC series is split up is 3 categories, viz: · Versions intended to be used in economy TV receivers with all basic functions (envelope: S-DIP 56 and QFP 64) · Versions with additional features like E-W geometry control, H-V zoom function and YUV interface which areintended for TV receivers with 110° picture tubes (envelope: S-DIP 56) · Versions which have in addition a second RGB input with saturation control and a second CVBS output (envelope: QFP 64)

FUNCTIONAL DESCRIPTION Vision IF amplifier

The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern E.G.Data creazione 01/11/99 17.27 14 / 30 F19MANU.doc

IF-IC's. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internalVCO. This VCO is calibrated by means of a digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 Cbus. To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital control circuit of the IF-PLL demodulator and can be read via the I 2 C-bus. For fast search tuning systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW bit. The AFC data is valid only when the horizontal PLL is in lock (SL = 1) Depending on the type the AGC-detector operates on top-sync level (single standard versions) or on top sync and top white- level (multi standard versions). The demodulation polarity is switched via the I 2 C-bus. The AGC detector time-constant capacitor is connected externally. This mainly because of the flexibility of the application. The timeconstant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 field periods no action detected the speed of the system is increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode. The circuits contain a video identification circuit which is independent of the synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a reliable search system. The ident output is supplied to the tuning system via the I 2 C-bus. The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the "internal" CVBS input (see Fig.6). This has the advantage that the ident circuit can also be made operative when a scrambled signal is received (descrambler connected between pin 6 (IF video output) and pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners). E.G.Data creazione 01/11/99 17.27 15 / 30 F19MANU.doc

The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit.
Video switches

The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When the Y/C input is not required the Y input can be used as third CVBS input. The switch configuration is given in Fig.6. The selection of the various sources is made via the I 2 Cbus. For the TDA 884X devices the video switch configuration is identical to the switch of the TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the TDA884X series) and the I 2 C-bus control is similar to that of the TDA 8374/75. For the TDA 885X IC's the video switch circuit has a second output (amplitude of 1 VP-P ) which can be set independently of the position of the first output. The input signal for the decoder is also available on the CVBS1-output. Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again.
Sound circuit

The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so that no adjustment is required. The volume is controlled via the I 2 C-bus. The deemphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin (via a buffer stage). The FM demodulator can be muted via the I 2 C-bus. This function can be used to switchoff the sound during a channel change so that high output peaks are prevented. The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which automatically stabilises the audio output signal to a certain level which can be set by the viewer by means of the volume control. This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. The AVL function can be activated via the I 2 C-bus.
Synchronisation circuit

E.G.Data creazione 01/11/99 17.27

16 / 30

F19MANU.doc

The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals. The first PLL has a very high statical steepness so that the phase of the picture is independent of the line frequency. The horizontal output signal is generated by means of an oscillator which is running at twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched-on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. To protect the horizontal output transistor the horizontal drive is immediately switched off when a power-on-reset is detected. The drive signal is switched-on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and after calibration the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. Via the I 2 C-bus adjustments can be made of the horizontal and vertical geometry. The vertical sawtooth generator drives the vertical output drive circuit which has a differential output current. For the E-W drive a single ended current output is available. A special E.G.Data creazione 01/11/99 17.27 17 / 30 F19MANU.doc

feature is the zoom function for both the horizontal and vertical deflection and the vertical scroll function which are available in some versions. When the horizontal scan is reduced to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen. Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched-off via the slow stop procedure but it is also possible that the drive is not switched-off and that just a protection indication is given in the I 2 C-bus output byte. The choice is made via the input bit PRD. The IC's have a second protection input on the 2 filter capacitor pin. When this input is activated the drive signal is switched-off immediately and switched-on again via the slow start procedure. For this reason this protection input can be used as "flash protection". The drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals the maximum vertical frequency is increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency like VGA. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit. The vertical deflection can be set in the deinterlace mode via the I 2 C bus. To avoid damage of the picture tube when the vertical deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is connected thisguard circuit will also blank the output signals. This can be overruled by means of the EVG bit.
Chroma and luminance processing

The circuits contain a chroma bandpass and trap circuit. The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the X-tal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for

E.G.Data creazione 01/11/99 17.27

18 / 30

F19MANU.doc

"front-end" signals and external CVBS signals. During SECAM reception the centre frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier frequencies. All IC's have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). The timeconstant for the black stretcher is realised internally. The resolution of the peaking control DAC has been increased to 6 bits. All IC's have a defeatable coringfunction in the peaking circuit. Some of these IC's have a YUV interface (see table on page 2) so that picture improvement IC's like the TDA 9170 (Contrast improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be applied. When the CTI IC's are applied it is possible to increase the gain of the luminance channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals are not affected.
Colour decoder

Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal oscillator, a killer circuit and two colour difference demodulators. The 90° phase shift for the reference signal is made internally. The IC's contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I 2 C-bus and which prevents that oversaturation occurs when signals with a high chroma-toburst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune an external comb filter (e.g. the SAA 4961). The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM IC's and in the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance (chroma comb filter). The demodulated colour difference signals are internally supplied to the delay line. The colour difference matrix switches automatically between PAL/SECAM and NTSC, however, it is also possible to fix the matrix in the PAL standard. E.G.Data creazione 01/11/99 17.27 19 / 30 F19MANU.doc

The "blue stretch" circuit is intended to shift colour near "white" with sufficient contrast values towards more blue to obtain a brighter impression of the picture. Which colour standard the IC's can decode depends on the external X-tals. The X-tal to be connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency is used to tune the line oscillator the value of the X-tal frequency must be given to the IC via the I 2 C-bus. It is also possible to use the IC in the so called "Tri-norma" mode for South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin 35. The switching between the 2 latter X-tals must be done externally. This has the consequence that the search loop of the decoder must be controlled by the µ-computer. To prevent calibration problems of the horizontal oscillator the external switching between the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so that the software can check the I 2 C-bus transmission. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in the control-5 subaddress. The IC's contain a so-called "Dynamic skin tone (flesh) control" feature. This function is realised in the YUV domain by detecting the colours near to the skin tone. The correction angle can be controlled via the I 2 C-bus.
RGB output circuit and black-current stabilisation

The colour-difference signals are matrixed with the luminance signal to obtain the RGBsignals. The TDA 884X devices have one (linear) RGB input. This RGB signal can be controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the insertion pin has a high level or not. The TDA 885X IC's have an additional RGB input. This RGB signal can be controlled on contrast, saturation and brightness. The insertion blanking of this input can be switched-off by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high level or not.

E.G.Data creazione 01/11/99 17.27

20 / 30

F19MANU.doc

The output signal has an amplitude of about 2 volts black-to-white at nominal input signals and nominal settings of the controls. To increase the flexibility of the IC it is possible to insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64 envelope). This blanking action at the RGB outputs has some delay which must be compensated externally. To obtain an accurate biasing of the picture tube a "Continuous Cathode Calibration" circuit has been developed. This function is realised by means of a 2-point black level stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting cathode currents with 2 different reference currents the influence of the picture tube parameters like the spread in cut-off voltage can be eliminated. This 2-point stabilisation is based on the principle that the ratio between the cathode currents is coupled to the ratio between the drive voltages according to:

[ I ki / Ik2 ] = [ Vdr1 / Vdr2 ]
The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the ratio between the reference currents (which are internally fixed) by changing the (black) level and the amplitude of the RGB output signals via 2 converging loops. The system operates in such a way that the black level of the drive signal is controlled to the cut-off point of the gun so that a very good grey scale tracking is obtained. The accuracy of the adjustment of the black level is just dependent on the ratio of internal currents and these can be made very accurately in integrated circuits. An additional advantage of the 2-point measurement is that the control system makes the absolute value of Ik1 and Ik2 identical to the internal reference currents. Because this adjustment is obtained by means of an adaption of the gain of the RGB control stage this control stabilises the gain of the complete channel (RGB output stage and cathode characteristic). As a result variations in the gain figures during life will be compensated by this 2-point loop. An important property of the 2-point stabilisation is that the off-set as well as the gain of the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the cathode is fixed by the relation between the test pulses, the reference current and the relative gain setting of the 3 channels. This has the consequence that the drive level of the CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different picture tubes may require different drive levels the typical "cathode drive level" amplitude can be adjusted by means of an I 2 C-bus setting. Dependent on the chosen cathode drive E.G.Data creazione 01/11/99 17.27 21 / 30 F19MANU.doc

level the typical gain of the RGB output stages can be fixed taking into account the drive capability of the RGB outputs (pins 19 to 21). More details about the design will be given in the application report. The measurement of the "high" and the "low" current of the 2- point stabilisation circuit is carried out in 2 consecutive fields. The leakage current is measured in each field. The maximum allowable leakage current is 100 µA When the TV receiver is switched-on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels. Via the AST bit a choice can be made between automatic start-up or a start-up via the µ-processor. In the automatic mode the RGB drive signals are switched-on as soon as the black current loop has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised. The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mod some delay can be introduced between the setting of the BCF bit and the switching of the AST bit so that switch-on effects can be suppressed. It is also possible to start-up the devices with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is activated with the BCO bit. The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking can be increased to the same value as that of the 50 Hz blanking. This can be set by means of the LBM bit. For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When this bit is activated the black current loop is switched-off, a fixed black level is inserted at the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the different requirements for the optimum cut-off voltage of the picture tube the RGB output level is adjustable when the VSD bit is activated. The control range is 2.5 ± 0.7 V and can be controlled via the brightness control DAC. It is possible to insert a so called "blue back" back-ground level when no video is available. This feature can be activated via the BB bit in the control2 subaddress.

E.G.Data creazione 01/11/99 17.27

22 / 30

F19MANU.doc

FOR VOLTAGE SINTHESIS ONLY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SIF AUDEXT NC NC PLLIF IFVIDEO OUT SCL SDA DECOUPLING CHR.IN EX.CVBS/Y IN VP1 INT CVBS IN GND AUDIO OUT DECOUPLING EX. CVBS IN BLKIN B OUT G OUT R OUT BCL/VG R IN G IN B IN RGB INSERT. Y IN Y OUT

TR500 UV 1 2 3 4 5 6 7 8 9 10 11 UHF

TDA884X
I.F. VIDEO AGC AFC DEM. IDENT

EF

EF
TR200 IIC

F 19
TO PIN 33 IC100 CVBS EF FOR TXT TR203 TO PIN 24 IC 100 (CVBS FOR TXT) TO PIN 9 IC 100 AV1 STATUS 19 8 15 11 7 16 20

TR201

MSD PAL (SECAM) NTSC

TR202

EF
VIDEO IN CINCH

SOUND PROCES. (MONO)

C.D. & RGB MATRIX VIDEO CONTROL

EF
TR204

SYNC PROCES. V. & H. TIME BASE

EXT RGB SWITCH & RGB DRIVE

SCART 1

IIC
TRANSRECEIVER

DECOUPLING DEENPHASIS AGC OUT DECOPLING I REF VERT. RAMP EHT PROTEC. IF IN 2 IF IN 1 V. DRIVE A V. DRIVE B E - W OUT GND 2 PH. 1 FILTER PH. 2 FILTER H. IN, S.C. OUT HOR. OUT DECOUPLING CVBS 1 OUT VP2 DET FILTER X TAL 2 X TAL 1 S.C. REF OUT R - Y IN B - Y IN R - Y OUT B - Y OUT

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

FROM PIN 1 IC 100 TR501 5V

TR503

IIC

VHF H VHF L TR502

FROM IC 100 PIN 14, 20, 21 BAND SWITCHING TR105

TR208 3.58MHz 8V 4.43MHz 3,57MHz FROM PIN 51 IC 100 TR205 TR206

A10
1 2 3 4 5

CTI & 4:3 TO 16 : 9

12 V TR211

EF
FROM PIN 6 IC100 AV1 / AV2 SWITCH CVBS IN TV CVBS FROM PIN 7 IC100 AV1 / TV SWITCH TO AV2 3 2 TO PIN 10 IC 100 AV2 STATUS 7 8 9 12 V 4 1 6 5 TR212 CVBS OUT

EF
5V

EF
SCART 2 8 20 19

RGB AMPLIFIER MODULE

6 7 8 9 10 11 12

1/3 0F IC201 LA7955
CVBS IN

FROM PIN 52 IC 100 4:3 TO 16:9 SWITCH

TO CRT
8V

FROM EHT

VIDEO SIGNAL PATH

F19VIDEP.DRW E.G. 14 / 11 / 99

IC204 TDA884X
26 23/24/25 19/20/21
RGB OUT

F19 RGB AMPLIFIER
12 V 200 V TO G1 TRC 3 1

18

RGB IN FAST BLK. IN RGB IN FROM SCART

2

R17,R18,R19 R215 R216 R217 R600 2 6/11/14 D800, D801, D802 9/12/15 E.F. R613 R614 R615 4/5/6 R604 R605 R606 1/3/4
TO RGB KATODE

5

7/10/13

STV 5112

F19 RGBCO.DRW E.G. 14 / 11 /99

3 X

F 19 FEATURE MODULE
Colour Transient Improvment

& 4 : 3 to 16 : 9 Signal Processing

SAA4981
Monolithic integrated 16 : 9 Compressor
FEATURES · Fixed horizontal compression by a factor of 4 ¤3 for most video standards · Three fixed screen positions (left, centre and right) · 5 MHz bandwidth · Bypass function · Inputs for luminance and chrominance of side panels · Standard video inputs and outputs (Y, (-Y) and (-Y)) · Horizontal and vertical sync signals are not processed · Pre filters and post filters on chip. GENERAL DESCRIPTION The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4 ¤3 from, for example, 52 ms to 39ms. This is necessary to display 4:3 video software on a 16 : 9 tube in the correctproportion. The capacitively coupled video inputs are Y, (-Y) and (-Y). The synchronisation input HREF is a line frequencyreference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, ( Y) and (-Y) and provides the following two possibilities: 1. Bypass function (the input signal is not compressed) 2. Compressed video by a factor of 4 ¤3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE. The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. FUNCTIONAL DESCRIPTION SAA4981 16:9 TO 4:3 PROCESSOR Pagina 1 di 3 e.g.SAA4981R.doc

VCCA

VEEA

VCCD

VEED

SUB

20

19

8

7

4

23 YIN

SC LINE MEMORY CLAMP 5 MHz LOW-PASS FILTER SC LINE MEMORY

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER

MUX Y

18

YOUT

SAA4981
C1 C2 C3

22 CLAMP

SC LINE MEMORY 5 MHz LOW-PASS FILTER SC LINE MEMORY

(B-Y)IN

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER

MUX BY

17

(B-Y)OUT

C1

C2

C3

21 CLAMP

SC LINE MEMORY 5 MHz LOW-PASS FILTER SC LINE MEMORY

(R-Y)IN

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER MUX RY

16

(R-Y)OUT

HREF

6

3 HORIZONTAL SEPARATION C1 CONTROLLER 54 MHz PLL C2 C3 CLAMP REFERENCE 3

C1

C2

C3

12 TEST

9

10 CTRL2

11

1

2

3

24

5

15

14

13

MHA277

CTRL1

CTRL3

pagewidth

YSIDE CLMY CLMBY CLMRY CLAOUT BGREF

BYSIDE RYSIDE

Applicable video standards The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reducedvideo bandwidth above 5 MHz. Clamping circuit The clamping circuits clamp the video input signals Y, (-Y) and (-Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories. Internal pre filters Before the signals are sampled in the time discrete and amplitude continuous area, lowpass filtering is necessary to avoid any aliasing. Even if the inputs have already been lowpass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz) SC line memories After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 4 ¤3 . The clocks and the horizontal starting pulses for the SC line memories are fed from the controller. Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with 13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz. The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters. Output multiplexer MUX Y, MUX (-Y) and MUX (-Y) SAA4981 16:9 TO 4:3 PROCESSOR Pagina 2 di 3 e.g.SAA4981R.doc

The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching. The input signals of the multiplexers for one component · The output signal of the post filter · The uncompressed signal after the input clamping · The clamping reference signal · The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE. The horizontal separation circuit The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the positive edge of the burst key of a sandcastle signal. 54 MHz horizontal PLL The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHzclock and the 18 MHz clock are line locked. Clamp reference Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories. Four external capacitors at the pins CLMY , CLMBY , CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages. A black level reference signal is available at CLAOUT. Controller The controller generates the clocks and the horizontal start signals for the SC line memories and, also, the control signals for the output multiplexers. The timing for the start reading signal for three different screen positions (left, centre and right) and the control signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass via the SC line memories and a bypass not via the SC line memories is available. When the signals do not pass the line memories, the frequencyresponse is not affected by the sifunction. SAA4981 16:9 TO 4:3 PROCESSOR Pagina 3 di 3 e.g.SAA4981R.doc

HREF 64 µs

1.5 µs 1.5 µs

(2) (2) (1)

sampled video 49 µs (used for compression) 6.3 µs 52 µs 36.75 µs side panel compressed video (centre position) side panel

side panel

compressed video (right position)

compressed video (left position)

side panel

bypassed video (bypass via the Line Memories)

(2) (2)

bypassed video

(1)

(full bypass not through the Line Memories)
MHA278

TDA4566
Colour transient improvement circuit

GENERAL DESCRIPTION The TDA4566 is a monolithic integrated circuit for colour-transient improvement (CTI) and luminance delay line in gyrator technique in colour television receivers. Features · Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and switching stages resulting in high transients of colour difference output signals · A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line · Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine adjustment of 37 ns · Two Y output signals; one of 180 ns less delay

TDA4566 CTI e.g.TDA4566R.doc

Pagina 1 di 1

F19 CTI & 16:9 TO 4 : 3 COMPRESSOR
6 9
15

10 12 V IC2 TDA4566
THESHOLD SWT.

5V
13 14 10 12
t = 180 ns

IC 1
23 CLAMP 11 Y R-Y 22 CLAMP

SAA4981
20 8 MUX LINE MEMORY LINE MEMORY LPF MUX LINE MEMORY LPF MUX LPF MUX 18 Y OUT LINE MEMORY LPF

7 4 3

8 1

Y R-Y

17 1

CLAMP

GYRATOR DELAY CELLS 7 x 90 ns

17

dV/dt
INTEGRATOR & PULSE FORMER

SWT. & STORE

8

R-Y OUT

dV/dt

SWT. & STORE

7

B-Y

21

CLAMP

LINE MEMORY LPF MUX LINE MEMORY LPF MUX

16 13

B-Y OUT

2

B-Y 2 3 4 5 6 9 18 6 HOR. SEPAR. 7 JS 7 JS 6 JS 5 20 54 MHz PLL 4 12 CONTROLLER CLAMP REFERENCE 19 1 2 3 24 5

14 15

11 10

9

H REF

5V TR1

5 8V
R4

C10 16 14 13 15 8 16 1 3 5 DUAL MONOSTABLE MULTIVIBRATOR M.M. M.M. 10 2

T2

16:9 TO 4:3 SWITCH SIGNAL

12

EF
C9

IC 4 HEF 4538 8V

D1

note: If CTI ( IC 2 TDA4566 IS NOT PRESENT THAN JS 5, JS 6 & JS7 MUST BE INSERTED

11

S.C INPUT

R2

12 V

F19FEAT.DRW E.G. 12/12/99

SCANNING SECTION SECTION

TDA8351
DC-coupled vertical deflection Circuit
FEATURES Few external components Highly efficient fully DC-coupled vertical output bridge circuit Vertical flyback switch Guard circuit Protection against: · · · · · · GENERAL DESCRIPTION The TDA8351 is a power circuit for use in 9 and 11 colour deflection systems for short-circuit of the output pins (7 and 4) short-circuit of the output pins to VP Temperature (thermal) protection High EMC immunity because of common mode inputs A guard signal in zoom mode.

field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. FUNCTIONAL DESCRIPTION The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. An external resistor (RM ) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical current signals. An external resistor (RCON ) connected between the differential input determines the output current through the deflection coil. TDA8351 VERTICAL OUTPUT Pagina 1 di 2 e.g. TDA8351R

The relationship between the differential input current and the output current is defined by: Idiff RCON =Icoil RM . The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM . The maximum input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the spread in the value of RCON . The flyback voltage is determined by an additional supply voltage VFB . The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). The output circuit is fully protected against the following: thermal protection · · short-circuit protection of the output pins (pins 4 and 7) short-circuit of the output pins to VP .

A guard circuit VO(guard) is provided. The guard circuit is activated at the following conditions: · · · · during flyback during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7) to VP or ground during open loop when the thermal protection is activated. This signal can be used for blanking the picture tubescreen.

TDA8351 VERTICAL OUTPUT

Pagina 2 di 2

e.g. TDA8351R

dth

VP VO(guard)

VFB 6

3 VP

8

CURRENT SOURCE

TDA8351

VP 7 VO(A) IS IT IT 9 VP V I(fb) VO(A)

I drive(pos)

1

I drive(neg)

2 V IS

4 VO(B)

VO(B)

5 GND
MBC988- 1

PINNING SYMBOL Idrive(pos) Idrive(neg) VP VO(B) GND VFB VO(A) VO(guard) VI(fb) PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION input power-stage (positive); includes II(sb) signal bias input power-stage (negative); includes II(sb) signal bias operating supply voltage output voltage B ground input flyback supply voltage output voltage A guard output voltage input feedback voltage

handbook, 2 columns

I drive(pos)

1 2

I drive(neg) VP VO(B) GND V FB