Text preview for : Datasheet_MCP607.pdf part of TES Extech TES-1335 Extech EA30 TES-1335 Digital Illuminance Meter Instruction Manual. Also known as Extech EA30 Light Meter User's Guide. Service Manual and Calibration.
Back to : 1335_EA30_Manuals.zip | Home
MCP606/7/8/9
2.5V to 6.0V Micropower CMOS Op Amp
Features
· Low Input Offset Voltage: 250 µV (maximum) · Rail-to-Rail Output · Low Input Bias Current: 80 pA (maximum at +85°C) · Low Quiescent Current: 25 µA (maximum) · Power Supply Voltage: 2.5V to 6.0V · Unity-Gain Stable · Chip Select (CS) Capability: MCP608 · Industrial Temperature Range: -40°C to +85°C · No Phase Reversal · Available in Single, Dual and Quad Packages
Description
The MCP606/7/8/9 family of operational amplifiers (op amps) from Microchip Technology Inc. are unity-gain stable with low offset voltage (250 µV, maximum). Performance characteristics include rail-to-rail output swing capability and low input bias current (80 pA at +85°C, maximum). These features make this family of op amps well suited for single-supply, precision, high-impedance, battery-powered applications. The single is available in standard 8-lead PDIP, SOIC and TSSOP packages, as well as in a SOT-23-5 package. The single MCP608 with Chip Select (CS) is offered in the standard 8-lead PDIP, SOIC and TSSOP packages. The dual MCP607 is offered in the standard 8-lead PDIP, SOIC and TSSOP packages. Finally, the quad MCP609 is offered in the standard 14-lead PDIP, SOIC and TSSOP packages. All devices are fully specified from -40°C to +85°C, with power supplies from 2.5V to 6.0V.
Typical Applications
· · · · · Battery Power Instruments High-Impedance Applications Strain Gauges Medical Instruments Test Equipment
Package Types
MCP606 PDIP, SOIC,TSSOP NC VIN VIN+ VSS 1 2 3 4 8 7 6 5 NC VDD VOUT NC MCP606 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 5 VDD 4 VIN
Design Aids
· · · · · SPICE Macro Models FilterLab® Software MindiTM Circuit Designer & Simulator Analog Demonstration and Evaluation Boards Application Notes
MCP607 PDIP, SOIC,TSSOP VOUTA VINA VINA+ VSS 1 2 3 4 8 7 6 5
MCP608 PDIP, SOIC,TSSOP 8 7 6 5 CS VDD VOUT NC
Typical Application
V OUT = V LM + I L R
SEN
( RF / RG )
IL To Load (VLP) VOUT
NC 1 VDD VOUTB VIN 2 VINB VIN+ 3 VINB+ VSS 4
RG 5 k 2.5V to 6.0V RSEN 10
RF 50 k
MCP609 PDIP, SOIC,TSSOP VOUTA VINA VINA+ VDD VINB+ VINB VOUTB 1 2 3 4 5 6 7 14 VOUTD 13 VIND 12 VIND+ 11 VSS 10 VINC+ 9 VINC 8 VOUTC
MCP606
To Load (VLM)
Low-Side Battery Current Sensor
© 2008 Microchip Technology Inc.
DS11177E-page 1
MCP606/7/8/9
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage and Current Limits".
Absolute Maximum Ratings
VDD VSS ........................................................................7.0V Current at Input Pins ....................................................±2 mA Analog Inputs (VIN+, VIN) ........ VSS 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD VSS| Output Short Circuit Current .................................Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature..................................65° C to +150° C Maximum Junction Temperature (TJ) ........................ .+150° C ESD Protection On All Pins (HBM; MM) .............. 3 kV; 200V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Ratio Input Bias Current and Impedance Input Bias Current At Temperature Input Offset Bias Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Range Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (Large-signal) DC Open-Loop Gain (Large-signal) Output Maximum Output Voltage Swing VOL, VOH VOL, VOH Linear Output Voltage Range VOUT VOUT Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: VDD IQ 2.5 -- -- 18.7 6.0 25 V µA IO = 0 ISC ISC VSS + 15 VSS + 45 VSS + 50 VSS + 100 -- -- -- -- -- -- 7 17 VDD 20 VDD 60 VDD 50 VDD 100 -- -- mV mV mV mV mA mA RL = 25 k to VL, 0.5V input overdrive RL = 5 k to VL, 0.5V input overdrive RL = 25 k to VL, AOL 105 dB RL = 5 k to VL, AOL 100 dB VDD = 2.5V VDD = 5.5V AOL AOL 105 100 121 118 -- -- dB dB RL = 25 k to VL, VOUT = 50 mV to VDD 50 mV RL = 5 k to VL, VOUT = 0.1V to VDD 0.1V VCMR CMRR VSS 0.3 75 91 VDD 1.1 -- V dB CMRR 75 dB VDD = 5V, VCM = -0.3V to 3.9V IB IB IOS ZCM ZDIFF -- -- -- -- -- 1 -- 1 1013||6 1013||6 -- 80 -- -- -- pA pA pA ||pF ||pF TA = +85°C VOS VOS/TA PSRR -250 -- 80 -- ±1.8 93 +250 -- -- µV µV/°C TA = -40°C to +85°C dB Sym Min Typ Max Units Conditions
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.5V and 5.5V. © 2008 Microchip Technology Inc.
DS11177E-page 2
MCP606/7/8/9
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 2.8 38 3 -- -- -- µVP-P nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz GBWP PM SR -- -- -- 155 62 0.08 -- -- -- kHz ° V/µs G = +1 V/V Sym Min Typ Max Units Conditions
MCP608 CHIP SELECT CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High CS Input High, GND Current Amplifier Output Leakage, CS High CS Dynamic Specifications CS Low to Amplifier Output Turn-on Time CS High to Amplifier Output Hi-Z CS Hysteresis tON tOFF VHYST -- -- -- 9 0.1 0.6 100 -- -- µs µs V CS = 0.2VDD to VOUT = 0.9 VDD/2, G = +1 V/V, RL = 1 k to VSS CS = 0.8VDD to VOUT = 0.1 VDD/2, G = +1 V/V, RL = 1 k to VSS VDD = 5.0V VIH ICSH ISS IO(LEAK) 0.8 VDD -- -2 -- -- 0.01 -0.05 10 VDD 0.1 -- -- V µA µA nA CS = VDD CS = VDD CS = VDD VIL ICSL VSS -0.1 -- 0.01 0.2 VDD -- V µA CS = 0.2VDD Sym Min Typ Max Units Conditions
CS tON VOUT ISS ICS Hi-Z -50 nA (typical) -50 nA (typical)
VIL
VIH tOFF Hi-Z -18.7 µA (typical) -50 nA (typical) -50 nA (typical)
FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608.
© 2008 Microchip Technology Inc.
DS11177E-page 3
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-TSSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: JA JA JA JA JA JA JA -- -- -- -- -- -- -- 256 85 163 124 70 120 100 -- -- -- -- -- -- -- °C/W °C/W °C/W °C/W °C/W °C/W °C/W TA TA TA -40 -40 -65 -- -- -- +85 +125 +150 °C °C °C Note 1 Sym Min Typ Max Units Conditions
The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
Test Circuits
The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.5 "Supply Bypass". VDD RN 0.1 µF 1 µF VOUT CL VDD/2 RG RF VL RL
VIN
MCP60X
FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.
VDD RN 0.1 µF 1 µF VOUT CL VIN RG RF VL RL
VDD/2
MCP60X
FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.
DS11177E-page 4
© 2008 Microchip Technology Inc.
MCP606/7/8/9
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
Percentage of Occurances ( ) 16% 14% 12% 10% 8% 6% 4% 2% 0% 0 -250 -200 -150 -100 -50 50 100 150 200 250 1200 Samples VDD = 5.5V 16% Percentage of Occurances 14% 12% 10% 8% 6% 4% 2% 0% -8 -6 -4 -2 0 2 4 6 Input Offset Voltage Drift (µV/°C) 8
206 Samples VDD = 5.5V
Input Offset Voltage (µV)
FIGURE 2-1: VDD = 5.5V.
Percentage of Occurances ( ) 16% 14% 12% 10% 8% 6% 4% 2% 0%
Input Offset Voltage at
FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V.
18% Percentage of Occurances 206 Samples VDD = 2.5V
1200 Samples VDD = 2.5V
16% 14% 12% 10% 8% 6% 4% 2% 0%
-50
0
-250
-200
-150
-100
50
100
150
200
250
Input Offset Voltage (µV)
-8
-6
-4 -2 0 2 4 6 Input Offset Voltage Drift (µV/°C)
8
FIGURE 2-2: VDD = 2.5V.
22 20 18 16 14 12 10 8 6 4 2 0
Input Offset Voltage at
FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V.
24 Quiescent Current per Amplifier (µA) 22 20 18 16 14 12 VDD = 2.5V VDD = 5.5V
Quiescent Current per Amplifier (µA)
TA = +85°C TA = +25°C TA = -40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-3: Quiescent Current vs. Power Supply Voltage.
FIGURE 2-6: Quiescent Current vs. Ambient Temperature.
© 2008 Microchip Technology Inc.
DS11177E-page 5
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
500 Input Offset Voltage (µV) 400 300 200 100 0
Representative Part
120 VDD =2.5V VDD = 5.5V Input Offset Voltage (µV) 100 80 60 40 20 0 -20 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TA = +85°C TA = +25°C TA = -40°C
VDD = 5.5V
4.0
4.5
80 70 50 40 30 20 10 60
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature.
120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 0.01 0.1
1 10 100 1k 10k 100k 1M Frequency (Hz)
FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage.
160 Gain Bandwidth Product (kHz) Open-Loop Phase (°) 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 Ambient Temperature (°C) VDD = 5.0V GBWP Phase Margin
RL = 25 k
90 45 0
Gain Phase
-45 -90 -135 -180 -225
0 100
FIGURE 2-8: vs. Frequency.
140 Channel to Channel Separation (dB) 130 120 110 100 90
Open-Loop Gain and Phase
FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature.
1000
Input Noise Voltage Density (nV/Hz)
100
Referred to Input 80 100 1k 10k 1.E+02 1.E+03 1.E+04 Frequency (Hz)
100k 1.E+05
10 1 10 100 1k 10k 100k 0.1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Frequency (Hz)
FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only).
FIGURE 2-12: vs. Frequency.
Input Noise Voltage Density
DS11177E-page 6
© 2008 Microchip Technology Inc.
Phase Margin (°)
5.0
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
100 Input Bias and Offset Currents (pA) 60 Input Bias and Offset Currents (pA) 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) IOS IB
VDD = 5.5V VCM = VDD
TA = 85°C VDD = 5.5V
10 IB 1 | IOS | 25 30 35 40 45 50 55 60 65 70 75 80 85 Ambient Temperature (°C)
0.1
-10
FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature.
135 DC Open-Loop Gain (dB) 130 125 120 115 110 105 100 100 1.E+02 VDD = 2.5V VDD = 5.5V
FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage.
150 DC Open-Loop Gain (dB) 140 130 120 110 100 90
RL = 25 k
1k 10k 1.E+03 1.E+04 Load Resistance ()
100k 1.E+05
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
FIGURE 2-14: Load Resistance.
120 CMRR and PSRR (dB) 100 80 60 40 20 0 0.1 1.E-01
1 1.E+00
DC Open-Loop Gain vs.
FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage.
100 CMRR and PSRR (dB) 95 90 85 80 75 PSRR CMRR
PSRRPSRR+
CMRR
10 100 1.E+01 1.E+02 Frequency (Hz)
1k 1.E+03
10k 1.E+04
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-15: Frequency.
CMRR, PSRR vs.
FIGURE 2-18: Temperature.
CMRR, PSRR vs. Ambient
© 2008 Microchip Technology Inc.
DS11177E-page 7
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
1000 Output Voltage Headroom (mV) 40 Output Voltage Headroom (mV) 35 30 25 20 15 10 5 0 0.1 1 10 Output Current (mA) 100 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 VDD = 2.5V VOL - VSS
VDD = 2.5V VDD = 5.5V
RL = 5 k8 VDD - VOH VDD = 5.5V
100
VDD - VOH
10
VOL - VSS
1
FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude.
10
FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 k.
6 Input and Output Voltages (V)
Maximum Output Voltage Swing (V)
VDD = 5.5V VDD = 2.5V 1
5 4 3 2 1 0 -1
G = +2 V/V VDD = 5.0V
VIN VOUT
0.1 100 1.E+02
1k 10k 1.E+03 1.E+04 Frequency (Hz)
100k 1.E+05
Time (100 µs/div)
FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency.
0.12 0.10 Slew Rate (V/µs) 0.08 0.06 0.04 0.02 0.00 -50 -25 0 25 50 75 100 Ambient Temperature (°C) High to Low Low to High
FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal.
25 20 15 10 5 0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) +ISC , VDD = 2.5V | -ISC |, VDD = 2.5V
Output Short Circuit Current Magnitude (mA)
+ISC , VDD = 5.5V | -ISC |, VDD = 5.5V
FIGURE 2-21: Temperature.
Slew Rate vs. Ambient
FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature.
DS11177E-page 8
© 2008 Microchip Technology Inc.
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Time (50 µs/div) 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Time (50 µs/div)
VDD = 5.0V
VDD = 5.0V
Output Voltge (V)
FIGURE 2-25: Pulse Response.
VDD = 5.0V
Large-signal, Non-inverting
FIGURE 2-28: Pulse Response.
Large-signal, Inverting
Output Voltage (20 mV/div)
RL = 25 k
Time (50 µs/div)
Output Voltage (20 mV/div)
Time (50 µs/div)
FIGURE 2-26: Pulse Response.
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 Hysteresis
Small-signal, Non-inverting
FIGURE 2-29: Response.
5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Output Hi-Z
Small-signal, Inverting Pulse
Internal CS Switch Output (V)
Amplifier Output Active
VDD = 5.0V
G = +1 V/V RL = 1 k to VSS CS Output Enabled
10 5 0 -5 -10 -15 -20
Output Hi-Z
CS Input High to Low
CS Input Low to High
VOUT
Amplifier Output Hi-Z 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CS Input Voltage (V)
-25 -30 -35
Time (5 µs/div)
FIGURE 2-27: (MCP608 only).
Chip Select (CS) Hysteresis
FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only).
© 2008 Microchip Technology Inc.
DS11177E-page 9
Chip Select Voltage (V)
15
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL, CL = 60 pF, and CS is tied low.
1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12
Input Current Magnitude (A)
+125°C +85°C +25°C -40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS).
DS11177E-page 10
© 2008 Microchip Technology Inc.
MCP606/7/8/9
3.0 PIN DESCRIPTIONS
PIN FUNCTION TABLE.
MCP607 SOT-23-5 1 4 3 5 -- -- -- -- -- -- 2 -- -- -- -- -- 1 2 3 4 5 6 7 -- -- -- 8 -- -- -- -- -- 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 8 1, 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- VOUT, VOUTA VIN, VINA VIN+, VINA+ VDD VINB+ VINB VOUTB VOUTC VINC VINC+ VSS VIND+ VIND VOUTD CS NC Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Output (op amp B) Output (op amp B) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Output (op amp D) Chip Select No Internal Connection MCP608 MCP609 Symbol Description Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP606 PDIP, SOIC, TSSOP 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- -- 1, 5, 8
3.1
Analog Outputs
3.4
Power Supply Pins
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents.
The positive power supply pin (VDD) is 2.5V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the output pins are at voltages between VSS and VDD; while the input pins are at voltages between VSS 0.3V and VDD + 0.3V. Typically, these parts are used in a single-supply (positive) configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors .
3.3
Chip Select Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS logic input. It is used to place the MCP608 op amp in a Low-power mode, with the output(s) in a Hi-Z state.
© 2008 Microchip Technology Inc.
DS11177E-page 11
MCP606/7/8/9
4.0 APPLICATIONS INFORMATION
VDD D1 V1 R1 V2 R2 R3 VSS (minimum expected V1) 2 mA VSS (minimum expected V2) R2 > 2 mA R1 > MCP60X D2 The MCP606/7/8/9 family of op amps is manufactured using Microchip's state-of-the-art CMOS process These op amps are unity-gain stable and suitable for a wide range of general purpose applications.
4.1
4.1.1
Rail-to-Rail Inputs
PHASE REVERSAL
The MCP606/7/8/9 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-23 shows the input voltage exceeding the supply voltage without any phase reversal.
4.1.2
INPUT VOLTAGE AND CURRENT LIMITS
The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad
FIGURE 4-2: Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, current through the diodes D1 and D2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-31. Applications that are high impedance may need to limit the useable voltage range.
VIN+ Bond Pad
Input Stage
Bond V IN Pad
4.1.3
NORMAL OPERATION
VSS Bond Pad
The input stage of the MCP606/7/8/9 op amps use a PMOS input stage. It operates at low common mode input voltage (VCM), including ground. WIth this topology, the device operates with VCM up to VDD 1.1V and 0.3V below VSS. Figure 4-3 shows a unity gain buffer. Since VOUT is the same voltage as the inverting input, VOUT must be kept below VDD1.2V for correct operation.
FIGURE 4-1: Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2.
VIN
+ MCP60X
VOUT
FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range.
DS11177E-page 12
© 2008 Microchip Technology Inc.
MCP606/7/8/9
4.2 Rail-to-Rail Output
10k
10000
There are two specifications that describe the output-swing capability of the MCP606/7/8/9 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load conditions. For instance, the output voltage swings to within 15 mV of the negative rail with a 25 k load to VDD/2. Figure 2-23 shows how the output voltage is limited when the input goes beyond the linear region of operation. The second specification that describes the output-swing capability of these amplifiers (Linear Output Voltage Range) defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. To verify linear operation in this range, the large-signal DC Open-Loop Gain (AOL) is measured at points inside the supply rails. The measurement must meet the specified AOL conditions in the specification table.
Recommended R ISO ()
1k
1000
GN = +1 GN = +2 GN +4 100 10p
100 10
100p 1n 10n Normalized Load Capacitance; CL/GN (F)
100
1000
10000
FIGURE 4-5: Recommended RISO Values for Capacitive Loads.
After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP606/7/8/9 SPICE macro model are helpful.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability problems for voltage-feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain-peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load.
4.4
MCP608 Chip Select
The MCP608 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 50 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pull-down resistor connected to VSS, so it will go low if the CS pins is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse.
4.5
Supply Bypass
RISO MCP60X VIN CL VOUT
With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts.
4.6
Unused Op Amps
FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
An unused op amp in a quad package (MCP609) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current.
© 2008 Microchip Technology Inc.
DS11177E-page 13
MCP606/7/8/9
1. ¼ MCP604 (A) VDD R1 R2 VDD VREF ¼ MCP604 (B) VDD Non-inverting Gain and Unity-gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain (convert current to voltage, such as photo detectors) amplifiers: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN) to the input with a wire that does not touch the PCB surface.
2.
R2 V REF = V DD -----------------R1 + R2
FIGURE 4-6:
Unused Op Amps.
4.7
PCB Surface Leakage 4.8
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP606/7/8/9 family's bias current at 25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7.
Application Circuits
LOW-SIDE BATTERY CURRENT SENSOR
4.8.1
The MCP606/7/8/9 op amps can be used to sense the load current on the low-side of a battery using the circuit in Figure 4-8. In this circuit, the current from the power supply (minus the current required to power the MCP606) flows through a sense resistor (RSEN), which converts it to voltage. This is gained by the the amplifier and resistors, RG and RF . Since the non-inverting input of the amplifier is at the load's negative supply (VLM), the gain from RSEN to VOUT is RF/RG . V OUT = V LM + I L R ( RF / RG ) IL RG 5 k 2.5V to 6.0V RSEN 10 MCP606 RF 50 k To Load (VLP) VOUT To Load (VLM)
VIN-
VIN+
VSS
SEN
Guard Ring
FIGURE 4-7: for Inverting Gain.
Example Guard Ring Layout FIGURE 4-8: Sensor.
Low Side Battery Current
Since the input bias current and input offset voltage of the MCP606 are low, and the input is capable of swinging below ground, there is very little error generated by the amplifier. The quiescent current is very low, which helps conserve battery power. The rail-to-rail output makes it possible to read very low currents.
DS11177E-page 14
© 2008 Microchip Technology Inc.
MCP606/7/8/9
4.8.2 PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high output impedance can be connected to a transimpedance amplifier. The transimpedance amplifier converts the current into voltage. Photodiodes are one sensor that produce an output current. The key op amp characteristics that are needed for these circuits are: low input offset voltage, low input bias current, high input impedance and an input common mode range that includes ground. The low input offset voltage and low input bias current support a very low voltage drop across the photodiode; this gives the best photodiode linearity. Since the photodiode is biased at ground, the op amp's input needs to function well both above and below ground. operate at a much higher speed. This reverse bias also increases the dark current and current noise, however. Resistor R2 converts the current into voltage. Capacitor C2 limits the bandwidth and helps stabilize the circuit when D1's junction capacitance is large. VB < 0 V OUT = I D1 R 2 C2 R2 ID1 Light D1 VB VOUT VDD MCP606
4.8.2.1
Photo-Voltaic Mode
Figure 4-9 shows a transimpedance amplifier with a photodiode (D1) biased in the Photo-voltaic mode (0V across D1), which is used for precision photodiode sensing. As light impinges on D1, charge is generated, causing a current to flow in the reverse bias direction of D1. The op amp's negative feedback forces the voltage across the D1 to be nearly 0V. Resistor R2 converts the current into voltage. Capacitor C2 limits the bandwidth and helps stabilize the circuit when D1's junction capacitance is large. V OUT = I D1 R C2 R2 ID1 Light D1 VOUT VDD MCP606 R1 VREF
FIGURE 4-10: Photodiode (in Photo-conductive mode) and Transimpedance Amplifier. 4.8.3 TWO OP AMP INSTRUMENTATION AMPLIFIER
2
The two op amp instrumentation amplifier shown in Figure 4-11 serves the function of taking the difference of two input voltages, level-shifting it and gaining it to the output. This configuration is best suited for higher gains (i.e., gain > 3 V/V). The reference voltage (VREF) is typically at mid-supply (VDD/2) in a single-supply environment.
R 1 2R 1 VOUT = ( V 1 V 2 ) 1 + ------ + --------- + V REF R2 RG
RG R2 R2 R1 VOUT
FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. 4.8.2.2 Photo-Conductive Mode
V2 V1
½ MCP607
½ MCP607
Figure 4-9 shows a transimpedance amplifier with a photodiode (D1) biased in the Photo-conductive mode (D1 is reverse biased), which is used for high-speed applications. As light impinges on D1, charge is generated, causing a current to flow in the reverse bias direction of D1. Placing a negative bias on D1 significantly reduces its junction capacitance, which allows the circuit to
FIGURE 4-11: Amplifier.
Two op amp Instrumentation
The key specifications that make the MCP606/7/8/9 family appropriate for this application circuit are low input bias current, low offset voltage and high common-mode rejection.
© 2008 Microchip Technology Inc.
DS11177E-page 15
MCP606/7/8/9
4.8.4 THREE OP AMP INSTRUMENTATION AMPLIFIER 4.8.5 PRECISION GAIN WITH GOOD LOAD ISOLATION
A classic, three op amp instrumentation amplifier is illustrated in Figure 4-12. The two input op amps provide differential signal gain and a common mode gain of +1. The output op amp is a difference amplifier, which converts its input signal from differential to a single ended output; it rejects common mode signals at its input. The gain of this circuit is simply adjusted with one resistor (RG). The reference voltage (VREF) is typically referenced to mid-supply (VDD/2) in single-supply applications.
2R 2 R 4 VOUT = ( V 1 V 2 ) 1 + --------- ----- + V REF R G R 3
In Figure 4-13, the MCP606 op amps, R1 and R2 provide a high gain to the input signal (VIN). The MCP606's low offset voltage makes this an accurate circuit. The MCP601 is configured as a unity-gain buffer. It isolates the MCP606's output from the load, increasing the high-gain stage's precision. Since the MCP601 has a higher output current, with the two amplifiers being housed in separate packages, there is minimal change in the MCP606's offset voltage due to loading effect.
VOUT = V IN (1 + R 2 / R 1 )
V2
½ MCP607 R3 R2 RG R2 R3 MCP606 VREF R4 R4 VOUT
VIN
MCP606 MCP601 VOUT R1 R2
FIGURE 4-13: Load Isolation.
Precision Gain with Good
V1
½ MCP607
FIGURE 4-12: Three op amp Instrumentation Amplifier.
DS11177E-page 16
© 2008 Microchip Technology Inc.
MCP606/7/8/9
5.0 DESIGN AIDS
5.5
Microchip provides the basic design tools needed for the MCP606/7/8/9 family of op amps.
Analog Demonstration and Evaluation Boards
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP606/7/8/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Two of our boards that are especially useful are: · P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board · P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board
5.6
Application Notes
5.2
FilterLab® Software
Microchip's FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental reference resources. ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 AN723: "Operational Amplifier AC Specifications and Applications", DS00723 AN884: "Driving Capacitive Loads With Op Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits An Overview", DS00990 These application notes and others are listed in the design guide: "Signal Chain Design Guide", DS21825
5.3
MindiTM Circuit Designer & Simulator
Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation.
5.4
MAPS (Microchip Advanced Part Selector)
MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparasion reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts.
© 2008 Microchip Technology Inc.
DS11177E-page 17
MCP606/7/8/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP606) Example:
XXNN
SB25
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP606 I/P256 0722 MCP606 I/P e3256 0810
OR
8-Lead SOIC (150 mil)
Example: MCP606 I/SN0722 256 MCP606I SN e3 0810 256
XXXXXXXX XXXXYYWW NNN
OR
8-Lead TSSOP XXXX YYWW NNN
Example: 606 I810 256
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS11177E-page 18
© 2008 Microchip Technology Inc.
MCP606/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP609) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP609-I/P 0722256
OR
MCP609 I/P e3 0810256
14-Lead SOIC (150 mil) (MCP609)
Example:
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP609ISL 0722256
OR
MCP609 e3 I/SL^^ 0810256
14-Lead TSSOP (MCP609) XXXXXXXX YYWW NNN
Example: 609IST 0545 256
© 2008 Microchip Technology Inc.
DS11177E-page 19
MCP606/7/8/9
/HDG 3ODVWLF 6PDOO 2XWOLQH 7UDQVLVWRU 27 >627@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
b
N
E E1
1 e
2
3
e1 D
A
A2
c
A1
L L1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV /HDG 3LWFK 2XWVLGH /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H H $ $ $ ( ( ' / / I F 0,1 0,//,0(7(56 120 %6& %6& ± ± ± ± ± ± ± ± ± ± 0$;
/HDG :LGWK E ± 1RWHV 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS11177E-page 20
© 2008 Microchip Technology Inc.
MCP606/7/8/9
/HDG 3ODVWLF 'XDO ,Q/LQH 3 ± PLO %RG\ >3',3@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
N
NOTE 1 E1
1
2 D
3 E A2
A
A1 e b1 b
L
c
eB
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% ± ± 0,1
,1&+(6 120 %6& ± ± ± ± 0$;
1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc.
DS11177E-page 21
MCP606/7/8/9
/HDG 3ODVWLF 6PDOO 2XWOLQH 61 ± 1DUURZ PP %RG\ >62,&@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D e N
E E1
NOTE 1 1 2 3 b h c h
A
A2
A1
L L1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E ± 0,1
0,//,0(7(56 120 %6& ± ± ± %6& %6& %6& ± ± 5() ± ± ± ± ± ± 0$;
1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS11177E-page 22
© 2008 Microchip Technology Inc.
MCP606/7/8/9
/HDG 3ODVWLF 7KLQ 6KULQN 6PDOO 2XWOLQH 67 ± PP %RG\ >76623@ /HDG 3ODVWLF 6PDOO 2XWOLQH 61 ± 1DUURZ PP %RG\ >62,&@
1RWH 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D N
E E1
NOTE 1
1 b
2 e c
A
A2
A1
L1
L
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F ± 0,1
0,//,0(7(56 120 %6& ± ± %6& 5() ± ± 0$;
/HDG :LGWK E ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc.
DS11177E-page 23
MCP606/7/8/9
/HDG 3ODVWLF 'XDO ,Q/LQH 3 ± PLO %RG\ >3',3@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
N
NOTE 1
E1
1
2
3 D E A2 L c
A
A1 b
b1 e
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% ± ± 0,1 ,1&+(6 120 %6& ± ± ± ± 0$;
eB
1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS11177E-page 24
© 2008 Microchip Technology Inc.
MCP606/7/8/9
/HDG 3ODVWLF 6PDOO 2XWOLQH 6/ ± 1DUURZ PP %RG\ >62,&@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D N
E E1 NOTE 1 1 2 b 3 e h h A2 c
A
A1
L L1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E ± 0,1
0,//,0(7(56 120 %6& ± ± ± %6& %6& %6& ± ± 5() ± ± ± ± ± ± 0$;
1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc.
DS11177E-page 25
MCP606/7/8/9
/HDG 3ODVWLF 7KLQ 6KULQN 6PDOO 2XWOLQH 67 ± PP %RG\ >76623@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D N
E E1
NOTE 1 1 2 e b A A2 c
A1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F
L1
0,//,0(7(56 0,1 120 %6& ± ± ± %6& 5() ± ± 0$;
L
/HDG :LGWK E ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
DS11177E-page 26
© 2008 Microchip Technology Inc.
MCP606/7/8/9
APPENDIX A: REVISION HISTORY
Revision E (March 2008)
The following is the list of modifications: 1. 2. 3. 4. 5. Increased maximum operating VDD. Added test circuits. Updated performance curves. Added Figure 2-31. Added Section 4.1.1 "Phase Reversal", Section 4.1.2 "Input Voltage and Current Limits", ad Section 4.1.3 "Normal Operation". Updated Section 5.0 "Design AIDS" Updated Section 6.0 "Packaging Information". Updated package outline drawings.
6. 7.
Revision D (February 2005)
The following is the list of modifications: 1. 2. 3. 4. Added Section 3.0 "Pin Descriptions". Updated Section 4.0 "Applications Information". Added Section 4.3 "Capacitive Loads" Updated Section 5.0 "Design AIDS" to include FilterLab® and to point to the latest SPICE macro model. Corrected and updated Section 6.0 "Packaging Information". Added Appendix A: "Revision History".
5. 6.
Revision C (January 2001)
· Undocumented changes
Revision B (May 2000)
· Undocumented changes
Revision A (January 2000)
· Original Release of this Document.
© 2008 Microchip Technology Inc.
DS11177E-page 25
MCP606/7/8/9
NOTES:
DS11177E-page 26
© 2008 Microchip Technology Inc.
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples:
a) b) c) Device MCP606 = Single Op Amp MCP606T = Single Op Amp Tape and Reel (SOIC, TSSOP) MCP607 = Dual Op Amp MCP607T = Dual Op Amp Tape and Reel (SOIC, TSSOP) MCP608 = Single Op Amp with CS MCP608T = Single Op Amp with CS Tape and Reel (SOIC, TSSOP) MCP609 = Quad Op Amp MCP609T = Quad Op Amp Tape and Reel (SOIC, TSSOP) Industrial Temperature, 8LD PDIP package. MCP606-I/SN: Industrial Temperature, 8LD SOIC package. MCP606T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC package. MCP606-I/ST: Industrial Temperature, 8LD TSSOP package. MCP606T-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT-23 package. Industrial Temperature, 8LD PDIP package. MCP607T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC package. Industrial Temperature, 8LD SOIC package. MCP608T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC package. Industrial Temperature, 14LD PDIP package. MCP609T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC package. MCP609-I/P: MCP608-I/SN: MCP607-I/P: MCP606-I/P:
d) e)
a) b) c) a) b)
Temperature Range
I
=
-40°C to +85°C
Package
OT P SN SL ST
= = = = =
Plastic SOT-23, 5-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC (3.90 mm body), 8-lead Plastic SOIC (3.90 mm body), 14-lead Plastic TSSOP, 8-lead, 14-lead
a) b) c)
© 2008 Microchip Technology Inc.
DS11177E-page 27
MCP606/7/8/9
NOTES:
DS11177E-page 28
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: · · Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
·
· ·
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS11177E-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS11177E-page 30
© 2008 Microchip Technology Inc.