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S/M No. : CP385P-010
Service Manual
71 Cm STEREO Color Television MODEL CHASSIS
DTE-2898
CP-785
DAEWOO ELECTRONICS CO., LTD.
http : //svc.dwe.co.kr DEC. 1999
1-1 Specifications
TV standard Sound system Power consumption
PAL - SECAM B/G D/K, PAL I/I, SECAM L/L' NICAM B/G, I, D/K, L, FM 2Carrier B/G, D/K 28" : 75 W approx.
Sound Output Power 28" : 7W x 2 (at 60% mod, 10%THD) Speaker Teletext system Aerial input Channel coverage Tuning system Visual screen size 28" : 12W 8 ohm x2 10 pages memory FASTEXT (FLOF or TOP) 75 ohm unbalanced Off-air channels, S-cable channels and hyperband frequency synthesiser tuning system
Channel indication Program Selection Aux. terminal
Remote Control Unit
28" : 66cm On Screen Display 100 programmes EURO-SCART 1 : Audio / Video In and Out, R/G/B In, Slow and Fast switching. EURO-SCART 2 : Audio / Video In, SVHS In. Audio-Video Jack on front of cabinet in common connection with EURO-SCART 2. Headphone jack (3.5 mm) on front of cabinet R-40A01
21 Pin EURO-SCART 1 : Pin 1 2 3 4 5 6 7 8 9 10 Signal Description Audio Output Right Audio Input Right Audio Output Left Audio Earth Blue Earth Audio Input Left Blue Input Slow Switching Green Earth N.C. Matching value 0.5 Vrms, Impedance < 1 k, ( RF 54% Mod ) 0.5 Vrms, Impedance > 10 k 0.5 Vrms, Impedance < 1 k, ( RF 54% Mod )
0.5 Vrms, Impedance > 10 k 0.7 Vpp ±0.1V, Impedance 75 TV : 0 to 2V, AV 16/9 : 4.5 to 7V, AV 4/3 : 9.5 to 12V , Impedance > 10 k
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Pin 11 12 13 14 15 16 17 18 19 20 21
Signal Description Green Input N.C. Red Earth Blanking Earth Red Input Fast Switching Video Out Earth Video In Earth Video Output Video Input Common Earth
Matching value 0.7 Vpp ± 0.1V, Impedance 75W
0.7 Vpp ± 0.1V, Impedance 75W 0 to 0.4V : Logic "0", 1 to 3V : Logic "1", Impedance 75W
1 Vpp ± 3dB, Impedance 75W 1 Vpp ± 3dB, Impedance 75W
21 Pin EURO-SCART 2 : Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Signal Description N.C. Audio Input Right N.C. Audio Earth Earth Audio Input Left N.C. N.C. N.C. N.C. N.C. N.C. Earth Earth Chroma Input N.C. Earth Video In Earth N.C. Video Input, Y In. Common Earth Matching value 0.5 Vrms, Impedance > 10 kW
0.5 Vrms, Impedance > 10 kW
± 3dB for a luminance signal of 1 Vpp
1 Vpp ± 3dB, Impedance 75W
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1-2 Channel table FREQUENCY TABLE CP785 CH C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 EUROPE CCIR 46.25 48.25 55.25 62.25 175.25 182.25 189.25 196.25 203.25 210.25 217.25 224.25 53.75 82.25 183.75 192.25 201.25 471.25 479.25 487.25 495.25 503.25 511.25 519.25 527.25 535.25 543.25 551.25 559.25 567.25 575.25 583.25 591.25 599.25 607.25 615.25 623.25 631.25 FRANCE 47.75 (L') 55.75 (L') 60.5 (L') 63.75 (L') 176.00 184.00 192.00 200.00 208.00 216.00 189.25 (LUX) 69.25 (L') 76.25 (L') 83.25 (L') 90.25 97.25 471.25 479.25 487.25 495.25 503.25 511.25 519.25 527.25 535.25 543.25 551.25 559.25 567.25 575.25 583.25 591.25 599.25 607.25 615.25 623.25 631.25 GB(IRELAND) 45.75 53.75 61.75 175.25 183.25 191.25 199.25 207.25 215.25 223.25 231.25 239.25 247.25 49.75 57.75 65.75 77.75 85.75 471.25 479.25 487.25 495.25 503.25 511.25 519.25 527.25 535.25 543.25 551.25 559.25 567.25 575.25 583.25 591.25 599.25 607.25 615.25 623.25 631.25 EAST OIRT 49.75 59.25 77.25 85.25 93.25 175.25 183.25 191.25 199.25 207.25 215.25 223.25 471.25 479.25 487.25 495.25 503.25 511.25 519.25 527.25 535.25 543.25 551.25 559.25 567.25 575.25 583.25 591.25 599.25 607.25 615.25 623.25 631.25
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CH C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 S01 S02 S03 S04 S05 S06 S07 S08 S09
EUROPE CCIR 639.25 647.25 655.25 663.25 671.25 679.25 687.25 695.25 703.25 711.25 719.25 727.25 735.25 743.25 751.25 759.25 767.25 775.25 783.25 791.25 799.25 807.25 815.25 823.25 831.25 839.25 847.25 855.25 863.25 69.25 76.25 83.25 90.25 97.25 59.25 93.25 105.25 112.25 119.25 126.25 133.25 140.25 147.25 154.25 161.25
FRANCE 639.25 647.25 655.25 663.25 671.25 679.25 687.25 695.25 703.25 711.25 719.25 727.25 735.25 743.25 751.25 759.25 767.25 775.25 783.25 791.25 799.25 807.25 815.25 823.25 831.25 839.25 847.25 855.25 863.25 104.75 116.75 128.75 140.75 152.75 164.75 176.75 188.75 200.75
GB(IRELAND) 639.25 647.25 655.25 663.25 671.25 679.25 687.25 695.25 703.25 711.25 719.25 727.25 735.25 743.25 751.25 759.25 767.25 775.25 783.25 791.25 799.25 807.25 815.25 823.25 831.25 839.25 847.25 855.25 863.25 103.25 111.25 119.25 127.25 135.25 143.25 151.25 159.25 167.25
EAST OIRT 639.25 647.25 655.25 663.25 671.25 679.25 687.25 695.25 703.25 711.25 719.25 727.25 735.25 743.25 751.25 759.25 767.25 775.25 783.25 791.25 799.25 807.25 815.25 823.25 831.25 839.25 847.25 855.25 863.25 105.25 112.25 119.25 126.25 133.25 140.25 147.25 154.25 161.25
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CH S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41
EUROPE CCIR 168.25 231.25 238.25 245.25 252.25 259.25 266.25 273.25 280.25 287.25 294.25 303.25 311.25 319.25 327.25 335.25 343.25 351.25 359.25 367.25 375.25 383.25 391.25 399.25 407.25 415.25 423.25 431.25 439.25 447.25 455.25 463.25
FRANCE 212.75 224.75 236.75 248.75 260.75 272.75 284.75 296.75 136.00 160.00 303.25 311.25 319.25 327.25 335.25 343.25 351.25 359.25 367.25 375.25 383.25 391.25 399.25 407.25 415.25 423.25 431.25 439.25 447.25 455.25 463.25
GB(IRELAND) 255.25 263.25 271.25 279.25 287.25 295.25 303.25 311.25 319.25 327.25 335.25 343.25 351.25 359.25 367.25 375.25 383.25 391.25 399.25 407.25 415.25 423.25 431.25 439.25 447.25 455.25 463.25
EAST OIRT 168.25 231.25 238.25 245.25 252.25 259.25 266.25 273.25 280.25 287.25 294.25 303.25 311.25 319.25 327.25 335.25 343.25 351.25 359.25 367.25 375.25 383.25 391.25 399.25 407.25 415.25 423.25 431.25 439.25 447.25 455.25 463.25
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1-3 ATSS sorting method The TV set sweeps all the TV bands from beginning of VHF to end of UHF. The TV controlling software for each program checks if a VPS CNI code is transmitted. If no VPS CNI code is found, the system check if a CNI code is transmitted in the teletext lines ( Packet 8/30 format 1 ). If such a code ( VPS or teletext ) is found and if this code is in the ATSS list, the program is automatically named. The programs found are then sorted in 4 groups : Group I : It contains all the programs from the selected country and named by the TV controlling software. Within this group the sorting order is fixed by the ATSS list. Group II : It contains all the programs with a strong signal strength which are not listed in group I. Group III : It contains all the programs with a weak signal strength which are not listed in group I. Group IV : If two or more programs with the same code are found, only the strongest ( or if they have the same level the one with the lowest frequency) is listed in group I, II or III. The others are listed in group IV. Note : If two programs with the same name but a different code are found these two programs are listed in group I, II or III ( e.g. Regional program SW3 in Germany ). The sorting order within group II, III, and IV is based on the channel frequency. The program with the lowest frequency is allocated the first rank in its group, and so forth until the last program of the group which has the highest frequency.
Program number 1 2 ... n n+1 ... m m+1 ... p p+1 ... q q+1 ... 99 0
Group
Skip
Group I
Group II
Group III
Group IV
Program number 1 ... m m+1 ... p p+1 ... q q+1 ... 99 0
Group
Skip
Group II
Group III
Group IV
not used
4
not used
4 Special case : Country selection = Others
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Special case : France If France is selected the TV controlling software sweeps the whole TV bands firstly with France system selected ( positive video modulation) and secondly with Europe system selected ( negative video modulation). Special case : Switzerland If Switzerland is selected the TV controlling software sweeps the whole TV bands firstly with Europe system selected (negative video modulation) and secondly with France system selected ( positive video modulation). Special case : GB Note for satellite receiver users : Before starting ATSS turn On your satellite receiver and tune " SKY NEWS ". If GB is selected the TV controlling software seeks for programs only in UHF ( C21 to C70 ). The sorting order is : 1 - BBC1 2 - BBC2 3 - ITV 4 - CH4 5 - CH5 6 - NEWS If two or more " identical "programs ( same name but different code e.g. BBC1 and BBC1 Scotland ) are found the following programs in the list will be shifted up. (1 - BBC1, 2 - BBC1, 3 - BBC2, 4 ITV, 5 - CH4, 6 - CH5, 7 - NEWS, ..) If one of the program above is not found, the associated program number remains empty ( freq.=467.25 Mhz - Skip selected - no name - system=GB). example A : 1 - BBC1, 2 - BBC2, 3 - ITV, 4 - -----, 5 - CH5, 6 - NEWS, ... example B ( if 2 BBC1 found ) : 1 - BBC1, 2 - BBC1, 3 - BBC2, 4 - ITV, 5 - -----, 6 - CH5, 7 NEWS, ...
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2 - Safety instruction WARNING: Only competent service personnel may carry out work involving the testing or repair of this equipment. X-RAY RADIATION PRECAUTION 1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION. To avoid such hazards, the high voltage must not exceed the specified limit. The nominal value of the high voltage of this receiver is 25-26 KV (20"-21") or 26 KV (25" - 28") at max beam current. The high voltage must not, under any circumstances, exceed 27.5 KV (20"), 29KV (21"), 29.5 KV (25") or 30 KV (28"). Each time a receiver requires servicing, the high voltage should be checked. It is important to use an accurate and reliable high voltage meter. 2. The only source of X-RAY Radiation in this TV receiver is the picture tube. For continued X-RAY RADIATION protection, the replacement tube must be exactly the same type tube as specified in the parts list. SAFETY PRECAUTION 1. Potentials of high voltage are present when this receiver is operating. Operation of the receiver outside the cabinet or with the back board removed involves a shock hazard from the receiver. 1) Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions necessary when working on high voltage equipment. 2) Discharge the high potential of the picture tube before handling the tube. The picture tube is highly evacuated and if broken, glass fragments will be violently expelled. If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement Parts List. When replacing a high wattage resistor (oxide metal film resistor) in circuit board, keep the resistor 10 mm away from circuit board. Keep wires away from high voltage or high temperature components. This receiver must operate under AC 230 volts, 5O Hz. NEVER connect to DC supply or any other power or frequency.
2. 3. 4. 5.
PRODUCT SAFETY NOTICE Many electrical and mechanical parts in this equipment have special safety-related characteristics. These characteristics are often passed unnoticed by a visual inspection and the X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which have these special safety characteristics are identified in this manual and its supplements, electrical components having such features are identified by designated symbol on the parts list. Before replacing any of these components, read the parts list in this manual carefully. The use of substitutes replacement parts which do not have the same safety characteristics as specified in the parts list may create X-RAY Radiation.
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3 - Alignment instructions 3-1 Microcontroller configuration : Service mode To switch the TV set into service mode please see instruction below. 1 - Select pr. number 91 2 - Adjust sharpness to minimum and exit all menu. 3 - Quickly press the key sequence : RED - GREEN - menu To exit SERVICE menu press menu key or Std By key. In Service Mode press "OK" to stop the microcontroller i.e. the I2C bus is free and the set can be controlled by external equipment. Press "OK" again to allow the microcontroller to control the set again 3-2 Microcontroller configuration : Option Option 0 1 2 3 Tuner maker DAEWOO / SAMSUNG DAEWOO / SAMSUNG SIEL PHILIPS Remark
Option 3 is available from software version 3 only
3-3 TV set Alignment 3-3-1 - G2 alignement - TV in AV mode without video signal Black screen. - TV preset with WP Red, WP Green and WP Blue equal to 32. - TV preset with Black R, Black G equal to 8. - Set TV in NORMAL I mode - Adjust screen volume ( on FBT ) such that the highest cathod cut-off voltage measured on CRT board, is Vcut off ± 5V. Screen size 20" & 21" 25" & 28" Vcut-off 125 V 140 V
3-3-2 - White balance - Select a dark picture and adjust Black G and Black R to the desired colour temperature. - Select a bright picture and adjust WP Red, WP Green, WP Blue to the desired colour temperature.
3-3-3 - Focus - Adjust the Focus volume ( on FBT ) to have the best resolution on screen.
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3-3-4 - Vertical geometry
- Adjust the Vertical Amplitude, Shift, SCorrection and Slope to compensate for vertical distortion.
3-3-5 - Horizontal picture centering - Adjust H Shift to have the picture in the center of the screen. 3-3-6 - East / West correction ( Chassis CP785 only ) - Adjust the H Parall, H Bow, H Width, EW Parabo, Up Corner, Dw Corner, EW trapez to compensate for geometrical distortion.
H. Parall
EW.Parabo
H. Bow
Up Corner
H.Width
Dw Corner
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EW Trapez
3-3-7 - AGC - Adjust the antenna signal level at 68 dBµV± 2 (UHF - CH25) - Set RF AGC to 0. - Increase RF AGC level and stop when the level on pin 6 of TDA936x goes below 2.5 Vdc
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4 - IC description 4-1 TDA936x TV signal processor - Teletext decoder with embedded µ-Controller.
TV-signal Processor l Multi-standard vision IF circuit with alignment-free PLL demodulator l Internal (switchable) time-constant for the IF-AGC circuit l Source selection between 'Internal' CVBS and external CVBS or Y/C signals l Integrated chrominance trap circuit l Integrated luminance delay line with adjustable delay time l Asymmetrical `delay line type' peaking in the luminance channel l Black stretching for non-standard luminance signals l lntegrated chroma band-pass filter with switchable centre frequency l Only one reference (12 MHz) crystal required for the µ-Controller, Teletext and the colour decoder l PAL / NTSC or multistandard colour decoder with automatic search system l Internal base-band delay line l RGB control circuit with 'Continuous Cathode Calibration', white point and black level off set adjustment so that the colour temperature of the dark and the bright parts of the screen can be chosen independently. l Linear RGB or YUV input with fast blanking for external RGB/YUV sources. The Text/OSD signals are internally supplied from the µ-Controller/Teletext decoder l Contrast reduction possibility during mixed-mode of OSD and Text signals l Horizontal synchronisation with two control loops and alignment-free horizontal oscillator l Vertical count-down circuit l Vertical driver optimised for DC-coupled vertical output stages l Horizontal and vertical geometry processing l Horizontal and vertical zoom function for 16 : 9 applications l Horizontal parallelogram and bow correction for large screen picture tubes µ-Controller l l l l l l l l l l l l l 80C51 µ-controller core standard instruction set and timing 1µs machine cycle 32 - 128Kx8-bit late programmed ROM 3 - 12Kx8-bit Auxiliary RAM (shared with Display and Acquisition) Interrupt controller for individual enable/disable with two level priority Two 16-bit Timer/Counter registers WatchDog timer Auxiliary RAM page pointer 16-bit Data pointer IDLE and Power Down (PD) mode 14 bits PWM for Voltage Synthesis Tuning 8-bit A/D converter 4 pins which can be programmed as general I/0 pin, ADC input or PWM (6-bit) output
Data Capture l Text memory 10 pages
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l Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) l Data Capture for US Closed Caption l Data Capture for 525/625 line WST, VPS (PDC system A) and Wide Screen Signalling (WSS) bit decoding Automatic selection between 525 WST/625 WST l Automatic selection between 625 WST/VPS on line 16 of VBI l Real-time capture and decoding for WST Teletext in Hardware, to enable optimised µ-processor throughput l Automatic detection of FASTEXT transmission l Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters l Signal quality detector for video and WST/VPS data types l Comprehensive teletext language coverage l Full Field and Vertical Blanking lnterval (VBI) data capture of WST data
Display l Teletext and Enhanced OSD modes l Features of lever 1.5 WST and US Close Caption l Serial and Parallel Display Attributes l Single/Double/Quadruple Width and Height for characters l Scrolling of display region l Variable flash rate controlled by software l Enhanced display features including overlining, underlining and italics l Soft colours using CLUT with 4096 colour palette l Globally selectable scan lines per row (9/10/13/16) and character matrix [12x10, 12xl3, 12x16 (VxH)] l Fringing (Shadow) selectable from N-S-E-W direction l Fringe colour selectable l Meshing of defined area l Contrast reduction of defined area l Cursor l Special Graphics Characters with two planes, allowing four colours per character l 32 software redefinable On-Screen display characters l 4 WST Character sets (GO/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) l G1 Mosaic graphics, Limited G3 Line drawing characters l WST Character sets and Closed Caption Character set in single device Data Capture The Data Capture section takes in the analogue Composite Vidéo and Blanking Signal (CVBS), and from this extracts the required data, which is then decoded and stored in memory. The extraction of the data is performed in the digital domain. The first stage is to convert the analogue CVBS signal into a digital form. This is done using an ADC sampling at 12MHz. The data and clock recovery is then performed by a Multi-Rate Video Input Processor (MuIVIP). From the recovered data and clock the following data types are extracted WST Teletext (625/525), Closed Caption, VPS, WSS. The extracted data is stored in either memory (DRAM) via the Memory Interface or in SFR locations.
Data Capture Features - Video Signal Quality detector
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- Data Capture for 625 line WST - Data Capture for 525 line WST - Data Capture for US Closed Caption - Data Capture for VPS data (PDC system A) - Data Capture for Wide Screen Signalling (WSS) bit decoding - Automatic selection between 525 WST/625WST - Automatic selection between 625WST/VPS on line 16 of VBI - Real-time capture and decoding for WST Teletext in Hardware, to enable optimised microprocessor throughput - 10 pages stored On-Chip - lnventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) - Automatic detection of FASTEXT transmission - Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters - Signal quality detector for WST/VPS data types - Comprehensive Teletext language coverage - Full Field and Vertical Blanking Interval (VBI) data capture of WST data
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TV processor version and µ-Controller capacity IC version TV range QSS sound IF amplifier with separated input and AGC circuit PAL decoder SECAM decoder NTSC decoder Horizontal geometry (E-W) Horizontal and vertical zoom ROM size RAM size Teletext IC marking and version Chassis CP 385 IC marking ( line 3 ) DW9367/N1/3-AEx ( note : x is the software version ) OSD languages English, French, German, Italian, Spanish, Dutch, Danish, Finnish, Norwegian, Swedish ATSS country GB, France, Germany, Belgium, Spain, Italy, Switzerland, Austria, Denmark, Finland, Netherlands, Norway, Sweden, Ireland, Others Poland, Hungary, Czech rep., Others GB, France, Germany, Belgium, Spain, Italy, Switzerland, Austria, Denmark, Finland, Netherlands, Norway, Sweden, Ireland, Others Text Pan-European ( West ) TDA9365 Nx / 3 110° ü ü ü ü ü ü 64 k 2k 10 pages TDA9367 Nx /3 90° ü ü ü ü
64 k 2k 10 pages
CP 385
DW9367/N1/3-ADx ( note : x is the software version ) DW9365/N1/3-BE x ( note : x is the software version )
CP 785
English, Polish, Russian, Hungarian, Czech, Slovakian, Romanian, Greek English, French, German, Italian, Spanish, Dutch, Danish, Finnish, Norwegian, Swedish
Pan-European, East, Cyrillic, Greek. Pan-European ( West )
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Chassis CP 785
IC marking ( line 3 ) DW9365/N1/3-BDx ( note : x is the software version )
OSD languages English, Polish, Russian, Hungarian, Czech, Slovakian, Romanian, Greek
ATSS country Poland, Hungary, Czech rep., Others
Text Pan-European, East, Cyrillic, Greek.
PINNING SYMBOL n.u. SCL SDA SECAM L' out OCP RF AGC in Key-in S/SW VssC/P LED 1 LED 2 VSSA SEC PLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC SIFIN1 SIFIN2 GND2 SIF AGC REF0 HOUT FBISO PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DESCRIPTION Port 1.3 Not used. I2C bus clock line I2C Data line Port 2.0 : High when L' selected (PushPull ) Port 3.0 : Over Current Protection ADC 1 : For factory use only ( High impedance ) ADC 2 : local key input ( High impedance ) ADC 3 : Scart Slow switching input digital ground for µ-controller core and peripheral port 0.5 ( 8mA current sinking capability ) port 0.6 ( 8mA current sinking capability ) analog ground of teletext decoder and digital ground of TV processor SECAM PLL decoupling 2nd supply voltage TV-processor decoupling digital supply of TV-processor phase-2 filter phase-1 filter ground 3 for TV-processor bandgap decoupling East / West drive output vertical drive B output vertical drive A output IF input 1 IF input 2 reference current input vertical sawtooth capacitor tuner AGC output SIF input 1 SIF input 2 ground 2 for TV processor AGC sound IF n.u. horizontal output flyback input / sandcastle output
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SYMBOL QSS out EHT0 PLLIF IFVO VP1 CVBSINT GND1 CVBS/Y CHROMA AMOUT INSSW2 R2IN G2IN B2IN BCLIN BLKIN R0 G0 B0 VDDA VPE VDDC OSCGND XTALIN XTALOUT RESET VDDP Audio Mute Power IR in
PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
DESCRIPTION QSS intercarrier output EHT/Overvoltage protection IF PLL loop filter IF video output main supply voltage TV-processor internal CVBS input ground 1 for TV-processor external CVBS/Y input chrominance input (SVHS) n.u. 2nd RGB insertion input 2nd R input 2nd G input 2nd B input beam current limiter input black current input RED Output GREEN Output BLUE Output analog supply of Teletext decoder and digital supply of TV-Processor (3.3V) OTP programming supply digital supply to core (3.3V) oscillator ground supply crystal oscillator input crystal oscillator output reset digital supply to periphery (3.3V) Port 1.0 : Audio mute output (PushPull ) Port 1.1 : Power output (PushPull ) Interrupt input 0 : R/C Infrared input
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4-2 MSP3415D Multistandard Sound Processor The MSP 3415D is designed as a single-chip Multistandard Sound Processor for applications in analogue and digital TV sets, video recorders, and PC cards. MSP 3415D features - sound IF input - No external filters required - Stereo baseband input via integrated AD converters - Two pairs of DA converters - Two carrier FM or NICAM processing - AVC : Automatic Volume Correction - Bass, treble, volume processing - Full SCART in/out matrix without restrictions - Improved FM-identification - Demodulator short programming - Autodetection for terrestrial TV - sound standards - Precise bit-error rate indication - Automatic switching from NICAM to FM/AM or vice versa - Improved NICAM synchronisation algorithm - Improved carrier mute algorithm - Improved AM-demodulation - Reduction of necessary controlling - Less external components Basic Features of the MSP 3415D Demodulator and NICAM Decoder Section The MSP 3415D is designed to simultaneously perform digital demodulation and decoding of NICAMcoded TV stereo sound, as well as demodulation of FM or AM mono TV sound. Alternatively, two carrier FM systems according to the German terrestrial specs can be processed with the MSP 3415D.
The MSP 3415D facilitates profitable multistandard capability, offering the following advantages: - Automatic Gain Control (AGC) for analogue input: input range: 0.10 - 3 Vpp - integrated A/D converter for sound-IF input - all demodulation and filtering is performed on chip and is individually programmable - easy realisation of all digital NICAM standards (B/G, I, L and D/K) - FM-demodulation of all terrestrial standards (include identification decoding) - no external filter hardware is required - only one crystal clock (18.432 MHz) is necessary - high deviation FM-mono mode (max. deviation: approx. ±360 kHz)
DSP-Section (Audio Baseband Processing) - flexible selection of audio sources to be processed - performance of terrestrial de-emphasise systems (FM, NICAM) - digitally performed FM-identification decoding and de-matrixing - digital baseband processing: volume, bass, treble - simple controlling of volume, bass, treble Analogue Section
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- two selectable analogue pairs of audio baseband input (= two SCART inputs) input level: <2 V RMS, input impedance: >25 k - one selectable analogue mono input (i.e. AM sound): Not used in this chassis - two high-quality A/D converters, S/N-Ratio: >85 dB - 20 Hz to 20 kHz bandwidth for SCART-to-SCART copy facilities - loudspeaker: one pair of four-fold oversampled D/A converters output level per channel: max. 1.4 VRMS output resistance: max. 5 k S/N-ratio: >85 dB at maximum volume max. noise voltage in mute mode: < 10 µV (BW: 20 Hz... 16 kHz) - one pair of four-fold oversampled D/A converters supplying a pair of SCART-outputs. output level per channel: max. 2 V RMS, output resistance: max. 0.5 k, S/N-Ratio: >85 dB (20 Hz... 16 kHz) Application Fields of the MSP 3415D In the following sections, a brief overview about the two main TV sound standards, NICAM 728 and German FM Stereo, demonstrates the complex requirements of a multistandard audio IC. NICAM plus FM/AM-Mono According to the British, Scandinavian, Spanish, and French TV-standards, high-quality stereo sound is transmitted digitally. The systems allow two high-quality digital sound channels to be added to the already existing FM/AM-channel. The sound coding follows the format of the so-called Near Instantaneous Companding System (NICAM 728). Transmission is performed using Differential Quadrature Phase Shift Keying (DQPSK. Table below offers an overview of the modulation parameters. In the case of NICAM/FM (AM) mode, there are three different audio channels available: NICAM A, NICAM B, and FM/AM-mono. NICAM A and B may belong either to a stereo or to a dual language transmission. Information about operation mode and about the quality of the NICAM signal can be read by the controlling software via the control bus. In the case of low quality (high bit error rate), the controlling software may decide to switch to the analogue FM/AM-mono sound. Alternatively, an automatic NICAM-FM/AM switching may be applied. German 2-Carrier System (DUAL FM System) Since September 1981, stereo and dual sound programs have been transmitted in Germany using the 2carrier system. Sound transmission consists of the already existing first sound carrier and a second sound carrier additionally containing an identification signal. More details of this standard are given in Tables below. For D/K very similar system is used.
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TV standards TV system B/G B/G L I D/K Position of sound carrier (MHz) 5.5 / 5.7421875 5.5 / 5.85 6.5 / 5.85 6.0 / 6.552 6.5 / 6.2578125 D/K1 6.5 / 6.7421875 D/K2 6.5 / 5.85 D/K-NICAM Sound modulation FM Stereo FM-Mono / NICAM AM - Mono / NICAM FM-Mono / NICAM FM Stereo FM-Mono / NICAM Color system PAL PAL SECAM-L PAL SECAM-East Country Germany Scandinavia, Spain France UK USSR Hungary
Architecture of MSP3415D Pin connections and short description Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Name TP NC NC TP TP ADR_SEL STANDBYQ NC I2C_CL I2C_DA Type Out Short description Test pin Not Connected Not Connected Test pin Test pin I2C bus Address select Standby ( Low-active) Not Connected I2C Clock I2C data
Out Out In In In / Out In / Out
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Pin No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Pin Name TP TP TP NC TP TP TP DVSUP DVSS NC NC NC NC RESETQ NC NC VREF2 DACM_R DACM_L NC TP NC NC NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP CAPL_M AHVSS AGNDC NC NC NC NC NC ASG2 SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN
Type In / Out In / Out Out Out Out Out
Short description Test pin Test pin Test pin Not Connected Test pin Test pin Test pin Digital power supply +5V Digital Ground Not Connected Not Connected Not Connected Not Connected Power-On-reset Not Connected Not Connected Reference ground 2 high voltage part Loudspeaker out Right Loudspeaker out Left Not Connected Test pin Not Connected Not Connected Not Connected Reference ground 1 high voltage part Scart output 1, right Scart output 1, left Not Connected Analog power supply 8.0V Volume capacitor MAIN Analog ground Analog reference voltage high voltage part Not Connected Not Connected Not Connected Not Connected Not Connected Analog Shield Ground 2 Scart input 2 in, left Scart input 2 in, right Analog Shield Ground 1 Scart input 1 in, left Scart input 1 in, right Reference voltage IF A/D converter Mono input
In
Out Out Out
Out Out
In In In In In
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Pin No. 56 57 58 59 60 61 62 63 64
Pin Name AVSS AVSUP ANA_IN1+ ANA_IN1NC TESTEN XTAL_IN XTAL_OUT NC
Type
In In In In Out
Short description Analog ground Analog power supply IF input 1 IF common Not Connected Test pin Crystal oscillator Crystal oscillator Test pin
4-3 TDA894xJ Stereo Audio Amplifier The TDA 8944J ( TDA 8946J ) is a dual-channel audio power amplifier with an output power of 2 x 7 W ( 2 x 15 W ) at an 8 W load and a 12 V supply. The circuit contains two Bridges Tied Load (BTL) amplifiers with an all-NPN output stage and standby/mute logic. The TDA8944J comes in a 17-pin DIL power package. Features Few external components Fixed gain Standby and mute mode No on/off switching plops low standby current High supply voltage ripple rejection Outputs short-circuit protected to ground, supply and across the load Thermally protected Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 Symbol OUT1GND1 Vcc1 OUT1+ n.c. IN1+ n.c. IN1IN2MODE SVR IN2+ Description negative loudspeaker terminal 1 ground channel 1 supply voltage channel 1 positive loudspeaker terminal 1 not connected positive input1 not connected negative input1 negative input2 mode selection input half supply voltage decoupling (ripple rejection) positive input2
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Block diagram TDA8944J
4-4 TDA835xJ Vertical Amplifier The TDA835xJ are power circuit for use in 90° and 110° colour deflection systems for field frequencies of 25 to 200Hz and 16/9 picture tubes. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. Due to the full bridge output circuit the deflection coils can be DC coupled. The IC is constructed in a Low Voltage DMOS process that combines Bipolar, CMOS and DMOS devices. MOS transistors are used in the output stage because of the absence of second breakdown. 4-4-1 TDA8357J Features : - Few external components - Highly efficient fully DC-coupled vertical output bridge circuit - Short rise and fall time of the vertical flyback switch - Guard circuit - Temperature (thermal) protection - High EMC because of common mode inputs
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Pinning
Pin 1 2 3 4 5 6 7 8 9
Symbol Vi(pos) Vi(neg) Vp VOB GND Vflb VOA VO(guard) VM
Description input voltage (positive) input voltage (negative) supply voltage output voltage B ground flyback supply voltage output voltage A guard output voltage input measuring resistor
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4-4-1 TDA8358J An East-West output stage is provided that is able to sink current from the diode modulator circuit. Features : - Few external components - Highly efficient fully DC-coupled vertical output bridge circuit - Short rise and fall time of the vertical flyback switch - Guard circuit - Temperature (thermal) protection - High EMC because of common mode inputs - East-West output stage
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4-5 TDA6107Q The TDA6107Q includes three video output amplifiers in one plastic DIL-Bent-SIL 9-pin medium power package, using high voltage DMOS technology, and is intended to drive the three cathodes of a colour CRT directly. To obtain maximum performance, the amplifier should be used with black-current control. Features - Typical bandwidth of 5.5 MHz for an output signal of 60 Vpp - High slew rate of 900V/ms - No external components required - Very simple application - Single supply voltage of 200V - Internal reference voltage of 2.5 V - Fixed gain of 50. - Black-current stabilisation (BCS) circuit - Thermal protection Pin description
Pin 1 2 3 4 5 6 7 8 9
Symbol Vi(1) Vi(2) Vi(3) GND Iom VDD VOC(3) VOC(2) VOC(1)
Description inverting input 1 inverting input 2 inverting input 3 ground (fin) black current measurement output supply voltage cathode output 3 cathode output 2 cathode output 1
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Block diagram TDA6107Q
4-6 24C08 8 Kbit EEPROM features : - 8 Kbit serial I2C bus EEPROM - Single supply voltage : 4.5 V to 5.5 V - 1 Million Erase/Write cycles (minimum) - 40 year data retention (minimum) Pin description Pin No. 1, 2, 3 5 6 7 8 4 Name E0, E1, E2 SDA SCL WC Vcc Vss Description Device address Serial Data/Address Input/Output Serial clock Write control Supply voltage Ground
The memory device is compatible with the I2C memory standard. This is a two wire serial interface that uses a bi-directionnal data bus and serial clock. The memory carries a built-in 4-bit unique device type identifier code (1010) in accordance with the I2C bus definition. Serial Clock (SCL) The SCL input is used to strobe all data in and out of the memory. Serial Data (SDA) The SDA pin is bi-directionnal, and is used to transfer data in or out of the memory
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4-7 STR - F6653 4-7-1 General description The STR-F6653 is an hybrid IC with a build-in MOSFET and control IC, designed for flyback converter type switch mode power supply applications.
4-7-2 Features - Small SIP fully isolated molded 5 pins package - Many protection functions : * Pulse-by-pulse overcurrent protection (OCP) * Overvoltage protection with latch mode (OVP) * Thermal protection with latch mode (TSD) 4-7-3 Block diagram
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4-7-4 Pins description
pin 1 2 3 4 5
name Overcurrent / feedback Source Drain Supply Ground
symbol O.C.P./ F.B. S D VIN GND
description Input of overcurrent detection signal and feedback signal MOSFET source MOSFET drain Input of power supply for control circuit Ground
4-7-5 Control part electrical characteristics
description Operation start voltage Operation stop voltage Circuit current in operation Circuit current in non-operation Maximum OFF time Minimum time for input of quaxi resonant signals Minimum off time O.C.P./F.B. terminal threshold voltage 1 O.C.P./F.B. terminal threshold voltage 2 O.C.P./F.B. terminal extraction current O.V.P. operation voltage Latch circuit sustaining voltage Latch circuit release voltage Thermal shutdown operating temperature
IC pins number 4-5 4-5 4-5 4-5 1-5 1-5 1-5 1-2 4-5 4-5 4-5 -
symbol VIN (on) VIN (off) IIN (on) IIN (off) TOFF (max) TTH (2) TOFF (min) VTH (1) VTH (2) IOCP/FB VIN (OVP) IIN (H) VIN (La.off) TJ (TSD) min. 14.4 9 45 0.68 1.3 1.2 20.5 6.6 140
rating typ. 16 10 0.73 1.45 1.35 22.5 -
unit max. 17.6 11 30 100 55 1.0 1.5 0.78 1.6 1.5 24.5 400 8.4 V V mA µA µsec µsec µsec V V mA V µA V 0 C
4-7-6 MOSFET electrical characteristics
description Drain-to-source breakdown voltage Drain leakage current On-resistance Switching time Thermal resistance
IC pins number 3-2 3-2 3-2 3-2 -
symbol VDSS IDSS RDS (on) tf CH -F min. 650 -
rating typ. -
unit max. 300 1.95 250 1.25 V µA nsec 0 C/W
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5 - Circuit description 5-1 Block diagram
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FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR Vision IF amplifier The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL demodulator is completely alignment-free.
The VCO of the PLL circuit is internal and the frequency is fixed to the required value by using the clock frequency of the µ-Controller/Teletext decoder as a reference. The setting of the various frequencies is made by the controlling software in subaddress 27H (38.9 Mhz for all system except L' or 33.9 MHz for system L'). Because of the internal VCO the IF circuit has a high immunity to EMC interferences.
QSS Sound circuit The sound IF amplifier is similar to the vision IF amplifier and has an external AGC decoupling capacitor.
The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved.
Video switches The video switch has one input for an external CVBS or Y/C signal. The selected CVBS signal can be supplied to pin 38, the IF video output. The selection between both signals is realised by the controlling software in subaddress 22H. The video ident circuit is connected to the selected signal. This ident circuit is independent of the synchronisation.
Synchronisation circuit The IC contains separator circuits for the horizontal and vertical sync pulses and a data-slicing circuit which extracts the digital teletext data from the analogue signal. The horizontal drive signal is obtained from an internal VCO which is running at a frequency of 25 MHz. This oscillator is stabilised to this frequency by using a 12 MHz signal coming from the reference oscillator of the µ-Controller/Teletext decoder. The horizontal drive is switched on and off via the soft start/stop procedure. This function is realised by means of variation of the TON of the horizontal drive pulses. The vertical synchronisation is realised by means of a divider circuit. The vertical ramp generator needs an external resistor and capacitor. For the vertical drive a differential output current is available. The outputs are DC coupled to the vertical output stage.
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In the type TDA9367, intended for 90° picture tubes the following geometry parameters can be adjusted: · Horizontal shift · Vertical amplitude · Vertical slope · S-correction · Vertical shift The types which are intended to be used in combination with 110° picture tubes have an East-West control circuit. The additional controls for these types are: · EW width · EW parabola width · EW upper and lower corner parabola correction · EW trapezium correction · Vertical zoom, horizontal parallelogram and bow correction.
Chroma and luminance processing The chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by means of gyrators and are tuned to the right frequency by comparing the tuning frequency with the reference frequency of the colour decoder. The luminance delay line and the delay cells for the peaking circuit are also realised with gyrators. The circuit contains a black stretcher function which corrects the black level for incoming signals which have a difference between the black level and the blanking level.
Colour decoder The ICs can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need external reference crystals but has an internal clock generator which is stabilised to the required frequency by using the 12 MHz clock signal from the reference oscillator of the µ-Controller/Teletext decoder.
The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 2OH) prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function.
SOFTWARE CONTROL The CPU communicates with the peripheral fonctions using Special function Registers (SFRS) which are addressed as RAM locations. The registers for the Teletext decoder appear as normal SFRs in the µ-Controller memory map and are written to these functions by using a serial bus. This bus is controlled by dedicated hardware which uses a simple handshake system for software synchronisation. For compatibility reasons and possible re-use of software blocks, the TV processor is controlled by I2C bus. The TV processor control registers cannot be read. Only the status registers can be read ( Read address 8A ). The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, via the divided 12 MHz reference frequency (obtained from the µ-Controller) which is used to tune the PLL to
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the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode.
The base-band delay line (TDA 4665 function) is integrated. This delay line is also active during NTSC to obtain a good suppression of cross colour effects. The demodulated colour difference signals are internally supplied to the delay line.
RGB output circuit and black-current stabilisation In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The ICs have a linear input for external RGB signals. The signals for OSD and text are internally supplied to the control circuit. The output signal has an amplitude of about 2 Volts black-to-white at nominal input signals and nominal settings of the various controls. To obtain an accurate biasing of the picture tube the 'Continuous Cathode Calibration' system has been included in these ICs. A black level off set can be made with respect to the level which is generated by the black current stabilisation system. In this way different colour temperatures can be obtained for the bright and the dark part of the picture. The black current stabilisation system checks the output level of the 3 channels and indicates whether the black level of the highest output is in a certain window or below or above this window. This indication is read from the status byte 01 and is used for automatic adjustment of the Vg2 voltage during the production of the TV receiver.
During switch-off of the TV receiver a fixed beam current is generated by the black current control circuit. This current ensures that the picture tube capacitance is discharged. During the switch-off period the vertical deflection is placed in an overscan position so that the discharge is not visible on the screen.
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5-2 IF The TDA936x has an alignment free IF PLL demodulator. The fully integrated oscillator is automatically calibrated, using the 12 Mhz crystal as a frequency reference. The IF frequency is simply set in TV-Processor by I2C bus. The AFC information is available via I2C bus from the TV-Processor status bytes. The controlling software uses this information for tuner frequency tracking ( automatic following ). The AFC windows is typically 125Khz wide. The minimum frequency step of the tuner is 62.5 Khz. This AFC function is disabled when a program is tuned using the direct frequency entry or after fine tuning adjustment. Therefore it is recommended to tune channel with the TV search function ( manual or ATSS ) or using the direct channel entry to enable the Automatic Frequency Control. SAW filters Ref. K3953M Standard B/G - D/K - I - L/L' Features - IF filter for video application - TV IF filter with Nyquist slopes at 33.9 MHz and 38.9 MHz - Constant group delay - IF filter for audio application - TV IF audio filter with two channels - Channel 1 (L') with one pass band for sound carrier at 40.40 MHz - Channel 2 ( L, D/K, I, B/G) with one pass band for sound carriers between 32.40 MHz and 33.40 MHz
K9650M
B/G - D/K - I - L/L'
For SECAM L and L' the TDA936x is switched to positive modulation via I2C bus. SECAM L' only occur in VHF band I and have their picture and sound carrier interchanged, compared to SECAM L and PAL B/G channels. For SECAM L' the picture carrier is situated at 33.9 MHz and the AM sound carrier at 40.40 MHz. The IF PLL reference is tuned from 38.9 to 33.9 Mhz, this is done via I2C Bus and the SIF filter is switched from channel 2 to channel 1 ; this is done by pin 4 of TDA 936x. The tuner AGC time constant is slower than for negative modulation, because the TDA936x reduces its AGC current. To even slower the AGC time constant an extra series resistor R103 is added. To prevent IF overload when jumping from a very strong transmitter to a weak transmitter a diode D101 has been added The SAW filter ( SF1 ) has a double Nyquist slope at 38.9 MHz and 33.9 MHz needed for this multistandard application. The disadvantage of this choice is that a 5.5 MHz trap filter ( Z501 ) is needed to suppress the residual sound carrier in the video for B/G signals.
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Chassis block diagram : IF
- 38 -
5-3 Source switching The TDA936x has only one external video input, the external video switching circuit made with Q504, Q505, Q507, Q508 and Q509 allows 2 external video signal inputs. The switching command can be either the SCART1 slow switching pin 8 or the µ-Controller pin 8 when the software takes control of the video source. The µ-Controller pin 8 is automatically configured by the controlling software ( See table below ). This pin is also capable of detecting the 3 Status ( 0, 1A, 1B ) described in SCART specifications for automatic format switching ( chassis CP785 only ).
TV mode RF auto RF Forced AV 1 Auto 4:3 AV 1 Auto 16:9 AV 1 forced AV 2 SVHS
µ-Controller pin 8 Status Input - High Impedance Input - High Impedance Input - High Impedance Input - High Impedance Output - Push Pull Output - Push Pull Output - Push Pull
Level < 1V not defined > 2.0 V 1 V < x < 2.0 V Max. 3.3V < 0.2 V < 0.2 V
The controlling software via I2C bus selects the signal source : - Video signal from tuner ( Pin 40 ). - External video ( SCART 1 or 2 ) depending on Q508 base level. - External SVHS from SCART 2. The sound source switching is done in the MSP3415D ( I601 ), by the µ-Controller via I2C bus. Fast R, G, B insertion : The external R, G, B insertion needs a fast switching and cannot be controlled by the software ( instruction cycle of 1µ sec ). The fast switching pin 16 of SCART 1 is directly connected to the TV processor pin 45 ( Fast blanking input ). The display is synchronised with the selected video source, i.e. to get stable R, G, B inserted signal they must be synchronised with the selected video source. The controlling software only enable or disable ( AV2, SVHS, or Forced RF source selected ) fast blanking. 5-4 µ-Controller I/O pin configuration and function The I/O pins of the µ-Controller can be configured in many way. All port functions can be individually programmed by use of the SFR registers. Each I/O port pin can be individually programmed in these configurations : Open drain In this mode, the port can function as in and output. It requires an external pull-up resistor. The maximum allowable supply voltage for this pull up resistor is +5V. So in this mode it is possible to interface a 5 Volt environment like I2C while the µ-Controller has a 3.3 Volt supply.
Push-Pull The push pull mode can be used for output only. Both sinking and sourcing is active, which leads to sleep slopes. The levels are 0 and Vddp, the supply voltage 3.3Volts.
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High impedance This mode can be used for input only operation of the port. Special port for LED Pin 10 and 11 have the same functionality as the general I/O pins but in addition, their current source and sink capacity is 8 mA instead of 4 mA. These pins are used for driving LED's via a series current limiting resistor.
µ-Controller I/O pin configuration and function table pin 1 2 3 4 5 name n.u. SCL SDA SECAM L' OCP configuration Stand by TV ON High impedance High impedance Open Drain Open Drain Open Drain Open Drain High impedance Push Pull High impedance High impedance description not used Serial clock line Serial data line SIF filter swiching Over Current Protection ( Switch the set OFF if the voltage on this pin is <2.33V ) For factory use only Local keyboard input external video switch
6 7 8 10 11 62
Key in S/SW Red LED Green LED Audio mute
High impedance High impedance High impedance High impedance Open Drain Push Pull
High impedance High impedance See table above Open Drain High impedance Push Pull
High in stand by mode
5-5 Sound processing Analogue sound IF - input section The input pins ANA_IN1+ and ANA_IN- offer the possibility to connect sound IF sources to the MSP 3415D. The analogue-to-digital conversion of the preselected sound IF signal is done by an A/D converter, whose output is used to control an analogue automatic gain circuit (AGC), providing an optimal level for a wide range of input levels. Quadrature Mixers The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two programmable quadrature mixers, two different audio sources ; for example, NICAM and FM-mono, may be shifted into baseband position. Phase and AM discrimination The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude information, whereas the phase information serves for FM and NICAM demodulation.
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In case of NICAM - mode, the phase samples are decoded according the DQPSK - coding scheme. The output of this block contains the original NICAM bitstream. DSP section All audio baseband functions are performed by digital signal processing (DSP). The DSP section controls the source and output selection, and the signals processing. Sound Mode switching In case of NICAM transmission, the controlling software read the bit error rate and the operation mode from the NICAM Decoder. When the set is in "Auto detection" mode ( default mode after ATSS ) the controlling software set automatically the sound mode ( NICAM mono, NICAM Dual 1 or NICAM Dual 2 ) depending on the transmitted mode. In case of 2 Carrier FM transmission, the controlling software read the transmission mode and the signal quality level from the Stereo Detection Register. When the set is in "Auto detection" mode the controlling software set automatically the sound mode ( mono, Stereo, Dual 1, Dual 2 ) depending on the transmitted mode. In "Auto detection" mode the controlling software evaluate the signal quality and automatically switch to the analogy sound carrier 1, if the transmission quality is too poor. To avoid unwanted automatic switching the threshold levels mono to stereo and stereo to mono is different. In "forced mono " mode ( Red OSD in recall section ), the controlling software configure the MSP3415D to demodulate only the analogue (FM or AM) sound carrier 1, no matter the signal quality. The sound mode " forced " or " Autodetect" is stored for each programme.
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Sound signal flow diagram
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5-6 Sound amplification The TDA8944J (TDA8946J) is a stereo BTL audio amplifier capable of delivering 2 x 7 W (2 x 15 W) output power to an 8 load at THD = 10%, using a 12 V power supply and an external heatsink. The voltage gain is fixed at 32dB. With the three-level MODE input the device can be switched from `standby' to `mute' and to `operating' mode. The TDA 8944J outputs are protected by an internal thermal shutdown protection mechanism and short-circuit protection. Power amplifier The power amplifier is a Bridge Tied Load (BTL) amplifier with an all-NPN output stage, capable of delivering a peak output current of 1.5 A. The BTL principle offers the following advantages : - Lower peak value of the supply current. - The ripple frequency on the supply voltage is twice the signal frequency. - No DC-blocking capacitor - Good low frequency performance Mode selection The TDA894xJ has several functional modes, which can be selected by applying the proper DC voltage to pin MODE. Mute : In this mode the amplifier is DC biased but not operational (no audio output). This allows the input coupling capacitors to be charged to avoid pop-noise. The devices is in mute mode when 2.5 V < VMODE < (Vcc-1.5 V). Operating : In this mode the amplifier is operating normally. The operating mode is activated at VMODE < 0.5 V. 5-7 Vertical deflection The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. The differential input circuit is voltage driven. The input circuit is especially intended for direct connection to driver circuits which deliver symmetrical current signals, but is also suitable for asymmetrical currents. The output current of these devices is converted to voltages at the input pins via resistors R350 and R351. The differential input voltage is compared with the output current through the deflection coils measured as voltage across R302, which provides internal feedback information. The voltage across R302 is proportional to the output current. Flyback voltage The flyback voltage is determined by an additional supply voltage Vflb. The principle of operation with two supply voltages (class G) makes it possible to fix the supply voltage Vp optimum for the scan voltage and the second supply voltage Vflb optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage Vflb is almost totally available as flyback voltage across the coil, this being possible due to the absence of a coupling capacitor. Protection The output circuit has protection circuits for : - Too high die temperature - overvoltage of output stage A Guard circuit The guard signal is not used by the TDA936x to blank the screen in case of fault condition. Damping resistor
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For HF loop stability a damping resistor (R305) is connected across the deflection coil. EAST-WEST Amplifier (TDA8358J only) The East-West amplifier is current driven. It can only sink currents of the diode modulator circuit. A feedback resistor R397 is connected between the input and output of this inverting amplifier in order to convert the East-West correction input into an output voltage.
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5-8 Power supply (STR-F6653) 5-8 -1 STR-F6653 general description The STR-F6653 is an hybrid IC with a build-in MOSFET and control IC, designed for flyback converter type switch mode power supply applications. 5-8 -2 Power supply primary part operations An oscillator generates pulses signals which turn on and off a MOSFET transistor. * Start -up circuit: VIN The start-up circuit is used to start and stop the operation of the control IC, by detecting a voltage appearing at VIN pin (pin 4).
T801 SMPS TRANS
2 D801 C804 D804
4
6 R805 D805
7
R819
D802
C803
D803
C805 L801
R802 C806 3 Drain Main AC voltage I801 STR-F6653 Ground
5
4 Vin
Power supply start-up circuit
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When the power switch is pushed on, VIN increases slowly. During this time, C806 is charged through R802. As soon as VIN reaches 16V, the STR-F6653 control circuit starts operating. Then, VIN is obtained by smoothing the winding voltage which appears between pin6 and pin7 of the SMPS transformer. As this winding voltage does not increase to the set voltage immediately after the control circuit starts operating, VIN starts dropping. However, as this winding voltage reaches the set value before VIN voltage drops to the shutdown voltage (at 11V), the control circuit continues operating (see below VIN voltage at start-up). R805 resistor prevents that VIN pin voltage varies according to the secondary side output current. VIN must be set higher than the shutdown voltage (VIN (off) = 11Vmax) and lower than the O.V.P. (overvoltage protection) operating voltage (VOVP = 20.5Vmin)
Vin O.V.P.voltage 20.5V
16V (TYP.)
Shutdown voltage 11V
t
Waveform of Vin pin voltage at start-up
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* STR-F6653 oscillating operation
3
TO PIN4 SM PS
STR-F6653
DRIVE
Rg2 DRAIN
Rg1
Comp.1 2 OSC V th(1) SOURCE 1 1.35mA OCP/FB R808
From PIN 6 SM PS (FEEDBACK) C850 R804
V th(2) Comp.2
C1
R1
5 GND
Oscillating operation
1 3 C1 (ST R -F 6 6 5 3 internal capacitor) 3.7V 4 2 6.5V
0.73V Pin 1 (O C P / F B ) 0V
I
D
(M O S F E T d r a i n c u r r e n t )
V
D S
(M O SFET drain - source voltage)
M O S F E T
sw i t c h i n g O N / O F F
O N
OFF
O N
OFF
O N
OFF
Waveforms during oscillating operation
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¬ When the MOSFET is ON, the STR-F6653 internal capacitor C1 is charged at the constant voltage 6.5V. At the same time, the voltage at pin 1 (OCP / FB) increases with the same waveform as the MOSFET drain current. - When the pin 1 voltage reaches the threshold voltage VTH1 = 0.73V, the STR-F6653 internal comparator 1 starts operating. The STR-F6653 internal oscillator is inverted and the MOSFET turns OFF. ® When the MOSFET turns OFF, charging of STR-F6653 internal capacitor C1 is released and C1 starts discharging by the STR-F6653 internal resistance R1. So, C1 voltage starts falling in accordance with the gradient regulated by the constant discharging time of C1 and R1. So, this means that the fixed time determined by C1 and R1 is the OFF-time of the MOSFET. ¯ When C1 voltage falls to around 3.7V, the STR-F6653 internal oscillator is reversed again and the MOSFET turns ON. C1 is quickly charged to around 6.5V The MOSFET continues to oscillate by repeating the above procedure. * STR-F6653 protection circuits · overcurrent protection function (OCP) Overcurrent protection is performed pulse by pulse detecting at STR-F6653 pin 1 (OCP) the peak of the MOSFET drain current in every pulse. · latch circuit This circuit sustains an output low from the STR-F6653 internal oscillator and stops operation of the power supply when overvoltage protection (OVP) and thermal shutdown (TSD) circuit are under operation · thermal shutdown circuit (TSD) This circuit triggers the latch circuit when the frame temperature of STR-F6653 IC exceeds 140°C · overvoltage protection circuit (OVP) This circuit triggers the latch circuit when the Vin voltage exceeds 22V (typ.)
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5-9 TV start-up, TV normal run and stand-by mode operations 5-9-1 TV start-up operations * Schematic diagram for start-up operations
I823 REG 3.3V IN 1 GND 2 OUT 3 IN RESET PULSE CIRCUIT OUT L511 L512
12 8V T801 SMPS TRANSFORMER 2 4
L510 61 56 54 Vddp Vddc VddA
60 Reset N
63 Power
I501 MICROCONTROLLER PART SCL 2 SDA 3
L801 D801... D804 (GRAETZ BRIDGE)
3 D I801 MOSFET AND
6
5 I702 EEPROM
SW801 POWER SWITCH
CONTROL IC
MAIN AC VOLTAGE
Start-up operations * TV start-up and microcontroller initialization - When SW801 power switch is pushed, main AC voltage is applied to T801 transformer (after rectification by D801...D804 diodes). Then, T801 SMPS transformer starts operating and supplies DC voltage to I823 (3.3V regulator). - This regulator provides 3.3V DC voltage to I501 microcontroller power supply pins (pins 54, 56, 61) and to the reset pulse circuit which provides reset pulse to I501 microcontroller reset pin (pin 60). - Then, the microcontroller starts its initialization. Its power pin (pin 63) is set to high which allows delivery of power supply voltages (123V, 8V, 5V...). At this step, all IC's start working but no picture appears on screen: I501 IC doesn't provide horizontal drive voltage. - Then, the microcontroller consults I702 EEPROM via I2C bus to know the last TV set mode (normal run mode or stand-by mode ) before switching off.
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. If the TV set was on normal run mode before switching off, the microcontroller delivers horizontal drive voltage at pin 33 and picture appears on screen. . If the TV set was on stand-by mode before switching off, the microcontroller switches TV set to stand-by mode, decreasing power pin voltage (pin 63). This matter will be explained on paragraph 5-9-2-b. * Reset pulse circuit
from I823 pin 3
R591 220 D591 DZ2.4
Q510 R592 10k
R594 10K
Q511
+
R593 10K
C501 50V 10µ F
to I501 pin 60
3.0V
3.3V
1.2V DC supply voltage I823 pin 3 0V 3.0V
1.2V
reset pulse I501 pin 60
0V
Reset pulse circuit and corresponding waveforms
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* Reset pulse circuit operations description - When DC supply voltage from I823 regulator starts rising (from 0V to 1.2V), no current flows through D591 zener diode. So, Q510 is in off mode. Also Vbe Q511 =Vcc/2 -Vcc = -Vcc/2 > -0.6V. So, Q511 is in off mode. Then, no voltage reaches I501 pin 60. - When this voltage reaches 1.2 V, Q510 stays in off mode but Vbe Q511 = -0.6V. So, Q511 is switched on and starts driving DC supply voltage to I501 pin 60. - When the DC supply voltage reaches (2.4V +0.6V ) =3.0V, Q510 starts conducting but as the Q511 base-emitter voltage is the same as the collector-emitter voltage of the saturated Q510, Q511 switches off and no voltage reaches I501 pin 60. - If the DC supply voltage decreases below 3 V, Q510 switches off immediately. Q511 starts conducting, pulling I501 pin 60 high. At the same time, it discharges the reset capacitor C501. Discharging this capacitor is necessary to garantee a defined reset pulse duration.
5-9-2 TV normal run and stand-by mode operations Depending on remote control commands, I501 microcontroller part pin 63 (power) is set to: - high for normal run mode - low for stand-by mode a) TV on normal run mode * I501 microcontroller part pin 63 (power) effect I501 microcontroller part pin 63 (power) is connected to the following circuit:
6V D C I810 C O N T R O L L E D R E C T IF IE R 11V DC L O W R870 R830 R820 C830 Q 811 L O W Q 807 C O N D U C T IN G Q 808 H IG H L O W L O W Q 810 N O T C O N D U C T IN G Q 809 R829 D811
H IG H
POW ER H IG H
I501 microcontroller part pin 63 (POWER) effect
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On normal run mode, I501 microcontroller pin 63 (power) is set to high · So, I810 controlled rectifier is not conducting - Q809 is conducting. So, Q808 is not conducting and Q807 is conducting - So, Q807 collector is connected to the ground and I810 controlled rectifier gate pin is set to low (no conducting) · So, current from 11V DC voltage (from T801 SMPS transformer pin 13) does not flow through Q811 and Q810 transistors but flows through I806 IC error amplifier - Q809 is conducting. So, Q810 is not conducting and no current flows from Q810 collector to the ground Therefore, the power supply circuit diagram is the one shown on the next paragraph * power supply circuit diagram during TV set normal run
5V 14.5V (CP785) 12.5V (CP385) 3 I820 5V REGULATOR 3 I823 3.3V REGULATOR 3.3V
1
1
6V 11V 1 D820
C832 C861 D860 D830
C823
822 8V
REGULATOR
3
8V
D831 13 11.5V 11V 16 143V 123V / 113V
C813 R823
9 14.5V 12.5V
143V (CP785) 123V-113V (CP385)
12 8.5V 8V
T801 SM PS TRANSFORM E R
1 I806 IC E R R O R A M P L I F I E R 2 3
2
4 R810 11V L801
D801... D804 (G R A E T Z B R ID G E )
3 D I801 M O SFET AND C O N T R O L IC
SW 801 POW ER SW ITCH
M A IN A C V O L T A G E
Power supply operation during TV set normal run
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* power supply functioning during TV set normal run mode
- I801 transmits controlled pulses to T801 which generates DC voltages after rectifications by secondary part diodes and electro capacitors (by example by D820 and C813 on 143V (CP785) / 123V -113V (CP385) supply voltage line). - 8V, 5V, 3.3V supply voltage lines have stabilized voltages obtained by I820, I822, I823 voltage regulators. - On 143V (CP785) / 123V-113V (CP385) supply voltage line, R823 resistor has been chosen to reach exact DC voltage required on this line. - 143V (CP785) / 123V-113V (CP385) supply voltage line includes an IC error amplifier (I806) which corrects unexpected DC voltage variations on this line. * power supply IC delivery during TV set normal run power supply line 143V (CP785) 123V-113V (CP385) IC power supply delivery Remarks FBT supplies 45V to I301 vertical IC FBT supplies 45V to T401 H- drive for CP785 FBT supplies 14V to I301 vertical IC FBT supplies 33V to the tuner FBT supplies 185V to I901 video amplifier pin 6
FBT
14.5V (CP785) 12.5V (CP385) 11V 8V
I602 sound amplifier pins 3-16 T401 H- drive I501 Main IC pins 14-39 I601 Sound Demod pins 38-3940 I703 IR receiver pin 1 I601 Sound Demod pins 7-1857 I702 EEPROM pin 8 tuner Main IC µcom part pins 54-5661
6V 5V
3.3V
b) TV set on stand-by mode * TV set circuit diagram on stand-by mode
- 53 -
I810 CONDUCTING controlled rectifier 1 D821
HIGH
I823 3.3V REGULATOR
3
C840 C841
AROUND 6V dc AROUND 3.3Vdc
16
D825
T801 SM PS TRA N S
R810 R713
2
4 D806 L801
8