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INTEGRATED CIRCUITS
ESG89001 Electro magnetic compatibility and printed circuit board (PCB) constraints
June 1989
Philips Semiconductors
Philips Semiconductors
Application note
Electro magnetic compatibility and printed circuit board (PCB) constraints
ESG89001
1.
INTRODUCTION
The routing of the traces on a Printed Circuit Board (PCB) largely effect the ElectroMagnetic Compatibility (EMC) performance of the PCB with respect to both ElectroMagnetic (EM) radiation as susceptibility to EM-fields. The PCB will connect electronic components such as passive components, transistors and ICs. Furthermore, cables to interconnect the PCB with other system parts, e.g., another PCB, signal generator, CATV wall-outlet, DC power source or an AC-mains connection, will largely influence the PCB with respect to EMC [7]. In order to get a PCB on which the circuits function properly, the trace routing, the placement of components/connectors and the decoupling used with certain ICs will have to be optimized according to the constraints given in this report. To reach an economic and functional PCB design, the following items have to be kept in mind: 3. Correct choice of the PCB format (mono, bi- or multi-layer) 4. Take care that "every" signaltrace has its signalreturn nearby 5. Proper decoupling for each IC or group of ICs 6. Allowed tracelengths and allowed loopareas 7. Placement of the connectors 8. Right cable choice with a proper connector 9. Proper use and placement of filters and filterparts.
These items with the appropriate measures will be further explained. The main target is to get control over your PCB currents.
2.2. Transmissionlines
By using the inductance of a single wire, Li, the mutual coupling, M, and the capacitance between the traces, Ci, a transmissionline, shown in Figure 2, can be defined of which the characteristic impedance, ZO, equals: ZO = (Leff / C) where: Leff = L1 + L2 2M, k = (L1 + L2) / M and C = C1 + C2. When the coupling, k, between the traces of the transmissionline is high, the effective inductance will decrease rapidly. Some coupling factors are given in Table 1. An indifferent signal path design (Figure 3a) can be changed into a transmissionline design (Figure 3b). This change will lower the effective inductance, Leff, between the two circuit blocks and will therefore lower the voltage drop between the two references of those circuits.
2.
GENERAL
2.1. Conductors
Single conductors have, as a rule of thumb, an inductance of 1µH/m. At low frequencies only, below 1kHz, Rdc applies. These impedances, together with the currents that will flow through these impedances, will be responsible for the voltage drop between points as Ohms law applies. The voltage drop can be diminished by either reducing the impedance or lowering the current through that impedance. In typical digital designs the voltage drop will be frequency independent. A square wave current, resulting from a square wave output voltage to a resistive load, can be described as a series of sinewaves of which the amplitude of the harmonics decrease proportional with the frequency (Fourier expansions), see Figure 1b. The impedance of the inductor increases proportional with frequency (see Figure 1a), therefore the product; voltage drop (Figure 1c) remains constant. When the current has a triangular waveshape, as function of time, due to capacitive loading, the amplitude of the harmonics decreases with the frequency square and the voltage drop across the inductor reduces proportional with frequency.
Table 1. Coupling Factors between the Conductors of a Transmissionline
TRANSMISSIONLINE TYPE Parallel wires Bi-layer PCB Multi-layer PCB Coaxial cable RG-58 coax COUPLING 0.5 0.7 0.6 0.9 0.9 0.97 0.8 1.0 0.996
Z = f(freq)
×
I = g(freq)
=
V = h(freq)
Z
×
I
=
V
> f
> f
> f
Figure 1. The relation between voltage drop as a result of current and impedance as function of frequency
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Signal line L1 C1 M R1 PCB #1 C2 Signal line L2 R2 VEE, VCC (a) Indifferent signal path NO coupling between SVEE, VCC VEE, VCC (b) Transmission line signal path GOOD coupling between SVEE, VCC PCB #2
Figure 2. A segment of a transmissionline and its network elements
Figure 3. Typical signal path design on a PCB
S2 single layer: d(S1GND) < d(S2S1)
S1
GND
S1
GND
S2
(a)
(b)
S1 bi-layer: (c) d(S1GND) < d(S2S2) or (d) d(S1GND) and d(S2GND) < d(S1S2) GND (c)
S2
S1
S2
S2
GROUND PLANE (d)
S1 VEE multi-layer: d(SiVEE) or d(SiVCC) < d(SiSj) 1 i, j number of traces VCC S3 S4 (e) 5-layer
S2 VEE VCC S1 S2
S5
S3 (f) 4-layer
Figure 4. Typical applications of the PCB-format
2.3. Capacitive and Inductive Coupling
Separately, the capacitive and inductive values, derived from the definition of the transmissionline, can also be used to calculate the crosstalk between adjacent traces, not being a function signal path. The capacitive coupling, representing and induced current, is given by: ICk = 1/CkdV/dt, where: Ck = coupling capacitance between adjacent traces; in practice: 100pF/m
(depends upon the vicinity of other traces, see Appendix A), and the inductive coupling, representing an induced voltage, is given by: VMk = MkdI/dt, where: Mk = mutual coupling between two traces (For further detail see Chapter 4.) In both coupling modes, the transfer function will typically show a high pass behavior.
3.
CHOICE OF THE PCB-MATERIAL
By a proper choice of the PCB-material and the routing of the traces, a good transmissionline with low coupling to other traces can be created. Low coupling, or little crosstalk, can be obtained when the distance, d, between the transmissionline conductors is less than their distance to other adjacent conductors (see Figure 4). By using these examples of geometry of traces the definition of the transmissionline between S1, S2, Si, j and (S2) GND, VEE and/or VCC are well defined and the coupling between the traces S2 and S1 is low.
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Electro magnetic compatibility and printed circuit board (PCB) constraints
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The most economic PCB format has to be chosen based on: the legal and/or functional EMC requirements for the product, trace density, assembly and manufacturer capabilities, CAD-system capabilities, design-costs, PCB quantities, and the costs of EM-shielding. Special attention must be given to the integral costs (components packaging/pinning + PCB-format + EM-shielding + construction + assembly) when a product definition is considered by using a NON-shielded cover. In many cases the choice of a proper PCB-format may expel the need for a metallized box within the plastic cover. To improve immunity and to lower unwanted emission, both in fast analog and all digital applications, transmissionlines are needed. Dependent upon the transition of the output signal, a transmissionline needs to be present between SVCC, SVEE, and VEEVCC, as indicated in Figure 5. The signal current will be determined by the output-stage symmetry of the circuit. For MOS: IOL = IOH, while for TTL: IOL > IOH. The Logic Family and functional reasons determine the typical characteristic impedance, ZO, for that transmissionline which is given in Table 2.
For two traces next to each other the following formula applies [10, 11]. ZO + where: h = distance between traces b = width of the trace c = thickness of the trace; typical 17µm, for two traces on top of each other: ZO + where: h = 1.5mm (typical thickness of epoxy). When the trace is above a goundplane the following formula applies: ZO + 87 ln(6.h (.8.b ) c)) (å 120 p (h (h ) b)) å 120 1n(p.h (b ) c)) å
4.
THE SIGNALTRACE AND ITS SIGNALRETURN
r
Signaltraces need to have their signal-returntraces as close as possible in order to prevent emission from that looparea enclosed by these traces and to reduce susceptibility due to voltages which can be induced in this loop, e.g., by RF-transmitters and ESD. Commonly, when the distance between two traces equals the width of the traces, the coupling factor is about 0.5 to 0.6. The effective inductance of the traces has gone down from 1µH/m to 0.4 0.5µH/m. This means that 40 to 50% of the signal-return current may run freely through the other traces of the PCB. For each signal path between two (sub-)blocks either analog or digital three properly defined transmissionlines need to be present with the impedances given in Table 2 and shown in Figure 5. With TTL logic the sink-current; the high-to-low transition, is higher than the source-current. In this case the transmissionline should be defined between VCC and S instead of VEE and S, which is commonly considered.
r
r)
2)
and in case of a trace between two (ground-) planes the formula yields: ZO + where: K = distance in-between the planes. Typically the permittivity for epoxy material equals: r = 4.7. 60 ln (4.K (.67.p.b.(.8 ) c b))) å
r
Table 2. The Transmissionline Impedances, ZO, for Several Signal Paths
FUNCTION/LOGIC Supply (typ.) Signal ECL Signal TTL Signal HC(T) ZO () <<10 50 100 200
> ICC, IOL
VCC (VSS) ICC = supply current IOL = output current low #1 IOH = output current high #1
IC #1
S < IOL > IOH
IC #2
< ICC, IOH
VEE (VDD)
Figure 5. Typical diagram of an interconnection between (digital) ICs which shows 3 specific transmissionlines
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The mutual coupling between two parallel traces can be calculated from the double integral [9]: M k + m (4.p).
11 12
ds1.ds2.dr
| r |
CONCLUSIONS: I. Use traces as thin as possible next to one another instead on top of each other (separation commonly less than 1.5mm ÷ epoxy thickness of a bi-layer). II. Create a layout where every signalline has its signal-return at the closest possible interval (applies to both signaland supply-traces).
capacitor value, Cdec., which need to be added with each output gate. The values of the decoupling capacitors for fast logic families may no longer be useful if the capacitor incorporates a large series inductance, either caused by the construction of the capacitor, long connecting wires or PCB traces. Additional small ceramic capacitors (100100pF) need then to be added, as close as possible to the pins of the IC, in parallel to these "LF-" decoupling capacitors. The resonance frequency of this ceramic capacitor (including the trace length towards the supply pins of the IC) should be above the bandwidth of the logic [ 1/ (.r)], where r is the voltage risetime of the logic. If the decoupling capacitor is placed with every IC the signalreturn current may choose which path is most convenient, VEE or VCC. This choice is determined by the mutual coupling present between the signaltrace and one of the supply traces. Between two decoupling capacitors, one for each IC, and the inductance, Ltrace, formed by the supply traces, a series resonant circuit will result. This resonance is only allowed when it occurs at low frequencies (<1MHz) or when the Q of this resonance circuit is low (<2). This resonance can be kept below 1MHz by using a choke with high RF-losses in series with the VCC network and the decoupled IC. Too less RF-losses can be compensated by either adding a resistor in parallel or in series (Figure 6).
where: l1, l2 = length of traces 1 and 2 relative distance between line r= segments, ds1, ds2, of each trace. Substituting the geometry of two parallel lines results in: Mk = 200 [ l.ln {(l+ (l2+h2)) / h } + (l2+h2) + h ] [ nH ] where: l = length of the two parallel traces and h = distance between the traces (trace thickness and width are neglected). If the coupling between the two conductors of a transmissionline is too low, a ferrite toroid (µr > 200 (5000)), with some windings, will increase this coupling to 1. By using ferrite toroids one can get full control over the signal- and signal-return currents. In case of parallel conductors, the characteristic impedance of this transmissionline may be influenced by the ferrite. In case of coaxial cable, the presence of the ferrite will only be noticeable on the outer parameters of the cable.
III. If the coupling between the conductors of the transmissionline is insufficient a ferrite toroid may be used.
5.
PROPER DECOUPLING WITH EACH IC
ICs will be commonly decoupled by capacitors only. Because capacitors are not ideal, resonances will occur. Above the resonance frequency the capacitor behaves as an inductor, which means that the dI/dt is limited. The value of this capacitor is determined by the voltage-fluctuations which are allowed across the power supply pins of the IC. According to good designers practice, this voltage fluctuation should be less than 25% of the signal-line worst-case noise margin. From the following equation the optimal decoupling capacitor for each logic family output gate can be calculated: I = c.dV/dt The worst-case signal-line noise margins for several logic families are given in Table 3, together with the recommended decoupling
Table 3. Recommended Decoupling Capacitor
FAMILY NOISE-MARGIN volt CMOS (5V) TTL-LS TTL-F HCT HC (5V) ACT 1.75 0.4 0.4 0.7 1.2 1.7 dI / dt mA 2 50 50 50 50 175 ns 100 10 23 23 23 12 Cdec. nF 0.5 5.0 22.0 12.8 7.5 35.0
Rp Ltrace VCC C VEE Figure 6. Suggested decoupling circuit with each IC Lchoke Cdec. IC <ZO IC
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The choke may never have an open core, because then it will either act as a RF-transmitter or a ferroceptor for magnetic fields. Example: 1MHz × 1µH Z1 = 6.28 Rs = 3.14 Q2 Rp = 12.56 Above the resonance frequency, the characteristic impedance, ZO, of the "transmissionline" (in this case the impedance of the IC sees at its supply terminals) will be equal to: ZO = (Ltrace / Cdecoupling). The series inductance of the decoupling capacitor and the inductance of the interconnecting traces have a negligible effect on the RF supply-current distribution,
when a choke of 1µH, for example, is used. Still it determines the voltage fluctuations between the supply pins of the IC. With a 25% signal-to-noise margin dissipation by the power supply, the recommended maximum inductances, Ltrace, are given in Table 4. With the decoupling as suggested in Figure 6, the number of transmissionlines between the two ICs has gone down from 3 to 1 (see Figure 7). CONCLUSION: IV. By using proper decoupling with each IC: Lchoke + Cdec., only one transmissionline needs to be defined between the circuit blocks. With high speed logic, r < 3ns, the total inductance in series with the decoupling capacitor needs to be low (see Table 4). A
trace, in series with the supply pins, of 50mm equals an inductance of 50nH. Together with the load conditions at an output, 50pF typical, this will give a minimum risetime of 3.2ns. If faster risetimes are required, shorter leads from the decoupling capacitor (preferred leadless) and shorter leads within the IC package are necessary. This can be obtained by using, for example, IC-decoupling capacitors, or better, using center (supply) pinned ICs in combination with small leadless ceramic capacitors with a 3E pitch (DIL). A multi-layer board with supply and ground planes can be another option. Further improvements can be reached by applying SO-packages with center pinned supply connections. CONCLUSION: V. When using fast logic: multi-layer panels should be used.
Table 4. Allowed (Supply) Series Inductance
FAMILY NOISE-MARGIN volt CMOS (5V) TTL-LS TTL-F HCT HC (5V) ACT 1.75 0.4 0.4 0.7 1.2 1.7 dI / dt mA 2 50 50 50 50 175 ns 100 10 23 23 23 12 Ltrace nF 200.0 20.0 4.0 7.0 12.0 2.4
> IDC Lchoke Lchoke
VCC
IC #1 C
S < IOL > IOH
IC #2 C
IDC = DC supply current ICC = supply current IOL = signal current sink IOH = signal current forward
> IOL < IOH
VEE
Figure 7. Proper decoupled circuit blocks
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6.
MINIMIZE TRACELENGTH AND LIMITED LOOPAREAS
The maximum tracelength is determined by reflections which will occur at NON-terminated transmissionlines. The loopareas and tracelengths are limited by the EM-radiation which is allowed by mandatory requirements for the product. The latter requirements will directly apply to the PCB if it is used in an unshielded box/cover.
determines the dynamic noise margin which by approximation is inverse proportional to the disturbance pulse halfwidth time. Applying the requirement that the noise, in this case the reflected signal, has to be less than 25% of the (dynamic) noise margin the tracelengths in Table 5 result. CONCLUSION: VI. A transmissionline should, if necessary, be series-terminated at the drivers side. If the trace lengths are long compared to those given in the table, END-termination is inevitable.
clock-rate, the limit of the dipole-moment strength should be divided by (n), in which n = number of loops, hence the signals will add as random noise. M(freq) = I(freq) . A . µr The limit value for the magnetic dipole-moment can be calculated from the radiated power [7, 8]: E = (7/r) . (Prad) Prad = 31200 . I2 . A2 / 4 = 31200 . M2 / 4 where: I = loopcurrent as function of frequency A = looparea = wavelength belonging to the frequency component of the loopcurrent By substitution the following results: E = (7/r) . 176 . I.A / 2 Filling in the requirement, given above, that E 100µV/m at 10 meters distance from the source the following equation results for the looparea and current as function of frequency: I.A / 2 8.1 107 [ A ], or M 8.1 107 . 2 [ A.m2 ]
6.1. Allowed Tracelengths Due to Reflections
The first limitation of the tracelength is determined by functional requirements. A transmissionline can be made reflection free by either adding a load resistor at the end of the line, which without series capacitance will cause DC-dissipation, or by adding a resistor in series with the driver. In this case the output impedance of the circuit plus the series resistor must be equal to the characteristic impedance of the transmissionline. When the transmissionline is NOT terminated the allowed trace length is determined by the noise-margin of the logic used, its bandwidth and the propagation delay of the line, which is assumed to be 5ns/m. The bandwidth
6.2. Allowed Loopareas Due to Radiation
The emission from a PCB (or a complete product) is limited to 100µV/m at 10 meters distance from the object at frequencies above 30MHz [FCC, IEC CISPR publications, class B]. This emission is determined by the product of the looparea, A, the loopcurrent, I, and the permeability of the medium within that loop, µr (commonly equal to 1). This product is called the magnetic dipole-moment, M. In case a number of loops are present, operating at the same frequency or
Table 5. Allowed NON- or Series-Terminated Tracelength
FAMILY NOISE-MARGIN volt CMOS TTL-LS TTL-F HCT HC ACT 1.75 0.4 0.4 0.7 1.2 1.7 dt ns 100 10 23 23 23 12 MAXIMUM TRACELENGTH (m) NON-TERMINATED 14.3 0.4 0.08 0.14 0.24 0.18 SERIES TERMINATED --1 0.5 0.15 --1 --1
NOTE: 1. If series termination is used in an asynchronous logic circuit design, attention must be given to the occurrence of metastability; especially symmetrical logic input-circuitry cannot decide whether the input signal is high or low and a non-defined output status may/will result.
S PCB #1 E, H-field
VEE, VCC
Figure 8. Radiation from a loop on a PCB
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The spectral current amplitude, for logic signals in the frequency domain, decrease above the bandwidth of the logic (= 1 /.r) proportional with frequency square. At this corner frequency, the radiation resistance of the loop still increases proportional with frequency square. Therefore one can calculate the maximum looparea which is determined by the clockrate or repetition rate, the risetime or bandwidth of the logic and the current amplitude in the time-domain. The current waveshape is derived from the voltage waveshape and the current halfwidth time is by approximation equal to the voltage risetime (Figure 9). The current amplitude at the corner frequency (=1 / .r) becomes: I(f) = 2.I.r / T
where: I = current amplitude in the timedomain, T = 1 / clockrate = period time, r = voltage risetime H current halfwidth time. From this equation the maximum looparea at a clockrate for a certain logic family can be calculated. These loopareas are given in Table 6. CONCLUSION: VII. The maximum looparea is determined by the clockrate, the logic family (= output current) and the number, n, of simultaneous switching loops on that PCB.
When a bi-layer is used with a thickness of 1.5mm, the maximum allowable tracelength, derived from the looparea, will be much less than the tracelength found from the reflection point of view. If clockrates are used above 30MHz, the use of a multi-layer will be inevitable. In this case the epoxy thickness depends upon the number of layers used and may vary between 60 300µm. When only a limited number of high clockrate signals are distributed on the PCB, careful routing, by using side-to-side traces, may lead to acceptable results on a bi-layer.
Table 6. The Allowed Single Looparea for Each Logic Family
FAMILY dI mA CMOS TTL-LS TTL-F HCT HC ACT 2 50 50 50 50 175 dt ns 100 10 23 23 23 12 f = 4MHz 4.5 106 1.8 106 1.8 106 1.8 106 1.8 106 515 MAXIMUM LOOPAREA IN mm2 AT CLOCKRATE OF: f = 10MHz 1.8 106 f = 30MHz -- 2400 480 480 480 69 f = 100MHz -- -- 144 144 144 21 (note 1)
7200 1400 1400 1400 206
NOTE: 1. In this case, when using common DIL packages, the looparea limit will be exceeded and additional shielding measures, together with proper filtering will be inevitable.
V r = t 1 t o
I H
to
t1
> time
to
t1
> time
(a) output voltage waveshape
(b) output current waveshape
Figure 9. Logic output voltage and current wave shapes in case of capacitive loading
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6.3. Allowed Tracelength Due to Radiation
The allowed tracelength are even less, when the transmissionline is directly coupled to the system reference and an unshielded outgoing cable leaving the product, then the values found up to now. A simple diagram is given in Figure 10. The voltage drop between the two references with each IC has become the driving source of the antenna formed by reference system and the outgoing cable. The worst case radiation resistance of the antenna is assumed to be 150 and frequency independent [7]. The amplitude of the driving source, U, is now limited to: Prad = U2 / 150. Applying the radiation requirements as given earlier the voltage drop has to be: U 1.75mV.
The voltage drop is determined by the current amplitude, at the logic bandwidth's frequency, and the effective inductance of the transmissionline between these points. U(f) = I(f).Z(f) = I(f).j..(L-M) = I(f).j..L.(lk) Taking Table 1 and the current amplitude in the frequency domain, the tracelengths in Table 7 can be found. This table shows that many practical applications shall not fulfill the radiation requirements. In most cases, filtering or shielding of the outgoing cable, which leaves the product will be sufficient. Shielding of the entire product, plus necessary filtering, becomes inevitable
when the magnetic loop constraints are exceeded. CONCLUSION: VIII. Circuit designs shall be made in such a way that the voltage drop between references shall not directly excite an antenna being any outgoing cable. Simple approximations will give the number for the required filtering or shielding performance whenever necessary. These can be found by using the Tables 6 and 7 and counting the number of correlated sources in the product. In the chapters 7, 8, and 9 some basic information is given about the cable shield performance and filtering techniques.
PRODUCT CABLE
PCB #2
S VEE, VCC
Figure 10. Radiation from a product, containing a PCB, with an outgoing cable
Table 7. Maximum Tracelength in Case of Direct Radiation
FAMILY dI mA CMOS TTL-LS TTL-F HCT HC ACT 2 50 50 50 50 175 dt ns 100 10 23 23 23 12 f = 4MHz 108 / -- 4.3 / -- 4.3 / 55 4.3 / 55 4.3 / 55 -- / 15.4 ALLOWED TRACELENGTH IN mm BI-LAYER / MULTI-LAYER f = 10MHz 44 / -- 1.75 / -- 1.75 / 40 1.75 / 40 1.75 / 40 -- / 3.2 f = 30MHz -- 0.6 / -- 0.6 / 4.4 0.6 / 4.4 0.6 / 4.4 -- / 2.1 f = 100MHz -- -- -- / 2.2 -- / 2.2 -- / 2.2 -- / 0.62
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7.
PLACEMENT OF THE CONNECTORS
All connectors, which provide the interconnections to other panels and/or units, must be placed as close as possible to one another. In this way common-mode currents, which are induced in those cables, will NOT flow through the traces of the circuit on the PCB. In addition, voltage drop between references on the PCB will not excite the (antenna)-cables. To avoid such common-mode effects, it may be necessary to make a separation between the reference-strip near to the connectors and the groundplane, groundgrid or reference of the circuitry on the PCB. This groundstrip shall, if applicable, be connected to the metal cover of the product. From this separate groundstrip, only high impedances; inductors, resistors, reed relays and opto-couplers are allowed in between these two grounds. This will be explained when the filter networks are described, Chapter 9. CONCLUSION: IX. All connectors need to be placed as close as possible to one another in order to prevent external currents running through the traces or reference of the PCB.
Determined by the amplitude and the frequency content of the signals flowing through these cables a choice shall be made. In case cables, leaving the enclosure of the product, contain data above a 10kHz clockrate, shielding will be inevitable (product requirement). This shielding shall be connected to ground (metal cover product) on both ends of the cable, this to assure that the shield acts both as an electric and a magnetic shield. If separate grounds are used, this shall be done to the "connector-ground" instead of the "circuit-ground". In case the clockrate is above 10kHz and below 1MHz and the risetime of the logic is kept as slow as possible, an optical coverage of 80% or more or a transferimpedance which equals less than 10nH/m will do. Above 1MHz clockrates, better shielded cables are always necessary. In general, coaxial cable excluded, the shield of the cable shall not be used as signalreturn. By using passive filters in series with the signal input/outputs to the ground/reference, to reduce the RF-content, the necessity of a high quality shielding and the corresponding connector can be avoided. A proper shielded cable will have a transferimpedance equal to or less than |j..10 nH/m|. Every wire has an inductance of 1 nH/mm (refer to chapter 2.1.). In case the shielding of such a cable is wrapped into a pigtail, the inductance of that pigtail will degrade the shielding performance, thus increase the transferimpedance, of the cable.
CONCLUSION: X. A good shielded cable deserves a proper connector.
9.
PROPER USE AND PLACEMENT OF FILTERS AND FILTER PARTS
Signal bandwidth reduction shall be achieved by using RC low-pass filters. In case the voltage drop across the series resistor is unacceptable an inductor with high RF-losses shall be used. The LC low-pass filter will always show resonances and therefore its Q must be kept low. The filter can be used in two directions; namely, to prevent emission from the PCB and to improve the immunity of the board to external sources, e.g. RF-transmitters, ESD, etc. The lay-out of the interconnection of the shield of the cable and a low-pass RCR-filter is given in Figure 12. The lay-out of the filter shall be such that the requirements for the maximum tracelength, Table 7, are not violated. CONCLUSIONS: XI. Currents, which do not belong to the circuit signals, should be by-passed using another path. XII. The bandwidth of signals should be limited to the lease functional bandwidth. Use the slowest logic family suitable for the function.
8.
RIGHT CABLE CHOICE WITH A PROPER CONNECTOR
Cables have, when they are shielded, a transferimpedance, see Appendix B.
CONN. 1 CONN. 4 AVOID THIS CURRENT FLOW! CONN. 2 THIS CURRENT FLOW IS FAVORABLE! CONN. 3 PREFERRED PHYSICAL GAP BETWEEN REFERENCES
Figure 11. Optimal connector placement on a PCB
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Shielded Cable
R
R
Logic S VEE
C short connection
"connector-"ground
"circuit-"ground
Figure 12. Lay-out of the interconnection and filtering of a shielded cable to a PCB
10.
PCB DEMO-BOARD, ROUTING AND DECOUPLING EFFECTS
series inductor may be short-circuited or added to the circuit. In total 4 relevant situations can be evaluated which are given in Table 8. Situation 1. Supply decoupling only takes place by the capacitors and the signalreturn has been established through the supply trace VEE (VDD). Situation 2. Supply decoupling only takes place by the capacitors and the signalreturn has been established through the supply trace VEE (VDD) and a trace in parallel to the signaltrace. The coupling between signal and signalreturn determines that only a small portion of the signal-return current will flow through the supply traces. Situation 3. The supply trace, VEE (VDD), has been taken out and the ICC and signal-return current have to flow through the trace next to the signalline. The high frequency components of the signal-return current shall still flow through the VCC (VSS) trace due to the (de-)coupling capacitors at the supply pins of the ICs. Situation 4. By adding the inductors, with sufficient RF-loss, in series with the supply trace, VCC, of both ICs ALL the signal-return
current will have to flow through the trace next to the signalline and radiation from the loop on the PCB has diminished. The effects with respect to the radiation can be measured both in time as in frequency-domain. The latter has the advantage of showing the differences between situation 3 and 4 which are marginally discernable on an oscilloscope. These RF-effects are of extreme importance with respect to radiation as explained in Chapter 6. To demonstrate the phenomena on an oscilloscope, a 50 (100) MHz bandwidth version shall be used. A small (electrically shielded) loop shall be used as measuring probe. If not available, a loop made by using a voltage probe of which the ground strap is short-circuited to the measuring tip can be used. This "loop" shall be placed on the PCB as some secondary loop near the supply traces. On the oscilloscope the effects of the positions of the switches can be observed. Measured results in the time domain are given in Appendix C. In case a spectrum analyzer is used, an electrically shielded measuring loop shall be placed on the PCB as some secondary loop near the supply traces. On the screen the effects of the positions of the switches can be observed. Measured results in the frequency domain are given in Appendix D.
An EURO-card PCB (100 × 160 mm2) has been chosen to demonstrate the effects of signallines and their signalreturns with respect to magnetic radiation. The board contains a relaxation oscillator, created by 3 inverters (NANDs) and an RC-network (1k, 560pF), which will produce a squarewave voltage signal. The frequency will be determined by the used logic and its threshold voltages. This oscillator is placed in one corner of the board together with some switches to change signal-return path and supply decoupling. In the opposite corner of the PCB another quad NAND has been placed as a capacitive load. These NANDs are all cascaded and will change status with some skew. The last NAND is terminated by a resistor. The supply decoupling of this IC can be altered as well. The diagram of the circuit with the switches is given in Figure 13 and the physical layout of the PCB and component placement are given in Figure 14. The layout has been chosen such that the supply traces are as close as possible to one another, which is commonly arranged by a proper CAD-tool. In parallel to the signaltrace a signalreturn trace has been placed, according to Chapter 4. At the supply pins of the ICs decoupling capacitors are added to each IC. By means of jumpers or switches a
Table 8. A List of the Relevant Configurations of the Switches on the Demo-board with Respect to Emission Measures.
POSITION OF THE SWITCHES SITUATION 1 2 3 4 SW 1 ON ON OFF OFF SW 2 ON ON ON OFF SW 3 ON ON ON OFF SW 5 OFF ON ON ON
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The behaviour of the PCB has been simulated with PHILPAC for a unity sinewave signalsource and the sum of the currents through the VEE and VDD traces are given in Figure 15. In the simulated circuit the parasitic capacitance across the chokes has been taken into account, which leads to the
same result at higher frequencies with respect to situation 3 and 4. As long as the measuring loop is kept from the oscillator area, which itself (also due to the switches) radiates the effects can be shown unambiguously.
REMARK: As radiation from a certain passive network is reciprocal, the same results could have been obtained in case of an immunity set-up.
1 1 2 3 4 5 R1 1000 C4 560pF 6 12 13 2 14
3
4 5
6
12 13
11
9 10
8
R2 VEE 270
VEE C1 22u 10V
SK1
L1 2.2 14 SK3
SK4
L2 2.2 14
C2 33n VCC 7 SK2
C3 33n 7
Figure 13. The circuit diagram of the demo-board
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Figure 14. The layout and components placement of the demo-board June 1989 2694
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Figure 15. PHILPAC AC analysis of the EM radiation behavior of the demo-board in the 4 conditions June 1989 2695
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11.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
REFERENCES
EMC in TV receivers and monitors, D. Teuling, ETV 8702 Philips Components, 1987, Eindhoven. Electromagnetic compatibility syllabus, J.J. Goedbloed, November 1987, Philips Central Training Department, The Netherlands. Low frequency approach to the electromagnetic radiation of the printed circuit boards, M. Coenen, Philips Research Lab. Note 316/85. Radiated emissions from common-mode currents, C.R. Paul, IEEE EMC symposium notes, 1987. EMC and loop inductances on printed wiring boards, B. Danker, 7th Symposium on EMC, Zurich, 1987. Electromagnetic compatibility design and layout guidelines of printed circuit boards, M.J.C.M. van Doorn, Philips Video Display Products, Pre-development, AR6-60.07, 1987. An evaluation method to characterize the EMC performance of PCBs containing ICs, M.J. Coenen, ESG 8801, Philips Components, 1988. Antenna theory, analysis and design, C.A. Balanis, Harper and Row Publishers, New York, 1982. Electromagnetic theory, J.A. Stratton, McGraw Hill, New York and London, 1941. Fast TTL Logic series, Handbook IC15 Philips, 1988. Advanced CMOS Logic Data Manual, Signetics/Philips, 1988. Taschenbuch der Hochfrequenztechnik, H. Meinke, F.W. Gundlach, Springer Verlag, Berlin, New York, 1968. Transmission-line methods aid memory-board design, E.A. Burton, Electronic Design, December 1988. EDN's advanced CMOS logic ground-bounce tests, EDN, March 1989.
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APPENDIX A.
CAPACITIVE COUPLING BETWEEN TRACES
It shows the necessity of a reference plane at a height, h, closer to the traces than the distance, D, to reduce the capacitive coupling between the traces.
In this appendix the graphical presentation is given of the capacitive coupling between two traces in free space and for two traces above a reference plane [12, form. 24.25].
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APPENDIX B.
THE TRANSFER IMPEDANCE OF VARIOUS CABLE SCREENS
The transfer impedance, Zt, is the relation between the current through the screen due to an external source and the induced voltage across the nominal load impedances of that cable. Further information about the measuring method to obtain information of the screening efficiency or the transfer impedance can be found in IEC publication 96.
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APPENDIX C.
MEASURED RESULTS IN THE TIME DOMAIN, 150MHz BANDWIDTH, FROM THE DEMO-BOARD, CONTAINING A 74HCT00, IN THE 4 CONDITIONS DESCRIBED IN CHAPTER 10.
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APPENDIX D1. MEASURED RESULTS IN THE FREQUENCY DOMAIN, PEAK DETECTION, FROM THE DEMO-BOARD, CONTAINING A 74HCT00, IN THE 4 CONDITIONS DESCRIBED IN CHAPTER 10.
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APPENDIX D2. MEASURED RESULTS IN THE FREQUENCY DOMAIN, PEAK DETECTION, FROM THE DEMO-BOARD, CONTAINING A 74HCT00, IN THE 4 CONDITIONS DESCRIBED IN CHAPTER 10.
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Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 940883409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.