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Hyundai
Plasma Display
PD421 Svc Manual
Plasma Display PD421


. Circuit Service Methods
1. W hite Ba lance A djustment
l Refer to adjustment specifications for information on makin g adjustments
m When white balance has to be adjusted during service
- If the module is replaced, it must be readjusted u sing VG -828 equipment,
according to the adjustment specifications
- When making progra m upgrades [ ROM (UM04) replacement] or replaci ng A/V
B/D, the values stored i n A/V B /D' s EPROM (UM12) should be written down
and re-ente red into the new new Rom or A/V .Board

The method of white Balane Adjustment before ROM or B/D IS Replaced


before Rom or B/D is
Replaced
Select "Device" from
the menu



select the Video Mode

Select AD9883




Enter into the Enter the Menu+42+
Factory Mode Mute key
R.G.B-Gain value
Separate Record(c)
R.G.B-Gain value


Select "White" from the
menu
Factory Mode Exit




R.G.B-Gain value
Separate Record(a) R.G.B-Blas value
Select the pc mode




Select "Device"
Enter into the Factory
mode


Select FLI2300
Separate Record(b) Brightness and
Contrast values
Select the Device




Factory Mode Exit

Select AD9883




Select the DTV mode

R.G.B-Gain value
Separate Record(d)
R.G.B-Gain valye


Enter into the Factory
mode




--1--
After ROM or B/D After selecting AD9883
replaced enter(c) Data recorded
in R,G and B-Gain and
Bi as values separately




Select the Video mode
After exiting from the
Factory select the
PC mode


Enter in to the Factory
mode
Enter the Facrory to
select the PC mode



After selecting "Whte"
enter (a) Data recorded
Enter(a) Data recorded
in Bias values
in R.G and B-Gain and
Separately
Bias values separately




After selecting
FLI2300, enter(b) Data After selecting AD9883
recorded in Brightness enter(c) Data recorded in
and Contrast values R.G and B-Gain and Bias
separately values separately




After exiting from
Completed adjustments of
Factory, select the
the White balance
DTV mode

:When ROM and AV B/D are
replaced without additional
equipment, this is how to
After entering into adjust the white balance
Factory to select
White enter(a) Data
recorded tn R,G and
B-Gain and Bias
values separately




--2--
Plasma Display PD421


2. A/V Circuit BLOCK Diagram
1) PC Mode
PC inputs, R, G, B , H, and V signals, are entered through D-S ub 15pin
(DSUB1). They are en tered into the DTV/ PC sele ction switch, B A7657
(UA01). When PC is selected in M CU, the signals are entered into the AD
converter, AD 9883 (UA02).
In AD9883, the signals are c onverted into 24 bits and entered into scaler
ASI500.
BA7657 selec ts PC when pin16 is high and selects DT V when pin 16 is low.
AD9883 is controlled using the SDA/SCL line of pin 57/
56.
PC inpu t resolu tion is fh: 30~70k a nd fv: 50~85Hz, and the ma ximum
resolution is 1080x768 at 85Hz.
If the resolution is above the specifications, an out of range m essage is
displayed on the upper left hand corner of the screen. However, even if the
resolution is within the specified range, if the input timing is different from
the timing indicated on the manual, a ` not found vesa o r out of range'
message can be displayed. Ple ase check the timing to identify the c ause of
the ` out of range' message.
PC input sync can rece ive H/V composite or separate, but if DPMS ON is
selected in the PDP menu, DPM S cannot o perate in composite and c an
operate only in separate sync.
The Auto Adjust function, which is used to adjust the picture position and
size, should be carried out in the Windows desktop screen or full cross hatch.
The D TV signals, 480p, 720p, and 1080i, from the set-top box with a D-Sub
out port, can be received through the D-Sub port and displayed in the PC
mode.


DVI Mode
Signals entering through the DVI port (D V101) are converted to 24bits in
the TMDS Rec eiver, SIL161B (UT02 ), and entered in scalar ASI500.
SIL161B is an output port and is activated when pin number 2 is high.
DTV signa ls 480p, 720p, and 1080i can be displayed through the DVI port .
However, PD421 cannot only display 60Hz DTV signals. It is unable to
display 50Hz DTV signals. PC can support both 50Hz and 60Hz signals.
The resolution of DVI Mode is the same as the PC Mode.




--3--
2) DTV Mode
DTV signals are entered as Y, P b(Cb), and Pr(Cr) component signals,
separated into Y, Cb, Cr, H, and V sync on (xan51AcuxA01) and entered to BA7 657.
If pin 1 is low, DTV signals are entered into ADC9883.
6
In the AD9883, like the PC signals, the DTV signals are converted to 24 bits
and entered into scalar ASI500.
DTV signa l is composed of 480p (50/60Hz) for SD, 720p (50/60Hz) for HD,
and 1080i (50/ 60Hz). If the video signal, 480i component (DVD component
output), is entered, the screen will not display properly. Also,
because synchronization signal is in Y singal color Data is in Cr/Cb
if the connections are incorrect, it will not operate properly


3) DVD Mode
DVD signals entered as Y, Pb, and Pr components are applied when entered
as 480i (NT or PAL). 480p DVD signals should be entered through the DTV
component port.
Y, Pb, and P r signals entered through the DVD component port are entered
into the video decoders, Main VPC3230 (UDM01) and Sub VPC3230 (U DS01),
where they are converted to Y (8bits) and UV (8bits) digital sig nals and sent
to the deinterlacer IC, F L I2310 (UF L 1).
UV digital signal means Pb(Cb), and Pr(Cr) signals that have been converted
to digital signals.
The v ideo decoder, VPC3230, automatically detects NTSC and PAL/S ECAM,
identifies them as broadcast signals, converts the interlacer signal into the
progressive signal (fh :15.7Khz-> 31Khz) in t he deinterlacer IC, F L I2310
(UF L 1), and sends to the scalar ASI500.
When the PD 421' s main screen is in PC, DVI or DTV mode, the sub-screen
of the PIP or POP function is processed in the Main VI DEO DECODER
(UDM01) and the MODE can be DVD, S-VHS, Video, or Scart.
PIP or POP between video modes is enabled by main video decoder (U DS01),
sub video decoder (UD S01), and F IFO memory, MS81V04160 (UF M01). If the
main screen is DVD, then the sub- screen will be S-VHS, Vid eo, or Sca rt.
Plea se refer to the table in the back for more information on PIP or POP.


4) S-Video
S-Video signals are entered as Y/ C signals, which is composed of Luminance




--4--
Plasma Display PD421


color signals. The NT SC and PAL /SECAM are automatically detected by the
video decoders, main VPC3230 and sub VPC3230, and converted to Y (8bits)
and UV (8bits) and sent to the deinterla cer IC, FLI2310, as 16bit digital
signal.
S-Video input and co mposite video input share a single audio jack.
Therefore, while the pictures for the two inputs can be viewed at the same
time, only one of the sounds can be heard. PIP/POP operati ons are the same
as described for the DVD mode.


5) Video
Video signal is a composite signal that combines the Luminance (Y) and color
(CHROMA) .
It is entered through the main VPC3230 and sub VPC3230 when selected in
the input selection switch, TA8851 (UMX01).
If the signal is NTSC, it is first entered into the 3D Comb Filt er (fi lter that
separates the composite to Y/C signal), UPD 64083 (UCF 01) and separated into
Luminance signal Y and color signal, C. The separated signals then enter the
mux switch, TA8851, sent to TA8851 pin44 LU MA IN and pin43 CROMA IN,
and finally sent to Main VPC3230.
When the video input is displayed on the main screen, it passes through the
3D comb filter, but if it is displayed on the sub- screen (w hen using PIP or
POP), the video input does not pass through the 3D comb filter a nd i s
displayed using the composite signal.
PAL/SECAM signal cannot be processed by the 3D comb filter. It i s sent as
composite signa to the main VPC3230 and sub VPC3230.
l
If the signal is NTSC, the video input switch, BF 7654 (UDM02), which is
located in front of the main VPC3230, select the 3D Comb-Y to send the
signal as a Y signal to the VPC 3230. If the signal is Pa l, it selects CVB S to
send the signal as a composite signal to the VPC3230.
Signals entered into VPC3230 are converted to 16bit digital signal (Y (8bits)
and UV (8bits)) and sent to the scalar through the deinterlacer IC, F L I2310.


6) Scart Mode
Scart only supports CV BS signals, which are processed in the same way as
video signals. The RF signal is not supported, and therefore, the Scart pin8
ID signal is ignored.




--5--
Plasma Display PD421


7) PIP/POP Support Mode Map
Sub
PC DTV DVD S-VHS Video Scart DVI
Main
PC X X O O O O X
DTV X X O O O O X
DVD O O X O O O O
S-VHS O O O X O O O
Video O O O O X O O
Scart O O O O O X O
DVI X X O O O O X
X: Not supported, O: Supported


Note: When displaying NT SC or P AL signals to PIP or POP , if the signals are displayed
as Main: NT SC, Sub: P AL or in reverse, the picture can be seen, but the size scaling for
the sub-scr een will not display properly. This is because the signal is meant for the
main screen. Main screen use s 50Hz PAL or 60Hz NTSC and sub scre en uses 60Hz
NTSC or 50Hz .
8) Sc aler Output
Sc aler output signals, R, G, a nd B (each 8bits), are outputted as 24bit TTL
signal, converted into LVDS signal in the LVDS converter, DS90C3 85
(ULV01), and sent to the logic B/D in the PDP module. Output timing:
fh : 29.1Khz
fv : PAL 50Hz
NTSC 60Hz
DCLK : about 27Mhz


9) Audio part
Audio input port for each mode:
Input Port Remark
PC/DVI RCA L/R 1E A Shared
DTV RCA L/R 1E A
DVD RCA L /R 1E A
CVBS/S-Video RCA L/R 1E A Shared
Scart S cart Ja ck L /R




--6--
Plasma Display PD421


Audio input signal for PC/DVI, DT V, and DV D modes is entered into the
audio processor IC, MSP3450G , and audio input signal for VID E O/S -VIDEO,
and SCART modes is first selected in MUX 8851 a nd entered into the audio
processor.
As in other chips, the audio processor (MSP34 50G) uses the SCL and SDA
line to control volume, and left/right balance and mono/stereo.
The L/ R audio signal sent by MSP3450 is a mplified in the amplifier, TA2 024
(UAU1) and sent to the speaker.
TA2024B support 10W(based on impedance 8Y ) of output for each L/R.


3. Trouble shooting
1) Diagnosing defective module
If the power does not come on or if the module operates abnormally, check
module defect. To do this, remove the rear cover and A/V B/D to reveal the
module s logic B /D. The following figure represe nts the s/w on the logic B/D.
'
SW 2001


1 2 3 4


Signal 1 2 3 4 Remark
External up up down up Forwarding
Criteria
Internal up down up down
If the switch is set to internal signals, it will operate without external signals,
but the screen will be displayed in full white.
Therefore the module operation can be checked without the A/V board.
Here, be aware that the pin 8 and pin 9 of the power B /D' s CN802(11p),
which is located above the module' s logic B /D, must be shorted and the A/C
power supplied in order for the module to operate normally. Pin 8 is marked
as PS-ON below the connector (CN802).
If module itself is tested and it does not power on or the picture is abnormal,
the module is defective.
When reconnecting the A/V B /D, make sure to change the switch to external
signals.
- The most common module defect i s the appearance of a black or bright
vertical line.




--7--
- B ar




This occ urs when the FPC wire, which connects the address line below the
module, is damaged. Because the wi re is on the bottom, it can be e asily
damaged when the module is lifted and assembled or from external shock. Use
caution when handling the module and use the handle on the bottom of the
module to lift or move.
If the vertical bar appears at the same location for all modes, the F PC wire is
damaged.
FPC wire cannot be replaced. The entire module needs to be replaced.
- If the module does not power on, it is mostlylikely due to an open fuse on the
power B/D. Check the black and round fuse on the power B/D.


2) Diagnosis by Problem Ty pe
- Power comes on, but the picture does display
Check the AV B/D ' s communication lines, SDL and SDA lines.
ICs c ontrolled by the SDA and SCL line are ADC9883, F L I2310, MSP 3450G,
VPC3230, 3D comb filter, and TA8851. If after powering on, the SDA and SCL
line' s Vp- p is less than 4V and checks below 2.5V, the communication line is
loaded at some point. Open and check each IC' s communi ation line.
c
- Can also occur when the connection between the graphic B/D and video B/D is
bad.
- If the picture turns off or the volume is muted while viewing through the set-
top box, please check the status of the set-top box first.
- For abnormal picture when using P IP/POP fun ction, refer to the s ection on
Video Mode in the manual
- If the OSD screen cracks or displays abnormally:
May be caused by bad connection between the graphic B/D' s sc aler a nd
SDRAM, K4S643232C (UF B 01, UFB02). Use the clea ner to clean the around
the scaler and the UF B01/02.
OSD is processed by the scaler (ASI 500).
- If the power is on and the input signals and connections are normal, but the
picture does not display:




--8--
Plasma Display PD421


Critical Parts Specification
AD9883
MC68HC705BD7B
Sync Detect fo Hot ugg ng
Midscale Clamping 8
B AIN CLAMP A/D B OUTA
Power-Down Mode
Low Power : 500mW tYPICAL MIDSCV
Composite Sync Applications Require an External Coast
HSYNC DTACK
SYNC
COAST PROCESSING HSOUT
AND CLOCK
CLAMP GENERATION VSOUT
FILT SOGOUT

REF REF
SCL BYPASS
SERIAL REGISTER
SDA AND
A0 POWER MANAGEMENT AD9883




GENERAL DESCRIPTION 12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at
The AD9883 is a complete 8-bit, 110 MSPS monolithic analog 10 MSPS. When the COAST signal is presented, the PLL
interface optimized for capturing RGB graphics signals from maintains its output frequency in the absence of HSYNC. A
personal computers and workstations. Its 110 MSPS encode sampling phase adjustment is provided. Data, HSYNC and
rate capability and full-power analog bandwidth of 300 MHz Clock output phase relationships are maintained. The AD9883
supports resolutions up to SXGA (1280X 1024 at 60Hz)
. also offers full sync processing for composite sync and sync-on-
T he AD9883 includes a 110 MHz triple ADC with internal green applications.
1.25 V reference, a PLL, and programmable gain, offset, and A clamp signal is generated internally or may be provided by the
clamp control. The user provides only a 3.3 V power supply, user through the CLAMP input pin. This interface is fully pro-
analog input, and HSYNC and COAST signals. Three- state grammable via a two-wire serial interface.
CMOS outputs may be powered from 2.5 V to 3.3 V. F abricated in an advanced CMOS process, the AD9883 is
The AD9883's on-chip PLL generates a pixel clock from HSYNC provided in space-saving 80-lead LQFP surface mount plastic
a
and COAST inputs. Pixel clock output freque ncies range from ackage and is specified over th e 0 C to 70 C temperature range
.




--9--
AD9883­SPECIFICA
TIONS
Analog Interface (V = 3.3 V, V 3.3 V, ADC Clock = Maximum Conversion Rate)
D DD =

T est AD9883KST-110
Parameter Temp Level Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY
Differential Nonlinearity 25 C I 0.5 +1.25/­1.0 LSB
Full VI +1.35/­1.0 LSB
Integral Nonlinearity 25 C I 0.5 1.85 LSB
Full VI 2.0 LSB
No MissingCodes Full VI Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 V p­p
Maximum Full VI 1.0 V p­p
Gain Tempco 25 C V 100 ppm/C
Input Bias Current 25 C IV 1 A
Full IV 1 A
Input Offset Voltage Full VI 7 50 mV
Input Full-Scale Matching Full VI 6.0 % FS
Offset Adjustment Range Full VI 46 49 52 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.32 V
Temperature Coefficient Full V 50 ppm/
C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 110 MSPS
Minimum Conversion Rate Full IV 10 MSPS
Data to Clock Skew Full IV ­0.5 +2.0 ns
tBUFF Full VI 4.7 s
tSTAH Full VI 4.0 s
tDHO Full VI 0 s
tDAL Full VI 4.7 s
tDAH Full VI 4.0 s
tDSU Full VI 250 s
tSTASU Full VI 4.7 s
tSTOSU Full VI 4.0 s
HSYNC Input Frequency Full IV 15 110 kHz
Maximum PLL Clock Rate Full VI 110 MHz
Minimum PLL Clock Rate Full IV 12 MHz
1
PLL Jitter 25 C IV 400 700 ps p-p
1
Full IV 1000 ps p-p
Sampling Phase Tempco Full IV 15 ps/C
DIGITAL INPUTS
Input Voltage, High (V IH ) Full VI 2.5 V
Input Voltage, Low (V IL ) Full VI 0.8 V
Input Voltage, High (V IH ) Full V ­1.0 A
Input Voltage, Low (V IL ) Full V 1.0 A
Input Capacitance 25 C V 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V OH ) Full VI V D ­ 0.1 V
Output Voltage, Low (V OL ) Full VI 0.1 V
Duty Cycle DATACK Full IV 45 50 55 %
Output Coding Binary




--10--
Plasma Display PD421



Test AD9883KST-110
Parameter Temp Level Min Typ Max Unit
POWER SUPPLY
V D Supply Voltage Full IV 3.0 3.3 3.6 V
V DD Supply Voltage Full IV 2.2 3.3 3.6 V
P VD Supply Voltage Full IV 3.0 3.3 3.6 V
I D Supply Current (V ) D 25 C V 132 mA
I DD Supply Current (V DD ) 2 25 C V 19 mA
IP VD Supply Current (P )VD 25 C V 8 mA
Total Power Dissipation Full VI 525 650 mW
Power-Down Supply Current Full VI 5 10 mA
Power-Down Dissipation Full VI 16.5 33 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 25 C V 300 MHz
Transient Response 25 C V 2 ns
Overvoltage Recovery Time 25 C V 1.5 ns
Signal-to-Noise Ratio (SNR) 25 C V 44 dB
(Without Harmonics) Full V 43 dB
fIN = 40.7 MHz
Crosstalk Full V 55 dBc
THERMAL CHARACTERISTICS
JC Junction-to-Case
Thermal Resistance V 16 C/W
JA Junction-to-Ambient
Thermal Resistance V 35 C/W
NOTES
1
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
2
DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.




--11--
CXA2151Q
MC68HC705BD7B

Description
The CXA2151Q is a bipolar IC developed for multi 48 pin QFP (Plastic)
scan TVs, and incorporates a four system video
switch (including HV sync signal processing) and a
YCbCr output matrix circuit.

Features
·Supports the 2IC bus
·Supports multi scan
·Four system video switch (of which two systems support D3 pins)
·Matrix circuit
·Each YCbCr output can be switched between 0dB, 6dB (gain adjustable) and mute.
·Sync signal automatic identification circuit (with fixed mode)
·Sync separation circuit (supports HD)
·HD Tri-level sync identification circuit
·Sync signal frequency counter (both H and V)
·Dummy sync output

Applications
Multi scan TVs

Structure
Bipolar silicon monolithic IC

Absolute Maximum Ratings(Ta = 25°C, GND1, 2, 3 = 0V)
·Supply voltage VCC 1, 2, 3 ­0.3 to +5.5 V
·Operating temperature Topr ­20 to +75 °C
·Storage temperature Tstg ­65 to +150 °C
·Allowable power dissipation P D 1400 mW
(when mounted on a 50mm 50mm board)
·Voltage at each pin ­0.3 to VCC 1, 2, 3 + 0.3 V

Recommended Operating Conditions
Supply voltage VCC 1, 2, 3 5 ± 0.25 V




--12--
SCL 30
SDA 31 I2C BUS
DEC.
Block Diagram




ADDRESS 32


IN1_1 33
Y
YPbPrJ/YCbCr 27 SEL Y_OUT
Plasma Display PD421




IN1_2 34
MATRIX 6dB Cb
AMP. 26 SELCB_OUT
IN1_3 35 SELECTOR
Cr
YPbPrU/YCbCr 25 SELCR_OUT
IN1_H/L1 36 1, 2, 3
IN1_V/L2 37 CLOCK
YGAIN 20 EXTCLK/XTAL
GBR/YCbCr
IN1_L3 38 CBGAIN GEN.
CRGAIN GAIN_SEL
IN1_SW 39 SELSTB_1
SELSTB_2
IN2_1 41 18 IREF
DECL1_1 MAT_OUT CLK_SEL
IN2_2 42
DECL2_1 H-NUMBER 40 Vcc1
IN2_3 43 SELDUM
DECL3_1 V-NUMBER
IN2_H/L1 44 DECSW_1 48 GND1
DECL1_2 SYNC
IN2_V/L2 45 IN1 to IN4 DECL2_2 COUNTER 28 Vcc2
SELECTOR DECL3_2
IN2_L3 46
24 GND2




--13--
DECSW_2
IN2_SW 47
3 DUMMY 12 Vcc3
IN3_1 1 SYNC
6dB 3S TATE 6 GND3
IN3_2 2 MACRO
IN3_3 3 EXISTENCE DISTINCTION
HYSW 3-STATE
IN3_H 4 MACRO H SYNC 22 SELH_OUT
SYNC
H INTELLIGENT SYNC SEP .
IN3_V 5 DET. VISION WIDTH

IN4_1 7
HSEP_SEL HS_MASK H_WIDTH
IN4_2 8 HD_TC FIX_SYNC 23 SEL V_OUT
V
IN4_3 9 V_TC
IN4_H 10 PRIORITY RANKING
HV > CS > SYNC ON Y/G
IN4_V 11


INPUT_SEL
15 16 13 14
V_PH

H_PH




YG_IN
YG_OUT
DS90C385

General Description This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
The DS90C385 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit- Features
ted in parallel with the data streams over a fifth LVDS link. - 20 to 85 MHz shift clock support
Every cycle of the transmit clock 28 bits of input data are - Best±in±Class Set & Hold Times on TxINPUTs
sampled and transmitted. At a transmit clock frequency of 85 - Tx power consumption < 130 mW (typ) @85MHz
MHz, 24 bits of RGB data and 3 bits of LCD timing and Grayscale
control data (FPLINE, FPFRAME, DRDY) are transmitted at - Tx Power-down mode < 200 W (max)
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz - Supports VGA, SVGA, XGA and Single/Dual Pixel
clock, the data throughput is 297.5 Mbytes/sec. Also avail- SXGA.
able is the DS90C365 that converts 21 bits of LVCMOS/
- Narrow bus reduces cable size and cost
LVTTL data into three LVDS (Low Voltage Differential Sig-
- Up to 2.38 Gbps throughput
naling) data streams. Both transmitters can be programmed
for Rising edge strobe or Falling edge strobe through a - Up to 297.5 Megabytes/sec bandwidth
dedicated pin. A Rising edge or Falling edge strobe transmit- - 345 mV (typ) swing LVDS devices for low EMI
ter will interoperate with a Falling edge strobe Receiver - PLL requires no external components
(DS90CF386/DS90CF366) without any translation logic. - Compatible with TIA/EIA-644 LVDS standard
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch - Low profile 56-lead or 48-lead TSSOP package
ball grid array (FBGA) package which provides a 44 % - DS90C385 also available in a 64 ball, 0.8mm fine pitch
reduction in PCB footprint compared to the TSSOP package. ball grid array (FBGA) package


Block Diagrams

DS90C385 DS90C365




DS100868-1 DS100868-29

Order Number DS90C385MTD or DS90C385SLC Order Number DS90C365MTD
See NS Package Number MTD56 or SLC64A See NS Package Number MTD48




--14--
Plasma Display PD421


Absolute Maximum Ratings (Note 1) DS90C385SLC 2.0 W
If Military/Aerospace specified devices are required, Package Derating:
please contact the National Semiconductor Sales Office/ DS90C385MTD 12.5mW/ C above +25 oC
Distributors for availability and specifications. Package Derating:
DS90C365MTD 16 mW/ C above +25 oC
Supply Voltage(VCC ) -0.3V to +4V DS90C385SLC 10.2mW/ C above +25 oC
CMOS/TTL InputVoltage -0.5V to (VCC + 0.3V) ESD Rating
LVDS DriverOutputVoltage -0.3V to (VCC + 0.3V) (HBM, 1.5kW, 100pF) > 7 kV
LVDS OutputShort Circuit (EIAJ, 0W, 200 pF) > 500V
Duration Continuous o
Latch Up Tolerance @ 25 C > +/- 300mA
JunctionTemperature +150oC
Storage Temperature -65 C to +150oC
Recommended Operating
Lead Temperature
(Soldering,4 sec) +260oC Conditions
Solder reflowTemperature
Min Nom Max Units
(20 sec for FBGA) +220oC
Supply Voltage(VCC ) 3.0 3.3 3.6 V
MaximumPackage Power Dissipation Capacity @ 25 oC
Operating Free Air
MTD56 (TSSOP) Package: o
Temperature(TA) -10 +25 +70 C
DS90C385MTD 1.63W
Supply Noise Voltage(VCC ) 100 mVPP
MTD48 (TSSOP) Package:
DS90C365MTD 1.98W TxCLKIN frequency 20 85 MHz

SLC64 (FBGA) Package:

Electrical Characteristics
Over recommendedoperatingsupplyand temperatureranges unless otherwisespecified.
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS
VIH High Level InputVoltage 2.0 VCC V
VIL Low Level InputVoltage GND 0.8 V
VCL InputClamp Voltage ICL = -18 mA -0.79 -1.5 V
IIN InputCurrent VIN = 0.4V, 2.5V or VCC +1.8 +10 A
VIN = GND -10 0 A
LVDS DC SPECIFICATIONS
VOD Differential utputVoltage
O R L = 100W 250 345 450 mV
DVOD Change in VOD between 35 mV
complimentary outputstates
VOS OffsetVoltage(Note 4) 1.125 1.25 1.375 V
DVOS Change in VOS between 35 mV
complimentary outputstates
IOS OutputShort Circuit Current VOUT = 0V, R L = 100W -3.5 -5 mA
IOZ OutputTRI-STATE Current Power Down= 0V, +/- 1 +/- 10 A
VOUT = 0 V or VCC
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current R L = 100W, f = 32.5MHz 31 45 mA
Worst Case CL = 5 pF, f = 40 MHz 32 50 mA
DS90C385 Worst Case Pattern f = 65 MHz 37 55 mA
(Figures 1, 4)
f = 85 MHz 42 60 mA
ICCTG Transmitter Supply Current R L = 100W, f = 32.5MHz 29 38 mA
16 Grayscale CL = 5 pF, f = 40 MHz 30 40 mA
DS90C385 16 Grayscale Pattern f = 65 MHz 35 45 mA
(Figures 2, 4)
f = 85 MHz 39 50 mA
ICCTW TransmitterSupply Current R L = 100 W, f = 32.5MHz 28 42 mA
Worst Case CL = 5 pF, f = 40 MHz 29 47 mA
DS90C365 Worst Case Pattern f = 65 MHz 34 52 mA
(Figures 1, 4)
f = 85 MHz 39 57 mA




--15--
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTG Transmitter
Supply Current R L = 100W, f = 32.5MHz 26 35 mA
16 Grayscale CL = 5 pF, f = 40 MHz 27 37 mA
DS90C365 16 Grayscale Pattern f = 65 MHz 32 42 mA
(Figures 3, 4)
f = 85 MHz 36 47 mA
ICCTZ Transmitter
Supply Current Power Down= Low 10 55 A
Power Down DriverOutputsin TRI-STATE under
Power DownMode
Note 1: TMAbsolute Maximum Ratings"are those values beyondwhichthe safetyof the device cannotbe guaranteed.They are not meantto implythatthe device
shouldbe operatedat these limits.The tablesof TMElectrical Characteristics" specify conditions for device operation.
Note 2: Typicalvalues are givenfor VCC = 3.3V and TA = +25C.
Note 3: Currentinto device pins is definedas positive.Currentout of device pins is definedas negative.Voltages are referencedto groundunless otherwise
specified(exceptVOD and DVOD).
Note 4: VOS previously referredas VCM.



Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN TransitionTime (Figure 6) 1.0 6.0 ns
TCIP TxCLK IN Period (Figure 7) 11.76 T 50 ns
TCIH TxCLK IN High Time (Figure 7) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 7) 0.35T 0.5T 0.65T ns
TXIT TxIN TransitionTime 1.5 6.0 ns


Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-HighTransitionTime (Figure 5) 0.75 1.5 ns
LHLT LVDS High-to-LowTransitionTime (Figure 5) 0.75 1.5 ns
TPPos0 OutputPulse Positionfor Bit 0 (Figures 13, 14)
Transmitter f = 40 MHz -0.25 0 0.25 ns
(Note 5)
TPPos1 Transmitter
OutputPulse Positionfor Bit 1 3.32 3.57 3.82 ns
TPPos2 Transmitter
OutputPulse Positionfor Bit 2 6.89 7.14 7.39 ns
TPPos3 Transmitter
OutputPulse Positionfor Bit 3 10.46 10.71 10.96 ns
TPPos4 Transmitter
OutputPulse Positionfor Bit 4 14.04 14.29 14.54 ns
TPPos5 Transmitter
OutputPulse Positionfor Bit 5 17.61 17.86 18.11 ns
TPPos6 Transmitter
OutputPulse Positionfor Bit 6 21.18 21.43 21.68 ns
TPPos0 OutputPulse Positionfor Bit 0 (Figures 13, 14)
Transmitter f = 65 MHz -0.20 0 0.20 ns
(Note 5)
TPPos1 Transmitter
OutputPulse Positionfor Bit 1 2.00 2.20 2.40 ns
TPPos2 Transmitter
OutputPulse Positionfor Bit 2 4.20 4.40 4.60 ns
TPPos3 Transmitter
OutputPulse Positionfor Bit 3 6.39 6.59 6.79 ns
TPPos4 Transmitter
OutputPulse Positionfor Bit 4 8.59 8.79 8.99 ns
TPPos5 Transmitter
OutputPulse Positionfor Bit 5 10.79 10.99 11.19 ns
TPPos6 Transmitter
OutputPulse Positionfor Bit 6 12.99 13.19 13.39 ns




--16--
Plasma Display PD421


Transmitter Switching Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
TPPos0 OutputPulse Positionfor Bit 0 (Figures 13, 14)
Transmitter f = 85 MHz -0.20 0 0.20 ns
(Note 5)
TPPos1 TransmitterOutput Pulse Position for Bit 1 1.48 1.68 1.88 ns
TPPos2 TransmitterOutput Pulse Position for Bit 2 3.16 3.36 3.56 ns
TPPos3 TransmitterOutput Pulse Position for Bit 3 4.84 5.04 5.24 ns
TPPos4 TransmitterOutput Pulse Position for Bit 4 6.52 6.72 6.92 ns
TPPos5 TransmitterOutput Pulse Position for Bit 5 8.20 8.40 8.60 ns
TPPos6 TransmitterOutput Pulse Position for Bit 6 9.88 10.08 10.28 ns
TSTC TxIN Setup to TxCLK IN (Figure 7) 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 7) 0 ns
TCCD TxCLK IN to TxCLK OUT Delay (Figure 8) TA = 25 C, VCC 3.8 6.3 ns
= 3.3V
TxCLK IN to TxCLK OUT Delay (Figure 8) 2.8 7.1 ns
TJCC Jitter Cycle-to-Cycle(Figures 15, 16) (Note 6)
Transmitter f = 85 MHz 110 150 ps
f = 65 MHz 210 230 ps
f = 40 MHz 350 370 ps
TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms
TPDD Transmitter Power DownDelay (Figure 12) 100 ns
Note 5: The Minimumand MaximumLimits are based on statisticalanalysis of the device performanceover process, voltage,and temperatureranges. This
parameteris functionality testedonlyon AutomaticTest Equipment(ATE).
Note 6: The limitsare based on benchcharacterization of the device'sjitterresponseover the powersupplyvoltagerange.Outputclockjitteris measured with a
cycle-to-cyclejitterof +/3nsappliedto the inputclocksignalwhiledata inputsare switching(See Figures 15 and 16).A jittereventof 3ns, represents worsecase
jumpin theclockedge frommostgraphicscontroller VGA chipscurrently available.Thisparameteris used whencalculatingsystemmarginas described in AN-1059.



AC Timing Diagrams




DS100868-4

FIGURE 1. TMWorst Case Test Pattern (Note 7)




--17--
P89C51RD2BA
DESCRIPTION FEATURES
The P89C51RB2/RC2/RD2 device contains a non-volatile - 80C51 Central Processing Unit
16kB/32kB/64kB Flash program memory that is both parallel
programmable and serial In-System and In-Application - On-chip Flash Program Memory with In-System Programming
Programmable. In-System Programming (ISP) allows the user to (ISP) and In-Application Programming (IAP) capability
download new code while the microcontroller sits in the application. - Boot ROM contains low level Flash programming routines for
In-Application Programming (IAP) means that the microcontroller
downloading via the UART
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link. - Can be programmed by the end-user application (IAP)
A default serial loader (boot loader) program in ROM allows serial - 6 clocks per machine cycle operation (standard)
In-System programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application - 12 clocks per machine cycle operation (optional)
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.
- Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
This device executes one machine cycle in 6 clock cycles, hence per machine cycle
providing twice the speed of a conventional 80C51. An OTP
configuration bit lets the user select conventional 12 clock timing
- Fully static operation
if desired. - RAM expandable externally to 64 kB
This device is a Single-Chip 8-Bit Microcontroller manufactured in - 4 level priority interrupt
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% compatible with
- 7 interrupt sources
the 80C51 instruction set. - Four 8-bit I/O ports
The device also has four 8-bit I/O ports, three 16-bit timer/event - Full-duplex enhanced UART
counters, a multi-source, four-priority-level, nested interrupt structure, ± Framing error detection
an enhanced UART and on-chip oscillator and timing circuits.
± Automatic address recognition
The added features of the P89C51RB2/RC2/RD2 makes it a
powerful microcontroller for applications that require pulse width
- Power control modes
modulation, high-speed I/O and up/down counting capabilities such ± Clock can be stopped and resumed
as motor control. ± Idle mode
± Power down mode
- Programmable clock out
- Second DPTR register
- Asynchronous port reset
- Low EMI (inhibit ALE)
- Programmable Counter Array (PCA)
± PWM
± Capture/compare




--18--
Plasma Display PD421


ORDERING INFORMATION
PHILIPS
(EXCEPT NORTH PHILIPS NORTH MEMOR Y FREQUENCY (MHz)
AMER CA TEMPERA TURE
AMER CA)
AMERICA) AMERICA VOLTAGE
FLASH RAM RANGE (5C) 6 CLOCK 12 CLOCK DWG #
PART ORDER PART ORDER RANGE
AND PACKAGE MODE MODE
NUMBER NUMBER
PART MARKING
1 P89C51RB2HBA P89C51RB2BA 16 kB 512 B 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
2 P89C51RB2HBBD P89C51RB2BBD 16 kB 512 B 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
3 P89C51RC2HBP P89C51RC2BP 32 kB 512 B 0 to +70, PDIP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
4 P89C51RC2HBA P89C51RC2BA 32 kB 512 B 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
5 P89C51RC2HFA P89C51RC2FA 32 kB 512 B ±40 to +85, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
6 P89C51RC2HBBD P89C51RC2BBD 32 kB 512 B 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
7 P89C51RC2HFBD P89C51RC2FBD 32 kB 512 B ±40 to +85, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
8 P89C51RD2HBP P89C51RD2BP 64 kB 1 kB 0 to +70, PDIP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
9 P89C51RD2HBA P89C51RD2BA 64 kB 1 kB 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
10 P89C51RD2HBBD P89C51RD2BBD 64 kB 1 kB 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1




--19--
BLOCK DIAGRAM


P0.0±P0.7 P2.0±P2.7




POR T 0 POR T 2
DRIVERS DRIVERS

VCC


VSS
RAM ADDR RAM POR T 0 POR T 2 FLASH
REGISTER LATCH LATCH




8

B STACK
REGISTER ACC
POINTER


PROGRAM
ADDRESS
TMP2 TMP1 REGISTER




BUFFER
ALU

SFRs
TIMERS PC
PSW INCRE-
P.C.A.