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Page Title Index Primary CPU (Socket 7) Clock Generator Triton II controller (TXC) Synchronous Cache, Lower 256K Synchronous Cache, Upper 256K Memory Modules 0 & 1 Memory Modules 2 & 3 System ROM PIIX3 PCI IDE Interface AIP Serial Ports, Floppy, USB Parallel Ports Keyboard/Mouse Ports Battery, RTC Circuit Front Panel PCI Slots 1 and 2 PCI Slots 3 and 4 ISA Slots Pullup/Pulldown Resistors Switching Power Supply Fiducials, Holes, Spare Gates Decoupling Caps
Released Rev. B.1
INTEL CORP. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. Title Index Size Document Number A 82430HX Date: June 19, 1997 Sheet REV B.1 24
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4..6 HD[0..63] CPUVCORE 1111111 111222333333 1890123456 789013000111 8888847890123456789188888888 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 HDPA0 HDPA1 HDPA2 HDPA3 HDPA4 HDPA5 HDPA6 HDPA7 3 HCLKCPU 116 102 112 101 97 96 91 90 72 55 54 36 71 35 53 17 34 52 16 69 33 51 15 68 50 48 67 47 66 46 65 45 44 63 43 62 42 61 41 60 59 2 78 20 58 39 77 38 57 76 56 94 75 100 74 99 105 109 110 115 120 119 125 129 73 70 49 64 40 95 93 130 256 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 CLK VVVVVVVVVVVVVVVVVVVVVVVVVVVV CCCCCCCCCCCCCCCCCCCCCCCCCCCC OOOOOOOOOOOOOOOOOOOOOOOOOOOO RRRRRRRRRRRRRRRRRRRRRRRRRRRR EEEEEEEEEEEEEEEEEEEEEEEEEEEE A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADSC# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# FERR# BREQ HITM# HIT# PCHK# HLDA AP LOCK# APCHK# PRDY PCD PWT CACHE# ADS# D/C# W/R# M/IO SCYC FRCMC# IERR# SMIACT# PM0/BP0 PM1/BP1 BP2 BP3 TCK TDO TDI TMS TRST# PICCLK PICD0 PICD1 PHITM# PHIT# PBGNT# PBREQ# BF0 BF1 283 301 263 319 282 300 262 318 281 280 261 279 260 278 259 277 258 276 216 228 211 222 246 227 221 265 264 302 245 285 270 252 271 253 272 254 273 255 140 229 268 250 215 230 248 225 210 200 220 267 159 231 249 287 155 274 182 135 219 139 145 149 150 126 131 132 136 141 106 111 122 199 189 205 209 181 176 TP084 1 HFRCMC# TP011 1 TP087 TP088 TP090 TP089 TP007 TP091 TP006 TP005 TP004 TP002 TP014 TP021 TP020 TP015 TP017 TP016 HBF0 HBF1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HBE#0 HBE#1 HBE#2 HBE#3 HBE#4 HBE#5 HBE#6 HBE#7 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31
HA[3..31]
3..6
CPUVCORE
C195 1 2 1uF C187 1 2 1uF C218 1 2 1uF C209 1 2 1uF HADSC# 5,6 4..6 C180 1 2 1uF C194 1 2 1uF C221 1 2 1uF C207 1 2 1uF C213 1 2 1uF HLOCK# 4 C174 1 2 1uF HCACHE# 4 HADS# 4 HD/C# 4 HW/R# 4..6 HM/IO# 4
C196 1 2 1uF C188 1 2 1uF C186 1 2 1uF C205 1 2 1uF C177 1 2 1uF C178 1 2 1uF C179 1 2 1uF C206 1 2 1uF C217 1 2 1uF C193 1 2 1uF
C212 1 2 1uF C219 1 2 1uF C199 1 2 1uF C200 1 2 1uF C201 1 2 1uF
CPUVIO
RP71 1 2 3 4 4.7K 8 7 6 5 HDPA0 HDPA1 HDPA2 HDPA3
HBE#[0..7]
RP69 1 2 3 4 4.7K 8 7 6 5 HDPA7 HDPA6 HDPA5 HDPA4
RP72 1 2 3 4 4.7K 8 7 6 5 HFRCMC# HPENA# HWB/WTA#
TP083 TP019 TP086 TP018 HAPA TP085 TP092 TP012 TP013
1 1 1 1 1 1 1 1
HFERR# TP198 HHITM# TP2 TP208 TP1 TP207 TP214 TP12 TP11
10 4
RP75 1 2 3 4 4.7K 8 7 6 5 HAPA HBUSCHKA# HFLUSHA# HSMIACT#
CPUVIO
U27D 15 HA20M# 1 2 9 7407S 8
TP206 TP197 HSMIACT# TP209 TP210 TP211 TP212 TP220 TP213 TP221 TP222 TP223 CPUVIO TP13 TP7 TP8 TP6 TP5 TP3 TP4 1 R102 2 330 1 HBF0R 3 5 JB3 R110 1 2 330 R114 1 2 C159 1 2 JB2 2 4 6 HBF1R 0.1uF C173 1 2 0.1uF C160 1 2 0.1uF C163 1 2 0.1uF 4 CORE/BUS SPEED RATIO 3/2X 2X 3X 5/2X JB2 1-3,2-4 3-5,2-4 1-3,4-6 3-5,4-6 C157 1 2 220uF C172 1 2 0.1uF C161 1 2 0.1uF C154 1 2 0.1uF C158 1 2 0.1uF C155 1 2 0.1uF C162 1 2 0.1uF C164 1 2 0.1uF C130 1 2 0.1uF
R100 4.7K 1 2 R98 4.7K 1 2 R111 4.7K 1 R97 2 4.7K 4 HBOFF# 10 HINTR 10 HNMI 10 HIGNNE# 4 HKEN# 4 HAHOLD 4 HEADS# 4 HBRDY# 10 HRESET 4 HNA# 4 HINIT 10 HSMI#
HA20M3V#
HFLUSHA#
1
R86 330
2
R92 10K 1 2 R87 4.7K 1 2 1 R93 4.7k 2
HBUSCHKA# HWB/WTA# TP224 1 TP003 HPENA#
10 HSTPCLK#
185 251 206 201 192 170 306 165 286 175 257 160 180 269 190 191 196 202 186 166 195 169
R130 330 1 2 1 2 R131 330
BOFF# A20# INTR NMI IGNNE# KEN# FLUSH# AHOLD EADS# BRDY# RESET INV NA# BUSCHK# WB/WT# INIT SMI# R/S# PEN# STOPCLK# HOLD EWBE#
R104 1 330 2
D/P# UPVRM#
212 226 266
TP093 TP901 TP097
1 1 1
TP215 TP9 TP218 R115 1 330
330
HHOLDA HEWBEA#
VCC2DET
R99 1 330 2 TP225 TP226 TP227 TP228 HBRDYC# 1 1 1 1 TP001 TP009 TP008 TP010 179 275 146 151 152 BRDYC# NC/MPBOFF# NC/BHOLD NC/CHOLD NC/DHOLD U33 P5II
CPUTYP
142
HCPUTYPA
2
NC/SUSPACK# NC/TEST1 NC/TEST3
171 172 320
TP094 TP095 TP096
1 1 1
TP216 TP217 TP67
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. Title
INTEL CORP. PRIMARY CPU (Socket 7) Size Document Number C 82430HX Date: June 19, 1997 Sheet
2 of
REV B.1 24
PIIX3OSC 10 CPUVIO PCLK(0:3) R88 HA27PU 2 1 4.7K 2 R89 4.7K 1 RAWOSC J30 3 2 JUMPER 1 1 2 JP3 J29 3 JUMPER 2 2 2 1 JP3 TP24 1 TP029 5 U28 OE 1 ISA14MHZ APIC14MHZ 28 27 PIIX3OSCR RAWOSCR 1 HCLK0 HCLK1 HCLK2 HCLK3 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 ALWAYS STUFFED L13 1 Y1 1 2 1.5uH 2 1 0 R80 2 CLKGENP1 1 14 20 26 8 1 C145 2 10pF C143 1 2 0.1uF C147 2 1 0.1uF J25 1 2,4..6 HA27 1 2 2 R154 8.2K HA27PD 3 JP3 JUMPER 3 C142 2 1 0.1uF C136 2 1 0.1uF C144 1 2 KBD_CLK1R 0.1uF 48MCLKFB2 48MCLKFB1 R77 48MCLKPU 2 22 4 1 0 12 11 P R CLK C L D 1 3 Q U26B 9 2 3 D P R CLK C L 1 74ALS74AS Q U26A R74 5 1 22 Q 6 74ALS74AS STUFF WITH 9159 2 1 R75 2 22 1 KBD_CLK 15 2 22 R72 1 AIPCLK 12 R67 R70 1 10K 2 VCC 1 22 2 USBCLK 10 R71 2 STUFF WITH 9169 22 1 PCLKPIIX3 10 R68 2 22 1 PCLKTXC 4 CLKVCC3 22 VCC3 VCC3 VCC3 VCC3 VCC3 ICS9159-02S GND GND GND GND 4 23 17 11 2 2 22 R64 1 PCLK3 19 24MHZ 12MHZ 24 25 AIPCLKR KBD_CLKR R62 2 22 R63 1 PCLK2 19 1 PCLK1 18 6 7 9 10 15 16 18 19 21 22 HCLKCPUR HCLKSRAM0R HCLKSRAM1R 22 TP022 PCLK0R PCLK1R PCLK2R PCLK3R PCLKTXCR PCLKPIIX3R 1 TP922 22 R66 CLKSEL0 CLKSEL1 13 12 SEL0SEL12 HCLKSRAM1 5 R69 2 HCLKSRAM0 6 22 22 22 1 DO NOT STUFF R79 22 R73 1 2 HCLKCPU 2 R81 1 1 1 R76 2 HCLKTXC 4 CLKSEL_PU 2 R78 22 U3D 74LS125S 12 11 OSCR 1 22 50MHz 60MHz 66MHz RESERVED BCLK(0:5) 25MHz 30MHz 33MHz RESERVED JUMPER 1 2-3 2-3 1-2 1-2 JUMPER 2 2-3 1-2 2-3 1-2 JUMPER 3 X 1-2 2-3 2-3 1 3 R5 2 OSC 20 R2 1 220 2 OSCPULLDN
XTAL1 XTAL2
2 3
X1 X2
R61 2 22 1 PCLK0 18
CPUVIO
14.31818MHz
1 C146 2 10pF
Q
8
48MFFOUT1
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Clock Generator Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
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2 HCACHE# 2 HKEN# 2 HSMIACT# 2 HADS# 2 HBRDY# 2 HNA# 2 HAHOLD 2 HEADS# 2 HBOFF# 3 HCLKTXC 2,3,5,6 HA[3..31] 1 5 8 H C L K I N 22111221112212 01698235313323 56751943983192 BEANBASKCHWDMH OAHARDMEAL///I FDO#DSINCORCIT FSL Y#A#HC##OM ## ##D # C/EK TI## #N V
HLOCK# HW/R# HD/C# HM/IO# HHITM#
2 2,5,6 2 2 2 2,5,6 2,5,6
HBE#[0..7] HD[0..63] HHHHHHHH BBBBBBBB EEEEEEEE ######## 76543210 11111111 76666555 76543210 BBBBBBBB EEEEEEEE 76543210 ######## HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 6666555555555544444444443333333333222222222211111111119876543210 321098765432109876543210987654321098765432109876543210 1111111111111111111111121222222222222222222222223333 244466868880010021213122333847799909001021214246462868416880000 1132123312413461274877565856098942341235163846786785877525658675 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 6666555555555544444444443333333333222222222211111111119876543210 321098765432109876543210987654321098765432109876543210 90 15 14 33 13 52 32 12 51 11 50 30 10 49 29 9 48 47 27 7 46 26 6 45 25 66 44 24 4 23 3 22 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
U23
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 MRAS#R0 MRAS#R1 MRAS#R2 MRAS#R3 TP027 TP026 TP025 TP024 RP67 MCAS#0 MCAS#4 MCAS#2 MCAS#6 1 2 3 4 10 8 7 6 5 MCAS#R0 MCAS#R1 MCAS#R2 MCAS#R3 MCAS#R4 MCAS#R5 MCAS#R6 MCAS#R7 7 7 8 8 MAA0 MAA1 MAB0 MAB1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7
275 315 252 316 312 272 271 311 291 251 310 270 290 250 309 289 269 249 273 254 253 294 293 274 313 314 255 295 292 121 110 109 96 187 197 186 196 145 159 131 173 130 144 120 172 276 236 296 256 317 297 277 257 237 298 258 319 318 278 133 123 146 113 132 124 134 122 235
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 RAS0# RAS1# RAS2# RAS3# RAS4# RAS5# RAS6# RAS7# CAS0# CAS1# CAS2# CAS3# CAS4# CAS5# CAS6# CAS7# MAA0 MAA1 MAB0 MAB1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MPD0 MPD1 MPD2 MPD3 MPD4 MPD5 MPD6 MPD7 MWE#
PCLKIN AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCLKTXC
3 10,18,19
AD[0..31]
7,8 MCAS#[0..7]
C/BE0# C/BE1# C/BE2# C/BE3# FRAME# DEVSEL# IRDY# TRDY# STOP# LOCK# REQ0# REQ1# REQ2# REQ3# GNT0# GNT1# GNT2# GNT3# PHLD# PHLDA# PAR SERR# RST# TEST# MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDMMMMMMMMMM 666655555555554444444444333333333322222222221111111111DDDDDDDDDD 3210987654321098765432109876543210987654321098765432109876543210 5131347111112222575726911112222237151799111222225333558111122223 5678909046891248456700816790246846779879478002663568890167912440 116804314 84908242 205091433 072891324 CC AACC DDCO VSSE #### 2232 7905 9909 GB WW EE ## 33 22 01 T ITT OII 1OO 098 333 220 433 CCC TTT AAA GGG 198 0 TTTTTTTT IIIIIIII OOOOOOOO 76543210 33222222 20838660 22281107 CCCCCCCC TTTTTTTT AAAAAAAA GGGGGGGG 76543210 T W E # 2 8 0
31 28 8 5 86 89 87 88 91 85 67 69 71 73 68 70 72 74 64 65 92 93 239 301
C/BE#0 C/BE#1 C/BE#2 C/BE#3
C/BE#[0..3]
10,18,19
RP68 MCAS#3 MCAS#7 MCAS#1 MCAS#5 1 2 3 4 10 8 7 6 5
FRAME# DEVSEL# IRDY# TRDY# STOP# PLOCK# PREQ#0 PREQ#1 PREQ#2 PREQ#3 PGNT#0 PGNT#1 PGNT#2 PGNT#3 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PGNT#[0..3]
10,18,19,21 10,18,19,21 10,18,19,21 10,18,19,21 10,18,19,21 18,19,21 4,18,19,21 4,18,19,21 4,18,19,21 4,18,19,21 18,19,21 VCC
R37 2
7,8
MA[2..11]
1 R52 TESTIN# 2 1 R57 10K 1
10K 1 PHOLD# PHLDA# PAR SERR# 2 10K PCIRST# VCC 2
10 CPUVIO 10 10,18,19,21 10,18,19,21 5,6,10,18,19
R56 100
VDD5V
94 TXC
VDD5V
1 C131 2 1.0uF
1 R54 330
2
7,8 MP[0..7] R153 1 2 22
7,8
MWE#
MWE#R
MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 6666555555555544444444443333333333222222222211111111119876543210 321098765432109876543210987654321098765432109876543210
CTWE# 7,8 MD[0..63]
5 5,6
CTAG[0..10]
CPUVIO 2 R91 330 10 PIIX3INIT U2B 15 KBRST# 3 4 74HCT14S KBRST 1 3 2 74ALS32S 7407S HINITD 1 2 HINIT 2 MRAS#R0 MRAS#R2 MRAS#R1 MRAS#R3 8 7 6 5 10 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. Title RP66 1 2 3 4 MRAS#0 MRAS#2 MRAS#1 MRAS#3 1 U16A U27A MRAS#R[0..3] MRAS#[0..3]
CBWE# 5,6 CGWE# 5,6 COE# 5,6 CCS# 5,6 CADS# 5,6 CADV# 5,6
7,8
INTEL CORP. Triton II controller (TXC) Size Document Number C 82430HX Date: June 19, 1997 Sheet 4 of
REV B.1 24
2,4,6HD[0..63] 2..4,6HA[3..18] 2,4,6HBE#[0..7] 3 HCLKSRAM1 4,6 CCS# 4,6 COE# 4,6 CADV# 2,6 HADSC# 4,6 CADS# 4,6 CBWE# 4,6 CGWE#
HA3 37 HA4 36 HA5 35 HA6 34 HA7 33 32 HA8 HA9 100 HA10 99 HA11 82 HA12 81 HA13 44 HA14 45 HA15 46 HA16 47 HA17 48 HBE#0 HBE#1 HBE#2 HBE#3 93 94 95 96
U22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 BW1# BW2# BW3# BW4#
89 98 92 97 86 83 84 85 87 88 64 6 CBURST_SEQ2 6 CBURST_SEQ1 6 CRPU1 VCC CPUVIO RP70 1 2 3 4 6 CRPU2 2,4,6HW/R# 4,6,10,18,19PCIRST# 10K 8 7 6 5 31 50 51 1 80 30 49
CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC# BWE# GW# ZZ MODE NC NC NC NC NC NC 32KX32 SRAM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD1 VDD2 RESET# W/R# NF1 NF2 FT#
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 16 66 38 39 42 43 14
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 VDD1A VDD2A PCIRST#D HW/R#D CTAG10D NF2D CRPU2
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 STUFFING OPTION VCC 0 1 1 0 C228 2 1 C227 2 0.01uF R132 2 2 R133 C229 1 3.3uF 2 2 C230 1 1uF HBE#4 HBE#5 HBE#6 HBE#7
37 36 35 34 33 32 100 99 82 81 44 45 46 47 48 93 94 95 96
U31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 BW1# BW2# BW3# BW4#
0.01uF 1
89 98 92 97 86 83 84 85 87 88 64 2 R83 220 1 31 50 51 1 80 30 49
CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC# BWE# GW# ZZ MODE NC NC NC NC NC NC 32KX32 SRAM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD1 VDD2 RESET# W/R# NF1 NF2 FT#
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 16 66 38 39 42 43 14
HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 VDD1B VDD2B PCIRST#C HW/R#C CTAG10C NF2C
STUFFING OPTION VCC 0 1 1 0 2 C232 0.01uF 1 2 R135 2 2 R136 2 C234 1 1uF
C233 2 C231 1 0.01uF 3.3uF 1
CPUVIO 0 2 R144 1
0 2
R156 1
0 R145 1 2 0 2 R146 1
0 R157 1 2 0 2 R158 1
10K R152 2 1
1K R149 2 1
CRPD3
CTAG10
CTAG[0..10] R65 CPUVIO HA18 2 0 1 R106 2 4.7K 1 R101 2 4.7K R84 1 2 4.7K R95 1 2 4.7K HA31 R96 HA31 2 1 4.7K 27 20 22 HA30 R94 HA30 2 1 4.7K HA29 R103 HA29 1 2 4.7K HA28 R107 HA28 1 2 4.7K HA13 HA14 HA15 HA17 HA7 HA5 HA12 HA10 HA9 HA8 HA16 HA6 HA11 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 U24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 WE# CE# OE# SRAM32KX8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 11 12 13 15 16 17 18 19 CTAG0 CTAG1 CTAG2 CTAG3 CTAG4 CTAG5 CTAG6 CTAG7 HA13 HA14 HA15 HA17 HA7 HA5 HA12 HA10 HA9 HA8 HA16 HA6 HA11 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 27 20 22 U25 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 WE# CE# OE# SRAM32KX8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 11 12 13 15 16 17 18 19 CTAG8 CTAG9 CTAG10T UNUSD11 UNUSD12 UNUSD13 UNUSD14 UNUSD15 1 CTAG10 2 R155 1
4,6
0 STUFFING OPTION VCC RP73 8 7 6 5 10K CPUVIO R82 CTAG10 1 2 100K R90 2 1 4.7K CONFIGURATION RESISTORS 1 2 3 4
CA18 4 CTWE#
6
CACHE CONFIG THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. NO SRAM 256K PBSRAM 512K PBSRAM
HA31 1 1 0
HA30 1 0 1
HA29 X 1 0
HA28 X 1 0 Title Synchronous Cache, Lower 256K Size Document Number C 82430HX Date: June 19, 1997 Sheet 5 of REV B.1 24 INTEL CORP.
2..5 HA[3..17] 2,4,5 HBE#[0..7] U29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 BW1# BW2# BW3# BW4# U32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 BW1# BW2# BW3# BW4#
37 HA3 36 HA4 35 HA5 34 HA6 33 HA7 32 HA8 HA9 100 HA10 99 HA11 82 HA12 81 HA13 44 HA14 45 HA15 46 HA16 47 HA17 48 HBE#0 HBE#1 HBE#2 HBE#3 93 94 95 96
3 HCLKSRAM0 4,5 CCS# 5 CA18 4,5 COE# 4,5 CADV# 2,5 HADSC# 4,5 CADS#
CRPU3
89 98 92 97 86 83 84 85 87 88 64 31 50 51 1 80 30 49
CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC# BWE# GW# ZZ MODE NC NC NC NC NC NC 32KX32 SRAM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD1 VDD2 RESET# W/R# NF1 NF2 FT#
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 16 66 38 39 42 43 14
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 VDD1C VDD2C PCIRST#B HW/R#B CTAG10B NF2B
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 STUFFING OPTION VCC 0 1 1 0 2 C236 0.01uF 1 2 R147 2 2 R148 C238 2 1 1uF HCLKSRAM0 CCS# CA18 CRPU3 COE# CADV# HADSC# CADS# HBE#4 HBE#5 HBE#6 HBE#7
37 36 35 34 33 32 100 99 82 81 44 45 46 47 48 93 94 95 96
C237 2 C235 1 0.01uF 3.3uF 1
89 98 92 97 86 83 84 85
CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC# BWE# GW# ZZ MODE NC NC NC NC NC NC 32KX32 SRAM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD1 VDD2 RESET# W/R# NF1 NF2 FT#
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 16 66 38 39 42 43 14
HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 VDD1D VDD2D PCIRST#A HW/R#A CTAG10A NF2A
STUFFING OPTION VCC 0 1 1 0 2 C240 0.01uF 1 2 R150 2 2 R151 C242 2 1 1uF
C241 2 C239 1 0.01uF 3.3uF 1
87 88 CRPD1 64 0 2 R138 1 31 50 51 1 80 30 49
0 2 0 2 0 2
R141 1 R142 1 R143 1
0 R139 1 2 0 2 R140 1 CTAG10
1K R137 2 1
1K R134 2 1
5 CBURST_SEQ1 4,5 CBWE# 4,5 CGWE# 4,5,10,18,19 PCIRST# 2,4,5 HW/R# 4,5 CTAG10 5 CRPU1
CBURST_SEQ1
HD[0..63] 1 CPUVIO RP74 1 2 3 4 10K 8 7 6 5 CRPU3 CRPU2 5 CBURST_SEQ2 2 5 R55 220
2,4,5
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Synchronous Cache, Upper 256K Size Document Number B 82430HX Date: June 19, 1997 Sheet 6 of REV B.1 24
MODULE 0 (BANK 1)
4,8 MRAS#[0..3] MRAS#0 MRAS#1 4,8 MCAS#[0..7] 4,8 MA[2..11] 4,8 MWE# U18 47 44 45 34 33 MCAS#0 MCAS#1 MCAS#2 MCAS#3 40 43 41 42 12 13 14 15 16 17 18 28 31 32 19 29 67 68 69 70 11 46 48 66 71 DRAM POWER 5 VOLTS 1-3,2-4 3.3 VOLTS 3-5,4-6 VCC 10 30 59 WRAS0RAS1RAS2RAS3CAS0CAS1CAS2CAS3A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ID1 ID2 ID3 ID4 RES1 RES2 RES3 RES4 RES5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64 36 37 35 38 MP0 MP1 MP2 MP3 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 TP27 TP28 TP29 TP30 1 1 1 1 MCAS#4 MCAS#5 MCAS#6 MCAS#7
MODULE 1 (BANK 1)
U19 47 44 45 34 33 40 43 41 42 12 13 14 15 16 17 18 28 31 32 19 29 67 68 69 70 11 46 48 66 71 10 30 59 WRAS0RAS1RAS2RAS3CAS0CAS1CAS2CAS3A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ID1 ID2 ID3 ID4 RES1 RES2 RES3 RES4 RES5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64 36 37 35 38 MP4 MP5 MP6 MP7 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
4 MAA0 4 MAA1
MAA0 MAA1
MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 TP23 TP923 TP25 TP26 1 1 1 1 TP039 TP038 TP041 TP040
MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 TP105 TP102 TP101 TP023
VCC VCC VCC 32MX36SIMV
DQ8/P0 DQ17/P1 DQ26/P2 VCC VCC DQ35/P3 VCC 32MX36SIMV
CPUVIO JB1 1 2 3 4 5 6 JB3
DRAMVCC 8,24
MD[0..63] MP[0..7]
4,8 4,8
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. INTEL CORP. Title Memory Modules 0 & 1 Size Document Number C 82430HX Date: June 19, 1997 Sheet REV B.1 24
7 of
MODULE 2 (BANK 2)
4,7 MRAS#[0..3] MRAS#2 MRAS#3 4,7 MCAS#[0..7] 4,7 MA[2..11] 4,7 MWE# U20 47 44 45 34 33 MCAS#0 MCAS#1 MCAS#2 MCAS#3 40 43 41 42 12 13 14 15 16 17 18 28 31 32 19 29 67 68 69 70 11 46 48 66 71 10 30 59 WRAS0RAS1RAS2RAS3CAS0CAS1CAS2CAS3A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ID1 ID2 ID3 ID4 RES1 RES2 RES3 RES4 RES5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64 36 37 35 38 MP0 MP1 MP2 MP3 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 TP45 TP46 TP47 TP48 1 1 1 1 MCAS#4 MCAS#5 MCAS#6 MCAS#7
MODULE 3 (BANK 2)
U21 47 44 45 34 33 40 43 41 42 12 13 14 15 16 17 18 28 31 32 19 29 67 68 69 70 11 46 48 66 71 10 30 59 WRAS0RAS1RAS2RAS3CAS0CAS1CAS2CAS3A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ID1 ID2 ID3 ID4 RES1 RES2 RES3 RES4 RES5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64 36 37 35 38 MP4 MP5 MP6 MP7 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
4 MAB0 4 MAB1
MAB0 MAB1
MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 TP41 TP42 TP43 TP44 1 1 1 1 TP112 TP111 TP110 TP109
MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 TP103 TP107 TP108 TP113
VCC VCC VCC 32MX36SIMV
DQ8/P0 DQ17/P1 DQ26/P2 VCC VCC DQ35/P3 VCC 32MX36SIMV
7,24 DRAMVCC
MD[0..63] MP[0..7]
4,7 4,7
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. Title
INTEL CORP. Memory Modules 2 & 3 Size Document Number C 82430HX Date: June 19, 1997 Sheet
8 of
REV B.1 24
VCC
1 U2C 5 6 74HCT14S 3 SA16/17 JP3 INSTALL IF 1M FLASH R9 1 0 INSTALL IF 2M FLASH R6 2 0 BIOSMSB 10,12,15,20,21 SA[0..19] 1 SA17 2 SA16 1 C36 2 O.1uF JP3 RECOVERY 2-3 FL_VPP FL_PNPPU 2 3 NON-PNP 2-3 PNP 1-2 SA16/17# J11 1 2 2 NORMAL 1-2 J12 1 MODE POS MODE POS R14 8.2K +12V
10,20,21 MEMW# 10,20,21 MEMR# 10 ROMCS#
SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 U16D 12 11 F002CE# 13 74ALS32S
40 1 2 3 4 5 6 36 7 8 14 15 16 17 18 19 20 21 9 24 22 10
U6 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
25 26 27 28 32 33 34 35
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
NC NC NC NC
13 29 37 38
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 31 24 22 30
U7 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
13 14 15 17 18 19 20 21
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
10,16 XOE#
WE# OE# CE# PWD# VPP 11 28F002BXTSOP
WE# OE# CE# PWD# VPP 28F001BX
1
OPTIONAL 2MB FLASH
R10 VCC 1 2 8.2K J3 1 O JP1 15,16 XD[0..7] ALLOWS PROGRAMMING OF BOOT BLOCK IN MANUFACTURING FL2MPU
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title System ROM Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
9 of
9,10,12,15,20,21 SA[8..19] U15 17 PWROK 3 PCLKPIIX3 3 PIIX3OSC 4,18,19 AD[0..31] 126 132 136 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE#0 C/BE#1 C/BE#2 C/BE#3 206 205 204 203 202 201 200 199 197 194 193 192 191 190 189 188 177 176 175 174 173 172 171 168 166 165 164 163 162 161 160 159 198 187 178 167 PWROK PCICLK OSC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BEOC/BE1C/BE2C/BE3PAR PHOLDSYSCLK BALE AEN LA17/DA0 LA18/DA1 LA19/DA2 LA20/CS3P LA21/CS1P LA22/CS3S LA23/CS1S SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 USBP0USBP0+ USBP1USBP1+ USBCLK MIRQ0 MEMCS16MEMWSMEMWMEMRSMEMRIOCHRDY IORIOWSD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 VCC/VCC3 INTR SMISTPCLKNMI IGNNEDACK0DACK1DACK2DACK3DACK5DACK6DACK7TC REFRESHSPKR XDIRXOERTCALE BIOSCSRTCCSKBCSRSTDRV 186 109 153 64 20 86 84 82 80 76 74 72 69 68 67 66 63 61 59 57 145 144 143 142 146 147 70 90 22 88 19 18 23 24 17 16 14 13 11 9 8 7 92 94 96 98 100 101 102 107 130 122 123 124 135 121 85 29 60 21 89 93 97 62 31 117 141 140 148 137 138 139 28 114 113 112 115 116 119 118 127 128 134 129 MEMWR# SMEMWR# MEMRR# SMEMRR# IORR# IOWR# SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 PBFVCC 0 HINTR 2 HSMI# 2 HSTPCLK# 2 HNMI 2 HIGNNE# 2 DACK#0 DACK#1 DACK#2 DACK#3 DACK#5 DACK#6 DACK#[0..7] DACK#7 22 R35 2 1 T/CR T/C REFRESH# 20,21 SPKR 17 XDIR# 16 XOE# 9,16 RTCALE 16 ROMCS# 9 RTCCS# 16 ROM_KB# 15 ICHRDY 11 IIOR#R 11 IIOW#R 11 DDAK0 11 DDAK1 11 11 SDIR SOE# VCC IOCHRDY SD[0..15] 12,20,21 12,16,20,21 2 MIRQ0 MEMCS16# SYSCLKR BALER AENR LA17 LA18 LA19 LA20 LA21 LA22 LA23 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 PAR 4,18,19,21 PHOLD# 4 2 1 BALE R34 22 R45 2 22 LA[17..23] SA[0..7] 11,20,21 9,10,12,15,20,21 SOE# SDIR 19 1 1 AEN 12,20 DD[0..15] DD0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 2 3 4 5 6 7 8 9 U14 A1 A2 A3 A4 A5 A6 A7 A8 18 17 16 15 14 13 12 11 SA8 SA15 SA14 SA13 SA12 SA11 SA10 SA9
20,21
B1 B2 B3 B4 B5 B6 B7 B8
G DIR 74ALS245
DD14 DD15 VCC 2 R48 10K 1 USBCLK 11,21 20,21 2 3 2 R32 22 R44 22 2 R33 22 1 R46 22 R42 22 R40 2 22 R53 1 0 INSTALL FOR PIIX3 2 CPUVIO VCC 1 IOW# 16,20,21 1 IOR# 16,20,21 2 SMEMR# 20,21 1 MEMR# 9,20,21 1 SMEMW# 20,21 1 MEMW# 9,20,21 VCC INSTALL FOR PIIX DD8 DD9 DD10 DD11 DD12
USBP0USBP0+ USBP1USBP1+
13 13 13 13
2 3 4 5 6 7 8 9 19 1
U17 A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
18 17 16 15 14 13 12 11
SA16 SA17 SA18 SA19 SBHE# 20,21
G DIR 74ALS245
RP57 5 6 7 8 10K DDSAPU1 4 3 2 1 DDSAPU2 DDSAPU3 DDSAPU4
4,18,19 C/BE#[0..3]
4,18,19,21 FRAME# 4,18,19,21 TRDY# 4,18,19,21 IRDY# 4,18,19,21 STOP# 1 2 AD18 PXIDSEL 4,18,19,21 DEVSEL# PIRQ#0 18,19,21 PIRQ#[0..3] PIRQ#1 PIRQ#2 PIRQ#3 4,18,19,21 SERR# 4 PHLDA# 220 R51 11,12,15,16,20,21 IRQ[0..15] IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15
179 181 180 185 154 184 149 150 151 152 3 110 4 58 56 34 33 32 5 10 73 75 77 83 81 120 125 87 30 12 25 91 95 99 71 6 15 55 50 49 48 47 46 45 44 43 41 40 39 38 37 36 35 108 111
FRAMETRDYIRDYSTOPIDSEL DEVSELPIRQAPIRQBPIRQCPIRQDSERRPHLDAIRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8IRQ9 IRQ10 IRQ11 IRQ12/M IRQ14 IRQ15 FERREXTSMIDREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7 IOCS16IOCHKZEROWS-
SYSCLKR
RP59 R39 1 2 VCC INSTALL FOR PIIX 1 2 3 4 10K 8 7 6 5
U27E R50 21 DIVCLK 11 7407S 12,20 12,20 J28 1 2 JP2 CLOSE = CLK/4 OPEN = CLK/3 10 1 22 2 SYSCLK 20
2 HFERR# 17 EXTSMI# 12,20,21 DRQ[0..7] DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 20,21 IOCS16# 20,21 IOCHK# 12,20,21 0WS# 11,21 DD[0..15] DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 11 DDRQ[0..1] DDRQ0 DDRQ1
PWROK
RSTDRV
12
U11D 12 11 13 74ALS08S 1
U2A 2 74HCT14S RSTISA 20 RSTDRV# 11,15
DD0/SA8 DD1/SA9 DD2/SA10 IORDY DD3/SA11 DIORDD4/SA12 DIOWDD5/SA13 DDAK0DD6/SA14 DDAK1DD7/SA15 SOEDD8/SA16 SDIR DD9/SA17 DD10/SA18 DD11/SA19 CPURST DD12/SBHE- PCIRST-/APICACKTESTIN-/APICREQDD13 INIT DD14/APICCSDD15/PCSDDRQ0 DDRQ1 PIIX3_0.2
TESTIN#
HRESET PCIRST# PIIX3INIT
2 4..6,18,19 4
1
4.7K R43 2
VCC
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title PIIX3 Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
10 of
10,21 DD[0..15] RP37 10 DDAK1 10,11 DDRQ1 10,11 DDRQ0 10,15 RSTDRV# 1 2 3 4 33 2 R31 5.6K 1 1 2 R30 5.6K 5 6 7 8 1.0K RP49 4 3 2 1 8 7 6 5 SDDAK1 SDDRQ1 DRQ0R IRSTA# VCC IDA7 IDA6 RP20 5 6 7 8 22 RP22 IDA8 IDA9 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15 IDA5 IDA4 5 6 7 8 22 RP23 IDA3 IDA2 PIDEPU TP116 1 TP117 1 IDA2A ICS3A# TP78 TP76 5 6 7 8 22 2 47 RP63 R49 1 47 2 IIORB# PIDEPU SIDEPU HDACTB# HDACTA# 5 6 7 8 10K IRSTB# IDB7 IDB6 IDB5 IDB4 IDB3 IDB2 IDB1 IDB0 SDDRQ1 IIOWB# IIORB# RP62 U11B LA17 4 6 5 74ALS08S U11A LA18 1 3 2 74ALS08S U11C LA19 9 8 10 74ALS08S U12B 4 6 LA23 5 4.7K 74ALS00S RP51 U12A 1 3 LA22 2 74ALS00S DD10 DD5 DD4 DD3 5 6 7 8 4.7K RP44 DD8 DD7 DD6 DD9 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. 5 6 7 8 4.7K Title PCI IDE Interface Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24 4 3 2 1 INTEL CORP. CS3S# DD1 DD11 DD2 DD12 5 6 7 8 4.7K RP47 4 3 2 1 4 3 2 1 ICS3A# ICS1A# 1 2 3 4 33 33 RP36 8 7 6 5 CS3P# CS1P# CS1S# DD14 DD0 DD15 5 6 7 8 RP55 4 3 2 1 RP41 ICS3B# IRSTB# IDA2B DA2 1 2 3 4 8 7 6 5 CS3S# RSTDRV# DA2 IDA2A DA2 VCC 22 IDB1 IDB0 5 6 7 8 RP54 4 3 2 1 DD14 DD1 DD0 DD15 DA1 22 DA0 5 6 7 8 33 4 3 2 1 SDDAK1 SINTERRUPT IDA1B IDA0B ICS1B# 17 HDACTB# J23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RP43 IDB8 IDB9 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15 IDB7 IDB6 5 6 7 8 22 RP46 IDB5 IDB4 SIDEPU TP115 1 TP114 1 IDA2B ICS3B# TP77 TP75 5 6 7 8 5 6 7 8 22 RP50 IDB3 IDB2 4 3 2 1 DD12 DD3 DD2 DD13 4 3 2 1 DD10 DD5 DD4 DD11 4 3 2 1 DD8 DD7 DD6 DD9 4 3 2 1 IIORA# VCC 5 6 7 8 22 RP25 IDA1 IDA0 4 3 2 1 DD14 DD1 DD0 DD15 4 3 2 1 DD12 DD3 DD2 DD13 4 3 2 1 DD10 DD5 DD4 DD11 4 3 2 1 DD8 DD7 DD6 DD9
PRIMARY IDE
IRSTA# IDA7 IDA6 IDA5 IDA4 IDA3 IDA2 IDA1 IDA0 DRQ0R IIOWA# IIORA# J20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
10 ICHRDY 10 DDAK0 10,12,15,16,20,21 IRQ14
RP32 R28 10 IIOW#R 2 47 R47 1 47 R29 10 IIOR#R 1 2 IIOWB# 1 IIOWA# 5 6 7 8 33 4 3 2 1 SDDAK0 PINTERRUPT IDA1A IDA0A ICS1A# 17 HDACTA#
SECONDARY IDE
U12D 12 11 CS1P# 13 74ALS00S U12C
10,20,21 LA[17..23] LA21 10 SOE#
LA20
9 8 10 74ALS00S CS3P#
10,21 MIRQ0
11 of
9,10,15,20,21 SA[0..19] 10,16,20,21 SD[0..15] 10,20 DACK#[0..7]
SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 VCC SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
17 15 12 10 8 7 5 4 3 2 1 32 31 30 29 27 26 25 24
U8 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
DSKCHGHDSELRDDATAWPTRK0WEWRDATASTEPDIRFDME1FDS0FDS1FDME0INDXDRVDEN1 DRVDEN0 DTRBRIBCTSBSOUTB RTSBSINB DSRBDCDBDTRARIACTSASOUTA RTSASINA DSRADCDAPD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 STROBEAUTOFDINITSELECTINFAULTACKBUSY PERROR SELECT PPDIR/GCSIDECS1IDECS0HENDEN-
74 75 76 77 78 79 80 81 82 83 84 85 86 87 90 89 49 50 48 47 46 45 44 43 41 42 40 39 38 37 36 35 55 56 57 58 60 65 67 69 71 70 66 61 68 54 53 52 51 72 91 92 94 95 PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 PDR1 PDR0
DSKCHG# 13 SIDE1# 13 RDATA# 13 WPT# 13 TRK0# 13 WGATE# 13 WDATA# 13 STEP# 13 DIR# 13 MOTEB# 13 DRVSA# 13 DRVSB# 13 MOTEA# 13 INDEX# 13 DRATE0 13 FDDEN 13 DTR1# RI1# 13 CTS1# 13 TX1 13 RTS1# 13 RX1 13 DSR1# 13 DCD1# 13 DTR0# RI0# CTS0# 13 13 TX0 13 RTS0# 13 RX0 13 DSR0# 13 DCD0# 13 13 13
1 R18 4.7K 2 10,20,21 0WS# 10,20,21 IOCHRDY 10,20 AEN 15,16 XIOW# 15,16 XIOR# 10,20 T/C
IO16_PU
23 22 21 20 19 96 6 100 99 98 97 18 16 13 11 9 33
NOWSIOCHRDY AEN IOWCIORCIO16TC PPDREQ PPDACKFDDREQ FDDACKIRQ7 IRQ6 IRQ5 IRQ4 IRQ3 RSTDRV X2
DRQ5 DACK#5 DRQ2 DACK#2 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3
1 R16 10K 2
1 R17 10K 2
1 R12 10K 2
10 RSTDRV TP68 1 TP037
64
3 AIPCLK
63
X1/OSC
STB#R 14 AFD#R 14 INIT#R 14 SLIN#R 14 ERR# 14 ACK# 14 BUSY 14 PE 14 SLCT 14 PPDIR TP036 TP035 TP034 AIPDEN# 2 R15 10K 1 1 2 R13 10K PDR[0..7] 14 1 1 1 TP84 TP31 TP32
82091AA
IRQ[0..15] DRQ[0..7]
10,11,15,16,20,21 10,20,21
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title AIP Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
12 of
+12V
VCC
SP_RI0 SP_CTS0 SP_RXD0 SP_DTR0 SP_RTS0 SP_DSR0 SP_TXD0 SP_DCD0
1 2 3 4 5 6 7 8 9 10
U10 VCC+ VCC RA RY RA RY RA RY DY DA DY DA RA RY DY DA RA RY VCCGND GD75232SOP
20 19 18 17 16 15 14 13 12 11
RI0# 12 CTS0# 12 RX0 12 DTR0# 12 RTS0# 12 DSR0# 12 TX0 12 DCD0# 12
SP_DCD0 SP_DSR0 SP_RXD0 SP_RTS0 SP_TXD0 SP_CTS0 SP_DTR0 SP_RI0 1 2 C55 100pF 1 1 2 C66 100pF 1 2 C56 100pF 1 2 C53 100pF 1 2 C74 100pF 1 2 C63 100pF 1 2 C75 100pF
J18 1 2 3 4 5 6 7 8 9 10
COM 0 HEADER
-12V
+12V U9 VCC+ VCC RA RY RA RY RA RY DY DA DY DA RA RY DY DA RA RY VCCGND GD75232SOP
VCC
2 C49 100pF
SP_RI1 SP_CTS1 SP_RXD1 SP_DTR1 SP_TXD1 SP_DCD1 SP_RTS1 SP_DSR1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RI1# 12 CTS1# 12 RX1 12 DTR1# 12 TX1 12 DCD1# 12 RTS1# 12 DSR1# 12
SP_DCD1 SP_DSR1 SP_RXD1 SP_RTS1 SP_TXD1 SP_CTS1 SP_DTR1 SP_RI1 1 VCC VCC 2 C21 100pF 1 F3 1.25A 2 USBVFB1 1 L11 2 USBVFB0 1 L8 2 USBV0 USBD0USBD0+ USBG0 USBV1 USBD1USBD1+ USBG1 J19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 USB1FB 12 DSKCHG# 12 SIDE1# 12 RDATA# 12 WPT# 12 TRK0# 12 WGATE# 12 WDATA# 12 STEP# 12 DIR# 12 MOTEB# 12 DRVSA# 12 DRVSB# 12 MOTEA# 12 INDEX# 12 DRATE0 TP69 12 FDDEN 5 6 7 8 1K 1 R22 1.0K 2 1 F2 1.25A 1 2 C29 100pF 1 2 C38 100pF 2 C25 100pF 1 2 C31 100pF 2 C42 100pF 1 2 C32 100pF 2 C45 100pF 1 1 1
J10 1 2 3 4 5 6 7 8 9 10
COM 1 HEADER
-12V
USB HEADER
VCC RP42 4 3 2 1
2
FLOPPY INTERFACE HEADER
J21 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
2 R19 30 1 10 USBP110 USBP1+ 10 USBP010 USBP0+
2 R20 30 1
2 R21 30 1
2 R26 30 1 2 L12 1
1 2 C82 470pF 2 C84 470pF
1 2 C61 470pF 2 L9 1 2 L10 1 2 C72 470pF
1 1 2 C85 47pF
1
1
1
TP075
1
2 C83 47pF
1
2 C79 47pF
2 C71 47pF
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Serial Ports, Floppy Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
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1 C20 180pF 2
1 C48 180pF 1 C16 180pF VCC 1 2 D1 IN4148 3 PAR5VOLTS 1 RP4 12 PDR[0..7] 1 2 3 4 RP2 PDR0 PDR1 5 6 7 8 33 RP8 1 2 3 4 1K 12 INIT#R PDR2 12 SLIN#R PDR3 RP11 5 6 7 8 33 RP7 1 2 3 4 1K RP13 PDR4 PDR5 PDR6 PDR7 5 6 7 8 33 RP15 1 2 3 4 1K 12 ERR# 12 SLCT 12 PE 12 BUSY 12 ACK# RP9 1 2 3 4 1K 8 7 6 5 1 C41 180pF 2 1 C73 180pF 2 8 7 6 5 1 C37 180pF 2 4 3 2 1 8 7 6 5 1 C40 180pF 2 1 C64 180pF 2 4 3 2 1 1 C28 180pF 2 C62 180pF 8 7 6 5 C30 180pF 4 3 2 1 1 2 1K 1 C54 180pF 2 8 7 6 5 1 C24 180pF 2 STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT C52 180pF 2 1 C27 180pF 2 C51 180pF 2 2 2
PARALLEL HEADER
J9 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 AFD# ERR# INIT# SLIN#
12 STB#R 12 AFD#R
1 2
1 C65 180pF 2
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Parallel Port Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
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VCC RP3 1 2 3 4 4.7K 8 7 6 5
KEYLOCK# 17 RP1 5 6 7 8 VCC 10K KBCLK# MSCLK# KB_XT1 3 KBD_CLK 10,11 RSTDRV# 1 R3 220 10 ROM_KB# KBDSS# EA_PD 29 2 43 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 U5 VDD P10 TEST0 P11 TEST1 P12 XTAL1 P13 XTAL2 P14 RESETP15 SSP16 CSP17 EA P20 RDP21 A0 P22 WRP23 D0 P24/OBF D1 P25/IBFD2 P26/DRQ D3 P27/DAKD4 D5 D6 PROG D7 SYNC 8242PCPL 30 31 32 33 35 36 37 38 24 25 26 27 39 40 41 42 28 13 KBDAT# MSDAT# KB_PU1 PASSWDCLR# PU_MFGTST COLOR KEYLOCK# MSEDAT MSECLK KBDCLK KBDDAT VCC 1 TP042 1 TP95 2 J4 JP2 JUMPER B JUMPER B JUMPER CLEAR POS PASSWORD CLEAR PASSWORD 9,16 XD[0..7] NORMAL OUT 1 KEYBOARD CONNECTOR KBDAT_FB# TP90 KBCLK_FB# U4A 1 7406S U4B 3 7406S U4C 5 7406S U4D 9 7406S 1 C17 2 470pf 1 C18 2 470Pf 1 C13 2 470Pf 1 C12 2 470Pf 2 1 8 2 L3 1 1 L1 6 2 L4 1 1 C10 2 0.1uF MSCLK_FB# TP93 1 TP043 4 2 L6 1 MSDAT_FB# TP92 1 TP044 J1 1 2 3 4 5 6 7 8 9 MOUSE CONNECTOR QUIETGND2 2 L2 2 2 L5 1 TP91 1 TP046 1 TP045 QUIETGND1 KB5V_FB J2 1 2 3 4 5 6 7 8 9 1-2 IN F U S E 1 2 L7 PU_CLCMOS 21 RP5 1 2 3 4 10K 8 7 6 5 VCC 4 3 2 1
12,16 XIOR# 9,10,12,20,21 SA2 2 12,16 XIOW#
2 R11 220 1
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
KBRST# HA20M# IRQ1 IRQ12
4 2 F1 1.25A 1
2 FUSE 1 10..12,15,16,20,21 10..12,15,16,20,21
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Keyboard/Mouse Interface Size Document Number B 82430HX Date: June 19, 1997 Sheet 15 of REV B.1 24
R1 1 220 1 10,20,21 IOR# 2 3 U3A 74LS125S R4 1 220 4 10,20,21 IOW# 5 6 U3B 74LS125S XIOW# 12,15 2 IOW#PD XIOR# 12,15 2 IOR#PD
U16B 4 6 10 RTCCS# 5 R36 74ALS32S 10 RTCALE 17 PWROK# 9 8 10 74ALS32S 2 R41 10K 1 VCC 1 220 U16C RTCWR# RTCRD# RTCRST# XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 2 RTC_MOT 1 13 14 15 17 18 4 5 6 7 8 9 10 11 U13 MOT CSSQW AS IRQR/WDS RESETX1 X2 AD0 AD1 BC AD2 AD3 RSV1 AD4 RSV2 AD5 AD6 AD7 DS12887A 1 23 19 2 3 20 21 22 TP051 1 TP103 IRQ8 10..12,15,20,21 1 TP100 1 1 TP101 TP99 TP104 1 JP2 R38 10K 2 VCC
TP048 TP047 TP049
RTCCEIN# TP050 1
J24 2
JUMPER 1 19 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 10,12,20,21 SD[0..7] 9 8 7 6 5 4 3 2 U1 DIR G A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 74ALS245S 11 12 13 14 15 16 17 18 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 CLEAR CMOS XD[0..7] 9,15 NORMAL
POS IN OUT
10 XDIR# 9,10 XOE#
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title BATTERY;RTC CICUIT Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
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VCC VCC 1 TP888 J36 1 2 3 4 R60 1 SPEAKER 15 KEYLOCK# 220 2 PON J33 1 2 3 4 5 POWER LED KEYLOCK
TP98
R127 2 1 68 SPK2 2 R126 1 68 R128 1 2.2K 3 Q8 2N3904 2
BUZZ2
1 C210 2 470pF
1 C198 2 470pF
10 SPKR
2
SPK1 1
1 C220 2 0.1 uF
VCC
VCC
1 R59 220 2 HDRV1 HARDDRV J32 1 2 3 4 HARD DRIVE LED U27B 11 HDACTA# 3 7407S 4 6 7407S U27C 5 HDACTB# 11 2 1 R58 220 2 J31 1 2 JP2 1 C149 2 0.22uF J34 1 2 JP2 C167 470pF 2 1 3 D3 1N4148 +12V
10 EXTSMI#
EXTSMI SWITCH
CPU COOLING FAN
VCC
-12V +12V POWER_GOOD PWROK# VCC J5 1 2 3 4 5 6 -5V 9 J13 1 2 3 4 5 6 8 U3C 74LS125S 1 U2F PWRGD1 1 R8 10K 1 0 2 R124 2 100 1 C8 2 10uF 2 C216 1 4.7nF RSTSW1 J35 1 2 33 74HCT14S 74HCT14S 13 12 11 U2E R7 10 PWROKR 2 1 PWROK 10 16
RESET SWITCH
+3_3V J22 1 2 3 4 5 6
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Front Panel Size Document Number B 82430HX Date: June 19, 1997 Sheet REV B.1 24
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10,19,21 PIRQ#[0..3] 4,10,19C/BE#[0..3] 4,10,19AD[0..31]
+3_3V VCC -12V J14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 CN120ED05B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
+3_3V VCC +12V
+3_3V VCC -12V J15 PTRST# 1 R54 5.6K TP112 1 TP057 PIRQ#2 PIRQ#0 PCIB0 TP058 PCIB1 TP059 19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 CN120ED05B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
+3_3V VCC +12V
PTRST#
TP109
1
TP056 PIRQ#1 PIRQ#3 PCIA0 TP055 PCIA1 TP054
PIRQ#0 PIRQ#2 TP063 TP062 TP061 1 1 TP105
2 1
PIRQ#1 PIRQ#3 TP067 TP066 TP065 1 1 1 TP114 TP115 TP116 PCIRST# 4..6,10,19 PGNT#1 TP064 AD30 AD28 AD26 AD24 PCIB2 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# 4,10,19,21 4,10,19,21 4,10,19,21 R23 1 220 2 1 AD29 TP117 4,18,19,21
TP110 1 C57 0.1UF 2 TP111 3 PCLK0
1
TP118 TP106 2 C58 0.1UF TP113 3 PCLK1
1
1 TP107 PCIRST# 4..6,10,19 PGNT#0 4,18,19,21 1 TP108 AD28
1
1 2 C68 1 0.1UF
4,18,19,21PREQ#0 1 C67 2 0.1uF AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 4,10,19,21IRDY# 4,10,19,21DEVSEL# 4,19,21PLOCK# 19,21PERR# 4,10,19,21SERR# C/BE#1 AD14 AD12 AD10
TP060 AD30 AD28 AD26 AD24 PCIA2 AD22 AD20 AD18 AD16
4,18,19,21PREQ#1 AD31 AD29 AD27 AD25
R27 1 220 AD21 AD19 AD17 C/BE#2 FRAME# TRDY# STOP# 4,10,19,21 4,10,19,21IRDY# 4,10,19,21 4,10,19,21DEVSEL# 4,10,19,21 4,19,21PLOCK# 19,21PERR# SBO# 19,21 4,10,19,21SERR# C/BE#1 AD14 AD12 AD10 PAR 4,10,19,21 2 C/BE#3 AD23
SDONE
SDONE 19,21 SBO# 19,21 AD15 AD13 AD11 AD9 C/BE#0 AD6 AD4 AD2 AD0 REQ64S#1 18,19,21 PAR 4,10,19,21
AD15 AD13 AD11 AD9 C/BE#0 AD6 AD4 AD2 AD0
AD8 AD7 AD5 AD3 AD1 18,19,21ACK64S#0
AD8 AD7 AD5 AD3 AD1 REQ64S#0 18,19,21 18,19,21ACK64S#1
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title PCI Slots 0 and 1 Size Document Number C 82430HX Date: June 19, 1997 Sheet REV B.1 24
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10,18,21PIRQ#[0..3] 4,10,18C/BE#[0..3] 4,10,18AD[0..31] 18 PTRST# +3_3V VCC -12V J16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 CN120ED05B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 CN120ED05B +3_3V VCC +12V +3_3V VCC -12V J17 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 +3_3V VCC +12V
TP123
1
TP071 PIRQ#3 PIRQ#1 PCIC0 TP070 PCIC1 TP069
TP126 PIRQ#2 PIRQ#0 TP068 TP078 TP077 1 1 TP119 TP132 TP120 2 1 TP121 PCIRST# 4..6,10,18 PGNT#2 4,18,19,21 1 TP122 AD30 AD28 AD26 AD24 PCIC2 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONE SBO# AD15 AD13 AD11 AD9 C/BE#0 AD6 AD4 AD2 AD0 REQ64S#2 18,19,21 18,21 4,10,18,21 R24 1 220 2 C60 0.1UF 1 2 C70 1 0.1UF TP127
1
TP072 PIRQ#0 PIRQ#2 PCID0 TP073 PCID1 TP074
PIRQ#3 PIRQ#1 TP082 TP081 TP080 1 1 1 TP128 TP129 TP130 PCIRST# 4..6,10,18 PGNT#3 TP079 AD30 AD28 AD26 AD24 PCID2 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# 4,10,18,21 4,10,18,21 4,10,18,21 R25 1 220 2 1 AD31 TP131 4,18,19,21
TP124 2 C59 1 TP125 3 PCLK2
1
1
1
1
3 PCLK3 TP076 AD30 4,18,19,21PREQ#3 AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 4,10,18,21IRDY# 4,10,18,21 4,10,18,21DEVSEL# 4,10,18,21 4,18,21PLOCK# 18,21PERR# 4,10,18,21SERR# PAR 4,10,18,21 C/BE#1 AD14 AD12 AD10
4,18,19,21PREQ#2 AD31 AD29 2 C69 1 0.1uF AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2 4,10,18,21IRDY# 4,10,18,21DEVSEL# 4,18,21PLOCK# 18,21PERR# 4,10,18,21SERR# C/BE#1 AD14 AD12 AD10
SDONE 18,21 SBO# 18,21 AD15 AD13 AD11 AD9 C/BE#0 AD6 AD4 AD2 AD0 REQ64S#3 18,19,21 PAR 4,10,18,21
AD8 AD7 AD5 AD3 AD1 18,19,21ACK64S#2
AD8 AD7 AD5 AD3 AD1 18,19,21ACK64S#3
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title PCI Slots 2 and 3 Size Document Number C 82430HX Date: June 19, 1997 Sheet REV B.1 24
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10..12,15,16,21IRQ[3..15] 10,12,21DRQ[0..7] 10,12DACK#[0..7]
VCC VCC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 J7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 A1 A2 SD7 A3 SD6 A4 SD5 A5 SD4 A6 SD3 A7 SD2 A8 SD1 A9 SD0 A10 A11 A12 SA19 A13 SA18 A14 SA17 A15 SA16 A16 SA15 A17 SA14 A18 SA13 A19 SA12 A20 SA11 A21 SA10 A22 SA9 A23 SA8 A24 SA7 A25 SA6 A26 SA5 A27 SA4 A28 SA3 A29 SA2 A30 SA1 A31 SA0 C1 C2 LA23 C3 LA22 C4 LA21 C5 LA20 C6 LA19 C7 LA18 C8 LA17 C9 C10 C11 SD8 C12 SD9 C13 SD10 C14 SD11 C15 SD12 C16 SD13 C17 SD14 C18 SD15 IOCHK# RSTISA IRQ9 -5V -12V IOCHRDY +12V AEN DRQ2 0WS# SMEMW# SMEMR# IOW# IOR# DACK#3 DRQ3 DACK#1 DRQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK#2 T/C BALE OSC VCC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 J6 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 A1 A2 SD7 A3 SD6 A4 SD5 A5 SD4 A6 SD3 A7 SD2 A8 SD1 A9 SD0 A10 A11 A12 SA19 A13 SA18 A14 SA17 A15 SA16 A16 SA15 A17 SA14 A18 SA13 A19 SA12 A20 SA11 A21 SA10 A22 SA9 A23 SA8 A24 SA7 A25 SA6 A26 SA5 A27 SA4 A28 SA3 A29 SA2 A30 SA1 A31 SA0 C1 C2 LA23 C3 LA22 C4 LA21 C5 LA20 C6 LA19 C7 LA18 C8 LA17 C9 C10 C11 SD8 C12 SD9 C13 SD10 C14 SD11 C15 SD12 C16 SD13 C17 SD14 C18 SD15 IOCHK# RSTISA IRQ9 -5V -12V IOCHRDY AEN +12V SMEMW# SMEMR# IOW# IOR# DACK#3 DRQ3 DACK#1 DRQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK#2 T/C BALE OSC DRQ2 0WS# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 J8 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 A1 A2 SD7 A3 SD6 A4 SD5 A5 SD4 A6 SD3 A7 SD2 A8 SD1 A9 SD0 A10 A11 A12 SA19 A13 SA18 A14 SA17 A15 SA16 A16 SA15 A17 SA14 A18 SA13 A19 SA12 A20 SA11 A21 SA10 A22 SA9 A23 SA8 A24 SA7 A25 SA6 A26 SA5 A27 SA4 A28 SA3 A29 SA2 A30 SA1 A31 SA0 C1 C2 LA23 C3 LA22 C4 LA21 C5 LA20 C6 LA19 C7 LA18 C8 LA17 C9 C10 C11 SD8 C12 SD9 C13 SD10 C14 SD11 C15 SD12 C16 SD13 C17 SD14 C18 SD15
10 RSTISA IRQ9 -5V -12V 10,12,210WS# +12V 10,21SMEMW# 10,21SMEMR# 10,16,21IOW# 10,16,21IOR# DRQ2
DACK#3 DRQ3 DACK#1 DRQ1 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK#2
10,21REFRESH# 10 SYSCLK
10,12T/C 10,21BALE 3 OSC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
IOCHK#
10,21
IOCHRDY 10,12,21 AEN 10,12
10,21MEMCS16# 10,21IOCS16#
SBHE#
IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK#0 DRQ0 DACK#5 DRQ5 DACK#6 DRQ6 DACK#7 DRQ7
MEMR# MEMW#
MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK#0 DRQ0 DACK#5 DRQ5 DACK#6 DRQ6 DACK#7 DRQ7 MASTER#
SBHE#
MEMR# MEMW#
MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK#0 DRQ0 DACK#5 DRQ5 DACK#6 DRQ6 DACK#7 DRQ7 MASTER#
SBHE#
10,21
MEMR# MEMW#
9,10,21 9,10,21
21 MASTER#
CD98ED10B
CD98ED10B
CD98ED10B
LA[17..23] SA[0..19] SD[0..15]
10,11,21 9,10,12,15,21 10,12,16,21
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. INTEL CORP. Title ISA Slots 0, 1 and 2 Size Document Number C 82430HX Date: June 19, 1997 Sheet REV B.1 24
20 of
10..12,15,16,20 IRQ[0..15] 9,10,12,15,20 SA[0..19] VCC RP31 1 2 3 4 10K RP29 1 2 3 4 10K RP27 1 2 3 4 10K RP24 1 2 3 4 10K RP21 1 2 3 4 10K RP18 1 2 3 4 10K RP16 1 2 3 4 10K RP61 1 2 3 4 10K RP40 1 2 3 4 10K RP45 1 2 3 4 10K RP30 1 2 3 4 CPUVIO 2.7K RP65 5 6 7 8 2.7K 1 2 3 4 2.7K RP64 5 6 7 8 2.7K THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. INTEL CORP. Title Pullup/Pulldown Resistors Size Document Number B 82430HX Date: June 19, 1997 Sheet 21 of REV B.1 24 4 3 2 1 PREQ#3 PREQ#2 4 3 2 1 PGNT#3 PGNT#2 PGNT#1 PGNT#0 5 6 7 8 2.7K RP38 8 7 6 5 PREQ#0 REQ64S#0 REQ64S#1 PREQ#1 RP33 4 3 2 1 REQ64S#2 REQ64S#3 ACK64S#1 ACK64S#0 8 7 6 5 ACK64S#2 ACK64S#3 PAR 4,10,18,19 8 7 6 5 IRQ14 IRQ15 MEMW# MEMR# 9,10,20 9,10,20 VCC 4,18,19 PREQ#[0..3] 18,19 REQ64S#[0..3] 18,19 ACK64S#[0..3] 1 2 3 4 4.7K 8 7 6 5 IRQ12 IRQ11 IRQ10 SBHE# 10,20 8 7 6 5 IRQ1 IRQ8 MIRQ0 10,11 VCC 10,18,19 PIRQ#[0..3] RP12 1 2 3 4 2.7K 8 7 6 5 PIRQ#2 PIRQ#3 PIRQ#0 PIRQ#1 330 RP60 1 2 3 4 1.0K RP53 8 7 6 5 DD13 10,11 10,20 8 7 6 5 1 2 3 4 8 7 6 5 SA17 SA18 SA19 IRQ9 8 7 6 5 SA14 SA15 SA16 PU_CLCMOS 15 RP19 1 2 3 4 5.6K 8 7 6 5 2.7K DRQ1 DRQ3 DRQ2 RP35 1 2 3 4 330 RP56 8 7 6 5 MASTER# 20 8 7 6 5 IOCS16# 10,20 MEMCS16# 10,20 REFRESH# 10,20 0WS# 10,12,20 8 7 6 5 IRQ7 SA11 SA12 SA13 10,12,20 DRQ[0..7] RP48 1 2 3 4 5.6K 8 7 6 5 DRQ7 DRQ6 DRQ5 DRQ0 2.7K RP26 1 2 3 4 8 7 6 5 DEVSEL# 4,10,18,19 TRDY# 4,10,18,19 IRDY# 4,10,18,19 FRAME# 4,10,18,19 1 2 3 4 8 7 6 5 IRQ5 IRQ6 SA9 SA10 1 2 3 4 10K 8 7 6 5 IRQ3 SA7 IRQ4 SA8 1 2 3 4 10K RP58 8 7 6 5 SD15 SD14 SD13 SD12 1 2 3 4 10K RP28 8 7 6 5 SBO# 18,19 PERR# 18,19 SDONE 18,19 PLOCK# 4,18,19 8 7 6 5 SA3 SA4 SA5 SA6 1 2 3 4 10K RP52 8 7 6 5 SD11 SD10 SD9 SD8 1 2 3 4 10K RP14 8 7 6 5 DIVCLK SMEMR# SMEMW# 10 10,20 10,20 8 7 6 5 SA0 SA1 SA2 BALE 10,20 1 2 3 4 10K RP6 8 7 6 5 SD4 SD5 SD6 SD7 1 2 3 4 2.7K RP17 8 7 6 5 IOR# IOW# 10,16,20 10,16,20
VCC
10,12,16,20 SD[0..15]
VCC
10,11,20 LA[17..23]
RP10 8 7 6 5 SD0 SD1 SD2 SD3 1 2 3 4
RP34 8 7 6 5 2.7K RP39 8 7 6 5 LA21 LA22 LA20 LA23 LA17 LA18 LA19 STOP# 4,10,18,19
IOCHRDY 10,12,20
IOCHK#
SERR#
4,10,18,19
4,18,19 PGNT#[0..3]
R85 REF C189 1 2 500pF R112 1 2 +12V 33K 1 1 TP033 TP032 1 2 3 4 Q1 COL REF COMP RMID V+ GNDF RTOP GNDS LT1431CS C223 2 1 0.1uF TP565 C184 1 2 120pF C168 1uF 1 TP052 ITH CT 8 7 6 5 TP098 1 3300pF VCC +12V VCC 5 3 13 11 7 6 4 12 1 2 U30 VIN PWRVIN PINV VFB_NC LBIN LBOUT SHDM TDRIVE SENSE+ ITH CT SENSEBINH BDRIVE SGND PGND LTC1266XS 2 10 14 1 9 8 16 15 RAWVIO VFB TP053 TDRIVE SENSE 1 TP564 1 2 3 4 Q2 S_0 D_3 S_1 D_2 S_2 D_1 G_0 D_0 SI4410DY 8 7 6 5 1.27K 1.5K C190 REFR 1 2 R105 2 R108 2 R113 2 965 R109 2 0 1 2 TP52 1 VRREF TP030 18.7K
J26 1 2 3 JP3
VRE 1-2
STD 2-3
1
1
1
VIO2
1
TP566 TP567
TP568
1 2
C169
1 2
C185
1 2
C191
220uF
220uF
220uF CPUVIO
2 C176 1 0.1uF L14 1 2.2uH C203 1 2 1nF SENSE# 1 R118 1 2 100 R117 2 100 D2 2 1 RAWVIO 1N5820 2 3 BDRIVE 4 Q4 S_0 S_1 8 7 6 5 6.3v 2 LRAWVIO 1 R123 2 0.03 1 R121 2 0.03 1 2 220uF C182 1 2 220uF C214 1 2 220uF C215 1 2 220uF C183
D_3 D_2 D_1 G_0 D_0 SI9410DY
+12V
2 R129 910 1 CORECATH 1 C222 2 0.01uF 2 C225 1uF 1 C O M P 2 R125 47K 1 2 3 Q7 CATH P A_0 A_3 A_1 A_2 TL431ACS 1 8 7 6 VCOREREFIN 1 R122 2 HEAT SINK 220 1 C208 2 100uF 1 C211 2 100uF 1 C192 2 100uF 1 C181 2 100uF HS1 1 1 TP028 TP031 1 1 TP570 TP569 1 3 Q5 2N3904SOT23 2 2 R120 910 1 1 2 R119 910 COREB2E 1 2 Q6 2N3906SOT23 3 R116 Z40DRV 1 2 22 JB3 1 3 5 7 JB4 P54C 2 4 6 8 P55C 2 Z40DRVR 1 3 1-2, 3-4, 5-6, 7-8 NONE Q3 IRFZ40 CPU TYPE
JUMPER
CPUVCORE
2 2 6021PB
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Switching Power Supply Size Document Number B 82430HX Date: June 19, 1997 Sheet 22 of REV B.1 24
MH1 1
MH4 1
MH7 1 1 MH9UV157 MH8 1 MH9UV157 MH9 1 MH9UV157 1 FM4 FM200B FM7 FM200B 1 FM5 FM200B FM8 FM200B 1 FM6 FM200B FM9 FM200B 1 GF1 FM200B 1 GF2 FM200B 1 GF3 FM200B H1 H120 1 H2 H120 1 H3 H120 1 H4 H158
MH9UV157 MH9UV157 MH2 1 MH5 1
MH9UV157 MH9UV157 MH6 1 MH9UV157
1
1
1
U2D U4E 9 11 7406S 10 TP100 1 TP929 74HCT14S 8 TP106 1 TP931
U4F 13 7406S 12 TP099 1 TP930 13
U27F 12 7407S TP104 1 TP926
SPARES
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Fiducials, Holes, Spare Gates Size Document Number B 82430HX Date: June 19, 1997 Sheet 23 of REV B.1 24
VCC
VCC
VCC
7,8 DRAMVCC C93 1 2 0.01uF C138 1 2 0.01uF C101 1 2 0.01uF C128 1 2 0.01uF C126 1 2 0.01uF C108 1 2 0.01uF C106 1 2 0.01uF C78 1 2 0.01uF C80 1 2 0.01uF C94 1 2 0.01uF C92 1 2 0.01uF C4 1 2 0.001uF C124 1 2 0.001uF C114 1 2 0.001uF +12V C96 1 2 0.1uF C99 1 2 0.1uF C88 1 2 0.1uF C98 1 2 0.1uF C95 1 2 0.1uF C87 1 2 0.1uF C97 1 2 0.1uF C102 1 2 0.1uF +3_3V C91 1 2 -5V 0.1uF C122 1 2 0.1uF C110 1 2 CPUVIO 0.1uF C123 1 2 0.1uF C107 1 2 0.1uF 2 C7 1 10uF
C112 1 2 0.1uF C111 1 2 0.1uF C26 1 2 0.1uF C6 1 2 0.1uF C44 1 2 0.1uF C100 1 2 0.1uF C139 1 2 0.1uF C5 1 2 0.1uF C104 1 2 0.1uF C19 1 2 0.1uF C137 1 2 0.1uF C120 1 2 0.1uF C103 1 2 0.1uF
C3 1 2 0.1uF C77 1 2 0.1uF C135 1 2 0.1uF C116 1 2 0.1uF C152 1 2 0.1uF C113 1 2 0.1uF C34 1 2 0.1uF C151 1 2 0.1uF C140 1 2 0.1uF C1 1 2 0.1uF C2 1 2 0.1uF C105 1 2 0.1uF C15 1 2 0.1uF C76 1 2 0.1uF C115 1 2 0.1uF C81 1 2 0.1uF C129 1 2 0.1uF C33 1 2 0.1uF C35 1 2 0.1uF C117 1 2 0.1uF C118 1 2 0.1uF C150 1 2 0.1uF C43 1 2 0.1uF
C86 1 2 10uF
C175 1 2 100uF C148 1 2 100uF
C109 1 2 C170 1 2 0.1uF C153 1 2 0.1uF C156 1 2 0.1uF C204 2 1 0.1uF C127 1 2 0.1uF C141 1 2 0.1uF C171 1 2 0.1uF 0.001uF C90 1 2 0.001uF C121 1 2 0.001uF C89 1 2 0.001uF C133 1 2 0.001uF
CPUVIO
CPUVCORE
C226 1 2 0.01uF
C132 1 2 100uF
C23 1 2 10uF
C202 1 2 0.001uF C197 1 2
C11 1 2 10uF C125 1 2 10uF C47 1 2 10uF C119 1 2 10uF C39 1 2 10uF C134 1 2 10uF -12V
C50 1 2 0.1uF C224 1 2 0.1uF
0.001uF C166 1 2 0.001uF C165 1 2 0.001uF
C22 2 1 10uF
C46 2 1 0.1uF
C9 1 2 100uF
C14 2 1 0.1uF
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
INTEL CORP. Title Decoupling Capacitors Size Document Number B 82430HX Date: June 19, 1997 Sheet 24 of REV B.1 24
Root schematic for netlisting multiple flat files.
|LINK |T2_1.SCH |T2_2.SCH |T2_3.SCH |T2_4.SCH |T2_5.SCH |T2_6.SCH |T2_7.SCH |T2_8.SCH |T2_9.SCH |T2_10.SCH |T2_11.SCH |T2_12.SCH |T2_13.SCH |T2_14.SCH |T2_15.SCH |T2_16.SCH |T2_17.SCH |T2_18.SCH |T2_19.SCH |T2_20.SCH |T2_21.SCH |T2_22.SCH |T2_23.SCH |T2_24.SCH
INTEL CORP. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. Title Root Schematic Size Document Number A T2 Date: June 19, 1997 Sheet REV B.1 24
25 of