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Intel 100 MHz Pentium(tm) II processor/440BX AGPset Dual Processor Customer Reference Schematics Revision 1.0
TITLE
COVER SHEET BLOCK DIAGRAM SLOT 1 CONNECTOR CLK SYNTHESIZER 82443BX FET SWITCHES DIMM SOCKETS
4
PAGE
1 2 3,4,5,6 7 8,9,10 11,12 13,14,15,16 17.18 19 20 21 22,23 24 25 26 27 28 29 30 31 32 33 34 35
INTEL CORPORATION
** Please note that these schematics are subject to change.
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. *Third-party brands and names are the property of their respective owners. Copyright * Intel Corporation 1997, 1998
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3
PIIX4E IOAPIC ULTRA I/O AGP CONNECTOR PCI CONNECTORS ISA CONNECTORS IDE CONNECTORS USB CONNECTORS FLASH BIOS
2
PARALLEL SERIAL/FLOPPY KEYBOARD/MOUSE VRM POWER CONNECTOR PROCESSOR BUS/CORE FREQ. PCI/AGP PULL-UPS & PULL-DOWNS ISA PULL-UPS 82443BX/DRAM DECOUPLING
2
36 37 38
Title PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630
1
1
BULK DECOUPLING TERMINATION DECOUPLING LM79 REVISION HISTORY
39 40
Intel Pentium(tm) II processor/440BX AGPset Dual Processor Cover Sheet S ize Custom Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
D
Rev 1.0 1
E
Sheet
of
40
A
B
C
1
2
3
4
5
6
7
8
APIC BUS
VRM VTT GEN.
PG. 31
A
PENTIUM(tm) II Processor
(SLOT 1)
PG. 3,4
CK100 ITP CON.
PG. 7
PENTIUM(tm) II Processor
(SLOT 1)
PG. 5,6
VRM VTT GEN.
PG. 31
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. iNTEL ISNOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
&
A
MAX1617 ME
PG. 3
MAX1617 ME
PG. 5
DEVICE TABLE
DEVICE TYPE
FUSES
ADDR
SMBus Interface
S Y S TEM BUS
IOAPIC 82093AA
PG. 19
AGP CONN.
CNTL PG. 21
DATA ADDR ADDR/DATA CNTL AGP SIDEBAND
ADDR
S Y S T EM BUS
CNTL
CNTL
DATA
REFERENCE DESIGNATOR
F1,F2,F3,F4
PAGE #
26,30
SMBus Interface
Slot 1 Connectors ITP Connector DIMM Sockets
J1A,B J2A,B J3 J4,J5,J6,J7 J8 J9,J10,J11,J12 J13, J14 J15, J16 J17,J18 J25,J26
3,4,5,6
82443BX
492 BGA PG. 8-10
CNTL
DATA
13,14,15,16 21 22,23 35 25 26 31
B
M E M O RY
4 SDRAM DIMM MODULES PG. 13-16
AGP Connector PCI Connector ISA Connector IDE Connector
ADDR
CKBF
PG. 8
DATA
USB Connector VRM8.2
B
BLM31A700S
ADD/DATA
L1-L13
26,30
CNTL
CK100 82443BX CKBF FET SWITCHES (74CBT16212)
U1 U2 - 1,2,3 U3 U4,5,6,7,8,9 U10A,B U11A,B,C,D,E,F U12 U13A,B,C,D U14 U15A,B,C,D,E,F U16 A,B,C,D,E,F U17 U20 A,B,C,D U21 A,B,C,D,E,F 5VSB U22 A,B,C U23A,B,C,D,E,F U24 U25
7 8,9,10 8 11,12 17,18 18, 32, 33 19 19,35 20 21,35 27,32,35 27 32,35 32,33,35 18,32 32,33 33 39
C
PCI BUS
ADD/DATA CNTL
2 USB CONN. PG. 26
82371EB (PIIX4E)
PG. 22-23 2 PCI IDE CONNECTORS
USB
CONTROL
PG. 17-18
USB
74LVC14
3VSB
82093AA (IOAPIC) 74LVC125 3VSB
PCI CONN
PCI CONN
PCI CONN
PCI CONN
PG. 25 CNTL
SECONDARY IDE
PRIMARY IDE
CNTL
82371EB 324 BGA
ADDR/DATA
FDC37C932FR (Ultra I/O) 74AS07 74HCT14 E28F002BC-T(FLASH) 74ALS08
ADDR/DATA
C
INTERRUPTS
CONTROL ADDR CNTL DATA
74ALS05
ISA BUS
P G 35
CNTL DATA ADDR
74HC10 74F07 74FCT3244 LM79
ADDR
MAX 1617 ME
ADDR
U28,U29 5VSB U30 U32 5VSB U36A,B,C,D,E,F VR1 VR2
3,5 18,35 18 18, 32, 35 31 31
ISA CONN
ISA CONN
74HCT14 74HC112 74F07 LT1575 LT1585
FLASH BIOS PG. 27
DATA
X-BUS
KEYBOARD PG. 30
ULTRA I/O
PG.14 CNTL
LM79
PG. 38
D
MOUSE PG. 30
Crystal (14.318 MHz)
DATA
Y1
7
D
FLOPPY CONN. PG. 29
PARA. CONN. PG. 28
SER. CONN. PG .29 SER. CONN.
INTEL CORPORATION
RESET, POWER CONNECTORS PCI, AGP, & ISA RESISTORS DECOUPLING CAPACITORS
PG. 32
P L A T F O R M COMPONENTS DIVISION 1 9 0 0 P R A I R I E CITY RD. FM5-62 FOLSOM, CA 95630 Title I n t e l 1 0 0 M H z P e n t i u m ( t m ) I I p r o c essor/440BX AGPset Block Dia gram
PG. 34-35
PG. 36-37
Size Custom Date:
Document Number Intel(R) 440BX AGPset T hursday, April 09, 1998
7
Rev 1.0 Sheet 2
8
of
40
1
2
3
4
5
6
A
B
C
D
E
VTT
VCC3 VCC3
4
V C C C O RE1 J1A B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 EMI_PD3 EMI_PD2 EMI_PD1
EMI FLUSH# SMI# INIT# VCC_VTT STPCLK# TCK SLP# VCC_VTT TMS TRST# RESERVED VCC_CORE RESERVED RESERVED LINT[1] VCC_CORE PICCLK BP#[2] RESERVED 100/66# PICD[1] PRDY# BPM#[1] VCC_CORE DEP#[2] DEP#[4] DEP#[7] VCC_CORE D#[62] D#[58] D#[63] VCC_CORE D#[56] D#[50] D#[54] VCC_CORE D#[59] D#[48] D#[52] EMI D#[41] D#[47] D#[44] VCC_CORE D#[36] D#[40] D#[34] VCC_CORE D#[38] D#[32] D#[28] VCC_CORE D#[29] D#[26] D#[25] VCC_CORE D#[22] D#[19] D#[18] EMI D#[20] D#[17] D#[15] VCC_CORE D#[12] D#[7] D#[6] VCC_CORE D#[4] D#[2] D#[0] VCC_CORE VCC_VTT GND VCC_VTT IERR# A20M# GND FERR# IGNNE# TDI GND TDO PWRGOOD TESTHI1 GND THERMTRIP# RESERVED LINT[0] GND PICD[0] PREQ# BP#[3] GND BPM#[0] BINIT# DEP#[0] GND DEP#[1] DEP#[3] DEP#[5] GND DEP#[6] D#[61] D#[55] GND D#[60] D#[53] D#[57] GND D#[46] D#[49] D#[51] GND D#[42] D#[45] D#[39] GND RESERVED D#[43] D#[37] GND D#[33] D#[35] D#[31] GND D#[30] D#[27] D#[24] GND D#[23] D#[21] D#[16] GND D#[13] D#[11] D#[10] GND D#[14] D#[9] D#[8] GND D#[5] D#[3] D#[1]
VTT
C111 R281 4 . 7K U28 15 S M B SLAVE A D D R ESS = 0011000b 0.1 uF 2
5,34 F L U S H # 5,19 H S M I# 5 , 1 8,34 HINIT# 5 , 1 8,34 STPCLK# 7 TCK_1 5 , 1 8,34 SLP# 7 TMS_1 5,7 TRST# D+ D3 4 C198 2200pF
S T BY#
6 10
ADD1 ADD0
MAX1617 ME
16p QSOP
5 , 33,34 LINT1 7 P I C CLK_P1 5 , 7 ,16 100/66# 5 , 19,34 P I C D 1 7 P R D Y #0 THERM# 5 , 18,34
5 , 8 , 1 5,16,18,34,39 S M BDATA 5 , 8 , 1 5,16,18,34,39 SMBCLK
12 14
S M BDATA SMBCLK SMB_ALERT# 11
3
1 5 9 13 16
GND
GND
R E SV R E SV R E SV R E SV R E SV
H D # 62 H D # 58 H D # 63 H D # 56 H D # 50 H D # 54 H D # 59 H D # 48 H D # 52 H D # 41 H D # 47 H D # 44 H D # 36 H D # 40 H D # 34 H D #38 H D #32 H D #28 H D #29 H D #26 H D #25 H D # 22 H D # 19 H D # 18 H D # 20 H D #17 H D # 15 H D # 12 HD#7 HD#6 HD#4 HD#2 HD#0
MAX1617_2
2
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73
4
A20M# 5 , 33,34 F E R R# 5 , 1 8,34 I G N N E # 5 , 33,34 T D I_1 7 TDO_1 5 , 7 P W R G O O D 5 , 27,32 T E S THI 5,34 T H E RMTRIP# 5,34 LINT0 5,33,34 P I C D0 5 , 19,34 ITPREQ#0 7
V+
3
H D #61 H D #55 H D #60 H D #53 H D #57 H D #46 H D #49 H D #51 H D #42 H D #45 H D #39 H D #43 H D #37 H D #33 H D #35 H D #31 H D #30 H D #27 H D #24 H D #23 H D #21 H D #16 H D #13 H D #11 H D #10 H D #14 HD#9 HD#8 HD#5 HD#3 HD#1
7
8
2
SLOT1_0.8
SLOT 1a
5,10 H D # [ 6 3 : 0]
1
R1 0
R2 0
R3 0
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title F I R S T S L O T 1 (PART I) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E
1
* Please place as close to the connector as possible
Rev 1.0 3 of 40
A
B
C
D
A
B
C
D
E
V C C C O RE1 VCC
4
VCC3 J1B
4
6 , 7,8 H R E SET# 6 BREQ1#
H A # 29 H A # 26 H A # 24 H A # 28 HA#20 H A # 21 H A # 25 HA#15 HA#17 HA#11 H A # 12 HA#8 HA#7
3
HA#3 HA#6 3 2 ,34 A _ SLOTOCC# H R E Q#0 H R E Q#1 H R E Q#4
6,8 H L O CK# 6,8 D R D Y # 6,8 RS#0 6,8 HIT# 6,8 RS#2
V I D _ A3 R 4 V I D _ A0 R 6
0 0
VA3 VA0
B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121
RESET# BREQ1# FRCERR# VCC_CORE A#[35] A#[32] A#[29] EMI A#[26] A#[24] A#[28] VCC_CORE A#[20] A#[21] A#[25] VCC_CORE A#[15] A#[17] A#[11] VCC_CORE A#[12] A#[8] A#[7] VCC_CORE A#[3] A#[6] EMI SLOTOCC# REQ#[0] REQ#[1] REQ#[4] VCC_CORE LOCK# DRDY# RS#[0] VCC_5 HIT# RS#[2] RESERVED VCC_3 RP# RSP# AP#[1] VCC_3 AERR# VID[3] VID[0] VCC_3
GND BCLK BREQ0# BERR# GND A#[33] A#[34] A#[30] GND A#[31] A#[27] A#[22] GND A#[23] RESERVED A#[19] GND A#[18] A#[16] A#[13] GND A#[14] A#[10] A#[5] GND A#[9] A#[4] BNR# GND BPRI# TRDY# DEFER# GND REQ#[2] REQ#[3] HITM# GND DBSY# RS#[1] RESERVED GND ADS# RESERVED AP#[0] GND VID[2] VID[1] VID[4]
A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121
C P U H C LK1 7 BREQ0# 6 , 8
H A # 30 H A # 31 H A # 27 H A # 22 H A # 23 H A # 19 H A # 18 H A # 16 H A # 13 H A # 14 H A # 10 HA#5
3
HA#9 HA#4 BNR# 6,8 B P RI# 6 , 8 HTRDY# 6,8 D E F ER# 6 , 8 H R E Q#2 H R E Q#3 HITM# 6 , 8 D B S Y# 6 , 8 RS#1 6 , 8 A D S# 6 , 8
VA2 VA1 VA4
R5 R7 R8
0 0 0
V I D _ A2 V I D _ A1 V I D _ A4
SLOT1_0.8
2
SLOT 1b
2
6 , 8 H A # [ 3 1 : 3] 6 , 8 H R E Q # [ 4 :0] 31 VID_A[4:0] EMI_PD5 EMI_PD4 VCC JP1 V I D _ A0 2 3 1 S E L _VID_A0 R9 8 . 2K
* Please place as close to the c o n n ector as possible
R10 0
R11 0 V I D _ A1 2
JP2
1 S E L _VID_A1 3
R12 8 . 2K
VRM optional override jumpers & resistors
Jumper position 1-2 is s t u f f e d a s the default. To override, R4-R8 must be removed.
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title F I R S T S L O T 1 (PART II) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E 1
JP3 V I D _ A2 2
1 S E L _VID_A2 3
R13 8 . 2K
1
JP4 V I D _ A3 2
1 S E L _VID_A3 3
R14 8 . 2K
JP5 V I D _ A4 2
1 S E L _VID_A4 3
R15 8 . 2K
Rev 1.0 4 of 40
A
B
C
D
A
B
C
D
E
VTT
V C C C ORE2 VCC3 VCC3 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 EMI_PD8 EMI_PD7 EMI_PD6 J2A
EMI FLUSH# SMI# INIT# VCC_VTT STPCLK# TCK SLP# VCC_VTT TMS TRST# RESERVED VCC_CORE RESERVED RESERVED LINT[1] VCC_CORE PICCLK BP#[2] RESERVED 100/66# PICD[1] PRDY# BPM#[1] VCC_CORE DEP#[2] DEP#[4] DEP#[7] VCC_CORE D#[62] D#[58] D#[63] VCC_CORE D#[56] D#[50] D#[54] VCC_CORE D#[59] D#[48] D#[52] EMI D#[41] D#[47] D#[44] VCC_CORE D#[36] D#[40] D#[34] VCC_CORE D#[38] D#[32] D#[28] VCC_CORE D#[29] D#[26] D#[25] VCC_CORE D#[22] D#[19] D#[18] EMI D#[20] D#[17] D#[15] VCC_CORE D#[12] D#[7] D#[6] VCC_CORE D#[4] D#[2] D#[0] VCC_CORE VCC_VTT GND VCC_VTT IERR# A20M# GND FERR# IGNNE# TDI GND TDO PWRGOOD TESTHI1 GND THERMTRIP# RESERVED LINT[0] GND PICD[0] PREQ# BP#[3] GND BPM#[0] BINIT# DEP#[0] GND DEP#[1] DEP#[3] DEP#[5] GND DEP#[6] D#[61] D#[55] GND D#[60] D#[53] D#[57] GND D#[46] D#[49] D#[51] GND D#[42] D#[45] D#[39] GND RESERVED D#[43] D#[37] GND D#[33] D#[35] D#[31] GND D#[30] D#[27] D#[24] GND D#[23] D#[21] D#[16] GND D#[13] D#[11] D#[10] GND D#[14] D#[9] D#[8] GND D#[5] D#[3] D#[1]
VTT
4
3,34 F L U S H# 3,19 H S M I# 3 , 18,34 HINIT# C112 3 , 18,34 STPCLK# 7 TCK_2 3 , 18,34 SLP# 7 TMS_2 3 , 7 TRST# C199 2200pF
R282 4.7K U29 15
0.1 uF 2
S T BY# D+ DADD1 ADD0 3 4 3 , 3 3,34 LINT1 7 P I CCLK_P2 3 , 7 ,16 100/66# 3 , 19,34 P I C D1 7 P R D Y #1
SMB SLAVE A D D RESS = 0011010b 3 , 8 , 1 5,16,18,34,39 S M BDATA 3 , 8 , 1 5,16,18,34,39 SMBCLK
6 10
MAX1617 ME
16p QSOP
12 14
S M BDATA SMBCLK SMB_ALERT# 11
3
1 5 9 13 16
GND
GND
R E SV R E SV R E SV R E SV R E SV
THERM# 3 , 18,34 H D # 62 H D # 58 H D # 63 H D # 56 H D # 50 H D # 54 H D # 59 H D # 48 H D # 52 H D # 41 H D # 47 H D # 44 H D # 36 H D # 40 H D # 34 H D # 38 H D # 32 H D # 28 H D # 29 H D # 26 H D # 25 H D # 22 H D # 19 H D # 18 H D # 20 H D # 17 H D # 15 H D # 12 HD#7 HD#6 HD#4 HD#2 HD#0
MAX1617_2
2
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73
4
A20M# 3 , 33,34 F E R R # 3 , 18,34 I G N N E # 3 ,33,34 TDO_1 3 , 7 TDO_2 7 P W RGOOD 3 , 27,32 T E S T HI 3 , 34 T H E R MTRIP# 3,34 LINT0 3 , 3 3,34 P I C D 0 3 , 19,34 ITPREQ#1 7
V+
3
H D # 61 H D # 55 H D # 60 H D # 53 H D # 57 H D # 46 H D # 49 H D # 51 H D # 42 H D # 45 H D # 39 H D # 43 H D # 37 H D # 33 H D # 35 H D # 31 H D # 30 H D # 27 H D # 24 H D # 23 H D # 21 H D # 16 H D # 13 H D # 11 H D # 10 H D # 14 HD#9 HD#8 HD#5 HD#3 HD#1
7
8
2
SLOT1_0.8
SLOT 1a
3,10 H D # [ 6 3 : 0]
1
R16 0
R17 0
R18 0
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title S E C O N D S L O T 1 (PART I) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E
1
* P lease place as close to the connector as possible
Rev 1.0 5 of 40
A
B
C
D
A
B
C
D
E
V C C C O RE2 VCC
4
VCC3 J2B
4
4 , 7,8 H R E SET# 4 , 8 BREQ0#
H A # 29 H A # 26 H A # 24 H A # 28 HA#20 H A # 21 H A # 25 HA#15 HA#17 HA#11 H A # 12 HA#8 HA#7
3
HA#3 HA#6 3 2 ,34 B_SLOTOCC# H R E Q#0 H R E Q#1 H R E Q#4
4,8 H L O CK# 4,8 D R D Y # 4,8 RS#0 4,8 HIT# 4,8 RS#2
VID_B3 VID_B0
R19 R21
0 0
VB3 VB0
B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121
RESET# BREQ1# FRCERR# VCC_CORE A#[35] A#[32] A#[29] EMI A#[26] A#[24] A#[28] VCC_CORE A#[20] A#[21] A#[25] VCC_CORE A#[15] A#[17] A#[11] VCC_CORE A#[12] A#[8] A#[7] VCC_CORE A#[3] A#[6] EMI SLOTOCC# REQ#[0] REQ#[1] REQ#[4] VCC_CORE LOCK# DRDY# RS#[0] VCC_5 HIT# RS#[2] RESERVED VCC_3 RP# RSP# AP#[1] VCC_3 AERR# VID[3] VID[0] VCC_3
GND BCLK BREQ0# BERR# GND A#[33] A#[34] A#[30] GND A#[31] A#[27] A#[22] GND A#[23] RESERVED A#[19] GND A#[18] A#[16] A#[13] GND A#[14] A#[10] A#[5] GND A#[9] A#[4] BNR# GND BPRI# TRDY# DEFER# GND REQ#[2] REQ#[3] HITM# GND DBSY# RS#[1] RESERVED GND ADS# RESERVED AP#[0] GND VID[2] VID[1] VID[4]
A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121
C P U H C LK2 7 BREQ1# 4
H A # 30 H A # 31 H A # 27 H A # 22 H A # 23 H A # 19 H A # 18 H A # 16 H A # 13 H A # 14 H A # 10 HA#5
3
HA#9 HA#4 BNR# 4,8 B P RI# 4 , 8 HTRDY# 4,8 D E F ER# 4 , 8 H R E Q#2 H R E Q#3 HITM# 4 , 8 D B S Y# 4 , 8 RS#1 4 , 8 A D S# 4 , 8
VB2 VB1 VB4
R20 R22 R23
0 0 0
VID_B2 VID_B1 VID_B4
SLOT1_0.8
2
SLOT 1b
2
4 , 8 H A # [ 3 1 : 3] 4 , 8 H R E Q # [ 4 :0] 31 V I D _ B [ 4 :0] EMI_PD10 EMI_PD9 VCC JP6 VID_B0 2 3 R26 0 VID_B1 2 3 JP8 VID_B2 2 3 JP9 VID_B3 2 3 JP10 1 S E L_VID_B4 VID_B4 2 3 1 S E L_VID_B3 1 S E L_VID_B2 JP7 1 S E L_VID_B1 1 S E L_VID_B0 R24 8 . 2K
* Please place as close to the connector as possible
R25 0
R27 8 . 2K
VRM optional override jumpers & resistors
Jumper position 1-2 is s t u f f e d a s the default. To override, R19-R23 must be removed.
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title S E C O N D S L O T 1 (PART II) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E 1
R28 8 . 2K
1
R29 8 . 2K
R30 8 . 2K
Rev 1.0 6 of 40
A
B
C
D
A
B
C
D
E
VCC3 1 L15 FBHS01L 2
CLOCK SYNTHESIZER
2 CD85 0.01 uF 16V CD86 0.01 uF 16V CD87 0.01uF 16V CD88 100pF 16V CD89 100pF 16V CD90 100pF 16V C168
L14 1 FBHS01L
VCC2.5
+
22uF
C172 100pF 16V
C173 1 0 0 pF 16V
C174 0.01uF 16V
C175 0.01uF 16V
C176 0.01uF 16V
C177
+
22uF
4
4
VCC3 9 15 19 21 33 48 V D D P C I0 V D D P C I1 VDDCORE0 V D D 4 8 M HZ V D D C O RE1 VDDQREF VCC3 VCC3 U1 R31 200 46 41 37 V D D A P IC VDDCPU0 VDDCPU1
*NOTE* Override to 66MHz only.
CPUCLK0 CPUCLK1 CPUCLK2 CPUCLK3 PCICLK_F PCICLK_1 PCICLK_2 PCICLK_3 PCICLK_4 PCICLK_5 PCICLK_6 PCICLK_7 48MHZ_0 48MHZ_1 APICCLK_0 APICCLK_1
40 39 36 35 7 8 10 11 13 14 16 17 22 23 45 44 1 2 47
R32 R33 R34 R35 R36 R37 R41 R42 R43 R44 R45 R47 R48 R51 R52 R53 22 22 22 22 22
22 22 22 22 22 22 22 22 22 22 22
CPUHCLK1 4 CPUHCLK2 6 BXHCLK 8 I T P C LK P X P CLK 1 8 P C L K 1 22 P C L K 2 22 P C L K 3 23 P C L K 4 23 B X P CLK 9 PCLKAPIC 19 4 8 M h z_0 1 8 APICCLK 19 OSC1 24 OSC2 18 OSC3 20
4 JP11 R38 8.2K R39 8.2K R40 8.2K R283 10K R284 R285 10K 10K
* N O T E * F o r p o w e r m a naged systems, the PIIX4 must be c o n n e c t e d t PCICLK_F of the CKE100 which is a free r u n n i ng PCLK not affected by the assertion of PCISTOP#.
X T A LIN
STUFFING OPTION
* N O T E* 10-15 pF caps to ground may be desirable to reduce the effects of EMI.
R46 10 P I C C L K _ P1 3
5 42 28 27 26 25
XTALOUT RESV RESV S E L0 S E L1 S E L _ 1 0 0 /66# P C I _ S TP# C P U _ S T P# PWRDWN#
CK100
3 , 5 , 1 6 1 0 0 / 6 6# 1 8 P C I _ S T P#
3
R381 0 R382 0 R383 0 Y1
HPICCLK
R50 10
31 30 29
P I C C L K _ P2 5
VSSREF V S S PCI0 VSSPCI1 VSSPCI2 V S S CORE0 VSS48MHZ VSSCORE1 V S S C PU0 V S S C PU1 VSSAPIC
18 CPU_STP# 18 SUSA#
REF0 REF1 REF2
3
14.318MHz R54 0 C1 10pF C2 10pF C K 1 0 0 _05
DO NOT STUFF
Stuffing option to enable the stopping of the CPUCLKs, PCICLKs, and the powerdown of the CK100. Please note that the resistors are not stuffed.
Stuffing option to enable Spread# function for possible EMI reduction.
3 6 12 18 20 24 32 38 34 43 VCC2.5 VTT VCC2.5 R55 1K R56 1K R57 1K 5% VTT VTT
4,6,8 H R E S E T #
2
R60 240 I T P _RST
OPTIONAL ITP TEST CONNECTOR
J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
R61 330
R58 56 R63 330
R59 56
3 2 D B R E S ET# 3 T C K _1 R64 5 T C K _2 R65 3 T M S_1 R66 5 T M S_2 R69 47 I T P C LK 47 47 47
2
T R ST# 3 , 5 R_PRDY0 R67 R_PRDY1 R68 240 240 I T P R E Q#0 3 PRDY#0 3 I T P R E Q#1 5 PRDY#1 5 R70 680 R73 330 JP12 3 , 5 T D O _1 5 T D O _2 1 2 3 T D O _ J MP 2 3 TDI_JMP
1
VCC2.5
VCC2.5
ITP CONN
ITP_JMP CONFIG
TDO_JMP JP12 1-2
1
TDI_JMP JP13 1-2 1-2 2-3
CPU CONFIG SINGLE CPU1 DUAL CPU
R71 150
R72 150 JP13 1
TDI_1 3
2-3 2-3
INTEL CORPORATION
SINGLE CPU2
PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title CLOCK SYNTHESIZER Size Custom Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 7 of 40
A
B
C
D
A
B
C
D
E
VCC3 V21 Y21 F7 F9 F18 F20 G6 G21 J6 J21 AA7 AA9 AA18 AA20
4,6 H A # [ 3 1 : 3] U2-1 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 H A # 10 H A # 11 H A # 12 H A # 13 H A # 14 H A # 15 H A # 16 H A # 17 H A # 18 H A # 19 H A # 20 H A # 21 H A # 22 H A # 23 H A # 24 H A # 25 H A # 26 H A # 27 H A # 28 H A # 29 H A # 30 H A # 31 4 , 6 ,7 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 H R E SET# ADS# BNR# B P R I# DBSY# D E F ER# DRDY# HIT# HITM# H L O CK# HTRDY# BREQ0# RS#0 RS#1 RS#2 4 , 6 R S # [ 2 :0] H R E Q#0 H R E Q#1 H R E Q#2 H R E Q#3 H R E Q#4 G25 H22 G23 H23 G24 F26 G26 G22 F22 F23 F24 F25 E23 E26 E25 D25 D26 B25 C26 A25 C25 A24 D24 C23 B24 C24 A23 E22 D23 B23 K21 H24 H26 L23 J26 K23 L24 L22 K22 H25 B26 K26 L26 L25 J22 J23 K24 K25 J25 HA3# HA4# HA5# HA6# HA7# HA8# HA9# H A 1 0# H A 1 1# H A 1 2# H A 1 3# H A 1 4# H A 1 5# H A 1 6# H A 1 7# H A 1 8# H A 1 9# H A 2 0# H A 2 1# H A 2 2# H A 2 3# H A 2 4# H A 2 5# H A 2 6# H A 2 7# H A 2 8# H A 2 9# H A 3 0# H A 3 1# C P U R ST# A D S# BNR# B P R I# D B S Y# D E F ER# DRDY# HIT# HITM# H L O CK# HTRDY# BREQ0# RS#0 RS#1 RS#2 H R E Q#0 H R E Q#1 H R E Q#2 H R E Q#3 H R E Q#4
M A A [ 1 3:0] 1 3 ,14 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAB0# MAB1# MAB2# MAB3# MAB4# MAB5# MAB6# MAB7# MAB8# MAB9# MAB10 MAB11# MAB12# MAB13 CSA0# CSA1# CSA2# CSA3# CSA4# CSA5# CKE2/CSA6# CKE3/CSA7# CSB0# CSB1# CSB2# CSB3# CSB4# CSB5# CKE4/CSB6# CKE5/CSB7# DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 DQMB1 DQMB5 CKE0/FENA CKE1/GCKE SRAS_A# SRAS_B# SCAS_A# SCAS_B# AF17 AB16 AE17 AC17 AF18 AE19 AF19 AC18 AC19 AE20 AD20 AF21 AC21 AF25 AD16 AC16 AD17 AB17 AE18 AD19 AB18 AB19 AF20 AC20 AB20 AE21 AD21 AF22 AB14 AF15 AE15 AC15 AD15 AE16 AE24 AD23 AE25 AD24 AD26 AC24 AC26 AB23 AC23 AF24 AD13 AC13 AC25 AB26 AE14 AC14 AA22 AA24 AE13 AD14 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB#11 MAB#12 MAB13 CS_A#0 CS_A#1 CS_A#2 CS_A#3 CS_A#4 CS_A#5 CS_A#6 CS_A#7 CS_B#0 CS_B#1 CS_B#2 CS_B#3 CS_B#4 CS_B#5 CS_B#6 CS_B#7 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 DQMB1 DQMB5 DQMB1 15,16 DQMB5 15,16 F E N A 11,12 G C KE 10 47 VCC3
4
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
4
M A B #[13:0] 15,16
82443BX
492 BGA
L16 2 F B H S01L 100pF C S _ A # [1:0] 13 . 0 1 uF C S _ A # [3:2] 14 C S _ A # [5:4] 15 . 0 1 uF C S _ A # [7:6] 16 C S _ B #[1:0] 13 C S _ B #[3:2] 14 C S _ B #[5:4] 15 C S _ B #[7:6] 16 . 0 1 uF D Q M A [ 7:0] 1 3 ,14,15,16 . 0 1 uF . 0 1 uF C186 100pF C188 100pF C190 100pF C192 2 2 uF + C193 C191 C189 C187 C184 100pF C185 C183 1
VCC3
3
DRAM INTERFACE
SYSTEM INTERFACE
3
VCC3
R74 4.7k
U3
R75 8 . 2K
4,6 H R E Q # [ 4 :0] 7 BXHCLK N23 CRESET# M25 M26 A3
VDDIIC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
23 3 7 12 16 20 29 33 37 42 46
D C L K [ 1 5:0] 1 3 , 14,15,16
HCLKIN T E S TIN# CRESET# P C I RST#
2
33 C R ESET# 1 7 ,21,22,23 P C I RST#
**TESTIN# pullup may be removed after validation h a s been completed.
AC22 AF23 **On 4-DIMM solutions that don't support s e l f -refresh mode, GCKE should be N/C. R398 AF16 S R A S_A# 13,14 AA17 S R AS_B# 15,16 AF12 S C A S_A# 13,14 AB13 S C AS_B# 15,16 AE12 AC12 A B 2 1 R399 AD25 AB22 22 W E _ A # 13,14 W E _ B# 15,16
38 11 25 24 1 2 47 48
OE
CKBF
BUF_IN SCLOCK S D ATA R E SV R E SV R E SV R E SV
AE22 AE23 P22
R E S VA R E SVB R E S VC
WE_A# WE_B# DCLKO DCLKWR DCLKRD
VSSIIC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D C L K REF
SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17
4 5 8 9 13 14 17 18 31 32 35 36 40 41 44 45 21 28
R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R92 R93 R385
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D C LK10 D C LK11 D C LK6 D C LK7 D C LK0 D C LK1 D C LK14 D C LK15 D C LK13 D C LK12 D C LK3 D C LK2 D C LK5 D C LK4 D C LK9 D C LK8 D C L K REF
**PLEASE NOTE** These clock assignments may not be optimum.
2
S R CLK 10
CKBF C3 2 0 pF
443BX_10
slave address = 1101001b
*The unused SDRAM clocks m a y be disabled using the S M B u s interface.
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A1 A14 A26 C5 C9 C18 C22 E3 E12 E15 E24 F6 F8 F19 F21 H6 H21 J3 J24
1
* * L o cate R398 close to CKBF and R399 close to 443BX. **Locate "T" and cap close to BX. ** Please make DCLKREF trace length equal to 2.5" more than the DCLK outputs to the DIMMs. DCLK outputs to the DIMMs should all be the same recommended length. E x a m ple: if DCLK[0-11] = 2.5" then DCLKREF = 2.5" + 2.5".
A B C D
26 6 10 15 19 22 27 30 34 39 43
SMBCLK 3 , 5 , 1 5,16,18,34,39 S M BDATA 3 , 5 , 1 5,16,18,34,39 I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title 8 2 4 4 3 B X S Y S T E M AND DRAM INTERFACES Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E 1
Rev 1.0 8 of 40
A
B
C
D
E
VCC3
L11 L13 L14 L16 M12 M15 N11 N16 P11 P16 R12 R15 T11 T13 T14 T16 N26
1 7 ,22,23 A D [ 3 1 : 0] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / BE#0 C / BE#1 C / BE#2 C / BE#3 1 7 , 22,23,34 1 7 , 22,23,34 1 7 , 22,23,34 1 7 , 22,23,34 1 7 , 22,23,34 17,22,23 1 7 , 22,23,34 22,23,34 F R AME# D E VSEL# IRDY# TRDY# STOP# PAR S E RR# PLOCK# K6 K2 K4 K3 K5 J1 J2 H2 H1 J5 H3 H5 H4 G1 G2 G4 D1 D3 D2 C1 A2 C3 B3 D4 E5 A4 D5 B4 B5 A5 E6 C6 J4 G3 E4 C4 E2 F3 E1 F5 F4 G5 F1 F2 B6 D6 AE3 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 A6 C7 F10 D8 D10 AD4 E7 D7 E10 E8 E9 AF3 AC4 C2 B2
U 2 -2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / BE0# C / BE1# C / BE2# C / BE3# FRAME# DEVSEL# IRDY# TRDY# STOP# PAR S E RR# PLOCK# P H OLD# P H L DA# WSC# P R E Q0#/IOREQ# PREQ1# PREQ2# PREQ3# PREQ4# S U STAT# P G N T 0 #/IOGNT# PGNT1# PGNT2# PGNT3# PGNT4# BX-PWROK C L K R U N# R E F V CC5 P C L K IN
P1 AE1 V6 Y6
G A D [ 3 1 :0] 21 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GC/BE0# GC/BE1# GC/BE2# GC/BE3# GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# GCLKOUT GCLKIN PIPE# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 RBF# ST0 ST1 ST2 GADSTB-A GADSTB-B SB-STB AB5 AE2 AD3 AD2 AD1 AC3 AC1 AB4 AB1 AA5 AA3 AA4 AA2 AA1 Y5 Y3 W1 V2 W2 U5 V1 U4 U3 U1 T3 T4 T2 T1 U6 R3 R4 R2 AB2 Y4 V4 U2 W3 W5 V5 W4 Y1 Y2 L5 L3 P5 N5 M3 K1 M2 M1 N2 P2 P4 P3 R1 M4 L4 L2 L1 AC2 T5 N3 N4 R101 100 1% ST0 ST1 ST2 S T [ 2 :0] 21 A D S T B-A 21,34 A D S TB-B 21,34 SBSTB 21,34 R97 R98 22 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 P I PE# 21,34 22 G A D0 G A D1 G A D2 G A D3 G A D4 G A D5 G A D6 G A D7 G A D8 G A D9 G A D10 G A D11 G A D12 G A D13 G A D14 G A D15 G A D16 G A D17 G A D18 G A D19 G A D20 G A D21 G A D22 G A D23 G A D24 G A D25 G A D26 G A D27 G A D28 G A D29 G A D30 G A D31 GCBE#0 GCBE#1 GCBE#2 GCBE#3 G F RAME# 21,34 G D EVSEL# 2 1 ,34 G I R D Y # 21,34 G T R D Y# 21,34 GSTOP# 21,34 G P A R 21,34 G R EQ# 21,34 G G N T# 21,34 G C L KOUT 21
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
4
VDD VDD VDD VDD
4
82443BX
492 BGA
P C I INTERFACE
3
3
1 7 ,22,23 C / B E # [ 3:0]
G C / B E # [3:0] 21
VCC3 R95 10K
17,34 P H L D# 17,34 P H L D A# 19 W S C # 1 7 , 22,23,34 P R E Q #[3:0]
AGP INTERFACE
2
18 S U STAT#
R400 0
34 PREQ#4 2 2 ,23,34 P G N T # [ 3:0]
** Note** Please make the GCLKIN trace length 3.3" more than the GCLKOUT recommended trace length. Stub to tee should be 1" MAX.
P C I ARB & PWR MGT
2
DO NOT STUFF
S t u f fing option to enable and test 34 PGNT#4 18,32 P W R O K the POS state.
18 V R E F 5V 7 BXPCLK
S B A [ 7 :0] 21 R B F# 21,34 VCC3
R99 150 1%
R294
AGPREFV VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
100 443BX
**NOTE** Locate circuitry close to 443BX.
1
N1 M5 L12 L15 M11 M13 M14 M16 M22 N12 N13 N14 N15 P12 P13 P14 P15 P26 T12 T15 R5 R11 R13 R14 R16 R22 V3 V24 W6 W21
C5 0 . 001uF
**NOTE: It is recommended that the tolerance on these resistors be 1% in order to meet the margins of this reference voltage.
1
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title 8 2 4 4 3 B X P C I A N D AGP INTERFACES Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998
A B C D
Rev 1.0 9 of 40
Sheet
E
A
B
C
D
E
VCC3 B1 N22 AF14 AF2 AE26 H D # [ 6 3 : 0] 3,5
11,12 M D [ 6 3:0] MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 12 M E C C [ 7:0] AF4 AE4 AF5 AD6 AE6 AB7 AC7 AF7 AB8 AB9 AC9 AE9 AB10 AC10 AF10 AD11 Y24 Y25 W23 W24 W26 W25 V26 U24 U23 T22 T23 T26 R24 R25 P23 N25 AC5 AE5 AB6 AC6 AF6 AD7 AE7 AC8 AD8 AF8 AE8 AF9 AD10 AE10 AB11 AC11 Y23 Y26 W22 V22 V23 V25 U22 U25 U26 T24 T25 U21 R23 R26 P24 P25 AE11 AA10 AA23 AA26 AF11 AD12 AA25 Y22
U2-3 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7
4
82443BX
492 BGA
3
2
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
B22 D22 E21 A22 D21 C21 A21 C20 B21 E20 A20 E19 B20 E18 D20 D19 D18 C19 B19 A18 A19 B18 C17 E17 D17 B17 C16 A17 C15 B16 D16 A16 B15 A15 D14 D15 B13 C14 E14 D13 A13 D12 B12 B14 C13 E13 D11 A12 B11 A11 B7 C12 C8 B10 A10 A9 A7 E11 D9 C11 C10 B8 A8 B9
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 H D # 10 H D # 11 H D # 12 H D # 13 H D # 14 H D # 15 H D # 16 H D # 17 H D # 18 H D # 19 H D # 20 H D # 21 H D # 22 H D # 23 H D # 24 H D # 25 H D # 26 H D # 27 H D # 28 H D # 29 H D # 30 H D # 31 H D # 32 H D # 33 H D # 34 H D # 35 H D # 36 H D # 37 H D # 38 H D # 39 H D # 40 H D # 41 H D # 42 H D # 43 H D # 44 H D # 45 H D # 46 H D # 47 H D # 48 H D # 49 H D # 50 H D # 51 H D # 52 H D # 53 H D # 54 H D # 55 H D # 56 H D # 57 H D # 58 H D # 59 H D # 60 H D # 61 H D # 62 H D # 63
VDD VDD VDD VDD VDD
R386 8 S R CLK
4 . 7K
U33 1 48 24 25 1EN C1 2EN C2
4
R396 4.7K C194 27pF
47 46 44 43 41 40 38 37 36
1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8
1
1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
**NOTE** The trace lengths of B C K E [ 7 : 0 ] should be 3.0"
B_CKE7 16
8 G C KE
**NOTE** GCKE trace length from the 443BX to the shift register should be between 1" MIN and 4" MAX.
B_CKE6 16
B_CKE5 15
B_CKE4 15
HOST DATA BUS
443BX_10
VTT
R102 75 1%
1
AB25 N24 AA6 AA8 AA19 AA21 AB3 AB12 AB15 AB24 AD5 AD9 AD18 AD22 AF1 AF13 AF26
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M E M O R Y DATA BUS
VTT R104 75 1% GTLREF1
2
2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
**NOTE** If GCKE is not used then each CKE requires a 22K pullup to VCC3.
35 33 32 30 29 27 26
B_CKE3 14
3
B_CKE2 14
B_CKE1 13
B_CKE0 13
S N 7 4 LVCH16374
**NOTE** The seven outputs that circle around to become inputs on the SN74LVCH16374 should have trace lengths no longer than 2".
2
G T LREF2 G T LREF1 M23 E16 M24 F17
GTLREFA GTLREFB VTTA VTTB
VTT
G T LREF2 I N T E L C O R P O RATION R105 150 1% P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title 8 2 4 4 3 BX MD/HD BUS Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet
E
1
R103 150 1%
C6 0 . 001uF
C7 0 . 0 01uF
Rev 1.0 10 of 40
A
B
C
D
A
B
C
D
E
VCC
FET-SWITCHES (MEMORY DATA LINES & ECC)
VCC R106 4 . 7K VCC FENA M D [ 63:0]
4
U4 1 56 55 MD12 R295 VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND 17 M D _ A [ 63:0] 1 2 ,13,14 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A0 MD_B0 MD_A1 MD_B1 MD_A2 MD_B2 MD_A3 MD_B3 MD_A4 MD_B4 MD_A5 MD_B5 MD_A6 MD_B6 MD_A7 MD_B7 MD_A8 MD_B8 MD_A9 MD_B9 MD_A10 MD_B10 MD_A11 MD_B11 P I 5C16212A R296 500 500 R297 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28 S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND 17 M D _ A [ 63:0] 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A12 MD_B12 MD_A13 MD_B13 MD_A14 MD_B14 MD_A15 MD_B15 MD_A16 MD_B16 MD_A17 MD_B17 MD_A18 MD_B18 MD_A19 MD_B19 MD_A20 MD_B20 MD_A21 MD_B21 MD_A22 MD_B22 MD_A23 MD_B23 M D _ B [63:0]
4
R107 4.7K U5 8,12 F E N A 10,12 M D [ 63:0] MD0 R299 R301 500 500 R303 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 1 56 55 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28 S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2
VCC
R298 500 500 R300
R302 500 500 R304
R305 500 500 R307
R306 500 500 R308
R309 500 500 R311
R310 500 500 R312
R313 500
3
R314 500 500
500
R315
3
R316 500 500 R317
R318 500 500
M D _ B [63:0] 1 2 ,15,16
VCC
PI5C16212A
FET ENABLE TRUTH TABLE
R108 4 . 7K U6 FENA M D [ 6 3:0] MD24
2
VCC
FUNCTION A1 TO B1, A2 TO B2
S2 H H
S1 H H
S0 [FENA] L H
A1 B1 B2
A2 B2 B1 A1 = DRAM DATA LINES A2 = GND B1 = DIMM 0,1 DATA LINES B2 = DIMM 2,3 DATA LINES
1 56 55 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28
S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2
VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND
17 M D _ A [ 63:0] 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A24 MD_B24 MD_A25 MD_B25 MD_A26 MD_B26 MD_A27 MD_B27 MD_A28 MD_B28 MD_A29 MD_B29 MD_A30 MD_B30 MD_A31 MD_B31 MD_A32 MD_B32 MD_A33 MD_B33 MD_A34 MD_B34 MD_A35 MD_B35 M D _ B [63:0]
A1 TO B1, A2 TO B2
2
R319 R320 500 500 R321
MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35
R322 500 500 R323
R324 500 500 R325
R326 500 500 R327
R328 500 500 R329
R330 500 500
1
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S O M, CA. 95630 Title F E T S W I T C H E S ( DP/4 DIMM Design) Size Document Number Intel(R) 440BX AGPset Custom Date: Thursday, April 09, 1998 S h eet
E
1
P I 5C16212A
Rev 1.0 11 of 40
A
B
C
D
A
B
C
D
E
FET-SWITCHES (DRAM DATA LINES & ECC)
VCC VCC
4
R109 4.7K U7 8,11 F E N A 10,11 M D [ 6 3:0] MD36 R331 R333 500 500 R335 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 1 56 55 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28 S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND PI5C16212A 17
VCC R110 4 . 7K U8 FENA M D _ A [ 63:0] 1 1 ,13,14 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A36 MD_B36 MD_A37 MD_B37 MD_A38 MD_B38 MD_A39 MD_B39 MD_A40 MD_B40 MD_A41 MD_B41 MD_A42 MD_B42 MD_A43 MD_B43 MD_A44 MD_B44 MD_A45 MD_B45 MD_A46 MD_B46 MD_A47 MD_B47 R332 R334 500 500 R336 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD48 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28 M D [ 63:0] 1 56 55 S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND P I 5C16212A 17 M D _ A [63:0] 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A48 MD_B48 MD_A49 MD_B49 MD_A50 MD_B50 MD_A51 MD_B51 MD_A52 MD_B52 MD_A53 MD_B53 MD_A54 MD_B54 MD_A55 MD_B55 MD_A56 MD_B56 MD_A57 MD_B57 MD_A58 MD_B58 MD_A59 MD_B59 M D _ B[63:0] VCC
4
R337 500 500 R339
R338 500 500 R340
R341 500 500 R343
R342 500 500 R344
R345 500 500
3
R346 500 500 R348
R347
3
R349 500 500 R351
R350 500 500 M D _ B [63:0] 1 1 ,15,16 R352
R353 500 500
R354 500 500
VCC
FET ENABLE TRUTH TABLE
R111 4.7K U9
2
VCC
FUNCTION
M D _ B [63:0]
S2 H H
S1 H H
S0 [FENA] L H
A1 B1 B2
A2 B2 B1 A1 = DRAM DATA LINES A2 = GND B1 = DIMM 0,1 DATA LINES B2 = DIMM 2,3 DATA LINES
2
A1 TO B1, A2 TO B2 A1 TO B1, A2 TO B2
FENA M D [ 6 3:0] MD60 R355 R356 500 500 R357 MD61 MD62 MD63 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7
1 56 55 2 3 4 5 6 7 9 10 11 12 13 14 15 16 18 20 21 22 23 24 25 26 27 28
S0 S1 S2 1A1 1A2 2A1 2A2 3A1 3A2 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 8A1 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2
VCC 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 GND GND GND GND
17 M D _ A [ 63:0] 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 30 29 8 19 38 49 MD_A60 MD_B60 MD_A61 MD_B61 MD_A62 MD_B62 MD_A63 MD_B63 M E CC_A0 MECC_B0 M E CC_A1 MECC_B1 M E CC_A2 MECC_B2 M E CC_A3 MECC_B3 M E CC_A4 MECC_B4 M E CC_A5 MECC_B5 M E CC_A6 MECC_B6 M E CC_A7 MECC_B7 I N T E L C O R P O RATION M E C C _ B[7:0] 1 3 ,14,15,16 P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S O M, CA. 95630 Title M E C C _ A [7:0] 1 3 ,14,15,16
R358 500 500 R359
R360 500 500 R361
R362 500 500 R363
R364 500 500
1
R365
1
R366 500 500 10 M E C C [ 7:0] PI5C16212A
F E T S W I T C H E S ( DP/4 DIMM Design) Size Document Number Intel(R) 440BX AGPset Custom Date: Thursday, April 09, 1998 S h eet
E
Rev 1.0 12 of 40
A
B
C
D
A
B
C
D
E
DIMM SOCKET 0
VCC3 VCC3 11,12,14 MD_A[63:0]
4 4
6 18 26 40 41 90 102 110 124
J4 MD_A0 MD_A1 MD_A2 MD_A3 MD_A4 MD_A5 MD_A6 MD_A7 MD_A8 MD_A9 MD_A10 MD_A11 MD_A12 MD_A13 MD_A14 MD_A15 MD_A32 MD_A33 MD_A34 MD_A35 MD_A36 MD_A37 MD_A38 MD_A39
3
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
49 59 73 84 133 143 157 168
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD_A16 MD_A17 MD_A18 MD_A19 MD_A20 MD_A21 MD_A22 MD_A23 MD_A24 MD_A25 MD_A26 MD_A27 MD_A28 MD_A29 MD_A30 MD_A31 MD_A48 MD_A49 MD_A50 MD_A51 MD_A52 MD_A53 MD_A54 MD_A55 MD_A56 MD_A57 MD_A58 MD_A59 MD_A60 MD_A61 MD_A62 MD_A63
VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC
8,14 MAA[13:0]
MD_A40 MD_A41 MD_A42 MD_A43 MD_A44 MD_A45 MD_A46 MD_A47 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
3
VCC3
8,14,15,16
DQMA[7:0] DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 MAA11 MAA12
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
R367 0 ohm
B_CKE0 10 B_CKE1 10 MECC_A0 MECC_A1 MECC_A2 MECC_A3 MECC_A4 MECC_A5 MECC_A6 MECC_A7 MECC_A[7:0]
**NOTE** If GCKE is not used then each CKE requires a 22K pullup to VCC3.
12,14,15,16
2
2
SLAVE ADDRESS = 1010000b
SMBDATA 3,5,8,15,16,18,34,39 SMBCLK 3,5,8,15,16,18,34,39 CS_A#[1:0] CS_A#0 CS_A#1 CS_B#0 CS_B#1 CS_B#[1:0] 8 8
WE_A# 8,14 SCAS_A# 8,14 SRAS_A# 8,14 DCLK12 DCLK13 DCLK14 DCLK15 DCLK[15:0] 8,14,15,16
SDRAM DIMM
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMP ONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 0 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 13 of 40
A
B
C
D
E
DIMM SOCKET 1
VCC3 VCC3 11,12,13 MD_A[63:0]
4 4
6 18 26 40 41 90 102 110 124
J5 MD_A0 MD_A1 MD_A2 MD_A3 MD_A4 MD_A5 MD_A6 MD_A7 MD_A8 MD_A9 MD_A10 MD_A11 MD_A12 MD_A13 MD_A14 MD_A15 MD_A32 MD_A33 MD_A34 MD_A35 MD_A36 MD_A37 MD_A38 MD_A39
3
49 59 73 84 133 143 157 168
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD_A16 MD_A17 MD_A18 MD_A19 MD_A20 MD_A21 MD_A22 MD_A23 MD_A24 MD_A25 MD_A26 MD_A27 MD_A28 MD_A29 MD_A30 MD_A31 MD_A48 MD_A49 MD_A50 MD_A51 MD_A52 MD_A53 MD_A54 MD_A55 MD_A56 MD_A57 MD_A58 MD_A59 MD_A60 MD_A61 MD_A62 MD_A63
VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC
8,13 MAA[13:0]
MD_A40 MD_A41 MD_A42 MD_A43 MD_A44 MD_A45 MD_A46 MD_A47 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA13
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
VCC3
3
8,13,15,16
DQMA[7:0] DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 MAA11 MAA12
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
R368 0 ohm
**NOTE** If GCKE is not used then each CKE requires a 22K pullup to VCC3.
B_CKE2 10 B_CKE3 10 MECC_A[7:0] 12,13,15,16
MECC_A0 MECC_A1 MECC_A2 MECC_A3 MECC_A4 MECC_A5 MECC_A6 MECC_A7 R_SA0
VCC3
2
R114 4.7K
SLAVE ADDRESS = 1010001b
SMBDATA 3,5,8,15,16,18,34,39 SMBCLK 3,5,8,15,16,18,34,39 CS_A#[3:2] 8 8
2
CS_A#2 CS_A#3 CS_B#2 CS_B#3
CS_B#[3:2]
WE_A# 8,13 SCAS_A# 8,13 SRAS_A# 8,13 DCLK8 DCLK9 DCLK10 DCLK11 DCLK[15:0] 8,13,15,16
SDRAM DIMM
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMP ONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 1 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 Sheet
E
Rev 1.0 14 of 40
A
B
C
D
E
DIMM SOCKET 2
VCC3 VCC3 11,12,16 MD_B[63:0]
4 4
6 18 26 40 41 90 102 110 124
J6 MD_B0 MD_B1 MD_B2 MD_B3 MD_B4 MD_B5 MD_B6 MD_B7 MD_B8 MD_B9 MD_B10 MD_B11 MD_B12 MD_B13 MD_B14 MD_B15 MD_B32 MD_B33 MD_B34 MD_B35 MD_B36 MD_B37 MD_B38 MD_B39 MD_B40 MD_B41 MD_B42 MD_B43 MD_B44 MD_B45 MD_B46 MD_B47 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB13 8,13,14,16 DQMA[7:0] DQMA0 8,16 D Q M B 1
2
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145
49 59 73 84 133 143 157 168
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD_B16 MD_B17 MD_B18 MD_B19 MD_B20 MD_B21 MD_B22 MD_B23 MD_B24 MD_B25 MD_B26 MD_B27 MD_B28 MD_B29 MD_B30 MD_B31 MD_B48 MD_B49 MD_B50 MD_B51 MD_B52 MD_B53 MD_B54 MD_B55 MD_B56 MD_B57 MD_B58 MD_B59 MD_B60 MD_B61 MD_B62 MD_B63 VCC3
VCC VCC VCC VCC VCC VCC VCC VCC VCC
3
VCC VCC VCC VCC VCC VCC VCC VCC
3
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate registered DIMMs.
8,16 MAB#[13:0]
R369 0 ohm
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
**NOTE** If GCKE is not used then each CKE requires a 22K pullup to VCC3.
B _ C K E 4 10 B _ C K E 5 10 MECC_B[7:0] 12,13,14,16 MECC_B0 MECC_B1 MECC_B2 MECC_B3 MECC_B4 MECC_B5 MECC_B6 MECC_B7
DQMA2 DQMA3 DQMA4 DQMA6 DQMA7 MAB#11 MAB#12
VCC3
Slave address = 1010010b
R_SA1 R116 4.7K S M B D A T A 3,5,8,16,18,34,39 S M B C L K 3,5,8,16,18,34,39 CS_A#[5:4] 8 CS_A#4 CS_A#5 CS_B#4 CS_B#5 CS_B#[5:4] 8
2
8,16 D Q M B 5
W E _ B # 8,16 SCAS_B# 8,16 SRAS_B# 8,16 DCLK4 DCLK5 DCLK6 DCLK7 DCLK[15:0] 8,13,14,16
SDRAM DIMM
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 2 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 S heet
E
Rev 1.0 15 of 40
A
B
C
D
E
DIMM SOCKET 3
VCC3 VCC3 11,12,15 MD_B[63:0]
4 4
6 18 26 40 41 90 102 110 124
J7 MD_B0 MD_B1 MD_B2 MD_B3 MD_B4 MD_B5 MD_B6 MD_B7 MD_B8 MD_B9 MD_B10 MD_B11 MD_B12 MD_B13 MD_B14 MD_B15 MD_B32 MD_B33 MD_B34 MD_B35 MD_B36 MD_B37 MD_B38 MD_B39 MD_B40 MD_B41 MD_B42 MD_B43 MD_B44 MD_B45 MD_B46 MD_B47 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB13 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 33 117 34 118 35 119 36 120 37 121 38 123 126 132 28 29 46 47 112 113 130 131 122 39 24 25 31 44 48 50 51 61 80 81 109 108 145 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
49 59 73 84 133 143 157 168
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NC NC NC NC NC REGE CKE0 CKE1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 SA0 SA1 SA2 SDA SCL /S0 /S1 /S2 /S3 /WE0 /CAS /RAS CK0 CK1 CK2 CK3
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 134 135 146 164 62 147 128 63 21 22 52 53 105 106 136 137 165 166 167 82 83 30 114 45 129 27 111 115 42 125 79 163
MD_B16 MD_B17 MD_B18 MD_B19 MD_B20 MD_B21 MD_B22 MD_B23 MD_B24 MD_B25 MD_B26 MD_B27 MD_B28 MD_B29 MD_B30 MD_B31 MD_B48 MD_B49 MD_B50 MD_B51 MD_B52 MD_B53 MD_B54 MD_B55 MD_B56 MD_B57 MD_B58 MD_B59 MD_B60 MD_B61 MD_B62 MD_B63
VCC VCC VCC VCC VCC VCC VCC VCC VCC
3
VCC VCC VCC VCC VCC VCC VCC VCC
3
VCC3
3,5,7 100/66#
R120 10K JP16 IOQ DEPTH SEL
MAB#12 8,15 MAB#[13:0] MAB#11
**NOTE ON ALL DIMM SOCKETS** Pin 147 should be pulled to a high state to accommodate R370 0 ohm registered DIMMs. **NOTE** If GCKE is not used then each CKE requires a 22K pullup to VCC3.
R119 10K 8,13,14,15 DQMA[7:0] DQMA0 8,15 D Q M B 1
2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (AP) A11 A12 A13 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 BA0 BA1 NC NC NC NC NC NC NC NC NC NC NC NC NC
B _ C K E 6 10 B _ C K E 7 10
MECC_B[7:0] 12,13,14,15 MECC_B0 MECC_B1 MECC_B2 MECC_B3 MECC_B4 MECC_B5 MECC_B6 MECC_B7 VCC3
DQMA2 DQMA3 DQMA4 DQMA6 DQMA7 MAB#11 MAB#12
R121 4.7K
Slave address = 1010011b
2
8,15 D Q M B 5
S M B D A T A 3,5,8,15,18,34,39 S M B C L K 3,5,8,15,18,34,39 CS_A#[7:6] 8 CS_A#6 CS_A#7 CS_B#6 CS_B#7 CS_B#[7:6] 8
MAB#11: 1 = IOQ depth of 4 (default), 0 = IOQ depth of 1
W E _ B # 8,15 SCAS_B# 8,15 SRAS_B# 8,15 DCLK0 DCLK1 DCLK2 DCLK3 DCLK[15:0] 8,13,14,15
SDRAM DIMM
1
1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title DIMM SOCKET 3 Size Custom Date:
A B C D
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 S heet
E
Rev 1.0 16 of 40
A
B
C
D
E
U10A AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 9 , 22,23 A D [ 3 1 : 0] C / BE#0 C / BE#1 C / BE#2 C / BE#3 B10 A10 D9 C9 B9 A9 D8 E8 B8 A8 D7 C7 B7 A7 D6 E6 E4 C4 B4 A4 D3 E3 C3 B3 E2 C2 B2 A2 D1 E1 C1 B1 C8 C6 D4 D2 C10 E5 A5 A3 B5 B6 A1 B12 A12 A6 D5 C5 E10 A11 B11 C11 C17 B17 A18 G19 A17 F18 A16 F17 F16 G20 C16 B16 D16 G16 G18 G17 F20 E18 E20 D18 D20 C20 B20 A20 A19 B19 C19 D19 D17 E19 E17 F19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C / B E#0 C / B E#1 C / B E#2 C / B E#3 C L O C K R U N# D E VSEL# F R AME# I D S EL IRDY# PAR P C I R ST# P H O LD# P H O L DA# S E R R# STOP# TRDY# REQ0# REQ1# REQ2# REQ3# S D A0 S D A1 S D A2 P D D A CK# S D D A CK# P D R EQ S D R EQ P D I O R# P D IOW# PIORDY S D I O R# S D IOW# SIORDY P D A0 P D A1 P D A2 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 P D D10 P D D11 P D D12 P D D13 P D D14 P D D15 PIIX4_15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SCS3# PCS3# SCS1# PCS1# SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 LA17 LA18 LA19 LA20 LA21 LA22 LA23 MEMCS16# MEMR# MEMW# SMEMR# SMEMW# SYSCLK BALE IOCHK# REFRESH# IOCS16# ZEROWS# SBHE# RSTDRV IOR# IOW# IOCHRDY AEN E15 B15 D14 C14 A14 C13 A13 C12 D12 B13 D13 B14 E14 A15 C15 D15 C18 H16 B18 H17 U11 T11 W11 Y11 T10 W10 U9 V9 Y9 T8 W8 U7 V7 Y7 V6 Y6 T5 W5 U4 V4 V3 W3 U2 T2 W2 Y2 T1 V1 W16 T16 Y17 V17 Y18 W18 Y19 W19 Y15 T14 W14 U13 V13 Y13 T12 Y12 V15 U15 W4 U3 T7 U10 Y1 W7 V12 Y3 W12 W1 Y5 T4 T3 Y4 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 S A [ 1 9 :0] 1 9 , 2 0,24,27,35,39 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 S D [ 1 5 :0] 2 0 ,24,35 LA17 LA18 LA19 LA20 LA21 LA22 LA23 L A [ 2 3:17] 24,35 MEMCS16# 24,35 MEMR# 1 9 ,24,27,35 MEMW# 1 9 ,24,27,35 SMEMR# 24 SMEMW# 24 S Y S CLK 24,39 BALE 24 I O C H K# 24,35 R E F R ESH# 24,35 I O CS16# 24,35 Z E R O W S # 24,35 SBHE# 24 R S T D RV 20,32 I O R# 2 0 , 24,35,39 IOW# 2 0 , 24,35,39 I O C H R D Y 2 0 ,24,35 A E N 20,24 I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S O M, CA 95630 Title 8 2 3 7 1 EB (PART I) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998
A B C D 1
4
IDE SIGNALS
S D D0 S D D1 S D D2 S D D3 S D D4 S D D5 S D D6 S D D7 S D D8 S D D9 S D D10 S D D11 S D D12 S D D13 S D D14 S D D15 S D D [ 1 5 :0] 25 SCS3# 25 PCS3# 25 SCS1# 25 PCS1# 25
4
PCI BUS INTERFACE
82371EB
3
9 , 22,23 C / B E # [ 3:0] 9 , 22,23,34 D E VSEL# 9 , 2 2,23,34 F R AME# R371 100 9 , 2 2,23,34 I R D Y # 9 , 22,23 P A R 8 , 2 1,22,23 P C I R ST# 9 , 34 P H L D# 9,34 P H L D A# 9 , 2 2,23,34 S E RR# 9 , 2 2,23,34 STOP# 9 , 2 2,23,34 T R D Y # 9 , 2 2,23,34 P R E Q #[3:0]
3
R _ AD18
R122 100 A D 18
25 S D A [ 2 : 0]
S D A0 S D A1 S D A2
2
25 25 25 25 25 25 25 25 25 25
P D D A CK# S D D A CK# P D R EQ S D R EQ P D I O R# PDIOW# PIORDY S D I O R# S D IOW# SIORDY
ISA/EIO SIGNALS
PREQ#0 PREQ#1 PREQ#2 PREQ#3
2
IDE SIGNALS
P D A0 P D A1 P D A2 P D D0 P D D1 P D D2 P D D3 P D D4 P D D5 P D D6 P D D7 P D D8 P D D9 P D D10 P D D11 P D D12 P D D13 P D D14 P D D15
25 P D A [ 2 : 0]
1
25 P D D [ 1 5:0]
Rev 1.0 17
E
Sheet
of
40
A
B
C
D
E
VCC3
VCC3
3VSB VCC3
F6 E11 F15 R6 R15
U10B 20,24 D A C K # [ 3 : 0 ]
4
E9 E12 E16 F5 F14 G6 R7 P15 T6
R16 N16 K5
24 DACK#[7:5]
DACK#0 DACK#1 DACK#2 DACK#3 DACK#5 DACK#6 DACK#7
U14 W6 Y10 V5 T15 V16 W17 W15 U6 V2 U5 Y16 U16 U17 M1 N2 P3 N1 P2 P4 V10 J17 H18 K18 H20 J20 T9 W9 U8 V8 Y8 Y20 U1 U12 W13 T13 V14 Y14 J19 R3 R4 P5 G1 M19 K19 L17 L18 L19 P1 L20 P20 N20 M20 M18 K17 V18
DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7# DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7 REQA#/GPI2 REQB#/GPI3 REQC#/GPI4 GNTA#/GPO9 GNTB#/GPO10 GNTC#/GPO11 TC APICACK#/GPO12 APICCS#/GPO13 APICREQ#/GPI5 IRQ0/GPO14 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8/GPI6 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 SERIRQ/GPI7 PIRQA# PIRQB# PIRQC# PIRQD# CPURST FERR# IGNNE# INIT INTR A20GATE NMI PX4_SMI# RCIN# A20M# PWROK SPKR TEST#
USBP1+ USBP1USBP0+ USBP0OC0 OC1
F1 H2 G2 H3 J1 J2 V20 W20 V19 U18 R1 R2 K16 H19 U19 M17 U20 P16 T20 R19 N17 P18
USBP1+ 26 USBP1- 26 USBP0+ 26 USBP0- 26 OC#0 26 OC#1 26 EXTSMI# 34,39 SUSA# 7 SUSC# C12 CPU_STP# 7 PCI_STP# 7 0.01 uF
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCC VCC VCC VCC VCC
VCCSUS VCCSUS VCCUSB
5VSB
USB
JP29 CONFIG.
3VSB 5VSB R413 10K
4
1-2 2-3
POWER MANAGEMENT
20,24,35 20,24,35 20,24,35 20,24,35 24,35 24,35 24,35
DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7
EXTSMI# SUSA# GPO15/SUSB# GPO16/SUSC# GPO17/CPU_STP# GPO18/PCI_STP# GPO19/ZZ GPI8/THERM# GPI9/BATLOW# RSMRST# PWRBT# GPI10/LID SMBDATA SMBCLK GPI11/SMBALERT# GPI12/RI#A
14 U11F 13 7 74LVC14 12
14 U36A 1 7 74F07 JP29 2
SAVE STATE ON POWER DOWN. PIIX4 POWERS ON SYS. AT POWER-UP.
DMA SIGNALS
34 REQ#A 34 REQ#B 34 REQ#C
20,24 T C 19 APICACK# 19,34 A P I C C S # 19,34 A P I C R E Q # 1 9 IRQ0 19,20,35 IRQ1 19,20,24,35 IRQ3 19,20,24,35 IRQ4 19,20,24,35 IRQ5 19,20,24,35 IRQ6 19,20,24,35 IRQ7 19,35 IRQ#8 19,20,24,35 IRQ9 19,20,24,35 IRQ10 19,20,24,35 IRQ11 19,20,24,35 IRQ12 19,20,24,25,35 IRQ14 19,20,24,25,35 IRQ15 3 4 GPI7 19,21,22,23,34 PIRQ#A 19,21,22,23,34 PIRQ#B 19,22,23,34 PIRQ#C 19,22,23,34 PIRQ#D PIRQ#A PIRQ#B PIRQ#C PIRQ#D
82371EB
T H E R M # 3,5,34 BATLOW# 34 RSMRST# 32 PWRBT# 32 LID 32,34 S M B D A T A 3,5,8,15,16,34,39 S M B C L K 3,5,8,15,16,34,39 SMBALERT# 34 A G P _ P M E # 21,34
3 2 1 B_SUSC 32
VCC3
**External logic shown is used to handle power loss condition.
JMP_3P
3
SUSCLK GPO20/SUS_STAT1# GPO21/SUS_STAT2# STPCLK# SLP#
P17 T17 T18 J18 K20
SUSTAT# 9 S T P C L K # 3,5,34 S L P # 3,5,34
D1 SCHOTTKY BAR43
VCC
R128 1K
3
5VSB 14 9 10 11 7
U22C
SPS3 8 R286 10K 1
3
G P O /GPI/GPIO/SCAN
IRQ SIGNALS CPU INTERFACE
VREF
J16
VREF5V 9
+
GPI1 GPI13 GPI14 GPI15 GPI16 GPI17 GPI18 GPI19 GPI20 GPI21 P19 L2 J3 L5 K3 K4 H1 H4 H5 G3 GPI13 GPI14 GPI15 GPI16 GPI17 GPI18 GPI19 GPI20 P C I _ P M E # 22,23,34
C13 1.0 uF
C14 0.1 uF 5VSB 5VSB
SUSC# GPI[20:13] 34
Q8 2N7002 2
WOLLID
32
3,5,34 F E R R # 33,34 P X 4 _ I G N N E # 3,5,34 HINIT# 19,33,34 PX4_INTR 20,34 A 2 0 G A T E 33,34 P X 4 _ N M I 19,34 P X 4 _ S M I # 3VSB 20,34 K B R S T # 33,34 P X 4 _ A 2 0 M# 9,32 P W R O K 32 SPKR 34 TEST# D2 SCHOTTKY BAR43
74HC10 GPI21 2 9
SPS2 RTC_BAT
2
GPO0 GPO8 GPO27 GPO28 GPO29 GPO30 MCCS#
G4 T19 G5 F2 F3 F4 N4
GPO0 GPO8 GPO27 GPO28
FAN_LED 32 1 1 TP3 TP4 IRQ9OUT
3
10K 19 8.2K R414 R387 1
Q6 2N7002 2
POWER-ON
32
2
20 XOE# 2 0 XDIR# 27 BIOSCS# RTC_BAT
VB2
R129 1K
1 3 C15 0.1 uF
JP17
2 RTCX2 RTCX1 R287 0
M4 M3 M2 L1 K2 K1 L16 R20 N19 L3 V11 D11
XOE#/GPO23 XDIR#/GPO22 BIOSCS# RTCALE/GPO25 RTCCS#/GPO24 KBCCS#/GPO26 VBAT RTCX2 RTCX1 48Mhz OSC PCICLK
5VSB U32A Q 5 10 4 L4 N5 J4 N18 N3 M5 M16 R5 R17 R18 PGCS#0 PGCS#1 32 PS_POK 1.5K 5VSB PX4_CFG1 34 14 3 7 R130 8.2K 74HCT14 0.1uF U30B 4 GPO8# 1 TP5 P G C S # 1 34,39 R388 1K U32B Q 9 10K R415 CL Q 7 3 2 R288 8.2K 1 RSMRST# C113 Q5 2N7002
PR
N/C N/C N/C N/C N/C N/C CONFIG1 CONFIG2
R389
1 2 8
CLK K GND CL Q 6
13 12 8
CLK K GND
15
74HC112 JK_CLR
14
PR
X-BUS
PGCS0# PGCS1#
16 3
VCC J
16 11
VCC J
74HC112
Y2 2 1 32.768KHz C16 18pF C17 18pF PIIX4_15
R131 1K 1 VB1
D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12
CLEAR CMOS
BT1
J5
VSS_USB
D3 SCHOTTKY BAR43 CMOS_CLR
7 48Mhz_0 7 OSC2 7 PXPCLK
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
RTC_BAT
JP6 CONFIG 1 -2 2-3 NORMAL CLEAR CMOS
INTEL CORPORATION P L A TFORM COMPONENTS DIVISION 1 9 0 0 P R A IRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title 82371EB (PART II) Size Custom Date:
A B C D 1
1
2
Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998
E
Rev 1.0 Sheet 18 of 40
A
B
C
D
E
IOAPIC
4
VCC
4
19
51
U34 7 P C L K APIC 7 A P I C C LK 33 CRESET 18,34 A P I C CS# 18 9 1 7 , 24,27,35 1 7 , 24,27,35 A P I C A CK# WSC# MEMR# MEMW# 2 62 60 61 10 8 12 11 13 14 15 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 A P C _I8 17 34 35 25 26 27 28 29 31 30 24 23 22 16 18 21 37 38 39 40 41 42 43 44 3 CLK A P I C C LK RESET CSA P I C A C K1A P I C A C K2RDWRA0 A1 D/IINTIN0 INTIN1 INTIN2 INTIN3 INTIN4 INTIN5 INTIN6 INTIN7 INTIN8 INTIN9 INTIN10 INTIN11 INTIN12 INTIN13 INTIN14 INTIN15 INTIN16 INTIN17 INTIN18 INTIN19 INTIN20 INTIN21 INTIN22 INTIN23 T E S T IN82093AA 4.7K 33 C R S T_STBY 3 V SB 1
VCC
VCC
V C C PINS : 19, 51, 64
APICREQSMIOUTNC NC NC NC NC NC NC NC NC NC APICD0 APICD1 9 6 7 20 32 36 45 46 47 48 49 63 4 5 1 PX4_SMI# 3 A P I C R EQ# 18,34 A P C_SMI# 34 JP18 2 H S M I# 3 , 5
VCC
64
1 7 , 2 0,24,27,35,39 S A 0 1 7 , 2 0,24,27,35,39 S A 1 1 7 , 20,24,27,35 S A 4
3
82093AA
**NOTE** JP18 is used for validation purposes and will not be necessary on production boards.
3
JP19 1 -2 3 -4
SMI SOURCE APIC SMI PIIX4 SMI
P I C D0 3 , 5,34 P I C D1 3 , 5,34 X D [ 7:0] 2 0 ,27,39
1 8 ,33,34 P X 4_INTR 1 8 ,20,24,35 I R Q [ 7 : 1 ] 18 I R Q 0
1 8 , 20,24,35 1 8 , 20,24,35 1 8 , 20,24,35 1 8 , 20,24,35
IRQ9 I R Q 10 I R Q 11 I R Q 12
1 8 , 20,24,25,35 I R Q 14 1 8 , 20,24,25,35 I R Q 15 1 8 , 21,22,23,34 1 8 , 21,22,23,34 1 8 , 22,23,34 1 8 , 22,23,34 18 P I R Q #A P I R Q#B P I R Q #C P I R Q #D I R Q 9 O UT
D0 D1 D2 D3 D4 D5 D6 D7
59 58 57 56 55 54 53 50
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
VCC
RP1 R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 10
P U _ I21 P U _ I22
GND PINS : 1, 33, 52
2
1
2
PU
18,34 PX4_SMI# P U _ I13 P U _ T S TIN
GND
GND
33
14 18,35 I R Q#8 2 7 3 U13A 74LVC125 A P C _I8
1
52
1
GND
I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title IOAPIC Rev 1.0 19 of 40
1
Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998
A B C D
Sheet
E
1
2
3
4
5
6
7
8
VCC U14 121 122 124 22 68 69 70 80 90 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 72 73 74 75 76 77 78 79 89 D R Q0 D R Q1 D R Q2 D R Q3 D A C K#0 D A C K#1 D A C K#2 D A C K#3 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 B _ IRQ#8 IRQ9 I R Q 10 I R Q 11 I R Q 12 I R Q 14 I R Q 15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 1 1 1 1 1 1 1 1 S I O _PU2 TP080 TP081 TP082 TP083 TP084 TP079 TP078 TP085 82 84 86 88 81 83 85 87 67 66 65 64 63 62 61 59 58 57 56 55 54 41 42 43 44 45 46 47 48 49 50 51 52 53 27 28 29 26 23 24 25 30 31 34 33 32 92 91 94 93 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
D
21 60 101 125 139
A
7 OSC3 1 7 ,24,35,39 I O R # 1 7 ,24,35,39 IOW# 17,24 A E N 17,32 R S T D RV 17,24,35 I O C H R D Y 17,24,35 S D [ 1 5 :0]
V B AT XTAL1 XTAL2 1 4 C LOCKI IOR# IOW# AEN R S T D RV IOCHRDY SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 TC D R Q0 D R Q1 D R Q2 D R Q3 D A C K0 D A C K1 D A C K2 D A C K3 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 I R Q8# IRQ9 I R Q10 I R Q11 I R Q12 I R Q14 I R Q15
14CLK01 14CLK02 14CLK03 16CLK 24CLK INDEX# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# SIDE1# DSKCHG# MTR0# MTR1# DRVSEL0# DRVSEL1# DRVDEN0 DRVDEN1 MEDID0 MEDID1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLIN# INIT# AFD# STB# BUSY ACK# PE SLCT ERR# RXD1 TXD1 RTS1# CTS1# DTR1# DSR1# DCD1# RI1# RXD2 TXD2 RTS2# CTS2# DTR2# DSR2# DCD2# RI2# GP10/IRQIN GP11/IRQIN GP12/IRRX GP13/IRTX GP14/RS GP15/WS GP16/JOYRS GP17/JSWS GP20/IDE2_OE GP21/EEDIN GP22/EDOUT GP23/EECLK GP24/EEEN GP25/8042_P21
37 38 39 36 35 14 9 10 11 12 15 16 17 13 18 4 7 6 5 2 3 20 19 138 137 136 135 134 133 132 131 140 141 143 144 128 129 127 126 142 145 146 148 149 150 147 152 151 155 156 158 159 160 157 154 153 96 97 98 99 100 102 103 104 105 106 107 108 109 110
VCC VCC VCC VCC VCC
TP076 TP077 TP088
1 1 1
TP6 TP7 TP8 INDEX# 29 D I R # 29 STEP# 29 W D ATA# 29 WGATE# 29 TRK0# 29 W P T# 29 R D A TA# 29 S I DE1# 29 D S K C HG# 29 MOTEA# 29 MOTEB# 29 D R V S A# 29 D R V SB# 29 R E D W C # 29 D R ATE0 29
A
R401 R402
1K 1K
Stuff for 93X only
18,24 TC 1 8 ,24,35 D R Q [ 7 : 0]
TP090 I R R 4_MODE P D R0 P D R1 P D R2 P D R3 P D R4 P D R5 P D R6 P D R7
1
TP9
Stuff for 93XFR R403 0
18,24 D A C K # [ 3 :0]
P D R [ 7 : 0] 28
VCC
1 8 , 19,24,35 I R Q [ 7 : 0]
B
R374 10K 1 8 , 19,24,35 1 8 , 19,24,35 1 8 , 19,24,35 1 8 , 19,24,35 1 8 , 19,24,25,35 1 8 , 19,24,25,35 1 7 , 1 9,24,27,35,39 S A [ 1 9:0] IRQ9 I R Q 10 I R Q 11 I R Q 12 I R Q 14 I R Q 15
FDC37C932FR 160 PIN QFP
B
S L I N #R 28 INIT#R 28 A F D # R 28 STB#R 28 B U S Y 28 A C K# 28 PE 28 SLCT 28 E R R# 28 RX0 29 TX0 29 CTS0# 29 DTR0# 29 DSR0# 29 RLSD0# 29 R I 0# 29 RX1 29 TX1 29 RTS1# 29 CTS1# 29 DTR1# 29 DSR1# 29 RLSD1# 29 R I 1# 29 TP092 TP091 I R RX IRTX TP073 TP072 TP087 TP075 R_GP21 TP071 TP070 TP069 1 1 1 1 1 1 1 1 1 TP13 TP15 TP18 TP20 TP22 TP23 KBRST# 18,34 TP24 TP25 TP26 A20GATE 18,34
Config Port Address
VCC 3 7 0 h I / O Decode R404 10K RTS0# 29 R132 1K 3 F 0 h I / O Decode ( D E F A ULT) C18 4 7 0pF VCC
VCC
R133 8.2K
C
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 S A 1 2/CS S A 1 3 / HDCS2# S A 1 4 / HDCS3# S A 1 5 / IDE2_IRQ I D E 1 _IRQ IDE1_OE# H D C S 0# H D C S 1# I O ROP# IOWOP# I D E _A0 I D E _A1 I D E _A2 KCLK K D AT MSCLK MSDAT RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 ROMCS# R O M DIR# F D C 3 7 C932FR_1.3
JP19
C
VCC RP2 1 2 3 4 4 . 7K 30 30 30 30 KBCLK# K B DAT# MSCLK# MSDAT# 8 7 6 5 Stuff for 93XFR
VCC
TP10 TP11 TP12 TP14 TP16
KEY
6 5 4 3 2 1 INFRARED HDR
R405 TP17 0 TP19 TP21
C19 470pF C21 0 . 1 uF
C20 470pF C22 0.1 uF
111 112 113 114 115 116 117 118 119 120
VCC R134 8.2K VSS VSS VSS VSS VSS VSS VSS I N T E L C O R P O RATION P L A T F O R M C O M P O NENTS DIVISION 1 9 0 0 P R A I R I E C I T Y RD. FM5-62 F O L S OM, CA 95630 Title I / O C O N T R O L L E R ( U LTRA I/O) Size Document Number Intel(R) 440BX AGPset Custom D a t e : Thursday, April 09, 1998 Sheet 20
8 D
1 9 ,27,39 X D [ 7:0] 18 XOE# 18 X D IR#
Stuff for 93XFR
R406 1K
1 8 40 71 95 123 130
ULTRA I/O
1 2 3 4 5 6
Rev 1.0 of 40
7
A
B
C
D
E
AGP CONNECTOR
VCC3 VCC3
9 SBA[7:0] 9 ST[2:0]
4
VCC3 26 AGP_OC# R136 4.7K
J8 VCC
+12V
VCC3
4
B1 B2 B3
OVRCNT# 5V 5V USB+ GND INTB# CLK REQ# VCC3.3 ST0 ST2 RBF# GND SPARE SBA0 VCC3.3 SBA2 SB_STB GND SBA4 SBA6
12V SPARE RESERVED USBGND INTA# RST# GNT# VCC3.3 ST1 RESERVED PIPE# GND SPARE SBA1 VCC3.3 SBA3 RESERVED GND SBA5 SBA7
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 SBA3 SBA1 ST1
R135 4.7K
26 USBAGP+ U15C 6 74AS07
B4 B5
USBAGP- 26 PIRQ3#A 3 U15B 4 74AS07 PIRQ#A 18,19,22,23,34
18,19,22,23,34 PIRQ#B
5
PIRQ3#B 9 GCLKOUT
B6 B7 B8 B9 ST0 ST2 B10 B11 B12 B13 B14 SBA0 B15 B16 SBA2 B17 B18 B19
PCIRST# 8,17,22,23 GGNT# 9,34
9,34 GREQ#
9,34 RBF#
PIPE# 9,34
9,34 SBSTB
3
SBA4 SBA6
B20 B21
3
SBA5 SBA7
GAD31 GAD29
B26 B27 B28
AD31 AD29 VCC3.3 AD27 AD25 GND AD_STB1 AD23 Vddq3.3 AD21 AD19 GND AD17 C/BE2# Vddq3.3 IRDY# SPARE GND SPARE VCC3.3 DEVSEL# Vddq3.3 PERR# GND SERR# C/BE1# Vddq3.3 AD14 AD12 GND AD10 AD8 Vddq3.3 AD_STB0 AD7 GND AD5 AD3 Vddq3.3 AD1 RESERVED
AD30 AD28 VCC3.3 AD26 AD24 GND RESERVED GC/BE3# Vddq3.3 AD22 AD20 GND AD18 AD16 Vddq3.3 FRAME# SPARE GND SPARE VCC3.3 TRDY# STOP# PME# GND PAR AD15 Vddq3.3 AD13 AD11 GND AD9 C/BE0# Vddq3.3 RESERVED AD6 GND AD4 AD2 Vddq3.3 AD0 RESERVED
A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
GAD30 GAD28
GAD27 GAD25
B29 B30 B31
GAD26 GAD24
9,34 ADSTB-B GAD23
B32 B33 B34 GAD21 GAD19 B35 B36 B37 GAD17 GC/BE#2 B38 B39 B40
GC/BE#3
GAD22 GAD20
GAD18 GAD16
2
9,34 GIRDY#
B41 B42 B43 B44 B45
GFRAME# 9,34
2
9,34 GDEVSEL#