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XG-V10WU
XG-V10WE
TECHNICAL MANUAL
TX0L1XG-V10WU
LCD PROJECTOR
XG-V10WU
MODELS XG-V10WE
CONTENTS
Page Page
1. CVIC INTERNAL BLOCK DIAGRAM ........................... 2 3-5. TLC5733A ............................................................ 29
2. CONNECTION BETWEEN CVIC AND SDRAM ........... 4 3-5-1. Outline ........................................................... 29
2-1. SDRAM (HY57V653220B-TC7) ............................. 6 3-5-2. Internal block diagram ................................... 29
2-1-1. Description ...................................................... 6 3-5-3. Pin layout ...................................................... 29
2-1-2. Features .......................................................... 6 3-5-4. Pin description .............................................. 30
2-1-3. Pin layout ........................................................ 7 3-5-5. Timing ........................................................... 31
2-1-4. Pin description ................................................ 7 3-5-6. V1 line system ............................................... 31
3. INPUT WIRING DIAGRAM AND ROUTE DIAGRAM ... 8 4. IX3399 PERIPHERAL IC WIRING DIAGRAM ............ 33
3-1. IX3434CE (Input section) ..................................... 13 4-1. I/O waveform ........................................................ 34
3-1-1. Outline ........................................................... 13 4-2. Block diagram ...................................................... 36
3-1-2. Internal block diagram ................................... 13 4-3. Pin layout ............................................................. 38
3-1-3. Pin description .............................................. 14 4-4. Pin description ..................................................... 39
3-1-4. Selection of sync signal per input ................. 15 4-5. Color irregularity correction .................................. 42
3-2. CXA3516R ........................................................... 15 5. D/A PERIPHERAL IC WIRING DIAGRAM ................. 46
3-2-1. Outline ........................................................... 15 5-1. D/A data I/O waveform ......................................... 47
3-2-2. Internal block diagram ................................... 15 5-2. D/A pin layout ....................................................... 47
3-2-3. Pin layout ...................................................... 16 5-3. D/A block diagram ................................................ 48
3-2-4. Pin description .............................................. 17 5-4. D/A pin description and I/O pin equivalent circuit 49
3-2-5. Outline of internal function blocks ................. 19 6. POWER CONTROL .................................................... 50
3-2-6. Timing chart when CXA3516R and 6-1. Description of Main-/Sub-microprcessor .............. 51
IX3434CE are connected .............................. 22 6-1-1. Main-microprocessor IC8001 (IX3270CE) pin layout ....... 51
3-3. SiI151 ................................................................... 23 6-1-2. Main-microprocessor IC8001 (IX3270CE) block diagram 52
3-3-1. Outline ........................................................... 23 6-1-3. Sub-microprocessor IC2601 (IX3502CE) pin layout ........ 53
3-3-2. Internal block diagram ................................... 23 6-1-4. Sub-microprocessor IC2601 (IX3502CE) block diagram . 54
3-3-3. Pin layout ...................................................... 24 6-2. Data transmission system between
3-3-4. Pin description .............................................. 25 main-microprocessor and sub-microprocessor .... 55
3-3-5. Timing ........................................................... 26 6-3. Simple check of RS-232C OUT port .................... 60
3-3-6. Power mode .................................................. 27 6-4. Key entry detection .............................................. 60
3-3-7. SiI151 timing chart ........................................ 27 6-5. Detection of remote controller operation .............. 60
3-4. TLC2933 .............................................................. 28 6-6. Temperature detection ......................................... 60
3-4-1. Outline ........................................................... 28 6-7. Detection of cooling fan rotation .......................... 61
3-4-2. Internal block diagram ................................... 28 6-8. Checking internal temperature and fan rotation all at once ..... 61
3-4-3. Pin layout ...................................................... 28 6-9. Appendix on power supply ................................... 61
3-4-4. Pin description .............................................. 28
This Technical Manual is now prepared to help servicing the
LCD Projector equipped models, and its descriptions are lim-
ited only to "Description of New Circuit" etc.
For more understanding of each model, refer to its respective
Service Manual already issued.
(This Technical Manual is based on Models XG-V10WU and
XG-V10WE.)
SHARP CORPORATION
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XG-V10WU
XG-V10WE
1. CVIC INTERNAL BLOCK DIAGRAM
Fig. 1 shows the data flow inside of the CVIC.
External I/O
Video Video
input output
Video Image Display
input processor output
controller module controller
Internal bus
External
SDRAM
bus CPU controller
controller
External CPU, SDRAM
etc.
Figure 1.
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Video input controller
Video data entrance to CVIC, which performs the following processing.
Conversion of the received video data into CVIC's internal data structure.
Storage of the converted video data into video buffer memory (SDRAM).
Collecting data to detect resolution or refresh rate of the received video data.
Collecting data for automatic synchronization.
Display output controller
Video data exit from CVIC.
External output of the video data read out from the video buffer memory (SDRAM) at the preset timing.
Conversion of the CVIC data structure into the one suitable for external use.
Gamma correction.
Overlapping OSD (On Screen Display) onto the video data.
In the OSD overlapping, any transparency can be set arbitrarily out of 256 grades.
External bus controller
Connecting unit between CVIC and external microprocessor or ROM.
Data interchange with 16-bit width.
External microprocessor or ROM can access the SDRAM data to read/write them.
Video buffer memory (SDRAM) data in CVIC can be read/written.
OSD buffer memory (SDRAM) data can be read/written.
External microprocessor or ROM can communicate with internal CPU of CVIC via the 32-bit width register.
Transfer of the program for CVIC, as well as the bit map data and the font data for OSD.
CPU
Executes the programs in SDRAM and controls each block (module) inside of CVIC.
SDRAM controller
Connecting unit between CVIC and external SDRAM.
Data input/output with 128-bit width data bus.
Operational clock frequency is 100MHz.
Image processor module
Video data converting unit.
IP conversion, enlarge/reduce of the video data, and filtering are performed.
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2. CONNECTION BETWEEN CVIC AND SDRAM
CVIC and SDRAM are connected in 128-bit data width as shown in the figure below.
SDRAM
CVIC
IC8319
IC8025
IC8320
IC8321
IC8322
Figure 2-1.
The following signals coming out from CVIC are common for each SDRAM: CLK, XCS, XRAS, XCAS, XWE,
SD_BA0, SD_BA1, and SDA0 to SDA10.
The data bus (SDD0 ~ SDD127) is allocated to the four SDRAMs in every 32 bits.
Due to CVIC's internal data structure, DQM0 ~ DQM7 is allocated irregularly as shown in the figure below.
MSB LSB
Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit 127-120 119-112 111-104 103-96 95-88 87-80 79-72 71-64 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0
DQM DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 DQM1 DQM0
Pixel 119-96 95-72 71-48 47-24 23-0
32-bit access 127-96 95-64 63-32 31-0
Figure 2-2.
CKE is tied to the high level (3.3V).
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The connection with each SDRAM is shown in the figures below.
The numerals in each SDRAM box designate the pin numbers.
Between CVIC and IC8319 Between CVIC and IC8321
CVIC CLK CLK 68 SDRAM CVIC CLK CLK 68 SDRAM
IC8025 XCS /CS 20 IC8319 IC8025 XCS /CS 20 IC8321
XRAS /RAS 19 XRAS /RAS 19
XCAS /CAS 18 XCAS /CAS 18
XWE /WE 17 XWE /WE 17
SD_BA0 BA0 22 SD_BA0 BA0 22
SD_BA1 BA1 23 SD_BA1 BA1 23
SDA0 ~ SDA10 A0 ~ A10 SDA0 ~ SDA10 A0 ~ A10
DQM0 DQM0 16 DQM2 DQM0 16
DQM1 71 DQM1 71
DQM2 28 DQM3 DQM2 28
DQM1 DQM3 59 DQM3 59
SDD0 ~ SDD31 DQ0 ~ DQ31 SDD32 ~ SDD63 DQ0 ~ DQ31
Figure 2-3. Figure 2-4.
Between CVIC and IC8320 Between CVIC and IC8322
CVIC CLK CLK 68 SDRAM CVIC CLK CLK 68 SDRAM
IC8025 XCS /CS 20 IC8320 IC8025 XCS /CS 20 IC8322
XRAS /RAS 19 XRAS /RAS 19
XCAS /CAS 18 XCAS /CAS 18
XWE /WE 17 XWE /WE 17
SD_BA0 BA0 22 SD_BA0 BA0 22
SD_BA1 BA1 23 SD_BA1 BA1 23
SDA0 ~ SDA10 A0 ~ A10 SDA0 ~ SDA10 A0 ~ A10
DQM4 DQM0 16 DQM6 DQM0 16
DQM5 DQM1 71 DQM1 71
DQM2 28 DQM2 28
DQM3 59 DQM7 DQM3 59
SDD64 ~ SDD95 DQ0 ~ DQ31 SDD96 ~ SDD127 DQ0 ~ DQ31
Figure 2-5. Figure 2-6.
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2-1. SDRAM (HY57V653220B-TC7)
2-1-1. Description
The HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which
require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1, 2, 4, 8 or full page), and the burst count sequence
(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command
or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not
restricted by a `2N` rule.)
2-1-2. Features
» JEDEC standard 3.3V power supply
» All device pins are compatible with LVTTL interface
» JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch
» All inputs and outputs referenced to positive edge of system clock
» Data mask function by DQM0, 1, 2 and 3
» Internal four banks operation
» Auto refresh and self refresh
» 4096 refresh cycles / 64ms
» Programmable Burst Length and Burst Type
-1, 2, 4, 8 or full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
» Programmable CAS Latency; 2, 3 Clocks
» Burst Read Single Write operation
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2-1-3. Pin layout
VDD 1 86 VSS
DQ0 2 85 DQ15
VDDQ 3 84 VSSQ
DQ1 4 83 DQ14
DQ2 5 82 DQ13
VSSQ 6 81 VDDQ
DQ3 7 80 DQ12
DQ4 8 79 DQ11
VDDQ 9 78 VSSQ
DQ5 10 77 DQ10
DQ6 11 76 DQ9
VSSQ 12 75 VDDQ
DQ7 13 74 DQ8
NC 14 73 NC
VDD 15 72 VSS
DQM0 16 71 DQM1
/WE 17 70 NC
/CAS 18 69 NC
/RAS 19 68 CLK
/CS 20 86pin TSOP II 67 CKE
NC 21 66 A9
BA0 22 400mil x 875mil 65 A8
BA1 23 0.5mm pin pitch 64 A7
A10/AP 24 63 A6
A0 25 62 A5
A1 26 61 A4
A2 27 60 A3
DQM2 28 59 DQM3
VDD 29 58 VSS
NC 30 57 NC
DQ16 31 56 DQ31
VSSQ 32 55 VDDQ
DQ17 33 54 DQ30
DQ18 34 53 DQ29
VDDQ 35 52 VSSQ
DQ19 36 51 DQ28
DQ20 37 50 DQ27
VSSQ 38 49 VDDQ
DQ21 39 48 DQ26
DQ22 40 47 DQ25
VDDQ 41 46 VSSQ
DQ23 42 45 DQ24
VDD 43 44 VSS
Figure 2-7.
2-1-4. Pin description
Pin Pin Name Description
CLK Clock The system clockinput. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh
/CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address Selects bank to be activated during / RAS activity
Selects bank to be read/written during /CAS activity
A0~A10 Address Row Address: RA0 ~ RA10, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
/RAS, /CAS, /WE Row Address Strobe /RAS, /CAS and /VVE define the operation
Column Address Strobe Refer function truth table for details
Write Enable
DQM0 ~ 3 Data Input/Output Mask Controls output buffers in read mode and masks input data in
write mode
DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Remarks: CKE is tied to the high level (3.3V).
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3. INPUT WIRING DIAGRAM AND ROUTE DIAGRAM
» Wiring diagram
IC8334, IC8335, IC8025
Noise filter, IC8336, IC8337
Peak clamp for IX3434CE
Sync On Green
IC8004
CX3516R
IC8325 HOLD RA0 RA7
P8012 G(Analog) EVEN/ODD GA0 GA7
1C0 SYNCIN1
1C1 1Y SYNCIN2
BA0 BA7
R(Analog) RB0 RB7
CLPIN GB0 GB7
G(Analog) G/YIN1 BB0 BB7
B(Analog) B/CbIN1
R/CrIN1 1/2CLK V0_RA[8]
G/YIN2 V0_GA[8]
R(Video) DSYNC/DIVOUT V0_BA[8]
B/CbIN2
G(Video) R/CrIN2 V0_RB[8]
B(Video) V0_GB[8]
IC8302 V0_BB[8]
1C0 V0_ACT
1C1 V0_VAL V0 lines
IH_CON V0_HSYNC
1C2 1Y
1C3 V0_VSYNC
2C0 V0_CSYNC
2C1 V0_GSYNC
IV_CON 2Y V0_HSYNC2
2C2
2C3 V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
CSYNC V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
SiI151 IC8298 V0_PADRST/NADRST[ECL]
DVI_RO V0_PDEN
RX2+
DVI_GO C1 2
RX2-
V0_HSYNF
C2 1 V0_HSYNR
DVI_BO 10 RX1+ QE23-QE0
C3 V0_CLP
9 RX1- QO23-QO0
IC8331 V1_RA[8]
18 RX0+ ODCK V1_GA[8]
6 3 C4 17 RX0- DE
V1_BA[8]
23 RXC+ HSYNC V1_RB[8]
IC8330 24 RXC- VSYNC
V1_GB[8]
6 3 8 V1_BB[8]
V1_ACT
V1_VAL V1 lines
P8001
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
IC8328 V1_HSYNC2
VH_IN V1_PVCLK/NVCLK[ECL]
TLC2933 V1_PVDCLK/NVDCLK[ECL]
VV_IN
VCO_OUT V1_VDCLK_I[TTL]
FIN_A V1_VDCLK_O[TTL]
FIN_B V1_PADCLK/NADCLK[ECL]
IC8323, PFD_INHIBIT V1_PADRST/NADRST[ECL]
IC8324, IC8000 V1_PDEN
IC8326 V1_HSYNF
TLC5733A V1_HSYNR
AIN V1_CLP
Clamp AD1-8
BIN BD1-8
circuit CIN CD1-8
EN1 CLK
Figure 3-1.
IX3434CE (Input section)
Sync detect, clock control, color space conversion, data structure conversion, and auto sync adjustment.
CXA3516R
3ch 8-bit 165MSPS A/D converter with built-in amplifier and PLL.
SiI151
Receiver for DVI digital input
TLC2933
PLL for V1 lines
TLC5733A
3ch 8-bit A/D converter (for component/composite signals of 480I/580I)
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* V0 lines are connected to CXA3516R and SiI151, while V1 lines to TLC2933 and TLC5733A.
» Route diagram
(a) NTSC, PAL, 480I/580I
IC8334, IC8335,
component signal input Noise filter, IC8336, IC8337
IC8025 CVIC (VIC section)
IX3434CE
Peak clamp for
Sync On Green
IC8004
CX3516R
IC8325 HOLD RA0 RA7
P8012 G(Analog) EVEN/ODD GA0 GA7
1C0 SYNCIN1
1C1 1Y SYNCIN2
BA0 BA7
R(Analog) RB0 RB7
CLPIN GB0 GB7
G(Analog) G/YIN1 BB0 BB7
B(Analog) B/CbIN1
R/CrIN1 1/2CLK V0_RA[8]
G/YIN2 V0_GA[8]
R(Video) DSYNC/DIVOUT V0_BA[8]
B/CbIN2
G(Video) R/CrIN2 V0_RB[8]
B(Video) V0_GB[8]
IC8302 V0_BB[8]
1C0 V0_ACT
1C1 V0_VAL V0 lines
IH_CON V0_HSYNC
1C2 1Y
1C3 V0_VSYNC
2C0 V0_CSYNC
2C1 V0_GSYNC
IV_CON 2Y V0_HSYNC2
2C2
2C3 V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
CSYNC V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
Sil151 IC8298 V0_PADRST/NADRST[ECL]
DVI_RO V0_PDEN
RX2+
DVI_GO C1 2
RX2-
V0_HSYNF
C2 1 V0_HSYNR
DVI_BO 10 RX1+ QE23-QE0
C3 V0_CLP
9 RX1- QO23-QO0
IC8331 V1_RA[8]
18 RX0+ ODCK V1_GA[8]
6 3 C4 17 RX0- DE
V1_BA[8]
23 RXC+ HSYNC V1_RB[8]
IC8330 24 RXC- VSYNC
V1_GB[8]
6 3 8 V1_BB[8]
V1_ACT
V1_VAL V1 lines
P8001
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
IC8328 V1_HSYNC2
VH_IN V1_PVCLK/NVCLK[ECL]
TLC2933 V1_PVDCLK/NVDCLK[ECL]
VV_IN
VCO_OUT V1_VDCLK_I[TTL]
FIN_A V1_VDCLK_O[TTL]
FIN_B V1_PADCLK/NADCLK[ECL]
IC8323, PFD_INHIBIT V1_PADRST/NADRST[ECL]
IC8324, IC8000 V1_PDEN
IC8326 V1_HSYNF
TLC5733A V1_HSYNR
R(VIDEO) AIN V1_CLP
Clamp AD1-8
G(VIDEO) BIN BD1-8
circuit CIN CD1-8
B(VIDEO)
EN1 CLK
Figure 3-2.
(b) DVI digital signal input IC8334, IC8335, IC8025 CVIC (VIC section)
Noise filter, IC8336, IC8337
Peak clamp for IX3434CE
Sync On Green
IC8004
CX3516R
IC8325 HOLD RA0 RA7
P8012 G(Analog) EVEN/ODD GA0 GA7
1C0 SYNCIN1
1C1 1Y SYNCIN2
BA0 BA7
R(Analog) RB0 RB7
CLPIN GB0 GB7
G(Analog) G/YIN1 BB0 BB7
B(Analog) B/CbIN1
R/CrIN1 1/2CLK V0_RA[8]
G/YIN2 V0_GA[8]
DSYNC/DIVOUT V0_BA[8]
B/CbIN2
R/CrIN2 V0_RB[8]
V0_GB[8]
IC8302 V0_BB[8]
1C0 V0_ACT
1C1 V0_VAL V0 lines
IH_CON V0_HSYNC
1C2 1Y
1C3 V0_VSYNC
2C0 V0_CSYNC
2C1 V0_GSYNC
IV_CON 2Y V0_HSYNC2
2C2
2C3 V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
CSYNC V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
Sil151 IC8298 V0_PADRST/NADRST[ECL]
DVI_RO V0_PDEN
RX2+
DVI_GO C1 2
RX2-
V0_HSYNF
C2 1 V0_HSYNR
DVI_BO 10 RX1+ QE23-QE0
C3 V0_CLP
9 RX1- QO23-QO0
IC8331 V1_RA[8]
18 RX0+ ODCK V1_GA[8]
6 3 C4 17 RX0- DE
V1_BA[8]
23 RXC+ HSYNC V1_RB[8]
IC8330 24 RXC- VSYNC
V1_GB[8]
6 3 8 V1_BB[8]
V1_ACT
V1_VAL V1 lines
P8001
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
IC8328 V1_HSYNC2
VH_IN V1_PVCLK/NVCLK[ECL]
TLC2933 V1_PVDCLK/NVDCLK[ECL]
VV_IN
VCO_OUT V1_VDCLK_I[TTL]
FIN_A V1_VDCLK_O[TTL]
FIN_B V1_PADCLK/NADCLK[ECL]
IC8323, PFD_INHIBIT V1_PADRST/NADRST[ECL]
IC8324, IC8000 V1_PDEN
IC8326 V1_HSYNF
TLC5733A V1_HSYNR
R(VIDEO) AIN V1_CLP
Clamp AD1-8
G(VIDEO) BIN BD1-8
circuit CIN CD1-8
B(VIDEO)
EN1 CLK
Figure 3-3.
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(c) DVI analog signal input IC8334, IC8335, IC8025 CVIC (VIC section)
Noise filter, IC8336, IC8337
Peak clamp for IX3434CE
Sync On Green
IC8004
CX3516R
IC8325 HOLD RA0 RA7
P8012 G(Analog) EVEN/ODD GA0 GA7
1C0 SYNCIN1
1C1 1Y SYNCIN2
BA0 BA7
R(Analog) RB0 RB7
CLPIN GB0 GB7
G(Analog) G/YIN1 BB0 BB7
B(Analog) B/CbIN1
R/CrIN1 1/2CLK V0_RA[8]
G/YIN2 V0_GA[8]
R(Video) DSYNC/DIVOUT V0_BA[8]
B/CbIN2
G(Video) R/CrIN2 V0_RB[8]
B(Video) V0_GB[8]
IC8302 V0_BB[8]
1C0 V0_ACT
1C1 V0_VAL V0 lines
IH_CON V0_HSYNC
1C2 1Y
1C3 V0_VSYNC
2C0 V0_CSYNC
2C1 V0_GSYNC
IV_CON 2Y V0_HSYNC2
2C2
2C3 V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
CSYNC V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
Sil151 IC8298 V0_PADRST/NADRST[ECL]
DVI_RO V0_PDEN
RX2+
DVI_GO C1 2
RX2-
V0_HSYNF
C2 1 V0_HSYNR
DVI_BO 10 RX1+ QE23-QE0
C3 V0_CLP
9 RX1- QO23-QO0
IC8331 V1_RA[8]
18 RX0+ ODCK V1_GA[8]
6 3 C4 17 RX0- DE
V1_BA[8]
23 RXC+ HSYNC V1_RB[8]
IC8330 24 RXC- VSYNC
V1_GB[8]
6 3 8 V1_BB[8]
V1_ACT
V1_VAL V1 lines
P8001
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
IC8328 V1_HSYNC2
VH_IN V1_PVCLK/NVCLK[ECL]
TLC2933 V1_PVDCLK/NVDCLK[ECL]
VV_IN
VCO_OUT V1_VDCLK_I[TTL]
FIN_A V1_VDCLK_O[TTL]
FIN_B V1_PADCLK/NADCLK[ECL]
IC8323, PFD_INHIBIT V1_PADRST/NADRST[ECL]
IC8324, IC8000 V1_PDEN
IC8326 V1_HSYNF