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harman/kardon
Service Manual
HK 990/230
2 x 200W INTEGRATED STEREO AMPLIFIER
Released EU2009
harman/kardon, Inc. 250 Crossways Park Dr. Woodbury, New York, 11797
Rev 0, 03/2009
Specifications
Continuous Average Power Per Channel (FTC) 20 Hz 20 kHz, both channels driven Dynamic Power (IHF, 1 kHz Tone Burst) High instantaneous current capability (HCC) Power Bandwidth @ Half-Rated output, 8 Frequency response @ 1W (+0/-3dB) Damping factor (20Hz-20k Hz) Signal-to-noise Ratio (Reference rated power output, A-WTD) Input sensitivity/Impedance 8 Ohms: 4 Ohms: 8 Ohms: 4 Ohms: NOMINAL 150 Watts@<0.03%THD 300 Watts@<0.3%THD 220 Watts 440 Watts ±200 Amps 20 Hz - 100 kHz 5 Hz - 120 kHz >200 100 dB 75 dB 350 mV/43k Ohms 10 mV/47k Ohms 1 mV/100 Ohms 2.8V 85 mV 8.5 mV ±10 dB/±10 dB AC 230V, 50 Hz 1000 W 1W 440 x 160 x 444 mm 24 kg
Overload
Tuner/CD Phono (MC): Tuner/CD Phono (MM): Phono (MC): Tuner/CD Phono (MM): Phono (MC):
Tone control range, Bass @ 100 Hz/Treble @ 10 kHz Power supply Power consumption Standby power consumption Dimensions (Width x Height x Depth) Depth includes Volume Button and Loudspeaker Terminals Weight
250 Crossways Park Drive, Woodbury, New York 11797 www.harmankardon.com Harman Consumer Group International: 2, Route de Tours, 72500 Château-du-Loir, France © 2008 Harman Kardon, Incorporated Part no. 8509 9012 0000
1
Controls and Functions
Power Indicator: This LED will illuminate in amber when the unit is in the Standby mode to signal that the unit is ready to be turned on. When the unit is in operation, the indicator will turn white. System Power Control: Press this button to turn on the HK 990; press it again to turn the unit off (to Standby). Entering Standby also saves all Setup parameters. Speaker 1/2 Selectors: Press to select speaker pair 1 or 2, or both, or neither (headphone output only). Record Out Selector: First press shows the record source presently selected in the display. Pressing on the the Source selectors within a few seconds after pressing changes the record source. Exit this function by pressing again, or wait for a few seconds until exit takes place automatically.
Input Source Selector: Select input source for listening by pressing one of the "Source" buttons repeatedly to scroll through all the Inputs either forwards or backwards, until the display shows the desired source. Input Setup Button: Press this Button to enter/exit the Input Setup Mode. Here you can select the physical connection for each source (Analog/Digital etc.) as well as Gain, Bass/Treble etc. Refer to the Setup section of this manual. Speaker Setup Selector: Press this Button to enter the Speaker Setup Menu, where you can switch subwoofers on and off, select crossover frequency, run automatic speaker setup (EzSet/EQ) etc. Refer to the Setup section of this manual. Up/Down Arrow Buttons: Press to scroll through various options for adjustment in a menu. Left/Right Arrow Buttons: Press to increase/decrease a parameter or to select between parameters after selecting a menu for adjustment with the Up/Down Arrow Buttons.
Level Settings Button: Press to enter/exit the Balance left/right adjustment for the speakers as well as subwoofer level. Headphone Jack/Setup Microphone Input: Plug in headphones if desired. With both "Speaker 1" and "2" selectors in the Off position, output is supplied only to headphones. When using the automatic loudspeaker setup and calibration system (EzSet/EQ), plug the microphone in here. Volume Control: Turn to raise or lower output volume. Remote Sensor Window: The sensor behind this window receives infrared signals from the remote control. Aim the remote at this area and do not block or cover it unless an external remote sensor is installed. Enter Button: Press to select a parameter for adjustment and to confirm. Main Information Display: This display delivers messages and status indications to help you operate the amplifier.
CONTROLS AND FUNCTIONS
2
Connections
Right Loudspeaker output, System 2. Right Loudspeaker output, System 1. RS-232 connector for possible future PC update. Update Switch. Input jacks for one or two subwoofer signals from external surround processor. Output jacks for two subwoofers. Digital coaxial output jack for digital recording. Also permits digital recording of analog sources. Preamplifier output jacks. Analog output jacks for tape recording. Analog output jacks for CD Recorder analog recording. AUX input jacks, suitable for analog signals from video games, video recorders etc. TV input jacks for analog sound input from your TV. TAPE input jacks for analog tape replay. CDR input jacks, for CD Recorder analog replay. Balanced analog inputs (XLR), for use with all signal sources that output balanced signals. Available via the CD Input function only, as an alternative to the unbalanced RCA jacks (Input ). Pin configuration for the XLR Inputs: Pin 1 is Ground, Pin 2 is Plus/Hot, Pin 3 is Minus/Cold.
Left Loudspeaker output, System 2. Left Loudspeaker output, System 1. Power lead AC input. TUNER analog Input jacks. PROCESSOR Analog Inputs. These Inputs go directly to the power amplifier section of the HK 990, bypassing the Volume and Tone Control. Here you can connect the Front Channel Pre Out L+R signals from an external surround processor, to benefit from the superior power of the HK 990 and control volume from the processor. NOTE: Only use the Processor Input with a device that has its own volume control! CD analog Input jacks. You can select either this Input or the Balanced Input as analog Input in the CD Input Setup Mode. Phono Input for record player with Moving Magnet (high output and high impedance) or High-Output Moving Coil cartridge. Phono Input for record player with Moving Coil (low output and low impedance) cartridge. If your record player has a separate Ground wire, attach it here to avoid hum noise.
Connect the trigger Input (if available) on one or two subwoofers to these trigger ON/ OFF output jacks. When you switch ON the HK 990, it sends a trigger signal, which switches ON the subwoofer. When switching OFF the HK 990, the subwoofer also switches OFF. HRS (High-Resolution Synchronization) Input. Use the included HRS-cable to connect the HD 990 CD player (or other similarly equipped player) for optimum sound quality. Optical Digital Inputs (TOS-Link). Connect any digital device with Optical Digital Output to one of these Inputs. Push the Optical Jack through the hinged door that covers the Input until it clicks into place. Coaxial Digital Inputs. Connect any digital device with Coaxial Digital Output to one of these Inputs. Usually, Coaxial Digital transmission is preferred to Optical, given a choice. Remote IN. To control your HK 990 with an external infrared remote sensor, connect the wire from the remote sensor here. Remote OUT. Connect other Harman Kardon devices (you may also experiment with other brands) that you wish to control with the HK 990 Remote Control to this Output.
CONNECTIONS
3
Remote Control
Band: Switches between frequency bands on a Tuner. FM Mode: Switches between Stereo and Mono on a Tuner. Auto: Switches between Automatic and Manual tuning on a Tuner. Mem: For memorizing a radio station in the Preset Memory of a Tuner. Clear: Clears the memory of a CD/CDR or clears a preset from Tuner station list. Check: Press this button to check the order of tracks programmed into a CD player's memory. Prog: Press this button to begin the process of programming a CD player to play the tracks of a disc in a specific order. Speaker Setup: Press to enter the HK 990 Speaker Setup functions. See below for explanation of the Speaker Setup process. Input Setup: Press to enter the HK 990 Input Setup functions. See below for explanation of the Input Setup process. Arrow Buttons ( ): This round button is used to navigate within the menus of the HK 990. EQ Preset: Press to enter the HK 990 Equalizer Preset functions. See below for explanation of the EQ Presets. Level Settings: Press to enter the HK 990 Level Setting functions. See below for explanation of the Level Setting process. Enter: Press to confirm a selection within a HK 990 setup procedure or to switch between selections. See under each Setup process for further explanations. Scroll : When listening to a Tuner, press + to tune to higher frequency stations and to tune to lower frequency stations. Also see the Owners Manual for your harman/kardon tuner. Volume : Press to adjust the HK 990 volume up or down. Select: When listening to a tuner, press this button to alternate between Auto Tune, Manual Tune or Preset Tune. Pause: When playing a CD, press this button to momentarily pause the disc. Press again to resume play. Mute: Press this button to momentarily silence the HK 990. "Muted" flashes in the front panel display. Press again to re-activate sound output. and (Search Buttons): Press one of these buttons to search fast forward or backward on a CD or Tape. You can hear intermittent sounds from the CD while searching. Normal playback resumes when you release the button. and (Skip Buttons): Press one of these buttons to move to the next track or to the previous track on a CD or Tape. Repeatedly pressing one of the buttons skips more tracks. On a CD, pressing Skip Forward while playing the last track skips to track 1, and pressing Skip Back while playing track 1 skips to the last track. Stop: Press this button to stop play of a CD or Tape. Play: Press this button to start playback of a CD or Tape. If the CD drawer is open, the drawer closes and play begins. Pressing the Play Button again pauses play momentarily, same as the Pause Button. 10 and 10: When playing a CD, press the +10 Button to skip 10 tracks forward and the -10 Button to skip 10 tracks backward from the track you are playing. More presses again skips 10 more tracks. If there are less than 10 tracks to the end or start of the CD, the last or first track is played. Folder and Folder : When playing a CD with MP3 files, these buttons move to the next or the previous folder with MP3 material. Repeat: When playing a CD, pressing this button once repeats the current track, shown as "Rep 1" in the CD player's display. Pressing once more repeats the entire CD, shown as "Rep All" in the CD player's display. Third press exits repeat play. Repeat A-B: When playing a CD, press once to establish a starting point (shown as "Rep A" in the CD player's display) and a second time to establish an end point (shown as Rep A-B in the CD player's display). The music between these two points is repeated as a loop until you press the button a third time, returning to normal play. Open/Close: Opens the CD drawer when it is closed and closes it when it is open. The drawer may also be closed by pressing Play. Random: When playing a CD, press this button to play all tracks in random order.
REMOTE CONTROL
4
AMP Adjustment Iding Adjustment Precaution for handling measuring instrument The ground side of the measuring instrument to be connected to the speaker terminal of this unit must be kept in floating condition because this unit is equiped with the floating balanced power amplifier. Condition * Start adjustment 5 minutes or more after the power is turned on. * Non loaded condition. Idling Adjustment Adjust R53 so that the DC voltage of TP1 becomes +38mV .
R53
TP1
5
6
a
High Performance Multibit - DAC with SACD Playback AD1955ARS
FUNCTIONAL BLOCK DIAGRAM
MASTER CLOCK INPUT CONTROL DATA INPUT 3 DSD BITSTREAM INPUT 4 DIGITAL SUPPLY
FEATURES 5 V Power Supply Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24-Bit, 192 kHz Sample Rate PCM Audio Data Supports SACD Bit Stream and External Digital Filter Interface Accepts a Wide Range of PCM Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit Sigma-Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACLow Sensitivity to Jitter Supports SACD Playback with "Bit Expansion" Filter Differential Current Output for Optimum Performance 8.64 mA p-p Differential Output 120 dB SNR/DNR (not muted) at 48 kHz Sample Rate (A-Weighted Stereo) 123 dB SNR/DNR (Mono) 110 dB THD + N 110 dB Stop-Band Attenuation with 0.0002 dB Pass-Band Ripple 8 Oversampling Digital Filter On-Chip Clickless Volume Control Supports SACD-Mute Pattern Detection Supports 64 fS/128 fS DSD SACD with Phase Mode Internal Digital Filter Pass-Through for External Filter Master Clock: 256 fS, 512 fS, 768 f S Hardware and Software Controllable Clickless Mute Serial (SPI) Control for Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-Emphasis, Mono Mode Digital De-Emphasis for 32 kHz, 44.1 kHz, and 48 kHz Sample Rates Flexible Serial Data Port with Right-Justified, LeftJustified, I2S, and DSP Modes 28-Lead SSOP Plastic Package APPLICATIONS High End DVD Audio SACD CD Home Theater Systems Automotive Audio Systems Sampling Musical Keyboards Digital Mixing Consoles Digital Audio Effects Processors
AUTO-CLOCK DIVIDER 16-/20-/24-BIT AUDIO DATA/ EXTERNAL DIGITAL FILTER INPUT 3/4 MUX
SPI CONTROL
DSD FILTER
SERIAL DATA INTERFACE
EXTERNAL FILTER I/F
RESET
MUTE DIGITAL FILTER ENGINE S/H ANALOG SUPPLY ZERO FLAGS
NOISE-SHAPED SCRAMBLING
MULTIBIT MODULATOR
I-DAC
I-DAC
VOLTAGE REFERENCE
L-CH R-CH DIFFERENTIAL CURRENT OUTPUT
PRODUCT OVERVIEW
The AD1955 is a complete, high performance, single-chip, stereo digital audio playback system. It is comprised of a multibit sigmadelta modulator, high performance digital interpolation filters, and continuous-time differential current output DACs. Other features include an on-chip clickless stereo attenuator and mute capability, programmed through an SPI compatible serial control port. The AD1955 is fully compatible with all known DVD audio formats including 192 kHz as well as 96 kHz sample frequencies and 24 bits. It is also backward compatible by supporting 50 µs/ 15 µs digital de-emphasis intended for "redbook" compact discs, as well as de-emphasis at 32 kHz and 48 kHz sample rates. The AD1955 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSPs, SACD decoders, external digital filters, AES/EBU receivers, and (continued on page 12)
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
7
AD1955ARS
ABSOLUTE MAXIMUM RATINGS * PACKAGE CHARACTERISTICS
Parameter DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering
Min 0.3 0.3 DGND 0.3 AGND 0.3 0.3
Max 6 6 DVDD + 0.3 AVDD + 0.3 +0.3 (AVDD + 0.3)/2 300 10
Unit V V V V V °C sec
Package (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case])
JA
Typ 109.0 39.0
Unit °C/W °C/W
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1955ARS AD1955ARSRL EVAL-AD1955EB
Temperature 40°C to +85°C 40°C to +85°C
Package Description 28-Lead SSOP 28-Lead SSOP Evaluation Board
Package Option* RS-28 RS-28 on 13" Reels
*RS = Shrink Small Outline Package
PIN CONFIGURATION
DVDD 1 LRCLK/EF_WCLK 2 BCLK/EF_BCLK 3 SDATA/EF_LDATA 4 EF_RDATA 5 DSD_SCLK 6 DSD_LDATA 7
28 DGND 27 MCLK 26 CCLK 25 CLATCH 24 CDATA
TOP VIEW 22 MUTE DSD_RDATA 8 (Not to Scale) 21 ZEROL DSD_PHASE 9 AGND 10 IOUTR+ 11 IOUTR 12 FILTR 13 IREF 14
20 ZEROR 19 AGND 18 IOUTL+ 17 IOUTL 16 FILTB 15 AVDD
AD1955
23 PD/RST
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1955 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
8
Advanced Monolithic Systems
FEATURES
· Three Terminal Adjustable or Fixed Voltages* 1.5V, 1.8V, 2.5V, 2.85V, 3.3V and 5.0V · Output Current of 1A · Operates Down to 1V Dropout · Line Regulation: 0.2% Max. · Load Regulation: 0.4% Max. · SOT-223, TO-252 and SO-8 package available
AMS1117
1A LOW DROPOUT VOLTAGE REGULATOR
APPLICATIONS
· High Efficiency Linear Regulators · Post Regulators for Switching Supplies · 5V to 3.3V Linear Regulator · Battery Chargers · Active SCSI Terminators · Power Management for Notebook · Battery Powered Instrumentation
GENERAL DESCRIPTION
The AMS1117 series of adjustable and fixed voltage regulators are designed to provide 1A output current and to operate down to 1V input-to-output differential. The dropout voltage of the device is guaranteed maximum 1.3V at maximum output current, decreasing at lower load currents. On-chip trimming adjusts the reference voltage to 1%. Current limit is also trimmed, minimizing the stress under overload conditions on both the regulator and power source circuitry. The AMS1117 devices are pin compatible with other three-terminal SCSI regulators and are offered in the low profile surface mount SOT-223 package, in the 8L SOIC package and in the TO-252 (DPAK) plastic package.
ORDERING INFORMATION:
PACKAGE TYPE TO-252 SOT-223 8L SOIC AMS1117CD AMS1117 AMS1117CS AMS1117CD-1.5 AMS1117-1.5 AMS1117CS-1.5 AMS1117CD-1.8 AMS1117-1.8 AMS1117CS-1.8 AMS1117CD-2.5 AMS1117-2.5 AMS1117CS-2.5 AMS1117CD-2.85 AMS1117-2.85 AMS1117CS-2.85 AMS1117CD-3.3 AMS1117-3.3 AMS1117CS-3.3 AMS1117CD-5.0 AMS1117-5.0 AMS1117CS-5.0 *For additional available fixed voltages contact factory.
OPERATING JUNCTION TEMPERATURE RANGE -40 to 125° C -40 to 125° C -40 to 125° C -40 to 125° C -40 to 125° C -40 to 125° C -40 to 125° C
8L SOIC Top View
GND/ADJ VOUT VOUT VIN
1 2 3 4 8 7 6 5
N/C V OUT V OUT N/C
PIN CONNECTIONS
3 PIN FIXED/ADJUSTABLE VERSION
SOT-223 Top View
TO-252 FRONT VIEW 3 2 1
TAB IS OUTPUT
1- Ground/Adjust 2- VOUT 3- VIN
1
2
3
Advanced Monolithic Systems, Inc.
www.advanced-monolithic.com
9
Phone (925) 443-0722
Fax (925) 443-0723
BSS123
N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR Features
· · · · · Low Gate Threshold Voltage Low Input Capacitance Fast Switching Speed Low Input/Output Leakage High Drain-Source Voltage Rating
SOT-23 Dim
A D
NEW PRODUCT
Min 0.37 1.20 2.30 0.89 0.45 1.78 2.80 0.013 0.903 0.45 0.085 0°
Max 0.51 1.40 2.50 1.03 0.60 2.05 3.00 0.10 1.10 0.61 0.180 8°
A B
B C
C D E G H
M
Mechanical Data
· · · · · · · ·
E
G TOP VIEW S D G H K J L
Case: SOT-23, Molded Plastic Case material - UL Flammability Rating 94V-0 Moisture sensitivity: Level 1 per J-STD-020A Terminals: Solderable per MIL-STD-202, Method 208 Terminal Connections: See Diagram Marking: K23 (See Page 3) Ordering & Date Code Information: See Page 3 Weight: 0.008 grams (approx.)
J K L M a
Drain
Gate
All Dimensions in mm
Source
Maximum Ratings
Drain-Source Voltage
@ TA = 25°C unless otherwise specified Symbol VDSS VDGR Continuous Continuous Pulsed VGSS ID IDM Pd RqJA Tj, TSTG BSS123 100 100 ±20 170 680 300 417 -55 to +150 Units V V V mA mW °C/W °C
Characteristic
Drain-Gate Voltage RGS £ 20KW Gate-Source Voltage Drain Current (Note 1) Total Power Dissipation (Note 1) Thermal Resistance, Junction to Ambient (Note 1) Operating and Storage Temperature Range Note:
1. Part mounted on FR-4 board with recommended pad layout, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
DS30366 Rev. 3 - 2
10
www.diodes.com
BSS123
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
FEATURES
· 6 LVCMOS / LVTTL outputs · Crystal oscillator interface · Output frequency range: 10MHz to 50MHz · Crystal input frequency range: 10MHz to 50MHz · Output skew: 10ps (typical) · 5V tolerant enable inputs · Synchronous output enables · Operating supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3Vcore/2.5V or1.8V operating supply, and mixed 2.5V core/1.8V operating supply · 0°C to 70°C ambient operating temperature · Lead-Free package fully RoHS compliant · Pin compatible to MPC905 · Industrial version available upon request
GENERAL DESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83905 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905 ideal for high performance, single ended applications that also require a limited output voltage.
BLOCK DIAGRAM
PIN ASSIGNMENT
BCLK0 XTAL_OUT ENABLE 2 GND BCLK0 VDD o BCLK1 GND BCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
BCLK1 XTAL_IN BCLK2
XTAL_OUT
ICS83905
BCLK3
BCLK4 ENABLE 1
16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package M Pacakge Top View
SYNCHRONIZE
BCLK5
ICS83905
16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm body package G Pacakge Top View
XTAL_OUT ENABLE2 ENABLE1 XTAL_IN
ENABLE 2
SYNCHRONIZE
GND GND BCLK0 VDDO BCLK1
1 2
20 19 18 17 16 ICS83905 15
nc
BCLK5 VDDO BCLK4 GND GND
20-Lead VFQFN 14 4mm x 4mm x 0.9mm 3 body package 13 4 K Package 12
5 6
GND
Top View
7
GND
11
BCLK3
8
BCLK2
9 10
VDD
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83905AM
http://www.icst.com/products/hiperclocks.html
REV. A JANUARY 20, 2005
11
®
OPA
134
OPA
213
4
OPA
413
4
OPA
134
OPA
2134
OPA
413
4
OPA134 OPA2134 OPA4134
High Performance AUDIO OPERATIONAL AMPLIFIERS
TM
FEATURES
SUPERIOR SOUND QUALITY ULTRA LOW DISTORTION: 0.00008% LOW NOISE: 8nV/Hz TRUE FET-INPUT: IB = 5pA HIGH SPEED: SLEW RATE: 20V/µs BANDWIDTH: 8MHz HIGH OPEN-LOOP GAIN: 120dB (600) WIDE SUPPLY RANGE: ±2.5V to ±18V SINGLE, DUAL, AND QUAD VERSIONS
DESCRIPTION
The OPA134 series are ultra-low distortion, low noise operational amplifiers fully specified for audio applications. A true FET input stage was incorporated to provide superior sound quality and speed for exceptional audio performance. This in combination with high output drive capability and excellent dc performance allows use in a wide variety of demanding applications. In addition, the OPA134's wide output swing, to within 1V of the rails, allows increased headroom making it ideal for use in any audio circuit. OPA134 op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. They can be operated from ±2.5V to ±18V power supplies. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over its wide input voltage range, minimizing distortion. OPA134 series op amps are unity-gain stable and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. The dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single and dual versions are available in 8-pin DIP and SO-8 surface-mount packages in standard configurations. The quad is available in 14-pin DIP and SO-14 surface mount packages. All are specified for 40°C to +85°C operation. A SPICE macromodel is available for design analysis.
OPA4134 Out A In A 1 2 A +In A 3 4 5 B In B Out B 6 7 14-Pin DIP SO-14 C 9 8 In C Out C D 12 11 10 +In D V +In C 14 13 Out D In D
APPLICATIONS
PROFESSIONAL AUDIO AND MUSIC LINE DRIVERS LINE RECEIVERS MULTIMEDIA AUDIO ACTIVE FILTERS PREAMPLIFIERS INTEGRATORS CROSSOVER NETWORKS
OPA134 Offset Trim In +In V
1 2 3 4
8 7 6 5
Offset Trim V+
OPA2134
Output NC
Out A In A
1 2 3 4
8
V+ Out B In B +In B
V+ +In B
A B
7 6 5
8-Pin DIP, SO-8
+In A V
8-Pin DIP, SO-8
International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111 · Twx: 910-952-1111 Internet: http://www.burr-brown.com/ · FAXLine: (800) 548-6133 (US/Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation
PDS-1339C
Printed in U.S.A. December, 1997
12
www.ti.com
PCA9554A REMOTE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS127A SEPTEMBER 2006 REVISED FEBRUARY 2007
FEATURES
· · · · · · · · · I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant I/Os 400-kHz Fast I2C Bus Three Hardware Address Pins Allow up to Eight Devices on the I2C/SMBus Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset
DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
· · · · ·
Power-Up With All Channels Configured as Inputs No Glitch on Power-Up Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
RGT PACKAGE (TOP VIEW)
RGV PACKAGE (TOP VIEW)
VCC
SDA
GND
P3
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The PCA9554A consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high or active low) registers. At power-on, the I/Os are configured as inputs with a weak pull up to VCC. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the PCA9554A in the event of a timeout or other improper operation by utilizing the power-on reset feature which puts the registers in their default state and initializes the I2C/SMBus state machine. The PCA9554A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9554A can remain a simple slave device. The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current consumption.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
P4
P5
8
9
Copyright © 20062007, Texas Instruments Incorporated
13
P3 GND P4 P5
A0 A1 A2 P0 P1 P2 P3 GND
1 2 3 4 5 6 7
16 15 14 13 12 11 10
VCC SDA SCL INT P7 P6 P5 P4
16 15 14 13
A2 1 P0 2 P1 3 P2 4
5 6 7 8
12 SCL 11
INT
10 P7 9 P6
A2 P0 P1 P2
16 15 14 13 12 SCL 2 11 INT 10 P7 3 1 4 5 6 7 8 9 P6
A1 A0 VCC SDA
A1
A0
Burr Brown Products from Texas Instruments
SR
C4
392
SRC4392
SBFS029B DECEMBER 2005 REVISED APRIL 2006
Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
FEATURES
· Two-Channel Asynchronous Sample Rate Converter (SRC) Dynamic Range with 60dB Input (A-Weighted): 144dB typical Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: 140dB typical Supports Audio Input and Output Data Word Lengths Up to 24 Bits Supports Input and Output Sampling Frequencies Up to 216kHz Automatic Detection of the Input-to-Output Sampling Ratio Wide Input-to-Output Conversion Range: 16:1 to 1:16 Continuous Excellent Jitter Attenuation Characteristics Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates Digital Output Attenuation and Mute Functions Output Word Length Reduction Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags Digital Audio Interface Transmitter (DIT) Supports Sampling Rates Up to 216kHz Includes Differential Line Driver and CMOS Buffered Outputs Block-Sized Data Buffers for Both Channel Status and User Data Status Registers and Interrupt Generation for Flag and Error Conditions User-Selectable Serial Host Interface: SPI or Philips I2CTM Provides Access to On-Chip Registers and Data Buffers · Digital Audio Interface Receiver (DIR) PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz Includes Four Differential Input Line Receivers and an Input Multiplexer Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs Block-Sized Data Buffers for Both Channel Status and User Data Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats) Audio CD Q-Channel Sub-Code Decoding and Data Buffer Status Registers and Interrupt Generation for Flag and Error Conditions Low Jitter Recovered Clock Output Two Audio Serial Ports (Ports A and B) Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic Slave or Master Mode Operation with Sampling Rates up to 216kHz Supports Left-Justified, Right-Justified, and Philips I2STM Data Formats Supports Audio Data Word Lengths Up to 24 Bits Four General-Purpose Digital Outputs Multifunction Programmable Via Control Registers Extensive Power-Down Support Functional Blocks May Be Disabled Individually When Not In Use Operates From +1.8V Core and +3.3V I/O Power Supplies Small TQFP-48 Package, Compatible with the SRC4382 and DIX4192
·
·
·
·
·
· ·
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Dolby is a registered trademark of Dolby Laboratories. I2C, I2S are trademarks of Koninklijke Philips Electronics N.V. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 20052006, Texas Instruments Incorporated
14
WM8740 24-bit, High Performance 192kHz Stereo DAC
Advanced Information, July 2000, Rev 1.7
DESCRIPTION
The WM8740 is a very high performance stereo DAC designed for audio applications such as CD, DVD, home theatre systems, set top boxes and digital TV. The WM8740 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8740 consists of a serial interface port, digital interpolation filter, multi-bit sigma delta modulator and stereo DAC in a small 28-pin SSOP package. The WM8740 also includes a digitally controllable mute and attenuator function on each channel. The internal digital filter has two selectable roll-off characteristics. A sharp or slow roll-off can be selected dependent on application requirements. Additionally, the internal digital filter can be by-passed and the WM8740 used with an external digital filter. The WM8740 supports two connection schemes for audio DAC control. The SPI-compatible serial control port provides access to a wide range of features including onchip mute, attenuation and phase reversal. A hardware controllable interface is also available.
FEATURES
· · · · · · · · 120dB SNR (`A' weighted mono @48kHz), THD+N: -104dB @ FS 117dB SNR (`A' weighted stereo @48kHz), THD+N: -104dB @ FS Sampling frequency: 8kHz to 192kHz Selectable digital filter roll-off Optional interface to industry standard external filters Differential mono mode needing no glue logic Input data word: 16 to 24-bit Hardware or SPI compatible serial port control modes: · Hardware mode: mute, de-emphasis, audio format control · Serial mode: mute, de-emphasis, attenuation (256 steps), phase reversal Fully differential voltage outputs
·
APPLICATIONS
· · · CD, DVD audio Home theatre systems Professional audio systems
BLOCK DIAGRAM
MODE ML/I2S MC/DM1 MD/DM0 DIFFHW MUTEB CSBIWO RSTB ZERO MODE8X AGNDR AVDDR (24) (28) (27) (26) (6) (25) (23) (22) (21) (4) (10) (9)
WM8740
CONTROL INTERFACE
(11) VMIDR
SCLK (5) BCKIN (3) LRCIN (1) DIN (2) SERIAL INTERFACE
MUTE/ ATTEN DIGITAL FILTERS MUTE/ ATTEN
MUX
SIGMA DELTA MODULATOR
RIGHT DAC
LOW PASS FILTER
(12) VOUTRP (13) VOUTRN
MUX
SIGMA DELTA MODULATOR
LEFT DAC
LOW PASS FILTER
(17) VOUTLP (16) VOUTLN
(18) VMIDL
(15) (8) AVDD DVDD
(20) (19) (14) AVDDL. AGNDL AGND
(7) DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk
Advanced Information data sheets contain preliminary data on new products in the preproduction phase of development. Supplementary data will be published at a later date.
2000 Wolfson Microelectronics Ltd.
15
PIC18F66J10 FAMILY
Device SRAM Data Flash # Single-Word Memory (bytes) (bytes) Instructions 32K 48K 64K 96K 128K 32K 48K 64K 96K 128K 16384 24576 32768 49152 65536 16384 24576 32768 49152 65536 2048 2048 2048 3936 3936 2048 2048 2048 3936 3936 I/O 10-bit A/D (ch) CCP/ ECCP (PWM) 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2 2 2 2 2 2 2 2 2 2 SPITM Y Y Y Y Y Y Y Y Y Y Master I2CTM Y Y Y Y Y Y Y Y Y Y External Bus N N N N N Y Y Y Y Y EUSART Program Memory MSSP Comparators 2 2 2 2 2 2 2 2 2 2 Timers 8/16-bit 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3
PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 PIC18F67J10 PIC18F85J10 PIC18F85J15 PIC18F86J10 PIC18F86J15 PIC18F87J10
50 50 50 50 50 66 66 66 66 66
11 11 11 11 11 15 15 15 15 15
2 2 2 2 2 2 2 2 2 2
Pin Diagrams
RE2/CS/P2B RE3/P3C RE4/P3B RE5/P1C RE6/P1B RE7/ECCP2(1)/P2A(1) RD0/PSP0 VDD VSS RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4/SDO2 RD5/PSP5/SDI2/SDA2 RD6/PSP6/SCK2/SCL2 RD7/PSP7/SS2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64-Pin TQFP
RE1/WR/P2C RE0/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D MCLR RG4/CCP5/P1D VSS VDDCORE/VCAP RF7/SS1 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIC18F6XJ10 PIC18F6XJ15
RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A
Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX configuration bit.
DS39663A-page 2
RF1/AN6/C2OUT ENVREG AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 VSS VDD RA5/AN4 RA4/T0CKI RC1/T1OSI/ECCP2(1)/P2A(1) RC0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Advance Information
16
2005 Microchip Technology Inc.
NJW1159M
2-CHANNEL ELECTRONIC VOLUME
GENERAL DESCRIPTION NJW1159 PACKAGE OUTLINE
NJW1159V
NJW1159M
NJW1159D
FEATURES BLOCK DIAGRAM
17
LM137/LM337 3-Terminal Adjustable Negative Regulators
November 2004
LM137/LM337 3-Terminal Adjustable Negative Regulators
General Description
The LM137/LM337 are adjustable 3-terminal negative voltage regulators capable of supplying in excess of -1.5A over an output voltage range of -1.2V to -37V. These regulators are exceptionally easy to apply, requiring only 2 external resistors to set the output voltage and 1 output capacitor for frequency compensation. The circuit design has been optimized for excellent regulation and low thermal transients. Further, the LM137 series features internal current limiting, thermal shutdown and safe-area compensation, making them virtually blowout-proof against overloads. The LM137/LM337 serve a wide variety of applications including local on-card regulation, programmable-output voltage regulation or precision current regulation. The LM137/ LM337 are ideal complements to the LM117/LM317 adjustable positive regulators. n n n n n n n n n Excellent thermal regulation, 0.002%/W 77 dB ripple rejection Excellent rejection of thermal transients 50 ppm/°C temperature coefficient Temperature-independent current limit Internal thermal overload protection P+ Product Enhancement tested Standard 3-lead transistor package Output is short circuit protected LM137 Series Packages and Power Capability Rated Device LM137/337 Package TO-3 (K) TO-39 (H) LM337 LM337 TO-220 (T) SOT-223 (MP) Power Dissipation 20W 2W 15W 2W Design Load Current 1.5A 0.5A 1.5A 1A
Features
n n n n Output voltage adjustable from -1.2V to -37V 1.5A output current guaranteed, -55°C to +150°C Line regulation typically 0.01%/V Load regulation typically 0.3%
Typical Applications
Adjustable Negative Voltage Regulator
Comparison between SOT-223 and D-Pak (TO-252) Packages
00906731
Scale 1:1
00906701
Full output current not available at high input-output voltages
C1 = 1 µF solid tantalum or 10 µF aluminum electrolytic required for stability
*C2 = 1 µF solid tantalum is required only if regulator is more than 4" from power-supply filter capacitor Output capacitors in the range of 1 µF to 1000 µF of aluminum or tantalum electrolytic are commonly used to provide improved output impedance and rejection of transients
© 2004 National Semiconductor Corporation
DS009067
www.national.com
18
LM117/LM317A/LM317 3-Terminal Adjustable Regulator
August 1999
LM117/LM317A/LM317 3-Terminal Adjustable Regulator
General Description
The LM117 series of adjustable 3-terminal positive voltage regulators is capable of supplying in excess of 1.5A over a 1.2V to 37V output range. They are exceptionally easy to use and require only two external resistors to set the output voltage. Further, both line and load regulation are better than standard fixed regulators. Also, the LM117 is packaged in standard transistor packages which are easily mounted and handled. In addition to higher performance than fixed regulators, the LM117 series offers full overload protection available only in IC's. Included on the chip are current limit, thermal overload protection and safe area protection. All overload protection circuitry remains fully functional even if the adjustment terminal is disconnected. Normally, no capacitors are needed unless the device is situated more than 6 inches from the input filter capacitors in which case an input bypass is needed. An optional output capacitor can be added to improve transient response. The adjustment terminal can be bypassed to achieve very high ripple rejection ratios which are difficult to achieve with standard 3-terminal regulators. Besides replacing fixed regulators, the LM117 is useful in a wide variety of other applications. Since the regulator is "floating" and sees only the input-to-output differential voltage, supplies of several hundred volts can be regulated as long as the maximum input to output differential is not exceeded, i.e., avoid short-circuiting the output. Also, it makes an especially simple adjustable switching regulator, a programmable output regulator, or by connecting a fixed resistor between the adjustment pin and output, the LM117 can be used as a precision current regulator. Supplies with electronic shutdown can be achieved by clamping the adjustment terminal to ground which programs the output to 1.2V where most loads draw little current. For applications requiring greater output current, see LM150 series (3A) and LM138 series (5A) data sheets. For the negative complement, see LM137 series data sheet.
Features
n n n n n n n n n Guaranteed 1% output voltage tolerance (LM317A) Guaranteed max. 0.01%/V line regulation (LM317A) Guaranteed max. 0.3% load regulation (LM117) Guaranteed 1.5A output current Adjustable output down to 1.2V Current limit constant with temperature P+ Product Enhancement tested 80 dB ripple rejection Output is short-circuit protected
Typical Applications
1.2V25V Adjustable Regulator
LM117 Series Packages
Part Number Suffix K H T E S EMP MDT
DS009063-1
Design Package TO-3 TO-39 TO-220 LCC TO-263 SOT-223 TO-252 Load Current 1.5A 0.5A 1.5A 0.5A 1.5A 1A 0.5A
Full output current not available at high input-output voltages *Needed if device is more than 6 inches from filter capacitors. Optional -- improves transient response. Output capacitors in the range of 1 µF to 1000 µF of aluminum or tantalum electrolytic are commonly used to provide improved output impedance and rejection of transients.
SOT-223 vs D-Pak (TO-252) Packages
DS009063-54
Scale 1:1
© 1999 National Semiconductor Corporation
DS009063
www.national.com
19
L7805CV
ABSOLUTE MAXIMUM RATINGS
Symbol Vi Io P tot T op T st g Parameter DC Input Voltage (for VO = 5 to 18V) (for V O = 20, 24V) Output Current Power Dissipation Operating Junction Temperature Range (for L7800) (for L7800C) Storage Temperature Range Value 35 40 Internally limited Internally limited -55 to 150 0 to 150 -65 to 150
o o o
Unit V V
C C C
THERMAL DATA
Symbol Parameter D PAK 3 62.5
2
TO-220 3 50
TO-220FP 5 60
TO-3 4 35
Unit
o o
R thj- ca se Thermal Resistance Junction-case Max R thj- amb Thermal Resistance Junction-ambient Max
C/W C/W
CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)
TO-220 & TO-220FP
D PAK
2
TO-3
Type L7805 L7805C L7852C L7806 L7806C L7808 L7808C L7885C L7809C L7812 L7812C L7815 L7815C L7818 L7818C L7820 L7820C L7824 L7824C
TO-220 L7805CV L7852CV L7806CV L7808CV L7885CV L7809CV L7812CV L7815CV L7818CV L7820CV L7824CV
D PAK (*) L7805CD2T L7852CD2T L7806CD2T L7808CD2T L7885CD2T L7809CD2T L7812CD2T L7815CD2T L7818CD2T L7820CD2T L7824CD2T
2
TO-220FP L7805CP L7852CP L7806CP L7808CP L7885CP L7809CP L7812CP L7815CP L7818CP L7820CP L7824CP
TO-3 L7805T L7805CT L7852CT L7806T L7806CT L7808T L7808CT L7885CT L7809CT L7812T L7812CT L7815T L7815CT L7818T L7818CT L7820T L7820CT L7824T L7824CT
Output Voltage 5V 5V 5.2V 6V 6V 8V 8V 8.5V 9V 12V 12V 15V 15V 18V 18V 20V 20V 24V 24V
(*) AVAILABLE IN TAPE AND REEL WITH "-TR" SUFFIX
2/25
20
Advanced Monolithic Systems
FEATURES
· Three Terminal Adjustable or Fixed Voltages 1.5V, 2.5V, 2.85V, 3.0V, 3.3V, 3.5V and 5.0V · Output Current of 3A · Operates Down to 1V Dropout · Load Regulation: 0.1% · Line Regulation: 0.015% · TO-220, TO-263 and TO-252 packages available
AMS1085CT
3A LOW DROPOUT VOLTAGE REGULATOR
APPLICATIONS
· High Efficiency Linear Regulators · Post Regulators for Switching Supplies · Microprocessor Supply · Battery Chargers · Constant Current Regulators · Notebook/Personal Computer Supplies · Portable Instrumentation
GENERAL DESCRIPTION
The AMS1085 series of adjustable and fixed voltage regulators are designed to provide 3A output current and to operate down to 1V input-to-output differential. The dropout voltage of the device is guaranteed maximum 1.5V at maximum output current, decreasing at lower load currents. On-chip trimming adjusts the reference voltage to 1%. Current limit is also trimmed, minimizing the stress under overload conditions on both the regulator and power source circuitry. The AMS1085 devices are pin compatible with older three-terminal regulators and are offered in 3 lead TO-220 package, 3 and 2 lead TO-263 (Plastic DD) and TO-252 (D PAK) package.
ORDERING INFORMATION:
PACKAGE TYPE 3 LEAD TO-220 AMS1085CT AMS1085CT-1.5 AMS1085CT-2.5 AMS1085CT-2.85 AMS1085CT-3.0 AMS1085CT-3.3 AMS1085CT-3.5 AMS1085CT-5.0 2&3 LEAD TO-263 AMS1085CM AMS1085CM-1.5 AMS1085CM-2.5 AMS1085CM-2.85 AMS1085CM-3.0 AMS1085CM-3.3 AMS1085CM-3.5 AMS1085CM-5.0 TO-252 AMS1085CD AMS1085CD-1.5 AMS1085CD-2.5 AMS1085CD-2.85 AMS1085CD-3.0 AMS1085CD-3.3 AMS1085CD-3.5 AMS1085CD-5.0 OPERATING JUNCTION TEMPERATURE RANGE 0 to 125° C 0 to 125° C 0 to 125° C 0 to 125° C 0 to 125° C 0 to 125° C 0 to 125° C 0 to 125° C
TO-220 FRONT VIEW TO-252 FRONT VIEW 3 TAB IS OUTPUT 3 2 1 TAB IS OUTPUT 2 1
PIN CONNECTIONS
FIXED VERSION 1- Ground 2- VOUT 3- VIN ADJUSTABLE VERSION 1- Adjust 2- VOUT 3- VIN
2L TO-263 FRONT VIEW 3 2 1 TAB IS OUTPUT
3L TO-263 FRONT VIEW 3 2 1
TAB IS OUTPUT
Advanced Monolithic Systems, Inc.
6680B Sierra Lane, Dublin, CA 94568 Phone (925) 556-9090 Fax (925) 556-9140
21
a
FEATURES High Speed 41 MHz, 3 dB Bandwidth 125 V/ s Slew Rate 80 ns Settling Time Input Bias Current of 20 pA and Noise Current of 10 fA/Hz Input Voltage Noise of 12 nV/Hz Fully Specified Power Supplies: 5 V to 15 V Low Distortion: 76 dB at 1 MHz High Output Drive Capability Drives Unlimited Capacitance Load 50 mA Min Output Current No Phase Reversal When Input Is at Rail Available in 8-Lead SOIC APPLICATIONS CCD Low Distortion Filters Mixed Gain Stages Audio Amplifier Photo Detector Interface ADC Input Buffer DAC Output Buffer PRODUCT DESCRIPTION
Low Cost, General Purpose High Speed JFET Amplifier AD825
CONNECTION DIAGRAM 8-Lead Plastic SOIC (R) Package
NC IN +IN VS
1 2 3 4
8
NC +VS OUTPUT NC
AD825
TOP VIEW (Not to Scale)
7 6 5
NC = NO CONNECT
The AD825 is a superbly optimized operational amplifier for high speed, low cost and dc parameters, making it ideally suited for a broad range of signal conditioning and data acquisition applications. The ac performance, gain, bandwidth, slew rate and drive capability are all very stable over temperature. The AD825 also maintains stable gain under varying load conditions. The unique input stage has ultralow input bias current and ultralow input current noise. Signals that go to either rail on this high performance input do not cause phase reversals at the output. These features make the AD825 a good choice as a buffer for MUX outputs, creating minimal offset and gain errors. The AD825 is fully specified for operation with dual ± 5 V and ± 15 V supplies. This power supply flexibility, and the low supply current of 6.5 mA with excellent ac characteristics under all supply conditions, makes the AD825 well suited for many demanding applications.
Figure 1. Performance with Rail-to-Rail Input Signals
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
22
TIP31/TIP31A/TIP31B/TIP31C -- NPN Epitaxial Silicon Transistor
July 2008
TIP31/TIP31A/TIP31B/TIP31C
NPN Epitaxial Silicon Transistor
Features
· Complementary to TIP32/TIP32A/TIP32B/TIP32C
1. Base 2. Collector 3. Emitter
Absolute Maximum Ratings TC=25 C unless otherwise noted
Symbol VCBO Collector-Base Voltage Parameter : TIP31 : TIP31A : TIP31B : TIP31C Value 40 60 80 100 40 60 80 100 5 3 5 1 40 2 150 - 65 ~ 150 Units V V V V V V V V V A A A W W C C
VCEO
Collector-Emitter Voltage : TIP31 : TIP31A : TIP31B : TIP31C Emitter-Base Voltage Collector Current (DC) Collector Current (Pulse) Base Current Collector Dissipation (TC=25 C) Collector Dissipation (Ta=25 C)
VEBO IC ICP IB PC
TJ TSTG
Junction Temperature Storage Temperature
© 2008 Fairchild Semiconductor Corporation TIP31/TIP31A/TIP31B/TIP31C Rev. A
www.fairchildsemi.com
23
TIP32/TIP32A/TIP32B/TIP32C -- PNP Epitaxial Silicon Transistor
July 2008
TIP32/TIP32A/TIP32B/TIP32C
PNP Epitaxial Silicon Transistor
Features
· Complementary to TIP31/TIP31A/TIP31B/TIP31C
1. Base 2. Collector 3. Emitter
Absolute Maximum Ratings TC=25 C unless otherwise noted
Symbol VCBO Collector-Base Voltage Parameter : TIP32 : TIP32A : TIP32B : TIP32C : TIP32 : TIP32A : TIP32B : TIP32C Value - 40 - 60 - 80 - 100 - 40 - 60 - 80 -100 -5 -3 -5 -3 40 2 150 - 65 ~ 150 Units V V V V V V V V V A A A W W C C
VCEO
Collector-Emitter Voltage
VEBO IC ICP IB PC
Emitter-Base Voltage Collector Current (DC) Collector Current (Pulse) Base Current Collector Dissipation (TC=25 C) Collector Dissipation (Ta=25 C)
TJ TSTG
Junction Temperature Storage Temperature
© 2008 Fairchild Semiconductor Corporation TIP32/TIP32A/TIP32B/TIP32C Rev. A
www.fairchildsemi.com
24
ULN2001A, ULN2002A, ULN2003A, ULN2004A DARLINGTON TRANSISTOR ARRAYS
SLRS027 DECEMBER 1976 REVISED APRIL 1993
D D D D D D
HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS
500-mA Rated Collector Current (Single Output) High-Voltage Outputs . . . 50 V Output Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Designed to Be Interchangeable With Sprague ULN2001A Series
D OR N PACKAGE (TOP VIEW)
description
1B 2B 3B 4B 5B 6B 7B E
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1C 2C 3C 4C 5C 6C 7C COM
The ULN2001A, ULN2002A, ULN2003A, and ULN2004A are monolithic high-voltage, high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington pairs may be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. For 100-V (otherwise interchangeable) versions, see the SN75465 through SN75469. The ULN2001A is a general-purpose array and can be used with TTL and CMOS technologies. The ULN2002A is specifically designed for use with 14- to 25-V PMOS devices. Each input of this device has a zener diode and resistor in series to control the input current to a safe limit. The ULN2003A has a 2.7-k series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. The ULN2004A has a 10.5-k series base resistor to allow its operation directly from CMOS devices that use supply voltages of 6 to 15 V. The required input current of the ULN2004A is below that of the ULN2003A, and the required voltage is less than that required by the ULN2002A.
logic symbol
CLAMP 1B 2B 3B 4B 5B 6B 7B 1 2 3 4 5 6 7 9 16 15 14 13 12 11 10 COM 1C 2C 3C 4C 5C 6C 7C
logic diagram
9 1B 2B 3B 4B 5B 6B 7B 1 2 3 4 5 6 7 16 15 14 13 12 11 10 COM 1C 2C 3C 4C 5C 6C 7C
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
25
www.ti.com
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B Floating-Point Digital Signal Processors
SPRS297E JULY 2005 REVISED JULY 2007
1 Second Generation AureusTM DSPs
1.1 Features
· · DA708/B/DA788B: 32-/64-Bit 250-/266-MHz Floating-Point DSP Upgrades to C67x+ CPU From DA6xx Family: 2X CPU Registers [64 General-Purpose] New Audio-Specific Instructions Compatible With the DA6xx C67x CPU Enhanced Memory System 256K-Byte Unified Program/Data RAM 768K-Byte Unified Program/Data ROM Single-Cycle Data Access From CPU Large Program Cache (32K-Byte) Supports RAM, ROM, and External Memory External Memory Interface (EMIF) Supports: 100-/133-MHz SDRAM (16-Bit) Async NOR Flash, SRAM (8- or 16-Bit) NAND Flash (8- or 16-Bit) Enhanced I/O System High-Performance Crossbar Switch Dedicated McASP DMA Bus Deterministic I/O Performance dMAX Dual Data Movement Accelerator: Memory-to-Memory Transfers Memory-to-Peripheral Transfers Packing/Unpacking Delay Data Circular Addressing Non-Sequential Addressing for Reverb Three Multichannel Audio Serial Ports Transmit/Receive Clocks up to 50 MHz Five Clock Zones and 16 Serial Data Pins Supports TDM, I2S, and Similar Formats DIT Only (McASP2) Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options Two Inter-Integrated Circuit (I2C) Ports Real-Time Interrupt Counter/Watchdog Oscillator- and Software-Controlled PLL Commercial or Extended Temperature 144-Pin, 0.5-mm, PowerPADTM Thin Quad Flatpack (TQFP) [RFP Suffix] Security Features Available
·
·
·
·
·
·
·
· · · · · · ·
Applications A/V and DVD Receiver Multizone A/V Receiver HDD Jukebox Navigation Systems High-Speed Encode With Simultaneous Multichannel Decode Software Support Dolby® Digital, Dolby® Digital EX, Dolby® Digital Plus, Dolby® TrueHD, Dolby® Pro Logic® IIx, Dolby® Headphone, Dolby® Virtual Surround, DTS®5.1, DTS-ESTM 6.1, DTS Neo:6TM, DTS 96/24TM, DTS-ES 96/24TM, DTS-HDTM (DA788B only) MPEG-2 AAC LC Decode MPEG-4 AAC LC Encode/Decode THX® Select 2, THX® Ultra 2, Neural-THX® Surround MP3 Encode, MP3 Decode WMA8 Encode, WMA9 Decode HDCD® Decode ATRAC3plus® Encode, ATRAC3plus® Decode Audyssey MultEQ XT®, MultEQ®, PrevEQ®, 2EQ® SRS® Circle SurroundTM II (CS II) TI Bass Boost TI Perfect PlaybackTM Compressed Audio Enhancer TI Virtualizer/Headphone TI Effects Library TI DSD-to-PCM Decode TI Filter Library TI Performance Audio Framework (PA/F) TI DSP/BIOSTM Chip Support Library and DSP Library
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 20052007, Texas Instruments Incorporated
27
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B Floating-Point Digital Signal Processors
SPRS297E JULY 2005 REVISED JULY 2007
www.ti.com
1.2 Trademarks
Aureus, Perfect Playback, DSP/BIOS, PowerPAD, TMS320C6000, C6000, Code Composer Studio, XDS, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. Audyssey MultEQ XT, MultEQ, PrevEQ, and 2EQ are registered trademarks of Audyssey Laboratories. SRS is a registered trademark of SRS Labs, Inc. in the U.S. and selected foreign countries. Circle Surround II is a trademark of SRS Labs, Inc. DTS-ES, DTS Neo:6, DTS 96/24, DTS-ES 96/24, and DTS-HD are trademarks of Digital Theater Systems, Inc. DTS is a registered trademark of Digital Theater Systems, Inc. Dolby and Pro Logic are registered trademarks of Dolby Laboratories. Philips is a registered trademark of Koninklijki Philips Electronics N.V. HDCD is a registered trademark of Microsoft Corporation in the United States and/or other countries. ATRAC3plus is a registered trademark of Sony Corporation in Japan and/or other countries/territories. THX is a registered trademark of THX Ltd. All trademarks are the property of their respective owners.
Second Generation AureusTM DSPs
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28
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B Floating-Point Digital Signal Processors
SPRS297E JULY 2005 REVISED JULY 2007
www.ti.com
2.13 Pin Maps
Figure 2-2 shows the pin assignments on the 144-pin RFP package.
VS S OMIS_0IPS S_0IPS VD DD ]0[0RXA VS S ]1[0RXA ]2[0RXA ]3[0RXA VS S ]4[0RXA PS/]5[0RXA S/]6[0RXA PS/]7[0RXA VC DD VS S VD DD A A VC DD VS S XA/]01[0RXA XA/]11[0RXA VC DD VS S XA/]21[0RXA XA/]31[0RXA VD DD A/]41[0RXA A/]51[0RXA 0RKLCA VS S 0RSFA 0XKLCA RKLCHA 0XSFA
901 011 111 211 311 411 511 611 711 811 911 021 121 221 321 421 521 621 721 821 921 031 131 231 331 431 531 631 731 831 931 041 141 241 341 441
1 2
3
4
5
6
7
8
9
01
11
21
31
41
51
61
71
81
91
02
12
22
32
42
52
62
72
82
92
03
13
23
33
43
53
VS S
VS S
Figure 2-2. 144-Pin Low-Profile Quad Flatpack (RFP Suffix)--Top View
Device Overview
A
0ETUMA 1ETUMA 1XKLCHA
1XKLCA VC DD 1RKLCA VD DD 1XSFA 1RSFA VS S TESER VS S VC DD NIKLC VS S SMT VC DD TSRT VCSO SS NICSO TUOCSO VCSO DD VS S VHLLP IDT ODT VS S VD DD ]0[UME VC DD ]1[UME KCT VS S
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29
63
8/1 LCS_0C2I0KLC_0IPS 701CS_0IPSLCS_1C2I/ S 601 VS S 501NE_0IPSADS_1C2I/ A 401 EO_ME 301 VD DD 201 WR_ME 101 VC DD 001 [SC_ME ]2 VS 99 S 8SAR_ME 9 79 ]0[SC_ME 60[AB_ME ]9 59 VS S 41[AB_ME ]9 301[A_ME ]9 29 VD DD 19 0[A_ME ] 09 VC DD 98 1[A_ME ] ] 88 2[A_ME 78 VS S 68 3[A_ME ] 58 VC DD 48 4[A_ME ] 38 5[A_ME ] 28 VS S 18 VD DD 08 6[A_ME ] 97 7[A_ME ] 87 VS S VC DD 77 67 8[A_ME ] 57 9[A_ME ] 4]11[A_ME 7 37 VD DD 27 96 86
VS S 17EKC_ME
07KLC_ME
VS S VD DD 76 EW_ME1[MQD_ ] 66 ]8[D_ME 56 VC DD 46 ]9[D_ME 3]01[D_ME 6 26 VS S 1611[D_ME ] 06 VD DD 9]21[D_ME 5 8]31[D_ME 5 75 VC DD 6]41[D_ME 5 5]51[D_ME 5 45 VS S 35 VC DD 25 ]0[D_ME 15 ]1[D_ME 05 VD DD 94 ]2[D_ME 84 ]3[D_ME 74 VS S 64 ]4[D_ME 54 ]5[D_ME 44 VC DD 34 ]6[D_ME 24 VD DD 14 ]7[D_ME 04 VS S 93 EW_ME0[MQD_ ] 83 EW_ME 73SAC_ME
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B Floating-Point Digital Signal Processors
SPRS297E JULY 2005 REVISED JULY 2007
www.ti.com
5.3
PowerPADTM Plastic Quad Flatpack Mechanical Data Drawing (RFP)
DA708/B/DA788B Device-Specific RFP (S-PQFP-G144) FLATPACK
801 37
PowerPADTM PLASTIC QUAD
901
27 daP lamrehT )D etoN eeS(
72,0 71,0
80,0
M
05,0
441
73
MON 31,0
1 PYT 05,71 02,02 08,91 02,22 08,12 50,1 59,0 QS QS
63 enalP egaG
51,0 50,0
52,0 0 °- ° 7 57,0 54,0
enalP gnitaeS XAM 02,1 80,0
30/12/2
A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external plane. This pad is electronically and thermally connected to the backside of the die and possibly selected leads. Actual size: 5.4 mm × 5.4 mm. Falls within JEDEC MS-026.
E.
Mechanical Data
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30
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No. First Version Release 1.0 1. Changed tOH: 2.0 --> 2.5 [tCK = 7 & 7.5 (CL3) Product] 1. Changed Input High/Low Voltage (Page 08) 2. Changed DC characteristics (Page 09) - IDD2NS: 18mA -> 15mA - IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA [Speed 200 / 166 / 143 / 133MHz] 3. Changed Clock High / Low pulse width Time (Page 11) 4. Changed tAC Time (Page11) 5. Changed tRRD Time (Page12) 1. Corrected Revision No.: 2.0 -> 1.1 2. Deleted Remark at Revision History 3. Corrected AC OPERATING CONDITION - CL 50pF -> 30pF 4. Changed DC OPERATING CONDITION - VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0 - VIL MIN VSSQ-2.0 -> -0.3 1. Modified note for Super Low Power in ORDERING INFORMATION 1. Corrected PIN ASSIGNMENT A12 to NC 1. Corrected comments for overshoot and undershoot Nov. 2004 History Draft Date Remark
1.1
Dec. 2004
1.2
Dec. 2004
1.3 1.4 1.5
Jan. 2005 Jan. 2005 Feb. 2005
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 / Feb. 2005
31
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of 1,048,576x16. HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
· · · · · · Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM · Internal four banks operation · Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks · · · Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No. HY57V641620E(L/S)T(P)-5I HY57V641620E(L/S)T(P)-6I HY57V641620E(L/S)T(P)-7I HY57V641620E(L/S)T(P)-HI Clock Frequency 200MHz 166MHz 143MHz 133MHz 4Banks x 1Mbits x16 LVTTL 54 Pin TSOPII Organization Interface Package
Note: 1. HY57V641620ET-xI Series: Normal power, Leaded. 2. HY57V641620ELT-xI Series: Low power, Leaded. 3. HY57V641620EST-xI Series: Super Low power, Leaded. 4. HY57V641620ETP-xI Series: Normal power, Lead Free. 5. HY57V641620ELTP-xI Series: Low power, Lead Free. 6. HY57V641620ESTP-xI Series: Super Low Power, Lead Free
Rev. 1.5 / Feb. 2005
32
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
PIN ASSIGNMENTS
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch
Rev. 1.5 / Feb. 2005
3
33
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
PIN DESCRIPTION
SYMBOL CLK TYPE Clock DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7 Auto-precharge flag: A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
CKE CS BA0, BA1
Clock Enable Chip Select Bank Address
A0 ~ A11
Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection
RAS, CAS, WE
UDQM, LDQM DQ0 ~ DQ15 VDD / VSS VDDQ / VSSQ NC
Rev. 1.5 / Feb. 2005
4
34
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row Counter
CLK CKE
State Machine
Row Active
1Mx16 BANK 3
Row Pre Decoder
1Mx16 BANK 2 1Mx16 BANK 1 1Mx16 BANK 0
DQ0
I/O Buffer & L