Text preview for : dvd02_Digital Video Player.pdf part of SONY Digital Video Player Training Manual for Digital Video
Player
Circuit Description and Troubleshooting
Back to : dvd02_Digital Video Playe | Home
S
®
Training Manual
Digital Video Player
Circuit Description and Troubleshooting Course: DVD-02
Course Description and Troubleshooting:
Model: DVP-S530D
Prepared by: National Training Department Sony Service Company A Division of Sony Electronics Inc.
Course presented by______________________________________ Date___________________________________________________ Student Name ___________________________________________
Sony Service Company A Division of Sony Electronics Inc ©1999 All Rights Reserved Printed in U.S.A.
"DTS" is a trademark of Digital Theater Systems, Inc. "AC-3" is a trademark of Dolby Laboratories Licensing Corporation. "Dolby" and "Dolby Surround" are trademarks of Dolby Laboratories Licensing Corporation. "Sony" and "Digital Cinema Sound" are trademarks of Sony. "THX" is a trademark of Lucasfilm, Ltd.
Table of Contents
Introduction to the DTS Audio Format
What is DTS? What do I need to play the DTS surround format? What do I need to play both the AC-3 and DTS surround formats? Will a 5.1 channel DTS CD play in my CD player? Why won't my older DVD player play DTS DVDs? Can DVD movies contain both DTS and AC-3 audio tracks? How does DTS work?
1
2 2 2 2 3 3 3
Regulation Concept Regulation Circuitry
13 13
Main Oscillator
Enable Start Run Regulation
15
15 15 15 15
Power Control
Plug In
17
17
Board Layout DVD Features Block Diagram
Power Supply Communications Servo Control Video and Audio Processing
5 6 7
7 7 7 9
Communications Block
Serial Data Parallel Data
21
21 21
Serial Data Communications
Serial Bus 0 Serial Bus 1
23
23 25
Parallel Data Communications
Communications from IC202 to Other ICs Communications from a Destination IC to IC202
27
29 29
Power Supply Block
Standby Power Supply Main Power Supply Power Consumption Oscillator Frequencies
11
11 11 11 11
Mechanism
Disc Tray and Laser Platform Position Tilt Motor Power ON Mechanical Sequence - No Disc Power ON Mechanical Sequence - DVD Disc
31
31 32 34 35
Standby Oscillator
Start Run
13
13 13
Tray Motor Drive
37
Initial Sled Motor Drive
Initial Sled Movement Home Position Detection
41
41 45
Manually Driving the Tilt Motor
71
Laser Servo KHM-220A DVD Optical Block
DVD Focus CD Focus Three Laser Beams from One Laser Photo Detectors
47 49
49 49 50 51
A/V Processing Block A/V Processing Test Mode
Test Mode Access Tests Additional Test Mode Self-Diagnostic Function (Customer Error Codes)
73 75 81
81 81 83 83
Troubleshooting
General Problems and Troubleshooting Guide
85
85
Disc Identification
Operation SACD Disc Type
53
53 53
Focus
Search Servo Focus Drive Focus Search Communications
55
55 55 57 57
Spindle Motor
Kick Mode CLV PB Mode
61
61 63
Tracking Servo
Tracking Counting in Pause or Picture Jump
65
65
Sled Motor Drive - PB
Following the Track
67
59
Tilt Servo
Operation
69
69
1
Introduction to the DTS Audio Format
Several major consumer audio formats that exist today are listed in this table: Audio Formats Year Chan Typical Typical Data Rate Compression Format (note 1) Class Used -nels sample (note 2) (Approx.)
1. Stereo 2. PCM (digital version of stereo) 3. Dolby Surround ® 4. Dolby Prologic ® 5. Dolby Digital ® 6. DTS ® 7. THX ® 1982 1987 1991 1993 1982 1933 2 2 3 4 6 6 2-6 Analog Digital Analog Analog Digital Digital Either 20 bits / sample 20 bits / sample 384 Kbytes/sec (44.1kHz sample) 1,411kbits/sec (44.1kHz sample) 75%
DTS Test CD DTS Test DVD
Test Disc
Signal Source (note 3) FM, VHS, CD, LD, etc.
linear 16 bits / sample. 705kbit/sec (44.1kHz sample) None None None 90%
Prologic test CD Dolby DVD-TEST1 Dolby DVD-TEST1
DVD, LD VHS VHS, theaters DVD, LD, DTV DVD, LD, CD Theaters, DVD, LD, VHS
Note 1 - All formats require decoders, except Stereo and THX. THX is not a processing system but an audio/video quality control approval system. Its certification stamp means that the video and audio quality at theaters and CD/DVD discs meet uniform standards. This means the same movie viewed at one theater will not be different when viewing it at another theater. Note 2 - Data rate = bits sampled X sample rate. A CD player (44.1kHz) rate was chosen for comparison. The DVD sample rate of 48kHz would make its data rate higher than shown. Note 3 - LD = Laser Discs; DVD = Digital videodiscs; DTV = Digital TV; theaters = Movie theaters; VHS = Videotape format. Test discs can be purchased from different distributors: Prologic test CD #SSTCD · Sony parts distributors. Call 1-800-222-Sony for a distributor Dolby DVD TEST 1 # 22707 $45. · USC Products Marketing Co.; 1 800 983 6529 DTS Test CD (digital output only) · Digital Sound Systems Entertainment 5171 Clareton Drive, Agoura Hills, Calif. 91301 1-818-706-3525 part #DTS-CD 96091 · Sony parts distributors. Call 1-800-222-Sony for a distributor CD part # J2501-154-A $7.76 list price DTS Test DVD #DTS-DVD 98061 · Digital Sound Systems Entertainment Agoura Hills, Calif. 91301 1-818-706-3525 part #DTS- DVD 98061
What is DTS?
Digital Theater Systems has developed a digital audio compression method similar to Dolby Digital AC-3. DTS processed audio is not as compressed as Dolby AC-3. Therefore it is said to have more surround detail (separation), envelopment and better bass because of less compression (losses).
AC-3 decoder in the Receiver:
5 Speakers
CD/DVD Player
6 Channel Receiver With DTS Decoder And AC-3 Decoder
What do I need to play the DTS surround format?
The DTS source can be a DVD movie or CD. The DTS decoder is commonly found in the receiver. 5 Speakers Digital output
preamp out to Sub Woofer
Will a 5.1 channel DTS CD play in my CD player? CD/DVD Player
Digital output
6 Channel Receiver With DTS Decoder
preamp out to Sub Woofer
Only digital noise will appear from the L/R analog outputs if not automatically muted. There will be digital output from the coaxial and optical ports. Either digital output can be fed to a DTS stand-alone decoder or a receiver with a DTS internal decoder. The DTS receiver will produce the six channels ("5.1") or be downmixed into two (front L/R) channels depending upon the user menu. A DTS CD compresses the six channels of audio into the space originally occupied by the two-channel uncompressed CD audio. In order for six compressed channels to fit on a CD, the data rate must be equal to or less than the rate of a normal uncompressed CD. Data rate of an uncompressed CD per channel = 16 bits/sample x 44, 100 samples/second = 706 Kbytes/sec. There are two channels so the rate is doubled. Therefore the data rate of a normal stereo CD = 1,412kbit/sec. This is just about the same data rate as a DTS compressed CD. The DTS data rate is 1,411kbits, so no analog sound will be output from a DTS CD. For comparison, CD, DTS, and AC-3 data rates are shown:
Data Rate Comparison (44.1 kHz sample rate) Format CD DTS Dolby Digital AC-3 Not compressed Compressed Compressed Output Data Rate 1,412 Kbytes/sec. 1,411 Kbytes/sec. 384 Kbytes/sec.
What do I need to play both the AC-3 and DTS surround formats?
The AC-3 source can be DVD or HDTV (future). The decoder can be found in the player or receiver. AC-3 decoder in the Player: 5 Speakers
CD/DVD Player With AC-3 decoder
Digital Output
6 Channel Receiver With DTS Decoder
preamp out to Sub Woofer
2
3 Why won't my older DVD player play DTS DVDs?
The DVD DTS flag was not established until Nov 1998. This flag must be inserted into the DVD's digital coax or optical output for the receiver to recognize and decode DTS. Therefore DVD units that are not marked "DTS ready" will not play DTS even though they have digital outputs.
MDCT Time to Frequency Conversion
Each single channel PCM source signal is grouped and allocated to one of 32 frequency bands for analysis. The process is commonly known as Modified Discrete Cosine Transformation (MDTC). This frequency band allocation allows for identification and removal of redundancy among the channels in the next compression stage.
Coefficients 6 CHANNELS
Can DVD movies contain both DTS and AC-3 audio tracks?
Yes they can. Currently the DVD audio choices are: · · · PCM Producing the conventional analog L/R sound Dolby Digital or AC-3 Compressed 5.1 channel surround sound DTS Compressed 5.1 channel surround sound
How does DTS work?
The DTS and AC-3 encoding formats are generally similar. DTS and AC3 can accept digital (PCM) audio with word lengths from 16 to 24 bits. Both encoders can accept the common 32, 44.1 and 48kHz PCM sampling frequencies, but DTS has 12 more optional frequencies. The general encoding of the DTS compression system will be explained. DTS has four blocks used to compress the PCM input audio into a single bit stream: PCM audio 6 Channels Time to Frequency Conversion 6 lines DTS Multiplexer Sync Packer Compressed Bit Stream Compression
Coefficients
Frequency
Frequency
Compression
Adaptive Predictive Coding (ADPCM) ADPCM involves smaller support stages to: Combine the same sounds found in other channels, Remove undetectable audio levels (below human hearing thresholds), Remove short interval noises that are swamped by louder sounds (psycho acoustic masking); and · Remove transient noises that do not repeat on the same or other channels. The support stages include transient, vector and prediction analysis stages to determine if the sound is short term, increasing or decreasing, and if the sound will repeat. Removal or the combination of sounds (compression) is determined by the analysis. · · ·
Multiplexer
Compression Block: ADPCM: From time to freq Converter The six compressed channels are combined into a single line for ease of delivery. To do this each channel is stored into a register made up of flipflops. A high speed Multiplexer removes the information at six times the storage (sample) speed. Multiplexer Multiplexer
Six Channels N sample frequency F/F type Registers
· · ·
Transient analysis Vector analysis Prediction analysis
Global Bit Management Variable Length Coding
6 lines
Packer
Global Bit Management Once compression has taken place, an examination of the six data streams for density is made. Bit groups are tagged and moved from a high-density channel to a low-density channel equalizing the amount of data. 0011100011000011111001010101 channel 1 0000001011000000000000000000 channel 3 Variable Length Coding Common fixed length codes and no data (00000000) codes are removed and replaced with shorter codes using a look up table. These shorter length code replacements are flagged for decoding. 0100011111 ROM Table 011 + flag The packer organizes the information into blocks and adds: · · Error correction Synchronization information to each block and groups of blocks
4
5
BOARD LAYOUT
DVD Features
0D 53 -S VP D 0D 55 -S VP D 00 77 -S VP D 0 60 -C VP D 0 33 -S VP D
DVD Models MSRP * General Single Optical Assembly Dual Optical Assembly Active laser platform tilt servo TV / receiver / DVD Remote Advanced Test Mode Glow in the dark Remote keys Glass Epoxy Circuit Boards Anti-Resonate Chassis & tray Copper Plated Shielded Chassis Video 10 bit Video D/A Converter Digital RF Processor Digital Noise Reduction Video Page Bookmark 2 Composite Video Outputs 2 S-Video Outputs Component Video (Y, U, V) Outputs Audio 96kHz / 24 bit audio D/A Converter Sony Digital Cinema Sound Virtual Surround Sound Dolby AC-3 Surround Decoder DTS Decoder 2 Analog Outputs Coax & Optical Digital Outputs 1/4" Headphone Output
$ 449.00 x x x x
$ 499.00 x x x x
$ 599.00 x
$ 899.00
$ 1,399.00
x x x x x
x x x x x x x x
x x
x x
x x
x x x
x x x x x x x
x x x x
x x x x x x x
x
x x x
x x x x x x
x x
x
x x
x x x
x x x
x x x
* MSRP = Manufacturer's Suggested List Price
6
7
Block Diagram
Name
ICs Checked During Start Up Number IC205 IC601 Purpose Start up program instructions Expansion port for System Control IC202 to indirectly communicate with others on the parallel bus. IC202's local memory Audio (AC-3) and Video (MPEG 2) decoder CD/DVD data processing and separation Analog servo control 1. Flash ROM 2. Hybrid Gate Array 3. SRAM 4. AV Decoder 5. ARP2 6. Servo 7. Audio DSP
There are four major stages within this DVD player. They operate in this sequence to produce the discs' video and audio: · · · · Power Supply Communications Servo Control Video and Audio Processing
IC204 IC401 IC303 IC701 IC501
Power Supply
The power supply block delivers five different voltages. Ever 5V is the only voltage present when the unit is plugged into AC. Ever 5V powers Interface IC201 to switch on the remainder of the voltages when it receives the power ON (P Cont) command.
Communications
Plug In
At plug in, Interface IC201 powers on the unit for 1.3 seconds, keeping the display dark. During this time there is a brief communication between Interface IC201 and System Control IC202 on the serial bus. At the conclusion of this communication "handshaking", the front panel Dolby Digital indicator lights and quickly extinguishes as the unit powers off. The front panel red standby light is on during the entire initial communication, never turning green when momentarily powering up at plug in.
Dolby Prologic, Rear channel delays, 5.1 channel downmixing to 2 channels If an IC does not reply, IC202 instructs IC201 to power off the set.
Servo Control
At the successful conclusion of the start up program, IC202 retrieves servo parameter data from EEProm IC201 using the serial bus. Then IC202 communicates with expansion port HGA IC601. IC601 relays the information to other ICs connected to it. One of those ICs is IC701. Servo IC701 is instructed to reset the base unit mechanism to the initial position and confirm it: · Tray closed · Tilt servo at mid position · Sled returned to home position If the initial position is not confirmed before a time limit ("time out"), IC201 will power off the set. Confirmation comes from IC701 through IC601 to IC202. IC202 then sends commands back to servo IC701 for disc detection.
Power ON
At power ON, the red standby light turns to green and the power supply is turned on. After another brief communication between IC201 and IC202, IC202 retrieves and implements the start up program stored in Flash Memory IC205. The start up program requires IC202 to check for the presence of these six ICs on the parallel bus and IC501 on the serial bus:
SPINDLE CONTROL IC802 MECHANISM OPTICAL DEVICE RF LD TK-51 BD. IC001 RF AMP RF
IC304 DRAM IC401 AV DECODER Y,C
IC402 IC403 SDRAM Y,Pb, Pr Y SPDIF, ACHI-6, CLK
AU212 BD.
S VIDEO OUT VIDEO BUFFERS COMPONENT V OUT COMPOSITE V OUT DIGITAL AUDIO OUT ANALOG AUDIO IC902 OUT DAC IC905-7 DAC 5.1 CH AC-3 OUT
DVD DATA IC303 ARP2 CD DATA, CLK
FE TE PI FOCUS COIL TRACK COIL
S. DATA CLK
IC501 AUDIO DSP
M TILT M SPINDLE M SLED
IC801 FOCUS & TRACKING COIL TILT MOTOR DRIVER IC802 SPINDLE, SLED, & LOADING MOTOR DRIVER
PARALLEL BUS
IC204 SRAM
IC701 SERVO
IC601 HGA
IC202 SYSTEM CONTROL
IC205 FLASH MEM
SERIAL BUS SPINDLE CONTROL IC303 EVER 5V POWER BLOCK 5V 12V -12V P CONT. IR REC FR150 BD. IC201 INTERFACE MICRO DISPLAY PANEL SWITCHES FL101 BD. IC201 EEPROM
MB-85 BD.
3.3V M LOADING
BLOCK DIAGRAM
1DVD02 1146
6 22 99
8
9
Video and Audio Processing
After the servos have begun, RF data will come from the optical assembly within the base unit. The "eye pattern" RF data is split into two paths to provide: 1. Feedback signal to lock the servos; and 2. Video and audio information. In the A/V processing chain, the RF data is processed by the following ICs:
Name IC
Audio / Video Processing ICs Audio or Video A/V (both) A/V (both) Purpose
RF Amp ARP2
IC001 IC303
Matrix the optical outputs to produce signals for servo and A/V circuits · · · 16 to 8 bit Demodulation Descrambles the main data using external memory IC304 Generates bit clock Video · MPEG decompression using the external IC402 and IC403 memories Crops the 16x9 image for a 4x3 TV picture Controls spindle motor speed Sends disc's control and menu data to IC202 On screen display graphics D/A Converter (analog video output) Audio MPEG audio decompression Dolby Digital AC-3 decompression using external SRAM IC402 / IC403 Sound enhancements when there is no AC-3 received (Rear channel delay) Downmixing of 6 channel AC-3 into 2 (L/R) channels Dolby Prologic decoding Digital coax and optical output Rear channel delay Front/rear level balancing
Decoder
IC401
A/V (both)
· · · · ·
· ·
DSP
IC501
A
·
· · · · · DAC DACs IC902 IC905IC907 A A
· Test tone generation Digital to analog converter for the front left and right channels 3 Digital to analog converters for the six AC-3 channels
SPINDLE CONTROL IC802 MECHANISM OPTICAL DEVICE RF LD TK-51 BD. IC001 RF AMP RF
IC304 DRAM IC401 AV DECODER Y,C
IC402 IC403 SDRAM Y,Pb, Pr Y SPDIF, ACHI-6, CLK
AU212 BD.
S VIDEO OUT VIDEO BUFFERS COMPONENT V OUT COMPOSITE V OUT DIGITAL AUDIO OUT ANALOG AUDIO IC902 OUT DAC IC905-7 DAC 5.1 CH AC-3 OUT
DVD DATA IC303 ARP2 CD DATA, CLK
FE TE PI FOCUS COIL TRACK COIL
S. DATA CLK
IC501 AUDIO DSP
M TILT M SPINDLE M SLED
IC801 FOCUS & TRACKING COIL TILT MOTOR DRIVER IC802 SPINDLE, SLED, & LOADING MOTOR DRIVER
PARALLEL BUS
IC204 SRAM
IC701 SERVO
IC601 HGA
IC202 SYSTEM CONTROL
IC205 FLASH MEM
SERIAL BUS SPINDLE CONTROL IC303 EVER 5V POWER BLOCK 5V 12V -12V P CONT. IR REC FR150 BD. IC201 INTERFACE MICRO DISPLAY PANEL SWITCHES FL101 BD. IC201 EEPROM
MB-85 BD.
3.3V M LOADING
BLOCK DIAGRAM
1DVD02 1146
6 22 99
10
11
Power Supply Block
The power supply is on a single board located to the left of the DVD mechanism. This board contains both the standby and the main power supply. The input line filter L101 and the board connectors are the only parts that are not available.
When a shorted spindle motor driver IC802 loaded the unfused +12V supply line, the main oscillator quit. The oscillator worked again when the short was removed.
Regulation
The 3.3Vdc output is used to regulate the main power supply. Error detector IC201 receives the 3.3Vdc and produces a correction voltage. If the input voltage increases, the error detector output decreases. The PC101 photocoupler passes the correction signal to the control transistor Q102. Q102 adjusts the off time of the oscillator signal to correct the 3.3Vdc output the secondary. If the DVD power consumption is normal, the remainder of the T101 outputs will be correct.
Standby Power Supply
This power supply produces Ever 5V as long as AC is present. Ever 5V is supplied to interface IC201 (MB85 board) and the mute transistors (AU212 board). The standby power supply consists of an oscillator and an error regulator. The oscillator consists of switch Q121 and a control transistor Q122. The oscillator output is applied to T102. T102's secondary is rectified to output Ever 5V.
Power Consumption
The current along each supply line was measured in both the idle and the DVD disc playback mode. Model DVP-S530D Current Consumption Part replaced Supply line Current by Ammeter Idle Disc PB
Ever 5V +12V partial +12V total +5V +3.3V L205 PS201 L201 PS202 PS203 * 30ma (set off) 196mA 236mA 281mA 894mA 77mA (set on ) 198mA 350-700mA 305mA 950mA
Regulation
The Ever 5V voltage regulation circuit uses: · IC202 error detector · PC121 photocoupler · Q122 control transistor. IC202 samples the Ever 5V output and produces a correction voltage. Photocoupler PC121 passes the error voltage from the cold ground circuit to the hot ground side circuit. The control transistor Q122 receives the error voltage and uses it to alter the base bias of switch Q121. The change in bias alters the off time of the oscillator signal. This changes the oscillator frequency. The changes in frequency affect the efficiency of the transformer, which regulates the Ever 5V.
Main Power Supply
The main power supply works similarly to the standby supply except the main supply is switched, handles more power and has multiple secondaries. The main power supply is switched ON by PCONT from the Interface IC on the FR148 board. A high at PCONT enables switch Q101 to begin oscillating. Transformer T101 produces several output voltages that are rectified into DC for the remainder of the DVD unit.
-12V PS204 129mA 130mA * Use short ammeter leads or the unit will not PB the disc and the display will not come on. The PS203 current without the display will only be 580mA.
Oscillator Frequencies
Power Supply Oscillator Frequencies Power Supply Standby (Q121/D) Main (Q101/C) 0 Set Off 57.45kHz Set On (stop mode) 49.65kHz 101.2kHz
SRV902UC BOARD +12V +5V Q101,102,T101 MAIN OSC. D101-104 RV201 PC101 PHOTO COUPLER L101 LINE FILTER IC201 ERROR DET. +3.3V L201 PS201 PS202 PS203 PS204 -12V
CN201 4 2 1 6 7 CN202 2 1 5
+12V +5V +3.3V -12V EVER 5V M+12V A+12V +5V TO AU212 BD. ANALOG AUDIO/ VIDEO
TO MB 85 BD. SERVO CONTROL
6 +3.3V 7 PC102,Q201 POWER CONTROL CN203 1 3 5 Q121,122,T102 STBY OSC. EVER 5V L205 2 PCONT +5V -12V EVER 5V TO FR148,FL101 BDS. INTERFACE/ DISPLAY
F101 PC121 PHOTO COUPLER 1 2 CN101 IC202 ERROR DET.
POWER SUPPLY BLOCK
2DVD02 1137
4 27 99
12
13
Standby Oscillator
The standby oscillator produces Ever +5 volts when the DVD player is plugged into 120VAC. This Ever 5V is applied to the Interface IC201 (on the circuit board behind the front panel) and the audio and video mute transistors (on the rear board). The standby oscillator stage consists of two transistors and a transformer. Regulation is performed using the Ever 5V output to control the off time of the oscillator cycle. The standby oscillator has three operational parts: · Start · Run · Regulation
The collapsing magnetic field induces a negative voltage into the lower secondary winding. The negative voltage takes two paths to reset the oscillator. The first path is through R126, R125 and C121 to keep oscillator transistor Q121 OFF. The second path is through D121 and R128 into the base of Q122. This turns off transistor Q122 in preparation for the next oscillator cycle.
Regulation Concept
Regulation of the Ever 5V line is accomplished by sampling the output voltage and using it to reduce the off time of the oscillator. By reducing the off time, the total oscillator cycle is reduced. Shortening the time it takes to complete a cycle means its frequency is increased. This oscillator signal is applied to transformer T102. A transformer has an optimum frequency that will allow maximum power transfer (at resonance). When the applied oscillator frequency is above resonance, the efficiency drops and its secondary voltage is reduced. By varying the applied frequency, the output voltage can be regulated.
Start
At AC plug in, the standby oscillator stage begins when R122 and R123 bring the FET Q121 gate voltage from 0 to about 1volt. This turns on the low power FET, allowing it to pass Drain to Source current and complete T102's primary circuit path to hot ground.
Regulation Circuitry
IC202 is the error regulator for this stage. Voltage divider R212, R209 and R210 reduce the Ever 5V so there is 2.5V at IC202's input. This allows its operation in the linear region. IC202's output (collector) is inversely proportional to its input. The collector output is connected to the opto-isolator diode that passes the error signal to the hot ground oscillator circuit. If the Ever 5V increased, the opto-isolator transistor would conduct more, reducing the resistance between the lower secondary winding and Q122's base. The reduced resistance allows more current to flow, permitting Q122 to turn on sooner. The sooner it turns on, the sooner the FET turns off, increasing its frequency of operation that results in a reduced output voltage for regulation. IMPORTANT VOLTAGES MEASURED WITH THE SET OFF:
Voltage Q101/Drain Q101/Gate D121/Anode 300Vp-p 13.8Vp-p 16Vp-p 2V 0V DC Voltage 166V
Run
Oscillator transistor Q121 turns ON As current flows in T102's upper left primary winding, a voltage is induced in the lower secondary winding that will keep FET oscillator Q121 turned ON. A positive voltage from the lower secondary winding takes two paths. The first path is through R126, R125 and C121 to Q121's gate. This keeps Q121 conducting. The second path is through R127 and R128 to Q122's base. Q122's collector is connected to the oscillator's gate. As a result, Q122 becomes an active resistor. Q122's conduction prevents the gate voltage from rising too high (protection) and later we will see that it is used for regulation. Oscillator transistor Q101 turns OFF When Q101 is saturated, there is no longer a change in T102's primary current. The voltage induced into the lower secondary winding decays. This reduction in bias voltage permits Q121 to turn OFF. With Q121 OFF, the magnetic field in T102's primary winding collapses, causing current flow thorough C123 and limiter R130.
MAIN OSC
D101-D104 R121 R122 C108 220 C102 C121 L101 LINE FILTER Q122 R125 R128 22k R127 D121 D122 R207 1k PC121 ON3131 IC202 AN1431 4.1V R208 2.5V R210 C212 R212 R209 R129 100 OHM R126 + C211 100 R124 R123 C123 Q121 D S D208 R130 D206 5V + C210 100 CN201
7
T102
L205
CN203
2
EVER 5V TO FR150 BD. (DISPLAY) EVER 5V TO AV212 BD. (MUTE)
R206 470 OHMS
STANDBY OSCILLATOR
29DVD02 1175
6 28 99
14
15
Main Oscillator
The main oscillator stage operates like the standby oscillator stage except that the main oscillator is switched ON/OFF and there are multiple secondaries to supply the needs of the DVD player. The main oscillator has four parts: · · · · Enable Start Run Regulation
Run
Q101 Turns ON When Q101 turns ON, current flows through the main transformer's primary winding at the upper left of T101. This induces a positive voltage to the lower T101 winding that follows two paths. The first path is through R106, R107, D109 and C113 to Q101's base to keep it conducting. The second path is through D108 and R109 to bias Q102. Q102 acts like an active resistor at Q101's base to keep the voltage from becoming excessive (protection) and is used later for regulation. Consequently the correct value components and transistors are critical. When Q101 reaches saturation, there is no longer a change in T101's primary current. The steady current flow no longer induces a voltage into the lower secondary winding and the secondary voltage decays. Q101 Turns OFF The reduction in secondary voltage turns Q101's OFF. The magnetic field in T101's primary collapses. D105, limiter, L102 and C110 short its energy. D106 is used to discharge C110 (when Q101 is ON). The collapsing (changing) magnetic field induces a negative voltage at the lower secondary winding. This negative voltage from T101 passes through R106, R107 and C113 to the base of oscillator transistor Q101. It is used to cut off Q101 to conclude this oscillator cycle.
Enable
Oscillator OFF The operation of the main oscillator is inhibited by PC102. When the unit is plugged into AC, Ever 5V is made by the standby oscillator stage and is used to turn on the opto-isolator LED in PC102. The LED's infrared light turns on the phototransistor and it conducts. PC102's phototransistor is connected to oscillator transistor Q101's start voltage applied to the base. When PC201 conducts, the start voltage from R102/R103 is grounded, stopping the oscillator. Oscillator ON Q201 removes the voltage to the opto-isolator diode in PC102, permitting the main oscillator stage to run. When PCONT from Interface IC201 goes high at CN203/pin 1, Q201 turns ON. Its conduction grounds the voltage from R211, removing voltage from the LED. PC102 transistor turns off, removing the ground from R103 so the main oscillator transistor Q101 can start.
Regulation
The 3.3-volt output is monitored by error regulator IC201 and used to control the conduction of phototransistor PC101. If the 3.3-volt line rises, the phototransistor conducts harder. This reduces the resistance between the lower secondary winding and Q102's base, increasing Q102 base current. The increased base current drives Q102 harder, lowering the oscillator's base bias voltage and causing the oscillator to be turned OFF sooner. When part of the oscillator waveform is shortened, its frequency increases. This reduces T101 efficiency and the 3.3V output voltage is returned to normal. IMPORTANT VOLTAGES: Q101/Collector = 336Vp-p; 150Vdc. PC101/collector = 2.6Vdc. PC101/emitter = 0.21Vdc Feedback secondary voltage at D108/cathode = 20Vp-p; 0.21Vdc.
Start
Once the PCONT control line at CN203/pin 1 goes high, PC102's transistor no longer conducts. The ground is removed from the start voltage at the junction of C111 and R104 so it rises. It will reach 6.6V, limited by the voltage divider formed by R102, R103 and R104. Sufficient current passes through C111 during this voltage increase to turn ON main oscillator Q101. This is how oscillator transistor Q101 starts conducting (turns ON) and the main oscillator starts.
CN202
2 M+12V 6
STBY OSC
PS201 0.5A R213
7 5 1
+3.3V +5V A+12V
TO MB85 BD.
T101
D201
L201 C201
CN201
4
AC D105 L105 R102 R103
C111 4.7mF L102
+12V
C202
PS202
2 +5V
C110
D202 C203 L202 L203
1A PS203
1
D106
TO AV212 BD.
+3.3V
Q101
D203
D110
R104
C113 D204 Q102 D109
RV201 3.3V ADJ.
6
-12V
D108 MTZJ3.0
R109 R106 47 1W R201
PS204 0.75A R204 2.5V R205 R203
R107
D107
EVER 5V R211 PC101 ON3131 4V
IC201 AN1431
C205
Q201 PC102 ON3131
P CONT
1
FROM FR150 BD.
CN203
MAIN OSCILLATOR
30DVD02 1174
7 12 99
16
17
Power Control
Plug In
When the DVD player is plugged into AC, the power supply only outputs Ever 5V to: · Analog audio mute transistors AU-212 board · Interface IC201/pin 16 FL101 board · Reset IC202/pin 5 - FL101 board The mute transistors are biased ON to keep the 5.1, headphones and L/ R channel audio outputs grounded. Ever 5V applied to Interface IC201 starts the 4MHz X201 crystal connected to pins 14 and 15. Reset IC202 on the FL101 board uses C211 to hold its pin 4 momentarily low when Ever 5V is first applied. This resets Interface IC201/pin 18. After reset, a brief communication occurs between IC201 and IC202. A momentary light of the front panel blue Dolby Digital LED (D203) marks the end of the plug in communications and the unit shuts down. The plug in sequence is listed below: 1. 2. 3. 4. 5. 6. AC plug in Ever 5V is applied to Interface IC201/pin 16 X201 becomes active and stays active Red power off/standby LED comes ON. PCONT from Interface IC201/pin 24 goes high to power the set Ready pulse is output IC201/pin 78 as an interrupt line to IC202 to begin communications. It is difficult to see this low going interrupt pulse on a a scope, but it will light a scope's "triggered" LED. 7. IC601 transfers this "ready" (interrupt) information to System Control IC202 by using another interrupt signal from IC601/pin 155 (low going). The low forces IC202 to generate a chip select (CS1 or CS4) so the data can be transferred to IC202 on the parallel bus. 8. System Control IC202 sends chip select (difficult to see the low going pulse from pin 97), bit clock (low pulses from pin 78) and serial data (high pulses from pin 77) to Interface IC201. 9. IC201 acknowledges by lighting the Digital Dolby LED D203
10. Interface IC201 brings PCONT low, removing power to the set. Unit is now in standby and ready to be powered ON.
IC201 IC202 Communications Waveforms
The following sets of waveforms show this communication between IC201 and IC202. Notice that the Dolby Digital LED is turned ON only at the conclusion of the plug in communications. The LED does not light when there are incomplete communications.
PM3394, FLUKE & PHILIPS ch1 T 1 ch2
ch3
2 ch4
3
CH1!5.00 V= 4 CH2!2.00 V= CH3!5.00 V= CH4!5.00 V= CHP MTB 200ms- 0.40dv ch1+
Plug in Communications between IC201 / IC202 Name Channel 1 Channel 2 Channel 3 Channel 4 Time base PCONT Dolby Digital LED CS from IC202 Data from IC201 Location CN203/pin 1 D203/anode CN006/pin 3 CN006/pin 4 200msec/div. Voltage/div 5Vp-p 2Vp-p 5Vp-p 5Vp-p
The following second set of waveforms is taken of IC202 CS signal (ch 3) that is replying to IC201. Notice that the return clock (ch 3) and data (ch 4) from IC202 occur before IC201 turns the LED (ch 2) ON.
FR150 EVER 5V 5 CN201/ CN002 R274 2 IC051 1 IR RECEIVER 3 GRN R072 6 R071 7 RED EVER 5V 5 R221 3 S071 POWER R222 14 32 31 16 4 9 5
IC202 RESET PST9140 4 C211 3 D203 DOLBY DIGITAL R285 18 30 CN202/ CN006 SIN 72 5 6 3 14
5V MB85 BD. IC203 BUFFER SN74 HCT08 3 6 11 1 4 12 77 SO01 78 SC0 CSOL 97 4 43
3.3V
IC201 INTERFACE CONTROL M38857 MCHE206FP
SCLK 70 SBUSY1 76
69 70
S OUT
71
4 R044 2 R036
SRDY1 78 15 24
93 IC202 SYSTEM CONTROL 11 76 MB91101 R045 SI0 PFV CS4 CS1 7 10
CE
37 47 26 IC205 FLASH ROM MBM29 LV160
X201 4MHz
DISPLAY
PARALLEL BUS 142 22 141 CS1 CS4 XIF INT
PARALLEL BUS
FRONT PANEL BUTTONS S212-S218 12 2 1
FL101 BD.
R037 3.3V
3.3V P CONT. EVER 5V SRV902UC PWR BLK 5V CN202 CN001/
6 2 5 3.3V 5V
1 20 40
IC601 HGA CXD8788Q
POWER CONTROL
13DVD02 1154
6 22 99
18
19
PM3394, FLUKE & PHILIPS ch1 T 1 ch2
Power ON IC check sequence (not shown in the diagram) Chip Select Source 1. CS 1 - IC202/pin 10
2
Destination IC SRAM IC204 / HGA IC601 Flash ROM IC205 AV Decoder IC401 HGA IC601 AV Decoder IC401 ARP2 IC303 Servo IC701
ch3
ch4
2. CE IC202/pin 11 3. CS 3 IC202/pin 8 4. CS 4 IC202/pin 7 5. CS 2 IC202/pin 9 6. XCS IC601/pin 111 7. HCS - IC601/pin 118
3
CH1!5.00 V= 4 CH2!2.00 V= CH3!5.00 V= CH4!5.00 V= CHP MTB 200ms- 0.40dv ch1+
Plug in Communications between IC201 / IC202 Name Channel 1 Channel 2 Channel 3 Channel 4 Time base PCONT Dolby Digital LED Bit clock from IC202 Data from IC202 Location CN203/pin 1 D203/anode CN006/pin 6 CN006/pin 5 200msec/div. Voltage/div 5Vp-p 2Vp-p 5Vp-p 5Vp-p
When all the replies have been received, Interface IC201 is informed and IC201 keeps the unit powered ON (PCONT remains high). At the same time, IC201 turns on the front panel blue Dolby Digital LED. If a communications failure occurs and there is no acknowledgement signal to IC202 within three seconds of power ON, the unit will turn off. The PCONT signal (from IC201/pin 24) will go low and the player power is removed. The green power ON light changes back to red (standby mode).
Power ON
IC201 The power ON operation works much like a modern day computer. When the power ON command is received, Interface IC201 begins a boot up sequence using IC202 and IC205 to finish it. IC201 causes: · The red standby light to turn to green; · PCONT (at IC201/pin 24) to go high, powering the set; and · Communications with System Control IC202, continuing the power ON operation IC202 IC202 continues the power ON operation, retrieving start up information from the Flash ROM IC205. This start up information instructs IC202 to check each IC on the parallel bus and wait for an acknowledgement signal. At power ON, these ICs are polled in the order shown in the table:
Post Power ON Check
Therefore, if the blue Dolby Digital LED lights, communications have taken place and the unit remains ON. The next step is to determine if there is a disc present. The disc check sequence is: 1. Tray up and chucked chuck switch feedback 2. Sled moves to home position photosensor feedback 3. Sled moves outward no feedback (stepping motor) 4. Laser is turned ON momentarily while focus searching 5. Focus Search is performed FE and PI feedback signal 6. Sled moves outward further no feedback 7. Laser is turned ON and Search is performed again 8. Sled moves outward further no feedback 9. Laser is turned ON and Search is performed a third time 10. Sled moves inward to home photosensor feedback 11. Laser is turned ON and Search is performed a fourth time 12. Spindle motor rotates FG amp kick drive feedback 13. Display reads NO DISC. If an IC fails to receive the correct feedback from its sensors, System Control will instruct IC201 to enter standby (red front panel light).
FR150 EVER 5V 5 CN201/ CN002 R274 2 IC051 1 IR RECEIVER 3 GRN R072 6 R071 7 RED EVER 5V 5 R221 3 S071 POWER R222 14 32 31 16 4 9 5
IC202 RESET PST9140 4 C211 3 D203 DOLBY DIGITAL R285 18 30 CN202/ CN006 SIN 72 5 6 3 14
5V MB85 BD. IC203 BUFFER SN74 HCT08 3 6 11 1 4 12 77 SO01 78 SC0 CSOL 97 4 43
3.3V
IC201 INTERFACE CONTROL M38857 MCHE206FP
SCLK 70 SBUSY1 76
69 70
S OUT
71
4 R044 2 R036
SRDY1 78 15 24
93 IC202 SYSTEM CONTROL 11 76 MB91101 R045 SI0 PFV CS4 CS1 7 10
CE
37 47 26 IC205 FLASH ROM MBM29 LV160
X201 4MHz
DISPLAY
PARALLEL BUS 142 22 141 CS1 CS4 XIF INT
PARALLEL BUS
FRONT PANEL BUTTONS S212-S218 12 2 1
FL101 BD.
R037 3.3V
3.3V P CONT. EVER 5V SRV902UC PWR BLK 5V CN202 CN001/
6 2 5 3.3V 5V
1 20 40
IC601 HGA CXD8788Q
POWER CONTROL
13DVD02 1154
6 22 99
20
21
Communications Block
Both serial and parallel bus structures are used in the same unit of today's DVD players. The serial data bus is a simple way to provide communications between ICs. On one line, data is transmitted one bit after another to the next IC in 8, 16, 20, 24 or 32 bit groups. On another line, corresponding clock pulses accompany the bits of data. One clock pulse identifies each bit of data - this is why this line is also called a bit clock. Therefore, it takes 8, 16, 20, 24 or 32 clock pulses to receive a group of data in a serial bus. A parallel data bus is used when large amounts of data need to be transmitted in a shorter time frame. In the parallel bus, multiple data lines are used along with a clock line. When a single clock pulse is sent, the 8, 16, 20, 24 or 32 lines each simultaneously transmit a bit of data to the receiving IC. (Only 16 data lines are used here.) Therefore, it takes only one clock pulse to receive a group of data in a parallel bus. The parallel bus is used in processing video information (IC401) and in the disc playback servo (IC701) where large amounts of data must be handled quickly.
Parallel Data
The parallel data bus is much more complicated than the serial bus. It consists of address lines, data lines and a clock line. Just before data is transmitted from one IC to another, a location is designated using address lines. Then clock pulses are sent from the master IC202 to transfer the data into the receiving IC. When communications are bi-directional on the parallel bus, an additional line identified as write enable (WE) and/or read enable (RE) is used. These lines determine the direction of the data to or from the master IC. When there is no WE or RE line, the bi-directional data communication is preestablished first as read-data from the master micro. Write-data occurs afterwards.
Serial Data
The serial data bus connects several ICs and consists of two or three lines. Serial data is transmitted from one IC to another on a unidirectional line (arrows shown in one direction). This data is accompanied by a clock signal for a total of two lines in a unidirectional serial communication. The interface control IC201 and System Control IC202 communicate bidirectionally (arrows shown in two directions). Three lines are necessary when bi-directional transmissions are called. There is a data line for each direction. The additional clock signal makes a total of three lines for a bi-directional serial bus. The clock signal usually comes from the controlling micro, which in this case is System Control IC202. System Control IC202 communications with Interface IC201, EEProm IC201 and DSP IC501 are bi-directional. System Control communications to the Digital to Analog Converters (DAC) IC902, IC905-7 are unidirectional.
CS FROM IC601
CS FROM IC202
CS FROM IC202
CS FROM IC202
CS FROM IC601
IC201 INTERFACE CONTROL
IC201 4k EEPROM
IC501 AUDIO DSP
IC902 AUDIO 2 CH DAC
IC905 DAC FRONT
IC906-7 DAC REAR, CENTER
CS CHIP SELECTS
SERIAL BUS CS FROM IC202 CS FROM IC202 CS FROM IC202 CS FROM IC601
CHIP SELECTS
IC202 SYSTEM CONTROL
IC205 FLASH
IC204 SRAM
IC601 HGA
IC701 SERVO
PARALLEL BUS
CS FROM IC202
IC401 AV DECODE
IC303 ARP2
CS FROM IC601
COMMUNICATIONS BLOCK
6DVD02 1149
6 23 99
22
23
Serial Data Communications
A close examination of the serial bus structure shows there are two serial buses. Both are active as long as the set is ON. Serial Bus 0 Serial Bus 1
IC202/pins 76 and 77 to occur. The entire operation is similar to someone working when interrupted by a doorbell. When he is ready, he will answer the door. Afterwards he returns to his work in the house or elsewhere. The IC201 to IC202 communications sequence is: System Control IC202 and Interface IC201 Data Transfer Sequence
Name of Signal 1. SRDY (ready) 2. CSOL (chip select) 3. SC0 (clock) 4. SI0 (data) 5. SO0 (data) 6. CSOL (chip select) Signal Source IC201pin 78 IC202/pin 97 IC202/pin 78 IC201/pin 71 IC202/pin 77 IC202/pin 97 Signal purpose Request communications Communications window (active low) Serial clock for data User commands Display update Communications ends (returns high)
Serial Bus 0
Bus 0 is used for bi-directional communications between: · System Control IC202 · Interface IC201 · EEProm IC201 System Control IC202 is the master IC. It sends and receives data on the serial data in (SI0, at IC202/pin 76) and out (SO0, at IC202/pin 77) lines. The data is always accompanied by serial clock (SC0, at IC202/pin 78) from IC202. There are always communications between these two ICs as long as there is power applied.
EEProm IC201
During playback or when playback is started, System Control IC202 retrieves information held in EEProm IC201. IC201 holds servo data and stores some disc parameters, such as how many information layers are on the disc. Some of this data is visible in the test mode. Bi-directional communications between System Control IC202 and EEProm IC201 is accomplished using: · Two single direction serial data lines (SO0 and SI0) · Clock pulses from IC202/pin 78 · Chip Select signal from IC601/pin 23 Periodically in IC202's routine, EEProm IC201is chip selected (when pin 3 is brought low). When this occurs, data is transferred between the ICs on the data lines (SO0 and SI0).
Interface IC201
System Control IC202 has the continuous task of transferring display information to the Interface IC201. The Interface IC201 must inform System Control IC202 that there is a new command such as play or stop. Communications begin when Interface IC201/pin 78 outputs a low going "ready" pulse. In this IC the ready command is more like an interrupt command. This low going pulse is received by IC601/pin 22, which is used as an expansion port to access System Control IC201 via the parallel bus. The interrupt input is periodically checked within IC202's program. When found, IC202 will enter a subroutine and acknowledge IC201's request to send data for processing. System Control IC202 acknowledges the interrupt signal by outputting two signals: a low chip select signal from pin 97 and a clock signal from pin 78. This allows for data communications on the SI0 and SO0 lines at
FL101 BD.
MB85 BD.
3 IC201 CS 4k EEPROM AK6440AF SC0 SO0 SI0 4 CN202/ CN006 SIN 1 S OUT 1 72 71 5 SO0 4 SI0 6 SC0 5 6
62 IC501 CS AUDIO DSP CDX1901R SC1 SI1 SO1 66 63 61
DISPLAY
CSO 28 IC902 AUDIO 2 CH DAC CXD8799N SC1 27 SO1 26
IC905 FRONT CS2 28 L/R DAC CXD8799N SC1 SO1 27 26 IC906 27 SC1 CS2 28 REAR L/R DAC 26 SO1 CXD8799N
SC1 70 IC201 INTERFACE CONTROL M38857MCH S BUSY SRDY 78 76
SERIAL BUS 1 IC601 HGA CXD8788Q 141 142 XDACS3 97 XDACS2 96 OICS 28 PARALLEL BUS XIFINT XECS 23 22
76
77
78 SC0
79 80 89 SI1 SO1 SC1 10 7
CS1 CS4
SI0 SO0
IC907 CS3 28 27 SC1 CENTER WOOFER DAC 26 SO1 CXD8799N
IC202 SYSTEM CONTROL MB91101PFV
XFMCS 3 2 XIF BUSY 97 CSOL
PB3 PB2
99 98
SERIAL DATA COMMUNICATIONS
4DVD02.DWG 1144
6 23 99
24
25
Serial Bus 1
Bus 1 is used for communications between: · System Control IC202 · Audio DSP IC501 · Audio 2 channel IC902 · Front, Rear, and Center D/A converters IC905 to IC907 System Control IC202 is the master IC. It sends and receives data on the serial data in (SI1, at IC202/pin 79) and out (SO1, at IC202/pin 80) lines. The data is always accompanied by serial clock (SC1, at IC202/pin 89) from IC202. There are always communications present at IC202/pins 79,80 and 89 as long as there is power applied just like in serial bus 0.
IC Name System Control Interface EEProm Audio DSP Audio 2 channel D/A Converter Front, Rear, Center, D/A Converter
IC Function Number IC202 IC201-FL101 Bd IC201-MB85 Bd IC501 IC902 IC905 - IC907 Function Main Micro Accepts user commands (play, open tray, next, etc) Stores servo info Delays (echoes) for speaker effects D/A Converter for analog audio D/A Converter for 5.1 AC-3 signal.
Audio DSP IC501
Bi-directional communications between System Control IC202 and IC501 is similar to that with EEProm IC201. Communications between System Control IC202 and Audio DSP IC501 are accomplished using: · Two serial data lines (SO1 and SI1) · Clock from IC202/pin 89 · Chip Select from IC601/pin 28 Periodically in IC202's routine, Audio DSP IC501 is chip selected. When the chip select pin 62 line is brought low, data is transferred between the ICs on the data lines (SO1 and SI1).
Audio 2 Channel D/A Converter IC902 Audio Front, Rear, and Center D/A Converters IC905 - IC907
System Control IC202 communicates with the remainder of the ICs on the serial bus 1 lines in a unidirectional manner. Each one of these D/A Converters has an individual chip select line from IC601. The SO1 data line from IC202/pin 80 is common to the D/A Converters. Data applies only to the D/A Converter when its chip line is low. The data as always is accompanied by bit clock from IC202/pin 89.
FL101 BD.
MB85 BD.
3 IC201 CS 4k EEPROM AK6440AF SC0 SO0 SI0 4 CN202/ CN006 SIN 1 S OUT 1 72 71 5 SO0 4 SI0 6 SC0 5 6
62 IC501 CS AUDIO DSP CDX1901R SC1 SI1 SO1 66 63 61
DISPLAY
CSO 28 IC902 AUDIO 2 CH DAC CXD8799N SC1 27 SO1 26
IC905 FRONT CS2 28 L/R DAC CXD8799N SC1 SO1 27 26 IC906 27 SC1 CS2 28 REAR L/R DAC 26 SO1 CXD8799N
SC1 70 IC201 INTERFACE CONTROL M38857MCH S BUSY SRDY 78 76
SERIAL BUS 1 IC601 HGA CXD8788Q 141 142 XDACS3 97 XDACS2 96 OICS 28 PARALLEL BUS XIFINT XECS 23 22
76
77
78 SC0
79 80 89 SI1 SO1 SC1 10 7
CS1 CS4
SI0 SO0
IC907 CS3 28 27 SC1 CENTER WOOFER DAC 26 SO1 CXD8799N
IC202 SYSTEM CONTROL MB91101PFV
XFMCS 3 2 XIF BUSY 97 CSOL
PB3 PB2
99 98
SERIAL DATA COMMUNICATIONS
4DVD02.DWG 1144
6 23 99
26
27
Parallel Data Communications
There are six ICs that communicate with System Control IC202 on the parallel bus: ICs on the Parallel Bus
Name 1. Flash ROM 2. Hybrid Gate Array 3. SRAM 4. AV Decoder 5. ARP2 6. Servo DSP Number IC205 IC601 IC204 IC401 IC303 IC701 Purpose Start up program instructions Expansion port for System Control IC202 IC202's local memory Audio (AC-3) and Video (MPEG 2) decoder CD/DVD data processing & separation Analog servo control
Chip Select Signals from IC202 (active low) CS Source 1. CS 1 - IC202/pin 10 2. CE IC202/pin 11 3. CS 2 IC202/pin 9 4. CS 4 IC202/pin 7 5. CS 3 IC202/pin 8 6. XCS IC601/pin 111 7. HCS - IC601/pin 118 Destination SRAM IC204 / HGA IC601 Flash ROM IC205 AV Decoder IC401 HGA IC601 AV Decoder IC401 ARP2 IC303 Servo IC701 Pulse Width/Polarity 0.56us / 0.9usec/0.56us / 0.7 & .26 usec/0.3usec/1.2usec/0.3usec/0.3usec/-
Chip Select Waveforms The following waveforms show the chip select signals going to the S RAM IC204 (ch 1) and AV Decoder IC401 (ch 2 and 3). They can be compared to the D1 data (ch 4) to show that the chip select (ch 1-3) signals occupy more than one bit clock interval. Note that on each of the CS 1 (ch 1) and CS 2 (ch 2) lines, two different pulse widths are used. These waveforms were taken with the unit on without a disc being played.
PM3394, FLUKE & PHILIPS ch1
Bi-directional communications between these ICs are accomplished using the following lines; however, not all ICs use the last three lines: · · · · · · Chip Select from IC202 Address from IC202 Data (bi-directional) Clock from IC202 Interrupt from destination IC Read/Write from IC202
ch2
1
ch3 T 2 ch4
3
Chip Select Line
CH1!5.00 V=
System Control IC202 systematically polls each IC on the communications bus with a chip select signal. This low or high going pulse identifies the individual destination IC that System Control wants to communicate with. The chip select output sequence is listed below:
Channel 1 Channel 2 Channel 3 Channel 4 Time base
CH2!5.00 V= CH3!5.00 V= 4 CH4!2.00 V= ALT MTB5.00us- 1.34dv ch2-
Chip Select signals from IC202 (active low) Name CS = CS1 CS = CS2 CS = CS3 Data = D1 Location IC202/pin 10 IC202/pin 9 IC202/pin 8 IC202/pin 26 5usec/div. Voltage/div 5Vp-p 5Vp-p 5Vp-p 2Vp-p
INTERRUPT
196 99 XCS3
198
WAIT/INTERRUPT IC601/72 IC402 16M SRAM KM416S1020 18 CS ADDRESS, WE, CAS, RAS, DATA 18 CS IC403 16M SRAM KM416S1020
IC205 16M FLASH MBM29LV160B 26 CE A1-20 DO-15
98 XCS2 SDCS OON 121 IC401 AV DECODER CXD1930Q SDCS1ON 120
MB85 BD.
95
8
9
11 AO-21 DO-15
CS3 CS2 CE IC202 SYSTEM CONTROL MB91101PFV CS4 CS1
AO-21 DO-15
IC304 16M DRAM KM416V1200 OE 33 17 DATA ADDRESS 152 148 XMWR IC303 ARP2 CXD8784R 151 RAS 150 CAS WE 18 34 35
ADDRESS & DATA PARALLEL BUS A1-16 DO-15 AO-5 A17-19 D8-15 A0-1 DO-7 AO-7 D8-15
7 10 SI SO SC 6 IC204 1M SRAM IDT71VD16S20 CS 141 142 INTERRUPTS SERIAL BUS TO IC201 IC501 IC902 IC905-7 INTERRUPTS IC601/PIN IC202 PIN 19 PIN 88 PIN 97 PIN 157 PIN 155 PIN 156
IC601 HGA CXD8788Q CS1 CS4
118
3
HCS IC701 SERVO DSP CXDP791Q 128 XOE
XCS1
115 107 111
INTERRUPT 83 84 XCS
ARP INTERRUPT
PARALLEL DATA COMMUNICATION
5DVD02 1146
6 29 99
28
29 Address Lines
Direct Addressing The parallel bus in this unit contains multiple address lines to designate the destination of the data within the IC that is chip selected. These address lines are labeled A0-21 from master IC202. Address lines are shared by some destination ICs and none use all 22 address lines. Column and Row Addressing IC401 and IC303 control three memory ICs. A memory IC has more data locations than can be accessed by one set of address lines directly. CAS and RAS lines are used to expand that number. Memory locations can be addressed like cells in a multiplication table. For example, when CAS is active, the address lines identify a column of memory locations. Then when RAS is active, the address lines now pin point the memory cell by identifying the row it is in.
Read / Write Lines
Bi-directional communications on the parallel bus may use a single write enable (WE) / read enable (RE) line from the master IC202. During the chip select interval, this line determines the direction of the data to or from the master IC202. A high is one data direction while a low is the other. In some systems, two individual read and write lines are used. When there are no interrupt, WE or RE lines, communications are preestablished to share the time to read and write during the chip select interval.
Communications from IC202 to Other ICs
IC202 can only send data to another IC after it chip selects the IC and supplies internal address and bit clock to carry the data. Consequently, a list of communications from IC202 would consist of the following: · Chip Select (usually active low) · Write control line (usually active low) · Address data (Identifies the registers/memory location in the destination IC to put the data) · Bit clock · Data
Data and Clock Lines
Serial data communications involve the fewest number of connections between ICs. When speed is important, the parallel data structure is used. Instead of having a single data line between the communicating ICs, there are 8 or 16 lines that carry data. As in the serial bus structure, on a separate line the parallel bus uses a bit clock signal. When a single bit clock pulse occurs, the entire group of 8 or 16 bits of data is transferred at once. Therefore, the data transfer rate of the parallel bus system is much faster than the serial bus.
Communications from Another IC to IC202
If another IC has finished a task and wants to reply with sensor information, it must request the service (signals) above to return data. Once the destination IC sends an interrupt pulse, IC202 will reply with all the signals listed above so the other IC can send data to IC202. The Read control line (from IC202) is active instead of the write line in the date reply to IC202. All or some of the address locations are checked by IC202. The number is dependent upon the firmware built into Syscon IC202. For example, IC202 may request the Servo IC701 perform a sled movement to home task. Later IC202 receives an interrupt from IC701. Instead of checking all of IC701's address locations, it will just access the one that contains the sled at home data.
Interrupt Lines
Interrupt signals are used when the destination IC has carried out the instruction given to it and wants to reply with resultant data (such as task completed or information such as AC-3 detected). A destination IC can not generate a clock or chip select lines to send data to the master IC202. The destination IC must send an interrupt signal to the master IC202 requesting attention. When the master IC202 is ready, it will send chip select and clock signals, allowing the destination IC to send data.
INTERRUPT
196 99 XCS3
198
WAIT/INTERRUPT IC601/72 IC402 16M SRAM KM416S1020 18 CS ADDRESS, WE, CAS, RAS, DATA 18 CS IC403 16M SRAM KM416S1020
IC205 16M FLASH MBM29LV160B 26 CE A1-20 DO-15
98 XCS2 SDCS OON 121 IC401 AV DECODER CXD1930Q SDCS1ON 120
MB85 BD.
95
8
9
11 AO-21 DO-15
CS3 CS2 CE IC202 SYSTEM CONTROL MB91101PFV CS4 CS1
AO-21 DO-15
IC304 16M DRAM KM416V1200 OE 33 17 DATA ADDRESS 152 148 XMWR IC303 ARP2 CXD8784R 151 RAS 150 CAS WE 18 34 35
ADDRESS & DATA PARALLEL BUS A1-16 DO-15 AO-5 A17-19 D8-15 A0-1 DO-7 AO-7 D8-15
7 10 SI SO SC 6 IC204 1M SRAM IDT71VD16S20 CS 141 142 INTERRUPTS SERIAL BUS TO IC201 IC501 IC902 IC905-7 INTERRUPTS IC601/PIN IC202 PIN 19 PIN 88 PIN 97 PIN 157 PIN 155 PIN 156
IC601 HGA CXD8788Q CS1 CS4
118
3
HCS IC701 SERVO DSP CXDP791Q 128 XOE
XCS1
115 107 111
INTERRUPT 83 84 XCS
ARP INTERRUPT
PARALLEL DATA COMMUNICATION
5DVD02 1146
6 29 99
30
31
Mechanism
Disc Tray and Laser Platform Position
Tray Movement The loading motor moves the disc tray in or out. Without the tray, the loading motor's shaft is seen on the right side.
Tab underneath
Teeth Pawl Channel
Mechanism
Bottom Tab
Tray Bottom
Loading Motor
Top View The rotation of the motor turns the three gears to its left. The final gear at the far-left mates with the teeth on the tray. Motor direction determines tray movement. Electrical feedback to stop the motor is an opened/closed electrical switch under the white activator arm. The tray at the end position pushes the arm. Platform Position When the loading motor drives the tray inward, a channel in the tray moves a spring-loaded pawl into the middle rotating gear. The gear's rotation continues to slide this pawl to the left. The front part of this pawl that faces the laser assembly platform lifts a pin connected to the platform. As the pawl slides left, the platform is lifted up. The pawl in the tray's channel prevents the tray from sliding out. No Power Tray Removal From the Bottom A spring-loaded pawl under the tray locks the tray closed. The bottom part of this pawl can be accessed from under the mechanism assembly.
1. Unplug AC power and press the power button to discharge the power supply capacitors. 2. At the mechanism top, remove the two screws and the mechanism's top cover. The cover acts as a tray stop. Cover removal allows the tray to be pulled out later. 3. At the rear of the mechanism remove the rear black screw for finger clearance. 4. Place your finger under the mechanism. Push the slider's bottom tab. 5. At the bottom of the assembly, slide the tab toward the center of the mechanism. This lowers the laser (unchucks), freeing the tray. 6. From the top of the mechanism, slide the tray out
No Power Tray Removal From the Top 1. Remove the two screws and the mechanism's top cover to expose the tray and laser platform. 2. Locate the top pawl under the tray by inserting a small screwdriver between the platform and tray. The pawl is just in front of the spindle motor.
Incline Gear
The stepping motor then increments the incline gear to the middle position. This position is stored in EEProm IC201 and updated during the test mode automatic adjustments. During DVD playback, if the RF level fluctuates, the tilt motor rotates until the RF level stabilizes. The incline gear remains at the middle position during CD playback.
Sled Position
3. Slide the pawl to the right to lower the platform and free the tray. 4. Remove the tray. The sled motor moves the laser assembly away from home position at the spindle motor. The laser assembly`s home position is marked as it blocks the light to a photo detector sensor. This picture shows the photosensor location under the sled motor shaft.
Tilt Motor
Purpose Maximum RF output level occurs when the laser beam is perpendicular to the disc's information layer. The tilt motor raises one end of the laser platform so its beam is perpendicular to the disc. Access and Operation The tilt motor is a stepping motor located next to the incline gear. At power OFF, the incline gear lowers one end of the laser platform. At power ON, the incline gear raises the platform to full height.
Sled Sensor
32
33 Focus Coil
Voltage applied to the focus coil that is connected to the lens opposes a stationary vertical magnet. The force generated moves the objective lens up or down to focus the laser spot on the information layer of the disc.
F Coil Magnet Lens
Laser
A ribbon cable connects the laser assembly to its circuit board. A circuit board connector clamps the assembly's ribbon cable. Free the cable from the connector by pulling the connector tabs on both sides 1mm toward the cable. The connector will slide out.. In this picture the left side of the cable is free from the connector.
Protection Spot
Left connector unlocked
Ribbon Cable
In a replacement laser assembly, a spot of solder is placed on the foils of the ribbon cable (see the focus coil picture) to protect the laser diode from static damage that will shorten its life. Remove the solder spot AFTER connecting the laser assembly cable to the circuit board.
Power ON Mechanical Sequence No Disc
Operation 1. Power On button is pressed. Purpose IC202 retrieves start up program from Flash ROM IC205. After the ICs are checked for basic communications, IC202 instructs Servo IC701 to start the mechanical sequence. The servo parameters are stored in EEProm IC201.
2. Disc tray is closed (if open) and placed into a Clamps a disc on the spindle motor platform. chucked position. 3. Sled moves the optical assembly to home position. 4. Tilt Motor resets laser platform to mid position. 5. Sled moves outward quickly, then slows down. Sled starting point. Presets the laser beam perpendicular to the disc for max RF. Optical assembly is moving under the disc's information area.
6. Laser is turned ON momentarily during focus Looks for a disc. Reflected light identifies a disc. search. 7. Focus search one time. 8. Sled increases speed moving further outward. 9. Sled slows down 10. Laser is turned ON momentarily during focus Looks for a disc using reflected light. search. 11. Focus search. Looks for the disc's information laye. 12. Sled again moves quickly outward then slows, Third attempt to locate a disc. followed by laser and focus search. 13. Sled moves inward to home and stops. 14. Laser is turned ON momentarily. 15. Focus search. 16. Spindle motor rotates. 17. Display reads NO DISC (laser is off) User feedback Disc check at home position. Final attempt to identify a disc. Optical assembly lens moves up then down, looking for the disc's information layer. Sled slows down in a second attempt to locate a disc.
34
35
Power ON Mechanical Sequence DVD Disc
Operation 1. Power On button is pressed. Purpose IC202 retrieves start up program from Flash ROM IC205. After the ICs are checked for basic communications, IC202 instructs Servo IC701 to start the mechanical sequence. The servo parameters are stored in EEProm IC201.
2. Disc tray is closed (if open) and placed into a Clamps a disc on the spindle motor platform. chucked position. 3. Sled moves the optical assembly to home position. 4. Tilt Motor resets laser platform to mid position. 5. Sled moves outward quickly then slows down. 6. Laser is turned ON momentarily during focus search. 7. Focus search one time. 8. Sled stops moving when a disc Is identified. 9. Spindle motor rotates. 10. Laser is turned ON a second time. 11. Focus search. 12. Focus servo is turned ON. 13. Tracking begins. 14. Tilt motor servo starts. 15. Disc PB begins. Display shows elapsed time. Rotates the disc. To begin playback. Focuses on the first information layer on the disc. Maintains focus on the layer. Keeps the laser beam at the information track's center. Maintains high RF level. Playback verification. Sled starting point. Presets the laser beam perpendicular to the disc for max RF. Optical assembly is moving under the disc's information area. Looks for a disc. Reflected light identifies a disc. Optical assembly lens moves up then down, counting the number of disc layers.
NOTES
36
37
Tray Motor Drive
The opening and closing of the disc tray involves two micro controllers, one gate array IC and a driver IC that powers the loading motor. The loading motor is powered by pressing the front panel open/close tray button S212. The following occurs when the tray button is pressed: 1. Interface Controller IC201 recognizes the tray button 2. IC201 turns on the display to show the command entered 3. IC201 communicates with System Control IC202 4. IC202 instructs Hybrid gate array IC601 to issue a drive command 5. Driver IC802 translates the command into loading motor current 6. The tray position switch returns information to IC201 (via IC601) The tray position switch information is sent to Interface IC201 via IC202 to complete the tray open cycle. The "OPEN" display disappears when the cycle is complete. This also sets the latch, permitting the tray to be closed the next time the tray button is pressed.
2. IC601 sends this information along the parallel bus to IC202. This occurs when IC601/pin 142 is periodically (chip) selected using CS1 or CS4 to send and receive data. Two chip select lines are used in different parts of the Hybrid Gate Array IC601. 3. When IC202 is ready, it outputs a low chip select signal (ch 4) from pin 97 to Interface IC201/pin 76. IC203, in-between IC201 and IC202, translates the signal to a 5-volt level for IC201. 4. IC202 simultaneously sends serial clock from pin 78 to IC201/pin 70 (ch 3) during the chip select interval. 5. Data is transmitted from IC201/pin 71 to IC202/pin 76 (ch 2). As seen below, the group of waveforms on the left in "tray 1" are of the serial communications between IC201 and IC202 when the DVD player is on. It consists of a low going interrupt pulse used for triggering at channel 1. This is better seen in the tray 2 waveform group taken at an expanded time base. Shortly after interrupt (ch 1), clock (ch 3) and a chip select (ch 4) pulse appear. Then data (ch 2) is transmitted to IC202.
PM3394, FLUKE & PHILIPS
PM3394, FLUKE & PHILIPS
Interface Controller IC201 Recognizes the Tray Button
Pressing the tray button S212 reduces the voltage at IC201/pin 5 from +5V to +0.65V.
ch1 T 1 ch2
ch1 T 1 ch2
ch3
ch3
ch4
2
ch4
2
IC201 Turns On the Display
Once the command is recognized by Interface Control IC201, the ND201 fluorescent display digits and segments lines are multiplexed with a LOW to illuminate the word OPEN.
=A G 3 3 CH1!5.00 V= CH2!5.00 V= 4 CH3!5.00 V= CH4!5.00 V= CHP MTB10.0ms- 0.72dv ch1CH1!5.00 V= CH2!5.00 V= 4 CH3!5.00 V= CH4!5.00 V= CHP MTB 200us- 0.72dv ch1-
IC201 Communicates with System Control IC202
At almost the same time the display is lit, serial communications occurs with System Controls IC202. The serial communications are always present as long as the DVD player is on, but an additional group of data is output when the S212 tray button is pressed. Serial communications in this DVD player occur in the following sequence: 1. IC201 starts it with a single low (almost undetectable) interrupt pulse from IC201/pin 78 (ch 1). Resistors R036 and R037 reduce the signal for IC601. The input voltage should never exceed the IC's supply voltage.
Waveform = tray 1
Waveform = tray 2
Waveforms Tray 1 and 2 = DVD Player Powered ON Name Location Voltage/div Channel 1 XIFint(interrupt) CN006/pin 2 5Vp-p Channel 2 Serial data (to IC202) CN006/pin 4 5Vp-p Channel 3 Serial clock (SCO) CN006/pin 6 5Vp-p Channel 4 Chip select (CSOL) CN006/pin 3 5Vp-p Time base Tray 1 = 10msec/div. Tray 2 = 0.2msec/div
5V EVER 5V S213-S218 FRONT PANEL BUTTONS R211 R213 R212 SBUSY1 76 IC201 16 INTERFACE CONTROL CN202/ M38857 CN006 MCH SIN 72 5 5 AN1 SCLK 70 6 3 14 IC203 BUFFER SN74 HCT08 3 6 11 1 4 12 77 SO01 78 SC0 CSOL 97 MB85 BD. MS-29 BD.
3.3V
4 43 69 IC202 SYSTEM 93 CONTROL MB91101 PFV 70 28 VCC 22 R812 R811 23 R866 R814 24 R865 9 2.3V MUTE S001 TRAY CLOSED 6 4 OPEN + DRIVER 2 IC802 1/3 BA5983FP CN011/ CN001 1 M TRAY LOADING M+12V
ON/OFF S071 (FR101 BD.) TRAY OPEN/CLOSE S212 DIGITS
S OUT
71
4 R044 R045 2 R036
SI0 76
CS4 7
SRDY1 78
CS1 10
PARALLEL BUS SEGMENTS ND201 FLUORESCENT DISPLAY
FL101 BD.
1.6V REF 142 141 92 R813 3.3V IC803/1 LD 22 CS4 2.5V REF R832 MP/ R037 CS1 XIF IC803/7 OMP D803 3.3V INT LDMM LDMM 91 1 R004 63 20 O