Text preview for : T118B(LED)_AI_64LQFP_v3.pdf part of Terawins T118B Video Display Controller
Back to : T118B(LED)_AI_64LQFP_v3.p | Home
T118B Advanced Information-Confidential P/N-T118B-Rev01
Copyright by Terawins, Inc. Advanced Information Version 1.0
Nov 12, 2006
T118B Video Display Controller
1
T118B Advanced Information-Confidential P/N-T118B-Rev01
Copyright by Terawins, Inc.
Table of Contents
1 INTRODUCTION .......................................................................................................................................................... 3 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 4.1 4.2 4.3 4.4 5 6 7 8 9 FEATURES ................................................................................................................................................................. 3 GENERAL DESCRIPTION ............................................................................................................................................ 4 APPLICATIONS ........................................................................................................................................................... 4 SYSTEM ARCHITECTURE ........................................................................................................................................... 5 SYSTEM CONFIGURATIONS ........................................................................................................................................ 6 PINOUT DIAGRAM ..................................................................................................................................................... 7 PIN DESCRIPTION ...................................................................................................................................................... 8 I²C COMMAND PROTOCOL ...................................................................................................................................... 10 ANALOG FRONT END .............................................................................................................................................. 12 Y/C SEPARATION AND CHROMA DECODER ............................................................................................................. 12 DIGITAL COLOR TRANSIENT IMPROVEMENT (DCTI) .............................................................................................. 14 DIGITAL LUMINANCE TRANSIENT IMPROVEMENT (DLTI) ...................................................................................... 15 FIR SCALER ............................................................................................................................................................ 15 BLACK-LEVEL EXTENSION (BLE)........................................................................................................................... 16 COLOR SPACE CONVERTER ..................................................................................................................................... 16 GAMMA CORRECTION ............................................................................................................................................. 17 OSD........................................................................................................................................................................ 18 TCON ..................................................................................................................................................................... 30 ADC REGISTER SET ................................................................................................................................................ 33 PICTURE ENHANCEMENT REGISTER SET ................................................................................................................. 44 SCALING REGISTER SET .......................................................................................................................................... 46 COLOR SPACE CONVERTER REGISTER SET .............................................................................................................. 52 OSD REGISTER SET ................................................................................................................................................ 55 LCD OUTPUT CONTROL REGISTER SET .................................................................................................................. 56 TCON REGISTER SET.............................................................................................................................................. 69 Y/C SEPARATION AND CHROMA DECODER REGISTER SET...................................................................................... 74 DIGITAL I/O PAD OPERATION CONDITION .............................................................................................................. 83 AC CHARACTERISTICS ............................................................................................................................................ 84 ANALOG PROCESSING AND A/D CONVERTERS ........................................................................................................ 84 ABSOLUTE MAXIMUM RATING ............................................................................................................................... 84
THEORY OF OPERATIONS..................................................................................................................................... 10
REGISTER DESCRIPTION....................................................................................................................................... 33
ELECTRICAL CHARACTERISTICS...................................................................................................................... 83
PACKAGE DIMENSIONS ......................................................................................................................................... 85 ORDERING INFORMATION ................................................................................................................................... 85 REVISIONS NOTE...................................................................................................................................................... 86 GENERAL DISCLAIMER ......................................................................................................................................... 86 CONTACT INFORMATION ..................................................................................................................................... 86
2
T118B Advanced Information-Confidential P/N-T118B-Rev01
Copyright by Terawins, Inc.
1 Introduction
1.1 Features
Integrated high efficiency DC-DC power conversion unit for gate and source drivers reduces energy consumption - Integrated LCD backlight inverter drive unit supports LED typed backlight - Software adjustable lamp dimming Color Management - Coef Programmable YCbCr-to-RGB Color Space Converter - Independent RGB Gamma Correction Built-in On Screen Display Engine - 3K-word OSD SRAM memory - 1K-word Built-in font ROM - Supports font or bitmap modes - Supports character blinking, overlay, shadow and border functions - Fully programmable character mapping - Supports alpha blending & Zoom-in/Zoomout function - Optional fonts can be stored in off-chip serial EEPROM Versatile VBI Data Decoder - Supports Close Caption, Wide Screen Signalling and Teletext Crystal Oscillator Circuit - Direct interface to a (27.0MHz or other frequency) Crystal - Also provide a buffered clock output for external Micro-controller Digital Test Pattern Generator - Programmable standard & special panel burn-in test patterns - Support special border frame blocking mode Independent Display Phase Lock Loop - Generates pixel clock output to panel - Supports free run OSD mode - Spread spectrum clock Serial Bus Interface - Supports 2-wire (normal speed) Pulse Width Modulation Outputs Design For Testability - Scan chain insertion - Separated analog & digital test modes Power Supply: +1.8V & +3.3V Package: 64-pin LQFP
Cost Effective Highly Integrated Triple ADC + + 2D Video Decoder + OSD + Scaler + TCON - Integrates 9-bit Analog to Digital Converters (ADC) & Phase Locked Loop (PLL) - Scaler supports 2-D adaptive intra-field deinterlacer and non-linear 16:9 aspect ratio. - Requires no external Frame Buffer Memory for deinterlacer. - Advanced On Screen Display (OSD) function - Programmable Timing Controller (Tcon) for Car TV applications - Multi-standard color decoder with 2D adaptive comb filter - Innovative and flexible design to reduce total system cost Triple 9-bit Analog to Digital Converters (ADC) 27 MSPS Conversion Rate - Built-in Pre-amp, mid-level & ground clamp circuit - Automatic Clamp Control for CVBS, Y/C and YPbPr - Programmable Static Gain Control or Automatic Gain Control for CVBS ,Y/C or YPbPr - Max Input configuration up to 6xCVBS, 2xSvideo and 2xCVBS or 1xCVBS, 1xS-Video and 1xYPbPr Digital Video Enhancement Separate Luminance and Chroma Enhancer - Y Supports Luminance Peaking, DLTI, Black Level Expansion, Contrast and Brightness adjustment - C Supports DCTI, Saturation and Hue adjustment. Advanced Scaling Engine Two Dimensions FIR Scaler - Coefficient based sharpness filters - 2-D edge enhancement - Independent vertical and horizontal scaling ratio - 16:9 Non-linear Aspect ratio - Cell-based scaling to detail horizontal image pixels LCD Interface - Provides 256-entry TBL Gamma correction for panel compensation - Supports image pan functions - Programmable Timing Controller - Built-in software adjustable VCOM voltage - 5.0v RGB Triple DAC output or Digital Serial RGB
3
T118B Advanced Information-Confidential P/N-T118B-Rev01 1.2 General Description
Copyright by Terawins, Inc.
The T118B is a highly integrated All-in-one Visual Processor that provides major cost saving solution for the portable applications. T118B has built-in high performance dual ADCs (support YCbCr), TCON, Triple DACs, Scaling Machine with sophisticated upscaling and downscaling algorithms.
The Innovative integrated "Frame-Buffer-Less" Deinterlacer can significantly reduce system cost. The T118B also integrates On Screen Display engine with 3K-words of font RAM and built-in 1K-words of font ROM. The device can interface to an external microcontroller through 2-wire serial bus interface.
1.3
Applications
1. 1.8-inch to 10-inch portable DVD or in-car TV 2. Progressive CRT TV
4
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 1.4 System Architecture
T118B Block Diagram
2D-Adaptive Comb Filter
Copyright by Terawins,
ADC ADC ADC
Analog Front End Control
Input Sample Rate Converter
Y/C Separation
U/V Demodulation
YCbCr Post-filtering
Line Buffer Format Detection Line Buffer Line Buffer Line Buffer
Input Capture
Scaler Peaking
Y
DLTI
Y
Contrast / Brightness
Line Buffer
CbCr
DCTI
CbCr
Saturation / Hue
Line Buffer Line Buffer Line Buffer
Black Level Expansion
PT_GEN
CSC Dither
LCD Out Control
Gamma
+ Timing Gen
Pin MUX
DAC DAC DAC
RSTB
SCAN TEST LOGIC
2-Wire Slave
OSD RAM
OSD
Display PLL
TCON
DC-to-DC Converter LED
Figure 1-1 System Architecture
5
XCLKO
XCLKI
SCAN_MODE
SDA, SCL
XCLK2MC
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
© Copyright 2006 Terawins, Inc.
Copyright by Terawins,
1.5
System Configurations
CVBS
Y
DAC Red Data
S-VIDEO
C
T118B
TV Tuner
Y Pb Pr
DAC Green Data
Video Display Controller
DAC Blue Data
TCON Signals
Component
HV DC-DC, BL Dimming
TFT-LCD
8051 MCU
Figure 1-2 System Configuration
6
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 1.6 Pinout Diagram
VS18PL L VD33PWM/ VD33DAC VCOMDC VCOMAMP VBFG RSET IOR IOG IOB VS33DAC VD5A GND VDD33 STV2/sD7 STV1/sD6 GOE/sD5
Copyright by Terawins,
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VEA CSS VFB CEXT VPWM VEAL VFBL VPWML CSSL CEXTL VIsenL VIsen NC VS33PWM VD33ADC1/VD33ADC2 VS33ADC1/VS33ADC2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
GCLK/sD4 LP/OEH/sD3 Q1H/sD2 CPH3/sD1 CPH2/sD0 GND VDD18 CPH1 DEN/STH2 VSO/STH1 VDD33 GND HSO/POL/VCOM UD RL PWM2
AY1 AY0 ACR1 ACR0 ACB1 ACB0 GND VDD18 RSTB SDA/IICA3 SCL CPUINT XTALI XTALO XCLK2MC PWM1
V1.0
Figure 1-3 Pinout Diagram
© Copyright 2006 Terawins, Inc.
7
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 1.7 Pin Description
Table 1-1 Pin Description
Symbol Pin # Type Description
Copyright by Terawins,
Power Supplies
VDD18 VDD33 VD5A VD33ADC1 VD33ADC2 VD33DAC VD33PWM GND VS18PLL VS33ADC1 VS33ADC2 VS33DAC VS33PWM RSET VBFG IOR IOG IOB CPH1 CPH2/sD0 CPH3/sD1 VSO/STH1 HSO/POL DEN/STH2 UD RL Q1H/sD2 LP/sD3 GCLK/sD4 GOE/sD5 STV1/sD6 STV2/sD7 VCOMAMP VCOMDC SCL SDA/IICA3 CPUINT RSTB 8,26 22,36 38 63 47 7,21,27,37 48 64 39 62 43 44 42 41 40 25 28 29 23 20 24 19 18 30 31 32 33 34 35 45 46 11 10 12 9 PWR PWR PWR PWR PWR GND GND GND GND GND AO AO AO AO AO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DI I/O I/O DI +1.8V digital core power supply +3.3V digital output power supply, +5.0V analog power supply +3.3V analog power supply for ADC +3.3V analog power supply for DAC Digital ground Analog ground for PLL Analog ground for ADC Analog ground for DAC Analog ground for backlight inverter DAC reference current adjustment Voltage reference output Channel R current output Channel G current output Channel B current output Output data clock Output data clock/the bit 0 of serial interfaced panel Output data clock/the bit 1 of serial interfaced panel Vertical synchronization output signal. Horizontal synchronization output signal. Horizontal data enable Vertical Up/Down control Horizontal Right/Left control Source Driver Q1H/the bit 2 of serial interfaced panel Latch pulse for source driver/the bit 3 of serial interfaced panel Gate driver clock/the bit 4 of serial interfaced panel Gate driver output enable/the bit 5 of serial interfaced panel Gate Driver start pulse/the bit 6 of serial interfaced panel Gate Driver start pulse/the bit 7 of serial interfaced panel Analog VCOM amplitude Analog VCOM DC offset 2-wire serial bus clock. Power down does not affect SCL. 2-wire serial bus data. Power down does not affect SDA. Internal Interrupt. Whole chip reset. (Internal Pull-up)
Output Interface Signals
Timing Controller Interface Signals
2-wire serial bus Interface Signals
Configuration interface Signals
8
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Symbol Pin # Type Description
Copyright by Terawins,
ADC Interface
AY1 AY0 ACR1 ACR0 ACB1 ACB0 XTALI XTALO XCLK2MC PWM1 PWM2 VEA CSS VFB CEXT VPWM VEAL VFBL VPWML CSSL CEXTL VIsenL VIsen NC 1 2 3 4 5 6 13 14 15 16 17 49 50 51 52 53 54 55 56 57 58 59 60 61 AI AI AI AI AI AI DI DO DO DO DO AO AO AI AO AO AO AI AO AO AO AI AI N/A Analog input 1 of input channel 2 Analog input 0 of input channel 2 Analog input 1 of input channel 1 Analog input 0 of input channel 1 Analog input 1 of input channel 3 Analog input 0 of input channel 3 Output PLL reference clock input Output PLL reference clock output Buffered XTALI for external microprocessor. Pulse Width Modulation for volume/backlight control. Pulse Width Modulation for volume/backlight control. Error amplifier output Soft start pin Feedback of Lamp current Switching frequency of DC-DC converter PWM output, connect to external N-channel power MOSFET Error Amplifier output Feedback of Lamp current PWM output, drive NMOSFET switch Soft start pin Switching frequency of Inverter Current sense Current sense
PLL Reference Clock
Power Management Interface Signals
9
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
2 Theory of Operations
2.1 I²C Command Protocol
Before your tester writes I²C commands to T118B, slave address must be set at 50h. The timing sequence can be shown as below. After 4 cycles, the tester can get started IIC commands. SDA(A3) can affect slave address. Set low for 40h. Set high for 50h.
2 Cycles 2 Cycles
XTALI
RSTB Don`t care SDA SCL Don`t care
Figure 2-1 Power-up initialization When tester issues commands to the T118B, the only way the user can program the T118B is using the 2-wire serial bus protocol. This section describes the 2-wire serial bus protocol. Data transfers on the 2-wire serial bus are initiated with a START condition and are terminated with a STOP condition. Normal data on the SDA line must be stable during the high period of the SCL. The transition on the SDA is only allowed while SCL is low. The START condition is unique case and is defined by a high-tolow transition on the SDA while the SCL is high. The STOP condition is a unique case and is defined by a low-to-high transition on the SDA while the SCL is high. Each data packet on the 2-wire serial bus consists of 8 bits of data followed by an ACK bit. Data is transferred with MSB first. The transmitter releases the SDA line during the ACK bit and the receiver of data transfer must drive the SDA line low during the ACK bit to acknowledge receipt of the data. The frequency of SCL can be from 50 Khz up to 1 Mhz.
SDA
B it7 B it6
SCL
S 1 2 3 7 8 9 ACK P
S ta rt C o n d it i o n
S to p C o n d itio n
Figure 2-2 2-wire serial bus Protocol
10
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
The timing below shows a typical T118B IIC single byte write command,
Slave Address Write CMD Register Address Data being written to Register
SDA
A7
A6
A1
R7
R6
R1
R0
D7
D6
D1
D0
SCL
S 1 2 7
8
9 ACK
1
2
7
8
9 ACK
1
2
7
8
9
P
Start Condition
Stop Condition
Figure 2-3 T118B IIC single byte write command
The timing below shows a typical T118B IIC single byte read command,
Slave Address Read CMD
Slave Address
Write CMD
Register Address
Restart
Data being Read Not Ack
SDA
A7
A6
A1
R7
R6
R1
R0
A7
A6
A1
D7
D6
D1
D0
SCL
S 1 2 7
8
9 ACK
1
2
7
8
9 ACK
1
2
7
8
9 ACK
1
2
7
8
9
P
Start Condition
Stop Condition
Figure 2-4 T118B IIC single byte read command
11
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.2 Analog Front End
Copyright by Terawins,
T118B contains 2 ADCs in Analog Front End. Each channel of ADCs can digitalize SDTV signals from analog to digital. The figure shown below can describe how to select a SDTV signal from 2 inputs prior to ADCs.
AI1SEL
ACR0 ACR1
VI_1_A VI_1_B VI_1_C
00 01 1x
CBINSEL
0
VI_1 ADC Ch1 VI_3
11 10 01 00
AI3SEL
0x19[5:4] CB
1
ACB0 ACB1
VI_3_A VI_3_B VI_3_C
00 01 1x
YINSEL
AI2SEL
11 10 01
0x19[3:2] Y/CVBS
AY0 AY1
VI_2_A VI_2_B VI_2_C
00 01 1x
00
CRINSEL VI_2 ADC Ch2
11
AI4SEL
0
0x19[1:0] CR/Chroma
1
VI_4
10 01 00
VI_4_A VI_4_B VI_4_C
00 01 1x
Figure 2-5 Analog Front End
2.3
Y/C Separation and Chroma Decoder
A composite video has luma(Y) and chroma(C) information mixed in the same video signal. This video signal can also be represented by the equation below,
CVBS = Y + U * Sin( wt ) + V * cos( wt )
Where w = 2f SC , f SC =3.58Mhz if NTSC, f SC =4.43Mhz if PAL The figure below shows a typical composite signal. The 2-D adaptive comb filter inside T118B is designed to separate Y and C from a composite video signal.
12
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Quadrature modulated Chroma
Copyright by Terawins,
Color burst
Black Level Blank Level
Figure 2-6 Typical Color SDTV Signal . The conventional 3-line comb filter fails to separate Y and C if there is a vertical transition. The 2-D adaptive comb filter is based on equally weighting factors that color changes along vertical and horizontal edges. Let the amount of color change along vertical and horizontal direction DCv and DCh , the weighting factor can be expressed as following equations,
DCv DCv + DCh DCh Wv = DCv + DCh Wh =
By employing adaptive method, chroma can be recovered by following equation,
C = Ch * Wh + Cv * Wv
After Y/C separation, Y and C should look like waveforms shown as in following figure. Y only contains low frequency part, while C contains high frequency part which is centered around subcarrier f SC .
13
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
2-D Adaptive Comb Filter 1H 1H
Y Y Y/U/V Postfiltering
U/V Demodulation 1H C
Cb
Cr
Color Burst Locked Loop
sin(wt) cos(wt)
Figure 2-7 Video Decoding Flow
2.4
Digital Color Transient Improvement (DCTI)
Usually, a composite or S-video SDTV signal may have bandwidth limitation that causes the loss chroma detail around two different color bars. Two pictures shown below illustrate the result before and after DCTI block. Without DCTI(the upper picture), we may see color transient wider than several pixels. A slow transient edge usually blurs image. T118B DCTI algorithm can sharpen those color transient edges. The lower picture shows that chroma data is enhanced by increasing the slope of edge transient without introducing the ring effects.
Figure 2-8 Comparison of DCTI
14
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.5 Digital Luminance Transient Improvement (DLTI)
Copyright by Terawins,
The Digital Luminance Transient Improvement is intended to sharpen luminance edge transient. The figure shown below is DLTI transfer function. DLTI doesn't increase peak-to-peak amplitude; rather it turns sloped waveforms into rectangular waveforms.
Y out
Without DLTI With DLTI
Y in
Figure 2-9 DLTI Transfer Curve
2.6
FIR Scaler
FIR Scaler can scale input H/V sizes to fit any LCD panel resolution. The flexible and independent H/V scalers allow users to program display area in 16:9 Full mode, 16:9 non-linear wide mode and 4:3 mode. FIR scaler also provides coefficient-based 2-D sharpness that can sharpen detail of picture.
16:9 Full Mode
16:9 Non-linear Wide
4:3
Figure 2-10 Practical Applications of FIR Scaler
15
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.7 Black-Level Extension (BLE)
Copyright by Terawins,
Black Level Expansion (BLE) can enhance image contrast that makes dark regions of image darker, while bright regions remain unchanged. The figure shown below is BLE transfer function.
Y out
Without BLE With BLE
BLE_threshold
Figure 2-11 BLE Transfer Curve
Y in
Yout = Yin - (Yoffset - Yin) * BLE _ Gain / 16 Where Yoffset and BLE _ Gain can be programmed by register P0_96h.
2.8 Color Space Converter
A pixel in YCbCr color space can be converted to RGB color space by using following equations,
R = YCoefCSC * (Y - 16) + CrCoef _ R * (Cr - 128) G = YCoefCSC * (Y - 16) - CrCoef _ G * (Cr - 128) - CbCoef _ G * (Cb - 128) B = YCoefCSC * (Y - 16) + CbCoef _ B * (Cb - 128) Where YCoefCSC is in 1.7-bit fixed point with default 1.164. CrCoef _ R in 1.7-bit fixed point with default 1.596. CrCoef _ G in 0.8-bit fixed point with default 0.813. CbCoef _ G in 0.8-bit fixed point with default 0.392. CbCoef _ B in 2.6-bit fixed point with default 2.017
The equations shown as below correspond to a typical YCbCR-to-RGB converter. In T118B, we make those coefficients adjustable.
16
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
R = 1.164 * (Y - 16) + 1.596 * (Cr - 128) G = 1.164 * (Y - 16) - 0.813 * (Cr - 128) - 0.392 * (Cb - 128) B = 1.164 * (Y - 16) + 2.017 * (Cb - 128)
2.9
Gamma Correction
The relation between input video signal and LCD panel may exist non-linear transfer function such as figure shown below,
R/G/B out
Gamma 255 Gamma 250
Gamma 0
R/G/B in
248 255 16 8
0
Ideal Transfer Function T118 Gamma Correction
Figure 2-12 Gamma Transfer Curve T118B uses 3 independent 256-entry RAM-based LUTs that are allowed to be programmed each point via register at P0_93h and P0_94h.
17
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
2.10 OSD
2.10.1 OSD Access
Table 2-1 OSD Access
I/O Port Index 00h 01h 02h 03h 04h 05h 06h A0h OSD_Index A1h OSD_Data 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh A2h ORAM_AL A3h ORAM_AH A4h ORAM_D Default 00h 00h 10h 08h 00h 38h 40h 00h 00h 0Ah 00h 0Ah 66h 00h 00h 00h 00h 00h OSD Control Register Character Delay_1 Character Delay_2 Character Delay_3 Alpha Blending Control Char_RAM Base Address Char_RAM Stop Address Reserved Reserved Blinking Control Bit_Map Window Size : Height Upper Bits and BMP Enlarge Control Bit_Map Window Size : Width Bit_Map Window Size : Height Reserved OSD LUT RAM data port (Write Only) Char Control Register OSD RAM Low Address Port of Starting Access OSD RAM High Address Port of Starting Access OSD RAM Data Port (Low Byte first, then High Byte). After two Writes, the address will be increased by 1. Description
18
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
2.10.2 RAM Addressing A[9:0]
Figure 2-13 OSD RAM Partition
19
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
2.10.3 Character RAM format
In Character Mode (contrast to Bit_Map Mode), the Characters displayed on OSD can be grouped to few rows; each row has its own row attribute which defines the behavior of current character row. And, there is maximum 30 characters in one row , each character has 1~2 bytes to define its character font number and its colors . Due to providing more flexible menu programming, T102 supports three character modes:
Table 2-2 Character Index Modes (Char_Idx_Mode) Char_Idx_Mode = 0
15 14 BG[2:0] BG[2:0] BG[2:0] 13 12 Blink Blink Blink 11 10 9 FG[3:0] FG[3:0] FG[3:0] 8 7 6 5 4 3 2 1 0 XXX-XXX0-0000 XXX-XXX0-0001 XXX-XXX0-0010 32 words BG[2:0] 000b Row_BG Blink 0 Row_Gap FG[3:0] 0000b CHS CWS Index (Char_29) Index to Blank Char XXX-XXX1-1101 XXX-XXX1-1110 XXX-XXX1-1111 Index (Char_0) Index (Char_1) Index (Char_2)
Char_Idx_Mode = 1
15 BG BG 14 FG FG 13 12 11 10 9 8 7 BG BG 6 FG FG 5 4 3 2 1 0 XXX-XXXX-0000 XXX-XXXX-0001 16 words BG BG Row_BG FG FG Index (Char_27) Index (Char_29) Row_Gap CHS CWS BG BG FG FG Index (Char_26) Index (Char_28) FG_C[3:0] XXX-XXXX-1101 XXX-XXXX-1110 XXX-XXXX-1111 Index (Char_1) Index (Char_3) Index (Char_0) Index (Char_2)
BG_C[2:0]
Char_Idx_Mode = 2
15 BG BG 14 13 12 11 10 9 8 7 BG BG 6 5 4 3 2 1 0 XXX-XXXX-0000 XXX-XXXX-0001 16 words BG BG Row_BG FG[1:0] FG[1:0] Row_Gap Index (Char_27) Index (Char_29) CHS CWS BG BG FG[1:0] FG[1:0] Index (Char_26) Index (Char_28) => LUT[0]~[3] XXX-XXXX-1101 XXX-XXXX-1110 XXX-XXXX-1111 FG[1:0] FG[1:0] Index (Char_1) Index (Char_3) FG[1:0] FG[1:0] Index (Char_0) Index (Char_2)
BG_C[2:0]
And the Word #1Eh in Char_Idx_Mode=0 is reserved, which must be filled with transparent color and pointed to blank font.
20
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.3.1 Character Index Data (Address to Font Select) Address Offset: no (part of menu char) Access: Write Only Default Value: XXh Size: 8 bits
Bit [7:6] [4:0] Access WO WO Symbol 00 or BG/FG CHRA[5:0]
Copyright by Terawins,
Description
Depends on Char_Idx_Mode Character Address (Index), selects the character font (i.e., 0,1,2,.. A,B,C, a,b,c,$,%,...). If the value is number N, then it selects the Nth font, and that font starting address is (N x Font_Height ). The Font_Height is defined in OSD_0Fh<5>. In Char_Idx_Mode=0, this Index is 8 bits, and selecting one of total 256 fonts (but OSD RAM is small, for 64 fonts maximum) In Char_Idx_Mode=1, this Index is 6 bits, and selecting one of total 64 fonts In Char_Idx_Mode=2, this Index is 5 bits, and selecting one of total 32 fonts
2.10.3.2 Character Attribute Address Offset: no (part of menu char) Access: Default Value: XXh Size:
Bit [7:5] [4] [3:0] Access WO WO WO Symbol BG_R, BG_G, BG_B Blink FG_R, FG_G, FG_B, FG_I
Write Only 8 bits
Description
Background R/G/B Color (Intensity=0). If all 0, then no background, i.e. transparent. Enable this Character display with blinking feature. Refer to section 2.10.4.8 for detail blinking control. Foreground R/G/B/Intensity Color. If the value is set as 0000b, then there will be no foreground, i.e. transparent.
2.10.3.3 Row Attribute Address Offset: no (part of menu char) Access: Default Value: XXh Size:
Bit [7] [6:2] [1] [0] Access WO WO WO WO Symbol RGAP_BG RGAP[4:0] CHS CWS
Write Only 8 bits
Description
Color Select of Row Gap. Set 1 for selecting the same color of background of current row character, 0 for selecting transparent color. Row Gap (=Row Space). Inserted range is 4 x (31d~0) scan lines before current Row. Character Height Select. Set 1 for double height, 0 for single height. Character Width Select. Set 1 for double width, 0 for single width. When set to 1, only the even numbered characters will be shown, odd numbered characters are skipped.
21
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.10.4 OSD Configuration Register
2.10.4.1 Cfg_00h OSD Control Register Address Offset: OSD_00h Default Value: 00h
Bit [7] [6] [5] [4] [3] [2] [0] Access R/W R/W R/W RO R/W R/W R/W Symbol OSD_En Bit_Map Bit2PP Reserved Font_Hx2 Early_hDE Font_WxN
Copyright by Terawins,
Access: Size:
Read/Write 8 bits
Description
Enabling the OSD function. Set 1 for enabling, 0 for disabling OSD Select Bit Mapped OSD display mode. Set 1 for Bit_Map Mode, 0 for Character Mode. Two bits per Pixel for Bit_Map mode. Set 1 for 2 Bits/Pixel, 0 for 1 Bit/Pixel. Character mode, fonts height double. let OSD a little shift left. Character mode, fonts width enlarge. Value 0~3 = x1, x2, x3, x4
2.10.4.2 Cfg_01h Character Delay_1 Address Offset: OSD_01h Default Value: 00h
Bit [7] [6:4] Access RO R/W Symbol Reserved VERTD[10:8]
Access: Size:
Read/Write 8 bits
Description
Vertical Starting Position (Upper bits) of Character displaying. These bits with Cfg_03h, total 11 bits, become 2048 steps, with an increment one pixel per step for each field. Horizontal Starting Position (Upper bits) of Character displaying. These bits with Cfg_02h, total 11 bits, become 2048 steps, with an increment one pixel per step.
[3] [2:0]
RO R/W
Reserved HORD[10:8]
2.10.4.3 Cfg_02h Character Delay_2 Address Offset: OSD_02h Default Value: 10h
Bit [7:0] Access R/W Symbol HORD[7:0]
Access: Size:
Read/Write 8 bits
Description
Horizontal Starting Position (Lower bits) of Character displaying. These bits with Cfg_01h<2:0>, total 11 bits, become 2048 steps, with an increment one pixel per step.
2.10.4.4 Cfg_03h Character Delay_3 Address Offset: OSD_03h Default Value: 08h
Bit [7:0] Access R/W Symbol VERTD[7:0]
Access: Size:
Read/Write 8 bits
Description
Vertical Starting Position (Lower bits) of Character displaying. This register with Cfg_01h<6:4>, total 11 bits become 2048 steps, with an increment one line per step for each field.
22
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.4.5 Cfg_04h Alpha Blending Control Address Offset: OSD_04h Default Value: 00h
Bit [7] Access R/W Symbol FG_NoAB
Copyright by Terawins,
Access: Size:
Read/Write 8 bits
Description
OSD Character ForeGround portion will be exclusive to be blended if set to one. Default is 0 as no matter the current displayed pixels are in Character foreground or border/shadow or background or in OSD window, all will be alpha blended with original Video source. Alpha Blending percentage (n/8). If set 000b, alpha blending is disabled (0/8 * Original Video Source + 8/8 * OSD display); If set 001b, blending as 1/8 * Original Video Source + 7/8 * OSD display; ... If set N, blending as N/8 * Original Video Source + (8-N)/8 * OSD display;
[6:3] [2:0]
RO R/W
Reserved AB_Set[2:0]
2.10.4.6 Cfg_05h Char_RAM Base Address Address Offset: OSD_05h Access: Default Value: 38h Size:
Bit [7] [6:0] Access RO R/W Symbol Reserved CharBA[6:0]
Read/Write 8 bits
Description
Programmable Character RAM Base Address. Those 7 bits become 128 steps, each step is 32 Bytes (one Character Row include Char_Index, Char_Attr, Row_Attr; i.e. 30 column maximum for each Row). The actual address will be 0RR-RRRX-XXXX (in Char_Idx_Mode=0 and the CharBA[0] should be 0), or 0RR-RRRRXXXX (for Char_Idx_mode=1 or 2). The RR-RRRR means the value of CharBA[6:0]; the X-XXXX is the nth Char Column. For trading off Font number and Character number in a single RAM (this version is 1Kx16 bits), user should carefully setting this register.
2.10.4.7 Cfg_06h Char_RAM Stop Address Address Offset: OSD_06h Access: Default Value: 40h Size:
Bit [7] [6:0] Access RO R/W Symbol Reserved CharEA[6:0]
Read/Write 8 bits
Description
Programmable Character RAM Stop/End Address (Available if Revision ID >= 0h). Those 7 bits become 128 steps, each step is 32 bytes. The actual stop address will be 0RR-RRRX-XXXX (The RRRRRRR means the value of CharEA[6:0]; the X-XXXX is the nth Char Column. and OSD will be displayed for Character Row >= CharBA and < CharEA.
23
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.4.8 Cfg_09h Blinking Control Address Offset: OSD_09h Default Value: 0Ah
Bit [7] [6:4] [3:2] Access R/W RO R/W Symbol En_Global_Blink Reserved BCLK[1:0]
Copyright by Terawins,
Access: Size:
Read/Write 8 bits
Description
Enable whole OSD Characters blinking if set to 1. Blinking Frequency Select (internal 4x BCLK for Blinking State Machine). Set 00b for Refresh Rate /16; 01b for 1/32; 10b for 1/64; 11b for 1/128. For adjusting the blinking duty cycle, Set: 00b for Global Blink Off, i.e., 0% Background, 100% OSD. 01b for 25% Background, 75% OSD. 10b for 50% Background, 50% OSD. 11b for 75% Background, 25% OSD.
[1:0]
R/W
Duty[1:0]
2.10.4.9 Cfg_0Ah Bit_Map Window Size: Height Upper Bits Address Offset: OSD_0Ah Access: Read/Write Default Value: 00h Size: 8 bits
Bit [7:6] [5:4] Access RO R/W Symbol Reserved BMH[9:8] Description Bit Map Window Height Upper bits (only available in Bit_Map mode). Please refer to OSD_0Ch for detail. User must be careful of the OSD RAM size limitation. Bit Map Window Vertical Enlarge (only available in Bit_Map mode). Set 00b for 1 line per dot, 01b for 2 lines per dot, 10b for 3 lines per dot, 11b for 4 lines per dot. Bit Map Window Horizontal Enlarge (only available in Bit_Map mode). Set 00b for 1 pixel per dot, 01b for 2 pixels per dot, 10b for 3 pixels per dot, 11b for 4 pixels per dot.
[3:2]
R/W
BMP_Height_xN [1:0]
[1:0]
R/W
BMP_Width_xN[1:0]
2.10.4.10 Cfg_0Bh Bit_Map Window Size: Width Address Offset: OSD_0Bh Access: Default Value: 0Ah Size:
Bit [7:0] Access R/W Symbol BMW[7:0]
Read/Write 8 bits
Description
Bit Map Window Width Lower bits (only available in Bit_Map mode This register has 8 bits, i.e., 256 steps (value 00h is not valid), each step is 16 or 8 dots depends on Bit2PP (OSD_00h<5>) setting. When Bit2PP=0 (i.e., 1 bit/pixel), each step is 16 dots. When Bit2PP=1 (i.e., 2 bits/pixel), each step is 8 dots. User must be careful of the OSD RAM size limitation.
2.10.4.11 Cfg_0Ch Bit_Map Window Size: Height Address Offset: OSD_0Ch Access: Default Value: 66h Size:
Bit [7:0] Access R/W Symbol BMH[7:0]
Read/Write 8 bits
Description
Bit Map Window Height Lower bits (only available in Bit_Map mode). This register combined with OSD_0Ah<5:4> and become 10 bits, i.e. 1024 height step: all 0 for reserved, 10'h001 for 1 line, 10'h3FF for 1023 lines. User must be careful of the OSD RAM size limitation.
24
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.4.12 Cfg_0Dh Bit_Map Window Size: Height Address Offset: OSD_0Dh Access: Default Value: 86h Size:
Bit [7:3] [2:0] Access R/W R/W Symbol FontH[4:0] FontW[3:1]
Copyright by Terawins,
Read/Write 8 bits
Description
Font Height. Value >=1 Font WeigthX2. Value 3~7 = width 6, 8, .., 14; others = width 16
2.10.4.13 Cfg_0Eh OSD Color LUT RAM Data Port Address Offset: OSD_0Eh Access: Default Value: XXh Size:
Bit [7:0] Access R/W Symbol LUT_D[7:0]
Write Only 8 bits
Description
The data will be written to (or read from) OSD Color LUT RAM. After each Read or Write access to LUT RAM, then the LUT address will be increased automatically. Note: Whenever the Configuration Index is programmed from other index value to 0Eh, the OSD Color LUT RAM becomes access capable and the address pointer is reset to 1 (the starting byte). In other words, whenever the index value is programmed to non-0Eh value, the OSD Color LUT RAM can not be access, and the pointer always kept at 1. Note: The order to fill LUT RAM is: 1. LUT[1]_Green/Blue 2. LUT[1]_0000b/Red 3. LUT[2]_Green/Blue 4. LUT[2]_0000b/Red 5. LUT[3]_Green/Blue 6. ---29. LUT[15]_Green/Blue 30. LUT[15]_0000b/Red 31. LUT[0]_Green/Blue (wrap to beginning) 32. LUT[0]_0000b/Red 33. LUT[1]_Green/Blue 34. LUT[1]_0000b/Red ---
2.10.4.14 Cfg_0Fh OSD Color LUT RAM Data Port Address Offset: OSD_0Fh Access: Default Value: 00h Size:
Bit [7] [6] Access RO R/W Symbol Reserved FontW_Byte
Read/Write 8 bits
Description
When font width = 6 or 8 (and only), this bit is optional for the font RAM utilization. When clear to 0, fonts stored in RAM as font width >=10. When set to 1, fonts stored in RAM: Even-indexed fonts put at the high byte in RAM, and Odd-indexed fonts put at the low byte in RAM.
[5:4] [3:2]
RO R/W
[1:0]
R/W
Character attribute/Index coding modes, 0 for original 2 bytes (256 index) mode. 1 for 1-byte (64 index) mode, 2 for 1-byte (32 index) mode, 3 for reserved. CRAM_ByteAccess[1:0] OSD RAM access pointer behavior: 0X: Word (2-bytes) R/W; (Fonts, BMP, Character Menu) 10: Low byte only; 11: High byte only; (Character Menu)
Reserved Char_Idx_Mode[1:0]
25
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.10.5 Functional Description
2.10.5.1 Host Access OSD RAM
Copyright by Terawins,
2.10.5.1.1 Writing Data
The OSD RAM size is 1Kx16, i.e., 1K word with each word is 2 bytes. The host interface is 8-bit data width, so whenever the host writes 2 times (one for data low byte, the other for data high byte) then it becomes one write with 16-bit data to OSD RAM. st rd th th The ORAM_D (OSD module base address + 04h) port when writing in the 1 /3 /5 /7 ..times, it will latch lower byte of OSD RAM writing nd th th th data when the host want to program Font or Character, Attribute, BMP values; and when writing 2 /4 /6 /8 ... times, it will use this 8bits data as high byte and write both two bytes to OSD RAM.
2.10.5.1.2 Reading Data
Read back data in OSD RAM is disabled.
2.10.5.1.3 Access Address
The OSD RAM access pointer is programmed by the host write access to ORAM_AL and ORAM_AH ports. The OSD RAM size is 1Kx16, so the pointer is required to cover 1K words, i.e., 11 address lines => A[10:0]. When the host read these ORAM_AL/ORAM_AH ports, the pointer value reflects the current OSD RAM accessing pointer.
26
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.5.2 OSD Displaying in Character Mode
Copyright by Terawins,
Character Mode
Visib area (original RGB)
VERTD[10:0] ( x HSYNC lines)
Main Manual
HORD[10:1] Fonts store here
( x 2 pixels)
Color Size & Position Contrast/Brightness Geometry
(Index / Attribute)
Last Row
Char. store here
First Row
Character Foreground color/Blinking Character Background color
CharBA[6:0] (Character Begin Address) CharEA[6:0] (Character Ending Address) OSD RAM
(1K x 16)
Figure 2-14 OSD Character Mode
27
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.5.3 OSD LUT Color Mapping
Copyright by Terawins,
16x12 RAM
Color Value Null Red Green Blue R G B Int 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Duplicate to High/Low nibble;
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
1. Character Mode
1. Char_Idx_Mode=0, FG[3:0] as Color_0= transparent; Color_1~15= LUT[1..15] BG[2:0] as Color_0= transparent; Color_1~7= LUT[2,4,..14] 2. Char_Idx_Mode=1, FG as Color_0= transparent; Color_1= depends on its Row_Attribute FG_C[3:0], then redirect to transparent or LUT[1..15] BG as Color_0= transparent; Color_1= depends on its Row_Attribute BG_C[2:0], then redirect to transparent or LUT[2,4,..14] 3. Char_Idx_Mode=2, FG[1:0] as Color_0= transparent; Color_1~3= LUT[1..3] BG as Color_0= transparent; Color_1= depends on its Row_Attribute BG_C[2:0], then redirect to transparent or LUT[2,4,..14]
2. Bit_Map Mode
1 Bit/Pixel mode: Color_0= transparent; Color_1= LUT[1] 2 Bits/Pixel mode: Color_0= transparent; Color_1~3= LUT[1..3]
Figure 2-15 OSD Color Look Up Table
28
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
2.10.5.4 Programming Examples
Copyright by Terawins,
2.10.5.4.1 Configuring OSD Function
To access OSD configuration registers, write register index to port A0h, and read/write data from port A1h. For example, set : IOW IOR IOW IOW A0h, 05h A1h; A0h, 06h A1h, 3Eh; ; point to OSD_05h (Char Base Address register). ; get Char Base Address. ; point to OSD_06h (Char Stop Address register). ; Set Char Stop Address of current menu.
2.10.5.4.2 Fill LUT RAM
LUT RAM size is 16 (address) x 12 (width). For example, need to fill LUT RAM as: LUT_RAM[1]=F5Ah, ...LUT_RAM[15]=EF0h IOW A0h, 0Eh ; point to OSD_0Eh (LUT RAM Data port), this will let LUT RAM be ; access-able and pointer starts from 0h of LUT RAM. IOW A1h, 5Ah; ; fill Green = 0101b and Blue = 1010h in LUT_RAM[1]. IOW A1h, 0Fh; ; fill Red = 1111b in LUT_RAM[1]. ; after this write, h/w will increase LUT RAM address to 2 automatically ....... IOW A1h, F0h; ; fill Green = 1111b and Blue = 0000h in LUT_RAM[15]. IOW A1h, 0Eh; ; fill Red = 1110b in LUT_RAM[15]. ; after this write, h/w will increase LUT RAM address to 0 automatically IOW A0h, non-0Eh ; Disable LUT RAM programming.
2.10.5.4.3 Load Fonts to OSD RAM
OSD RAM size is 1K (address: 000h ~ 3FFh) x 16 (width). Fonts storing starts from address 000h. For example, loading some fonts to OSD RAM as: Font[0] is a space (all zero), Font[1] is a character 2 with box, Font[14] is a graphic,.. IOW A2h, 00h ; set OSD RAM starting access address low byte. (bit [7:0] as A[7:0]) IOW A3h, 00h; ; set OSD RAM starting access address high byte. (bit [3:0] as A[11:8]) ; then the OSD RAM address pointer is set to 000h. IOW A4h, 00h; ; low byte of first row of Font[0]. IOW A4h, 00h; ; high byte of first row of Font[0], after this write, h/w will increase OSD ;RAM address to 1 automatically nd IOW A4h, 00h; ; low byte of 2 row of Font[0]. nd IOW A4h, 00h; ; high byte of 2 row of Font[0], after this write, h/w will increase OSD ;RAM address to 2 automatically . . . . . . . (for example, programmed font size is 18 (height) x 12 (width) th IOW A4h, 00h; ; low byte of 18 (last) row of Font[0]. th IOW A4h, 00h; ; high byte of 18 row of Font[0], after this write, h/w will increase OSD ;RAM address to 012h automatically IOW A4h, F0h; ; low byte of first row of Font[0]. (since font width is 12, the low bye bit[3:0] ; is no use) IOW A4h, FFh; ; high byte of first row of Font[0], after this write, h/w will increase OSD ;RAM address to 013h automatically ....... IOW A2h, 68h ; set OSD RAM starting access address low byte. (bit [7:0] as A[7:0]) IOW A3h, 01h; ; set OSD RAM starting access address high byte. (bit [3:0] as A[11:8]), ; then the OSD RAM address pointer is set to 168h = 14d * 18d. IOW A4h, 40h; ; low byte of first row of Font[14]. IOW A4h, A3h; ; high byte of first row of Font[14],
29
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.11 TCON 2.11.1 LCD Panel Pin Assignment
Copyright by Terawins,
In this section, we illustrate those pins connected to AU 7" TFT-LCD panel module in a T118B video system.
Table 2-3 T118B Rotation Control and LCD Panel Scanning Direction L/R 1 1 0 0 U/D 1 0 1 0 STH STH2 STH2 STH1 STH1 STV STV1 STV2 STV1 STV2 Reg 0xE1 0xBC 0xF4 0xA8 0xE0 Scanning Direction Down-to-up, left-to-right Up-to-down, left-to-right Down-to-up, right-to-left Up-to-down, right-to-left
STV2 STVL
STH2 STHL
STH1 STHR
au
STV1 STVR
Figure 2-16 Scanning Direction of AU 7" panel
30
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 2.11.2 TCON Timing
Copyright by Terawins,
T118B is designed for analog LCD panel. Each 24-bit color pixel must be converted into analog voltage via built-in triple DACs. The table 2-1 shows a typical setting for AU 7" panel with 10-Mhz operation clock.
Table 2-4 T118B TCON Register Set (C8 =1Bh, C9=03, CA=03h) Reg 0x20 0x21 0x23,0x22 0x24 0x26,0x25 0x28,0x27 0x2A,0x29 0x2B 0x30 0x32,0x31 0x34,0x33 0x35 Reg value 0x21 0x79 0x022D 0x0C 0x024B 0x021C 0x0029 0x01 0x01 0x01FB 0x0037 0x06 Operation Line-inverted Control Polarity Control Placement of OEH Duration of OEH Placement of POL Placement of GCLK Duration of GCLK Placement of STH Enable Placement of STV Placement of GOE Duration of GOE Placement of STV
R/G/B HS DE
Htotal
STH1
1.22 us 8.28 us
OEH
5.4 us
GOE
3.74 us 4.18 us
GLKV
POL
4.6 v
ViA 4.6 v ViDC
2.5 v
VR/G/B
0.4 v
Figure 2-17 AU 7" TCON Timing Spec
31
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
The waveforms shown below illustrate TCON location counting. Each TCON signal's placement and duration are allowed to program as alike as analog LCD panels require. On the figure 2-2, the pulse placement starts counting at the leading edge of DE. After placement counter meets the value we give to {P1_27h,P1_28h}, the duration counter starts to count until the duration meets {P1_29h,P1_2Ah}. All of location counting use LLCK as counter clock.
HS DE
Htotal
Htotal
GCLK
{P1_28h,P1_27h} {P1_2Ah,P1_29h}
Figure 2-18 Location Counting of GCLK
32
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Copyright by Terawins,
3 Register Description
Serial Bus Register Set Page 0
3.1 ADC Register Set 3.1.1 ADC Clamping Pulse Placement and Duration
Address Offset: Default Value:
Bit [7:5] [4:0] Access R/W R/W
04h 00h
Symbol STIPCLPL STIPCLDU
Access: Size:
Read/Write 8 bits
Description
Clamping pulse placement Clamping pulse duration
3.1.2 ADC Channel 0 Static Gain
Address Offset: Default Value:
Bit [7:0] Access R/W
07h 80h
Symbol ADCRSG
Access: Size:
Read/Write 8 bits
Description
This register can set a fixed gain for ADC channel 0 when static gain control is enabled
3.1.3 ADC Channel 1 Static Gain
Address Offset: Default Value:
Bit [7:0] Access R/W
08h 80h
Symbol ADCGSG
Access: Size:
Read/Write 8 bits
Description
This register can set a fixed gain for ADC channel 1 when static gain control is enabled
3.1.4 ADC ACR Channel Offset
Address Offset: Default Value:
Bit [7:2] [1:0] Access R/W R/W
0Ah 60h
Symbol ADC_ROFF RESERVED
Access: Size:
Read/Write 8 bits
Description
ADC Channel 0 DC Offset Control
3.1.5 ADC AY Channel Offset
Address Offset: Default Value:
Bit [7:2] [1:0] Access R/W R/W
0Bh 60h
Symbol ADC_GOFF RESERVED
Access: Size:
Read/Write 8 bits
Description
ADC Channel 1 DC Offset Control
3.1.6 ADC General Control Configuration Register
Address Offset: Default Value: 0Dh 20h Access: Size: Read/Write 8 bits
33
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Bit [7:6] Access R/W Symbol CLPMD Clamping mode
Copyright by Terawins,
Description
Mode 0 1 2 3
[5] [4] [3] [2] [1] [0] R/W R/W R/W R/W R/W R/W DCEN DCSEL RESERVED DC_CAL_RDY DC_CALEN DC_CALMD DC Clamping Enable Clamping Source Selection
Type Fixed window Locked Window Reserved Reserved
DC Calibration Ready DC Calibration Enable DC Calibration Mode
Mode 0 1
Type minimum average
3.1.7 ADC Power Down Control
Address Offset: Default Value:
Bit [7:6] [5] [4] [3:0] Access R/W R/W R/W R/W
0Fh 00h
Symbol RESERVED PD1 PD0 RESERVED
Access: Size:
Read/Write 8 bits
Description
1: Power down 0: Power up 1: Power down 0: Power up
3.1.8 YPbPr Clamping Control Register
Address Offset: Default Value:
Bit [7:6] Access R/W
11h 00h
Symbol GMIDSEL
Access: Size:
Read/Write 8 bits
Description
Clamping Voltage
Mode 0 1 2 3
Voltage Type Adaptiv Voltage 0.65*Ref 0.5*Ref 0.35*Ref
34
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
[5:4] R/W RMIDSEL Clamping Voltage
Copyright by Terawins,
Mode 0 1 2 3
[3] [2] [1] R/W R/W R/W ADSHARE2 ADSHARE1 GSCALE
Voltage Type Adaptiv Voltage 0.65*Ref 0.5*Ref 0.35*Ref
0: Take sampled data from channel 2 and channel 4 (used for CbCr) 1: Take sampled data from channel 2 or channel 4 0: Take sampled data from channel 1 and channel 3 (used for CbCr) 1: Take sampled data from channel 1 or channel 3 ADC Channel 2 Clamping Mode
Mode 0 1
[0] R/W RSCALE ADC Channel 1 Clamping Mode
Select Clamp to ground Clamp to midscale
Mode 0 1
Type Clamp to ground Clamp to midscale
3.1.9 Analog Source MUX Selection
Address Offset: Default Value:
Bit [7:6] Access R/W
18h 00h
Symbol AI4SEL
Access: Size:
Read/Write 8 bits
Description
Analog mux selection for channel 2 ADC AI4SEL=00: Channel 4 input signal is from GND AI4SEL=01: Channel 4 input signal is from GND AI4SEL=1x: Channel 4 input signal is from GND Analog mux selection for channel 1 ADC AI3SEL=00: Channel 4 input signal is from ACB0 AI3SEL=01: Channel 4 input signal is from ACB1 AI3SEL=1x: Channel 4 input signal is from GND Analog mux selection for channel 2 ADC AI2SEL=00: Channel 4 input signal is from AY0 AI2SEL=01: Channel 4 input signal is from AY1 AI2SEL=1x: Channel 4 input signal is from GND Analog mux selection for channel 1 ADC AI3SEL=00: Channel 4 input signal is from ACR0 AI3SEL=01: Channel 4 input signal is from ACR1
[5:4]
R/W
AI3SEL
[3:2]
R/W
AI2SEL
[1:0]
R/W
AI1SEL
AI3SEL=1x: Channel 4 input signal is from GND
3.1.10 Y/Cb/Cr Data Switching Control
Address Offset: Default Value:
Bit Access
19h 07h
Symbol
Access: Size:
Read/Write 8 bits
Description
35
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Bit [7] Access R/W Symbol INSEL2
Copyright by Terawins,
Description ADC input mux selection 0: Channel 2 ADC takes data from channel 2 (AY) 1: Channel 2 ADC takes data from channel 4 (GND) 0: Channel 1 ADC takes data from channel 1 (ACR) 1: Channel 1 ADC takes data from channel 3 (ACB) CB input selection 0: Channel 1 1: Channel 2 2: Channel 3 3: Channel 4 Y/Luma input selection 0: Channel 1 1: Channel 2 2: Channel 3 3: Channel 4 S-video Chroma or CR input selection 0: Channel 1 1: Channel 2 2: Channel 3 3: Channel 4
[6] [5:4]
R/W R/W
INSEL1 CBINSEL
[3:2]
R/W
YINSEL
[1:0]
R/W
CRINSEL
3.1.11 ADC Analog AGC Selection
Address Offset: Default Value:
Bit [7:6] Access R/W
1Ah 42h
Symbol AGC_GAINMD
Access: Size:
Read/Write 8 bits
Description
Mode 0 1 2 3
[5] [4:2] [1] R/W R/W R/W AGC_FreeMM RESERVED Y_AGC_SEL
Type Positive gain Positive gain 1x~2x Negative gain 1x~2x Negative gain
1: release dynamic gain control whenever no signal is present 0: allow dynamic gain control If 0, refer to ADCGSG
Mode 0 1
[0] R/W CR_AGC_SEL If 0, refer to ADCRSG
Type Static gain Dynamic gain Type Static gain Dynamic gain
Mode 0 1
3.1.12 Blank Sync Level
Address Offset: Default Value:
Bit [7:0] Access R/W
1Ch C0h
Symbol BLANK_SL
Access: Size:
Read/Write 8 bits
Description
36
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.13 ADC Read-back Selection
Address Offset: Default Value:
Bit [7:3] [2:0] Access R/W R/W
Copyright by Terawins,
1Dh 80h
Symbol RESERVED RBK_SEL
Access: Size:
Read/Write 8 bits
Description
1: Read Max of ADC data 0:Read Min of ADC data or Average of ADC data
3.1.14 ADC Read-back Data
Address Offset: Default Value:
Bit [7:0] Access R/W
1Eh 00h
Symbol RBK_ADC[7:0]
Access: Size:
Read/Write 8 bits
Description
3.1.15 ADC Read-back Data
Address Offset: Default Value:
Bit [7:2] [1:0] Access R R
1Fh 00h
Symbol RESERVED RBK_ADC[9:0]
Access: Size:
Read/Write 8 bits
Description
3.1.16 De-Interlaced Process & Vertical Shadow Control Register
Address Offset: Default Value:
Bit [7] [6] Access R/W R/W
30h 82h
Symbol CBCR_INTERP BLANK_LF_PRSVC
Access: Size:
Read/Write 8 bits
Description
[5]
R/W
VST_CHGSEL
1: Enable CbCr interpolation 0: Disable 1:When Left Cropping and this bit are enabled, the original YCbCr are preserved on blank interval. 0: When Left Cropping, the original YCbCr are reset as blank color 1:Vsync timing change determined by 8*# of XCLK 0:Vsynnc timing change determined by # of hsync # can be assigned at Reg 0x3A Interrupt polarity 1: positive 0: negative This bit control capture size for Scaler. 1: Hsize and Vsize are assigned by 54h ~57h 0: sizes assigned by input sources. Set 0 for normal operation Set 1 for interlaced video Set 0 for non-interlaced video
[4]
R/W
INT_EDGE
[3]
R/W
LB_SIZE_FIXED
[2] [1] [0]
R/W R/W R/W
ENQKHS ITLCPRO RESERVED
37
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.17 Source Select Register
Address Offset: Default Value:
Bit [7:5] [4] [3:0] Access R/W R/W R/W
Copyright by Terawins,
31h 00h
Symbol RESERVED RESERVED RESERVED
Access: Size:
Read/Write 8 bits
Description
3.1.18 Interrupt Status Register
Address Offset: Default Value:
Bit [7] [6] [5:0] Access R/W R R/W
32h 00h
Symbol RESERVED ITLCFLM INTSTS
Access: Size:
Read/Write 8 bits
Description
Indicates incoming video signal is interlaced
3.1.19 Interrupt Mask Register
Address Offset: Default Value:
Bit [7:6] [5:0] Access R/W R/W
33h FFh
Symbol RESERVED INTMASK
Access: Size:
Read/Write 8 bits
Description
3.1.20 Lower 8-bit Timer Counter Register
Address Offset: Default Value:
Bit [7:0] Access R/W
35h 00h
Symbol TM_1MS_L [7:0]
Access: Size:
Read/Write 8 bits
Description
Lower byte of the number of XCLK's in 1ms.
3.1.21 Upper 8-bit Timer Counter Register
Address Offset: Default Value:
Bit [7:0] Access R/W
36h 10h
Symbol TM_1MS_H [15:8]
Access: Size:
Read/Write 8 bits
Description
Higher byte of the number of XCLK's in 1ms.
3.1.22 VSYNC Missing Counter Register
Address Offset: Default Value:
Bit [7:0] Access R/W
37h 40h
Symbol V_MISS_CNT
Access: Size:
Read/Write 8 bits
Description
3.1.23 Lower 8-bit HSYNC Missing Counter Register
Address Offset: Default Value:
Bit [7:0] Access R/W
38h 00h
Symbol H_MISS_CNT_L[7:0]
Access: Size:
Read/Write 8 bits
Description
38
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.24 Upper 8-bit HSYNC Missing Counter Register
Address Offset: Default Value:
Bit [7:0] Access R/W
Copyright by Terawins,
39h 10h
Symbol H_MISS_CNT_L[15:8]
Access: Size:
Read/Write 8 bits
Description
3.1.25 VSYNC Delta Difference Result Register
Address Offset: Default Value:
Bit [7:0] Access R/W
3Ah 00h
Symbol VSYNC_DLT[7:0]
Access: Size:
Read/Write 8 bits
Description
3.1.26 HSYNC Delta Difference Result Register
Address Offset: Default Value:
Bit [7:0] Access R/W
3Bh 00h
Symbol HSYNC_DLT[7:0]
Access: Size:
Read/Write 8 bits
Description
3.1.27 Input Sync Signal Detection Register
Address Offset: Default Value:
Bit [7] [6] Access R/W R/W
3Fh 00h
Symbol HSTLSPVS AUTOVSD6
Access: Size:
Read/Write 8 bits
Description
1:use trailing edge of hsync to sample 0:use leading edge of hsync to sample When the edges of vsync and hsync are too close, input detection circuit can delay vsync 6 cycle of XCLK to avoid unstable detection 1:Automatically delay 6 cycles of XCLK if CFSEEDGE is true. 0:Dealy 6 cycles of XCLK if FCVSD6 is true
[5]
R/W
FCVSD6
AUTOVSD6 FCSVSD6T Auomatically delay VSync 6 XCLK if CFSEEDGE is true 1 x Force to delay VSync 6 XCLK 0 1 0 0 No Vsync Dealy
[4] [3:2] [1] [0] R R/W R/W R/W CFSEEDGE RESERVED VsHs_Sync_Edge VsHS_Sync_En VS and HS edges are to close.
1: leading edge of Vsi 0: falling edge of His 1:leading edge of Vsi starts at leading edge of Hsi 0:leading edge of Vsi starts at mid of Hsi
39
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.28 Left Border Cropping
Address Offset: Default Value:
Bit [7:6] [5:0] Access R/W R/W
Copyright by Terawins,
40h 00h
Symbol RESERVED CROP_LEFTB
Access: Read/Write Table 3-35 Left Border Croping
Description Remove noisy pixels appearing on left border. 1LSB =1 pixel
3.1.29 Gamma Correction for Video Source
Address Offset: Default Value:
Bit [7:6] Access R/W
42h 00h
Symbol VG_SEL
Access: Size:
Read/Write 8 bits
Description
0: Both Y ans C 1:C 2:Y 3:Reserved Enable Video gamma correction
[5:2] [1] [0]
R/W R/W R/W
RESERVED VGAM_EN RESERVED
3.1.30 Video Gamma Address Port Register
Address Offset: Default Value:
Bit [7:0] Access R/W
43h 00h
Symbol VGAM_ADR
Access: Size:
Read/Write 8 bits
Description
Video gamma coefficient table address. The Index range is 00h~FFh
3.1.31 Video Gamma Write/Read Port Register
Address Offset: Default Value:
Bit [7:0] Access R/W
44h 00h
Symbol VGA_WR_D
Access: Size:
Read/Write 8 bits
Description
Video gamma coefficient write data port.
3.1.32 VSYNC Timing Measurement Register
Address Offset: Default Value:
Bit [7] [6] Access R/W R/W
50h 00h
Symbol RESERVED HSPMD
Access: Size:
Read/Write 8 bits
Description
[5]
R
Register 0x5c and 0x5d can be HS pulse width or hsync period 1:Period in # of pixel clock. 0:Hsync pulse width in # of pixel clock. DONE_FRMXCLKCNT When EN_FRAMEXCLKCNT is enabled, a whole frame time can be obtained through XCLK counting. See registers 0x51, 0x52 and 0x53. After this bit read back as 1, then clear EN_FRAMEXCLKCNT first before reading 0x51~0x53 values. EN_FRAMEXCLKCNT When input VSync changes, enable this bit to start measurement on VSync using XCLK. RESERVED
[4] [3:0]
R/W R/W
40
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.33 VSYNC Measurement Counter L Register
Address Offset: Default Value:
Bit [7:0] Access R/W
Copyright by Terawins,
51h 00h
Symbol FRMXCLK_SUM[7:0]
Access: Size:
Read/Write 8 bits
Description
3.1.34 VSYNC Measurement Counter M Register
Address Offset: Default Value:
Bit [7:0] Access R/W
52h 00h
Symbol FRMXCLK_SUM[15:8]
Access: Size:
Read Only 8 bits
Description
3.1.35 VSYNC Measurement Counter H Register
Address Offset: Default Value:
Bit [7:0] Access R/W
53h 00h
Symbol FRMXCLK_SUM[23:16]
Access: Size:
Read Only 8 bits
Description
3.1.36 Hsize
Address Offset: Default Value:
Bit [7:0] Access R
54h 00h
Symbol HSIZE[7:0]
Access: Size:
Read Only 8 bits
Description
3.1.37 Hsize
Address Offset: Default Value:
Bit [7:4] [3:0] Access R/W R
55h 00h
Symbol RESERVED HSIZE[11:8]
Access: Size:
Read Only 8 bits
Description
3.1.38 Vsize
Address Offset: Default Value:
Bit [7:0] Access R
56h 00h
Symbol VSIZE[7:0]
Access: Size:
Read Only 8 bits
Description
3.1.39 Vsize
Address Offset: Default Value:
Bit [7:4] [3:0] Access R/W R
57h 00h
Symbol RESERVED VSIZE[11:8]
Access: Size:
Read Only 8 bits
Description
41
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.40 HSYNC Period LSB Register
Address Offset: Default Value:
Bit [7:0] Access R
Copyright by Terawins,
58h 00h
Symbol HS_PERIOD[7:0]
Access: Size:
Read Only 8 bits
Description
HSYNC period counted by XCLK
3.1.41 HSYNC Period MSB Register
Address Offset: Default Value:
Bit [7:0] Access R
59h 00h
Symbol HS_PERIOD[15:8]
Access: Size:
Read Only 8 bits
Description
HSYNC period counted by XCLK
3.1.42 VSYNC Period LSB Register
Address Offset: Default Value:
Bit [7:0] Access R
5Ah 00h
Symbol VS_PERIOD[7:0]
Access: Size:
Read Only 8 bits
Description
VSYNC period counted by input HSYNC
3.1.43 VSYNC Period MSB Register
Address Offset: Default Value:
Bit [7:4] [3:0] Access R/W R
5Bh 00h
Symbol RESERVED VS_PERIOD[11:8]
Access: Size:
Read Only 8 bits
Description
VSYNC period counted by input HSYNC
3.1.44 HSYNC Pulse Width LSB Register
Address Offset: Default Value:
Bit [7:0] Access R
5Ch 00h
Symbol HS_WIDTH[7:0]
Access: Size:
Read Only 8 bits
Description
HSYNC pulse width or period counted by dot clock See HSPMD for detail. Note: dot clock speed is in 1-pixel-per-clock mode
3.1.45 HSYNC Pulse Width MSB Register
Address Offset: Default Value:
Bit [7:4] [3:0] Access R R
5Dh 00h
Symbol RESERVED HS_WIDTH[11:8]
Access: Size:
Read Only 8 bits
Description
HSYNC pulse width or period counted by dot clock
3.1.46 VSYNC Pulse Width LSB Register
Address Offset: Default Value:
Bit Access
5Eh 00h
Symbol
Access: Size:
Read Only 8 bits
Description
[7:0]
R
VS_WIDTH[7:0]
VSYNC pulse width counted by input HSYNC
42
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.1.47 VSYNC Pulse Width MSB Register
Address Offset: Default Value:
Bit [7:4] [3:0] Access R R
Copyright by Terawins,
5Fh 00h
Symbol RESERVED VS_WIDTH[11:8]
Access: Size:
Read Only 8 bits
Description
VSYNC pulse width counted by input HSYNC
43
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.2 Picture Enhancement Register Set
Copyright by Terawins,
3.2.1 Bandwidth of Digital Color Transient Improvement
Address Offset: Default Value:
Bit [7] [6:1] [0] Access R/W R/W R/W
60h 02h
Symbol DCTI_EC RESERVED DCTI_BW
Access: Size:
8 bits
Description
DCTI Error Correction 0: high bandwidth 1: low bandwidth
3.2.2 Luma Peaking Control
Address Offset: Default Value:
Bit [7] [6] [5:0] Access R/W R/W R/W
61h 08h
Symbol PeakingEN HoldLR_PIX PeakingCo
Access: Size:
8 bits
Description
When this bit is enabled, the peaking doesn't affect pixels appearing at Left/Right borders.
3.2.3 Bandpass Peaking Coef
Address Offset: Default Value:
Bit [7:5] [4:0] Access R/W R/W
62h 04h
Symbol RESERVED BP_COEF
Access: Size:
8 bits
Description
3.2.4 Highpass Peaking Coef
Address Offset: Default Value:
Bit [7:5] [4:0] Access R/W R/W
63h 04h
Symbol RESERVED HP_COEF
Access: Size:
8 bits
Description
3.2.5 Lowpass Peaking Coef
Address Offset: Default Value:
Bit [7:3] [2:0] Access R/W R/W
64h 02h
Symbol RESERVED LP_COEF
Access: Size:
8 bits
Description
3.2.6 Gain and Coring of DLTI
Address Offset: 65h Access:
44
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc.
Default Value:
Bit [7:5] [4:0] Access R/W R/W
Copyright by Terawins,
08h
Symbol DLTI_GAIN DLTI_CO
Size:
8 bits
Description
3.2.7 Gain and Coring of DCTI
Address Offset: Default Value:
Bit [7:5] [4:0] Access R/W R/W
66h 08h
Symbol DCTI_GAIN DCTI_CO
Access: Size:
8 bits
Description
3.2.8 Contrast Adjust
Address Offset: Default Value:
Bit [7:0] Access R/W
68h 80h
Symbol LumaCON
Access: Size:
8 bits
Description
3.2.9 Brightness Adjust
Address Offset: Default Value:
Bit [7:0] Access R/W
69h 80h
Symbol LumaBRI
Access: Size:
8 bits
Description
3.2.10 Hue Sin Adjust
Address Offset: Default Value:
Bit [7:0] Access R/W
6Ah 00h
Symbol HueSin
Access: Size:
8 bits
Description
3.2.11 Hue Cos Adjust
Address Offset: Default Value:
Bit [7:0] Access R/W
6Bh 7Fh
Symbol HueCos
Access: Size:
8 bits
Description
3.2.12 Chroma Saturation Adjust
Address Offset: Default Value:
Bit [7:0] Access R/W
6Ch 80h
Symbol ChromSat
Access: Size:
8 bits
Description
45
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.3 Scaling Register Set
Copyright by Terawins,
3.3.1 Scaling General Control Register
Address Offset: Default Value:
Bit [7:6] [5] [4] [3:2] Access R/W R/W R/W R/W
70h 00h
Symbol RESERVED Inv_VideoF Dclki_is_Faster De-interlacing option
Access: Size:
Read/Write 8 bits
Description
Inv_VideoF: Reverse input odd field control for intra field scaling, only take action when ITLCPRO is set to 1.
Software need to turn this bit on when the freq of input pixel clock is higher than output pixel clock. 00:1/2 line 01:1/4 line 10: 1/8 line Reset coef table. 1: Reset write pointer to 0x00. 0: Don't Care
[0]
R/W
C16_Pointer_RST
3.3.2 Scaling Coefficient Data Port Register
Address Offset: Default Value:
Bit [7:0] Access R/W
71h 00h
Symbol Coef_Data_Port
Access: Size:
Read/Write 8 bits
Description
3.3.3 Horizontal Scale Step LSB Register
Address Offset: Default Value:
Bit [7:0] Access R/W
72h 00h
Symbol H_Scale_Step [7:0]
Access: Size:
Read/Write 8 bits
Description
3.3.4 Horizontal Scale Step MSB Register
Address Offset: Default Value:
Bit [7:0] Access R/W
73h 00h
Symbol H_Scale_Step [15:8]
Access: Size:
Read/Write 8 bits
Description
3.3.5 Vertical Scale Step LSB Register
Address Offset: Default Value:
Bit [7:0] Access R/W
74h 00h
Symbol V_Scale_Step [7:0]
Access: Size:
Read/Write 8 bits
Description
46
T118B Advanced Information-Confidential P/N-T118B-Rev01 Inc. 3.3.6 Vertical Scale Step MSB Register
Address Offset: Default Value:
Bit [7:0] Access R/W
Copyright by Terawins,
75h 00h
Symbol V_Scale_Step [15:8]
Access: Size:
Read/Write 8 bits
Description
3.3.7 Horizontal Aspect Ratio Register
Address Offset: Default Value:
Bit [7:0] Access R/W
76h 00h
Symbol HASPR[7:0]
Access: Size:
Read/Write 8 bits
Description
3.3.8 Horizontal Aspect Ratio Register
Address Offset: Default Value:
Bit [7] [6] [5:0] Access R/W R/W R/W
77h 00h
Symbol HASPEN HASP_C_ELG HASPR[13:8]
Access: Size:
Read/Write 8 bits
Description
3.3.9 Antialiasing Filtering
Address Offset: Default Value:
Bit [7:6] [5:4] Access R/W R/W
78h 00h
Symbol RESERVED LPF_AVE
Access: Size:
Read/Write 8 bits
Description
[3] [2] [1:0]
R/W R/W R/W
LPF_BND_DUP RESERVED LPF_SHPIX
3: LPF ==[0.25 0.25 0.25 0.25] 2: LPF ==[0.25 0.5 0.25] 0/1:LPF ==[0 1 0] Padding starting and ending pixels at starting and ending position. Pipelined alignment for antialiasing LPF
3.3.10 Half Sampling and Luma High Boost
Address Offset: Default Value:
Bit [7:6] [5] [4] [3:0] Access R/W R/W R/W R/W
79h 00h
Symbol RESERVED En_Half_Input RESERVED LumaHB[3:0]
Access: Size:
Read/Write 8 bits
Description
Half Sampling by pixel reduction. When this bit is enabled, P0_30h[7] must be disabled. Luma High Boost Coef
3.3.11 Chroma High Boost
Address Offset: Default Value:
Bit [7:4] [3:0]