Text preview for : EFL50-LS2766P-VGA-DDR2-R10-20051222A.pdf part of some brands - algumas marcas some schematic motherboards notebooks downloaded from www.freeservicemanuals.net. alguns esquemas placa-mae e notebook baixados de www.freeservicemanuals.net.
Back to : Notebook_MB schematic.par | Home
5
4
3
2
1
D
D
C
Mini (EFL50) ATI VGA/B M52-P
Revision 1.0
C
B
B
A
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title Size Date:
Compal Electronics, Inc.
Cover Sheet
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
EFL50 LS-2766P
12/23/05 14:40:19
Rev 1.0 Sheet
1
1
of
13
5
4
3
2
1
M54P/M52P BLOCK DIAGRAM
GDDR1
D
DDRA
K4D553235F-GC2A
8M*32
MDA[0:63] DQ[0:31] A[0:11] NMAA[0:13] DQA[0:63] MAA[0:13]
M54P/M52P
PCIE_TX[0:15]P, PCIE_TX[0:15]N PCIE_RX[0:15]P, PCIE_RX[0:15]N PCIE_REFCLKP, PCIE_REFCLKN PWRGD
PCIE Connector
PCIE_MTX_C_GRX_P[0:15], PCIE_MTX_C_GRX_N[0:15] PCIE_GT_MRX_P[0:15], PCIE_GTX_MRX_N[0:15] CLK_PCIE_VGA CLK_PCIE_VGA# PLTRST_VGA#
D
Samsung
CLK/CLK# PAGE 8
NMCLKA0/A0# NMCLKA1/A1#
CLKA[0:1] CLKA[0:1]#
DVI TV_OUT VGA_OUT
DVI_TXD[0:2](+,-); DVI_TXC+(-) VGA_TV_LUMA,VGA_TV_CRMA VGA_CRT_R, VGA_CRT_G, VGA_CRT_B, DACA_HSYNC, DACA_VSYNC VGA_DDC_CLK, VGA_DDC_DAT
DDRB
C
8M*32
MDB[0:63] DQ[0:31] A[0:11] NMAB[0:13] MDB[0:63] NMAB[0:13]
DDC1_I2C
C
K4D553235F-GC2A
LVDS Bus
DVPDATA[18:19] CLK/CLK# PAGE 9 NMCLKB0/B0# NMCLKB1/B1# CLKB[0:1] CLKB[0:1]# DIGON
Samsung
I2CC_SCL I2CC_SDA
VGA_ENVDD
27MHz SPREAD CLOCK
ASM3P1819N-SR PAGE 4
B
BLON
VGA_ENBKL
OSC_IN OSC_SPREAD PCIE_VDDR PCIE_PVDD
+1.2VS
+1.2VS
APW7057KC-TR PAGE 11
+1.5VS
+5VS
+1.5VS +5VS B+ +3VS +1.8VS +2.5VS
B
ACES 88069-1600A PAGE 3
THERMAL SENSOR
MAX6649MUA PAGE 4
D+/DTHERM_SDA, THERM_SCL THER_ALERT GPIO_AUXWIN VDDR3 VDDR4 VDDR5 VDDR1 VDD25, LVDDR, TXVDDR, AVDD, A2VDD PAGE 4,5,6,7 +3.3VS VDDC GPIO5 +VDD_CORE POWER_SEL
+VDD_CORE
SL6225BCA-T PAGE 11
B+
+1.8VS +2.5VS
A
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title Size Date:
Compal Electronics, Inc.
Block Diagram
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
EFL50 LS-2766P
12/23/05 14:40:19
Rev 1.0 Sheet
1
2
of
13
5
4
3
2
1
PCIE_GTX_MRX_P[0:15] PCIE_GTX_MRX_N[0:15] PCIE_MTX_C_GRX_P[0:15] PCIE_MTX_C_GRX_N[0:15]
PCIE_GTX_MRX_P[0:15] <4> PCIE_GTX_MRX_N[0:15] <4> PCIE_MTX_C_GRX_P[0:15] <4> PCIE_MTX_C_GRX_N[0:15] <4>
161
D
JP1
<4> VGA_CRT_R <4> VGA_CRT_G <4> VGA_CRT_B <4> CRT_VSYNC <4> CRT_HSYNC
VGA_CRT_R VGA_CRT_G VGA_CRT_B CRT_VSYNC CRT_HSYNC PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15
D
C
<4> VGA_CRT_CLK <4> VGA_CRT_DAT
B
VGA_CRT_CLK VGA_CRT_DAT
<5> <5> <5> <5> <5> <5> <5> <5>
DVI_TXC+ DVI_TXCDVI_TX0+ DVI_TX0DVI_TX1+ DVI_TX1DVI_TX2+ DVI_TX2-
<4> CLK_PCIE_VGA <4> CLK_PCIE_VGA# +5VALW
+2.5VS +1.8VS_D
A
162
ACES_88396-1G41
G2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
G1
B+
VGA_TV_Y VGA_TV_C VGA_TV_COMP PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9
VGA_TV_Y <4> VGA_TV_C <4> VGA_TV_COMP <4> C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCIE_GTX_MRX_P0 PCIE_GTX_MRX_N0 PCIE_GTX_MRX_P1 PCIE_GTX_MRX_N1 PCIE_GTX_MRX_P2 PCIE_GTX_MRX_N2 PCIE_GTX_MRX_P3 PCIE_GTX_MRX_N3 PCIE_GTX_MRX_P4 PCIE_GTX_MRX_N4 PCIE_GTX_MRX_P5 PCIE_GTX_MRX_N5 PCIE_GTX_MRX_P6 PCIE_GTX_MRX_N6 PCIE_GTX_MRX_P7 PCIE_GTX_MRX_N7 PCIE_GTX_MRX_P8 PCIE_GTX_MRX_N8 PCIE_GTX_MRX_P9 PCIE_GTX_MRX_N9 PCIE_GTX_MRX_P10 PCIE_GTX_MRX_N10 PCIE_GTX_MRX_P11 PCIE_GTX_MRX_N11 PCIE_GTX_MRX_P12 PCIE_GTX_MRX_N12 PCIE_GTX_MRX_P13 PCIE_GTX_MRX_N13 PCIE_GTX_MRX_P14 PCIE_GTX_MRX_N14 PCIE_GTX_MRX_P15 PCIE_GTX_MRX_N15
B C
PCIE_GTX_C_MRX_P10 C22 PCIE_GTX_C_MRX_N10 C23 PCIE_GTX_C_MRX_P11 C24 PCIE_GTX_C_MRX_N11 C25 PCIE_GTX_C_MRX_P12 C26 PCIE_GTX_C_MRX_N12 C27 PCIE_GTX_C_MRX_P13 C28 PCIE_GTX_C_MRX_N13 C29 PCIE_GTX_C_MRX_P14 C30 PCIE_GTX_C_MRX_N14 C31 PCIE_GTX_C_MRX_P15 C32 PCIE_GTX_C_MRX_N15 C33
VGA_DVI_CLK VGA_DVI_DAT DAC_BRIG DISPOFF# INVT_PWM PCIE_RST# VGA_ENBKL LCD_ID#
VGA_DVI_DET <5> VGA_DVI_CLK <5> VGA_DVI_DAT <5> DAC_BRIG <10> DISPOFF# <10> INVT_PWM <10> PCIE_RST# <4> susp# <10,11> VGA_ENBKL <4> LCD_ID# <10> +3VS_D
TP7 +1.5VS
+1.8VS_D
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
VGA Connector Size Document Number Custom Date: 12/23/05 14:40:19
PCIE Connector
EFL50 LS-2766P
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Rev 1.0 3 of 13
5
4
3
2
1
<3> PCIE_GTX_MRX_P[0:15] <3> PCIE_GTX_MRX_N[0:15]
PCIE_GTX_MRX_P[0:15] PCIE_GTX_MRX_N[0:15] <3> CLK_PCIE_VGA <3> CLK_PCIE_VGA# CLK_PCIE_VGA CLK_PCIE_VGA# PCIE_GTX_MRX_P0 PCIE_GTX_MRX_N0 PCIE_GTX_MRX_P1 PCIE_GTX_MRX_N1 PCIE_GTX_MRX_P2 PCIE_GTX_MRX_N2 PCIE_GTX_MRX_P3 PCIE_GTX_MRX_N3 PCIE_GTX_MRX_P4 PCIE_GTX_MRX_N4 PCIE_GTX_MRX_P5 PCIE_GTX_MRX_N5 PCIE_GTX_MRX_P6 PCIE_GTX_MRX_N6 PCIE_GTX_MRX_P7 PCIE_GTX_MRX_N7 PCIE_GTX_MRX_P8 PCIE_GTX_MRX_N8 PCIE_GTX_MRX_P9 PCIE_GTX_MRX_N9 PCIE_GTX_MRX_P10 PCIE_GTX_MRX_N10 PCIE_GTX_MRX_P11 PCIE_GTX_MRX_N11 PCIE_GTX_MRX_P12 PCIE_GTX_MRX_N12 PCIE_GTX_MRX_P13 PCIE_GTX_MRX_N13 PCIE_GTX_MRX_P14 PCIE_GTX_MRX_N14 PCIE_GTX_MRX_P15 PCIE_GTX_MRX_N15 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 R26 1 R2 1 R3 1 R1 R24 1
U2A
+3VS
Straps: (Internal pull down)
Transmitter power saving enable Transmitter de-emphasis enable Debug Access
VGA_ENBKL <3> Current bias for the PCI Express PHY PLL
AL28 AK28 AK27 AJ27 AJ25 AH25 AH28 AG28 AG27 AF27 AF25 AE25 AE28 AD28 AD27 AC27 AC25 AB25 AB28 AA28 AA27 Y27 Y25 W25 W28 V28 V27 U27 U25 T25 T28 R28 R27 P27 AJ31 AH31 AH30 AG30 AG32 AF32 AF31 AE31 AE30 AD30 AD32 AC32 AC31 AB31 AB30 AA30 AA32 Y32 Y31 W31 W30 V30 V32 U32 U31 T31 T30 R30 R32 P32 P31 N31
PCIE_REFCLKP PCIE_REFCLKN PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N PCIE_CALRN PCIE_CALRP PCIE_CALI PERST# PCIE_TEST PERST#_MASK
GPIO
<3> PCIE_MTX_C_GRX_P[0:15] <3> PCIE_MTX_C_GRX_N[0:15]
PCIE_MTX_C_GRX_P[0:15] PCIE_MTX_C_GRX_N[0:15]
D
PCI-Express Data Bus Lane Reversal and Polarity Inversion
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 NC VREFG
AD4 AD2 AD1 AD3 AC1 AC2 AC3 AB2 AC6 AC5 AC4 AB3 AB4 AB5 AD5 AB8 AA8 AB7 AB6 AC8 AK4 AL4 AF2 AF1 AF3 AG1 AG2 AG3 AH2 AH3 AJ2 AJ1 AK2 AK1 AK3 AL2 AL3 AM3 AE6 AF4 AF5 AG4 AJ3 AH4 AJ4 AG5 AH5 AF6 AE7 AG6
R63 R14 R13 R80 R16 1 GPIO9
1 1 1 1
2 @ 10K_0402_5% 10K_0402_5% 2 2 @ 10K_0402_5% 10K_0402_5% 2
VGA_ENBKL 2 10K_0402_5%
GPIO[0] GPIO[1]
0: 50% TX output swing 1: Full TX output swing 0: TX de-emphasis disable 1: TX de-emphasis enable
TP4 GPIO11 GPIO12 GPIO13 POWER_SEL OSC_SPREAD THER_ALERT# R53 2 R54 1 POWER_SEL <11>
GPIO[4] 0: OFF 1: ON GPIO[5] GPIO5 = 1
(must be pulled to 3.3V at reset using)
D
ROM ID Config
GPIO[9, GPIO[9]=1 External ROM Attached 13:11] GPIO[9]=0 No External ROM
For No External ROM: GPIO[13,12] is for MEM_AP_SIZE[1,0] (Internal GPIO[11] don't care Pull-down)
1 499_0402_1% +3VS 2 499_0402_1% C130 1 2 0.1U_0402_16V4Z
VIP_DEVICE
VSYNC
0: Slave VIP host device present 1: No slave VIP host device present
* The readback of this strap is the inverted with respect to the value on the pin
NC_DVOVMODE_0 NC_DVOVMODE_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23
VIP HOST/ EXTERNAL TMDS
Low -> VDDC=1.0V+-5% Performance Mode for M52 High -> VDDC=0.95V+-5% Battery Mode for M52
POWER_SEL R97 1
2 10K_0402_5%
GPIO9 GPIO11 GPIO12 GPIO13 R78 R79 R76 R77
+3VS
PCI EXPRESS
1 1 1 1
GPIO13 0 1 0 1
2 @ 10K_0402_5% 2 @ 10K_0402_5% 2 R256@10K_0402_5% 2 R64@ 10K_0402_5%
C
C
+3VS
Thermal sensor
1
+3VS R51 2.2K_0402_5% THM@
+3VS TP6 TP3 MEMID0 MEMID1 MEMID2 TP1 R12 1 R10 1 R11 R9 R8
GPIO12 0 0 1 1
SIZE 128MB 64MB 256MB Reserve
U7
2
1 2 3
VDD D+ D-
SCLK SDATA ALERT# GND
8 7 6 5
THERM_SCL THERM_SDA
THM@ R50 2.2K_0402_5% THER_ALERT#
1 1 1
2 4.7K_0402_5% 2 4.7K_0402_5% I2C_DAT I2C_CLK 2 10K_0402_5% R128@ 2 10K_0402_5% X76@ 10K_0402_5% HYN@ 2
Memory Aperture Size Select
I2C_DAT <10> I2C_CLK <10> +3VS
2
For DDRII Size 64MB 64MB Size (Speed) Vender Chips Samsung Samsung Hynix Hynix 2 4 2 4
D+ DC121 1 2 2200P_0402_50V7K THM@
Vedio Memory Config. (VGA Internal PD) MEMID[2:0]
1 R48
4
OVERT#
2 0_0402_5% THM@
1
CRT
MAX6649MUA_8UMAX THM@
R G B HSYNC VSYNC
AK24 AM24 AL24 AJ23 AJ22
VGA_CRT_R VGA_CRT_G VGA_CRT_B CRT_HSYNC CRT_VSYNC R32 1 R27 1
VGA_CRT_R <3> VGA_CRT_G <3> VGA_CRT_B <3> CRT_HSYNC <3> CRT_VSYNC <3>
0 0 1 1
+3VS
0 0 0 0
0 1 0 1
16M16 (300MHz) 16M16 (300MHz)
128MB 16M16 (300MHz) 128MB 16M16 (300MHz)
2 4.7K_0402_5% 2 4.7K_0402_5%
B
+1.2VS
DDC1DATA DDC1CLK GENERICA GENERICB RSET
AH22 AH23 AK22 AF23 AL22 AK15 AM15 AL15 AF15 AG15
VGA_TV_Y AJ15 VGA_TV_C AJ13 AH15 VGA_TV_COMP R28 R33
VGA_CRT_DAT VGA_CRT_CLK 1K_0402_5% 499_0402_1%
VGA_CRT_DAT <3> VGA_CRT_CLK <3>
B
2 2K_0402_1% AE24 2 562_0402_1% AD24 2 1.47K_0402_1% AB24 1 2 0_0402_5% 2 10K_0402_5% AG24 AA24 AF24
2 2
1 1
Internal SS, Programmed via register-GENERICA = NC GENERICB = GND.
<3> PCIE_RST#
TV
THERMAL
R2 G2 B2 H2SYNC V2SYNC Y C COMP R2SET ROMCS# PLLTEST TESTEN
+3VS
Close to VGA Cbip
VGA_TV_Y <3> VGA_TV_C <3> VGA_TV_COMP <3> R35 2 R39 VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_TV_Y VGA_TV_C R56 R30 R29 R36 R45
1
D+ R22
AG12 AH12 AE12 AF12 AL26 AM26
DPLUS DMINUS DDC3DATA DDC3CLK XTALIN XTALOUT
M52-P
SSC@ 0_0603_5% 2
Spread spectrum
U6 +SSVDD
+3VS R6 1 R7 1 4.7K_0402_5% 2 2 4.7K_0402_5%
DTHERM_SDA THERM_SCL
2 2 2 2 2
1 @ 150_0402_1% 1 @ 150_0402_1% 1 @ 150_0402_1% 1 @ 150_0402_1% 1 @ 150_0402_1%
AK14 2 AC7 AG14 AG22
R31 1
1 150_0402_1%
715_0402_1%
7 1 8
VDD
REF
5 4 3 6 1 R17 2 OSC_SPREAD 22_0402_5% SSC@
1
C38 SSC@ 0.1U_0402_16V4Z
1
XIN MODOUT XOUT VSS NC PD#
OSC_IN 1 R25
2 121_0402_1%
R23
XTAL
2 10K_0402_5%
2
2
A
R34 1K_0402_5% 2
1 2 C50 0.1U_0402_16V4Z X1 4 VDD OUT 1 OE GND
27MHZ_15P
1
2
+3VS
ASM3P1819N-SR_SO8 SSC@ Minimize distance from X1 pin3 to U3 pin1
1
71.5_0402_1%
A
Security Classification
3 2
OSC_IN
Compal Secret Data
2005/12/22 Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
M52-P Main
Rev 1.0 Sheet
1
Issued Date
Keep away from other signal at last 25mils
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:18
4
of
13
5
5
4
3
2
1
U2F U2G U2B
D
AE13 AF13 AF9 AG7 AE10 AE9 AF7 AF8 AH6 AF10 AG10 AH9 AJ8 AH8 AG9 AH7 AG8 AE23 Y23 K15 R10 AC17 AC14 M23 V10 K18 L10 K22 AA10
C66
GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GENERICC BBN BBN BBN BBN BBP BBP BBP BBP VDD25 VDD25 VDD25
EXPAND GPIO LVDS
TXCLK_UP TXCLK_UN TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N TXCLK_LN TXCLK_LP TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N VARY_BL DIGON GENERICD TXCM TXCP TX0M TX0P TX1M TX1P TX2M TX2P TX3M TX3P TX4M TX4P TX5M TX5P DDC2DATA DDC2CLK HPD1
AJ21 AK21 AG18 AH18 AK20 AJ20 AG20 AH20 AH21 AG21 AL18 AM18 AL19 AK19 AM20 AL20 AM21 AL21 AJ18 AK18 AD12 R44 1 AE11 AD23
R52 1
VGA_LVDSBC+ VGA_LVDSBCVGA_LVDSB0+ VGA_LVDSB0VGA_LVDSB1+ VGA_LVDSB1VGA_LVDSB2+ VGA_LVDSB2-
VGA_LVDSBC+ <10> VGA_LVDSBC- <10> VGA_LVDSB0+ <10> VGA_LVDSB0- <10> VGA_LVDSB1+ <10> VGA_LVDSB1- <10> VGA_LVDSB2+ <10> VGA_LVDSB2- <10>
TV GND
VGA_LVDSACVGA_LVDSAC+ VGA_LVDSA0+ VGA_LVDSA0VGA_LVDSA1+ VGA_LVDSA1VGA_LVDSA2+ VGA_LVDSA2-
VGA_LVDSAC- <10> VGA_LVDSAC+ <10> VGA_LVDSA0+ <10> VGA_LVDSA0- <10> VGA_LVDSA1+ <10> VGA_LVDSA1- <10> VGA_LVDSA2+ <10> VGA_LVDSA2- <10>
FOREARD COMPATIBILITY
VGA_ENVDD <10>
PLL GND
2 10K_0402_5% VGA_ENVDD 2 180_0402_5%
PCIE GND
AL9 AM9
R49 1
DVI_TXCDVI_TXC+
AK10 AL10
R46 1
DVI_TX0DVI_TX0+
INTERGRATED TMDS
2 180_0402_5%
DVI_TX1DVI_TX1+
DVI_TX0- <3> DVI_TX0+ <3> DVI_TX1- <3> DVI_TX1+ <3> DVI_TX2- <3> DVI_TX2+ <3>
LVDS PLL&I/O GND
2 180_0402_5%
DVI_TXC- <3> DVI_TXC+ <3>
+VDD25
C
AL11 AM11
R43 1
1
C81
1
2 180_0402_5%
DVI_TX2DVI_TX2+
AL12 AM12 AK9 AJ9 AK11 AJ11 AK12 AJ12 AH13 AG13 AF11 1
2
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
VGA_DVI_DAT VGA_DVI_CLK VGA_DVI_DET R114 100K_0402_5%
VGA_DVI_DAT <3> VGA_DVI_CLK <3> VGA_DVI_DET <3>
M52-P
if no DVI , dvi_det pull low
AH27 AC23 AL27 R23 P25 R25 T26 U26 Y26 AB26 AC26 AD25 AE26 AF26 AD26 AG25 AH26 AC28 Y28 U28 P28 AH29 AF28 V29 AC29 W27 AB27 V26 AJ26 AJ32 AK29 P26 P29 R29 T29 U29 W29 Y29 AA29 AB29 AD29 AE29 AF29 AG29 AJ29 AK26 AK30 AG26 N30 R31 AF30 AC30 V31 P30 AA31 U30 AD31 AK32 AJ28 Y30 AJ30 AK31
PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS
M52-P
TMDS GND
TXVSSR TXVSSR TXVSSR TXVSSR TXVSSR TPVSS AVSSQ AVSSN AVSSN VSS1DI A2VSSQ A2VSSN A2VSSN VSS2DI PVSS MPVSS LPVSS LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR PCIE_PVSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS
AJ7 AK7 AL7 AM7 AK8 AL8 AK23 AK25 AJ24 AL23 AK13 AM17 AL17 AJ17 AH14 A5 AE18 AK17 AJ19 AF18 AH17 AG17 AG19 AH19 AF22 AF17 AF21 W23 AB23 P24 R24 T24 U24 V24 W24 Y24 AC24 AH24 V25 AA25 R26 AA26 T27 AE27 AG31 W26 N24 AA23
CRT GND
Use 15mils trace connect to GND
B
B1 H1 L1 P1 U1 Y1 AD7 AE8 AL1 A2 AM2 AD10 E8 H5 K10 M8 T10 E12 AC9 AF14 AD8 C5 F10 J3 L6 M6 P6 AA4 AG11 V3 AG16 R3 C6 C9 F6 H7 J6 AD16 AA6 P7 P5 M3 M9 L7 M7 AD17 AH11 A8 U7 C10 E9 F3 J9 N7 N3 Y5 AM13 AC10 Y6 U6 E5 AL13 A11 U8 U9 U10 R6 AD6 V6 AD14 AD13 D11 J12 K12 A13 F13 E13 F15 K16 W18
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CORE GND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C27 E32 H28 J30 K17 K27 M32 A22 C20 E19 H20 J24 M28 J28 J16 F30 L29 A31 B32 E30 AE15 AG23 AD9 AF16 AH10 AJ10 AD15 AH16 K23 U18 AE16 AE17 A19 H32 F19 G19 N8 Y7 T19 V19 G21 C21 F21 AE14 AK16 U5 F22 F18 K30 C24 F24 M24 A25 D30 E25 G25 G20 G22 F27 E28 H21 J21 H16 T15 V17 C15 C4 U14 P15 A16 E16 G13 G16 P17 R16 R14 W16 C18 F16
D
C
2
B
M52-P
A
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
M52-P LVD,DVI,GND,Screw
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:18
5
of
13
5
4
3
2
1
U2D U2C <8,9> MDA[0..63] MDA[0..63] DQSA[0..7] DQSA#[0..7] DQMA#[0..7] MAA[0..12] A_BA[0..1] MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 +MVREFD_1 +MVREFS_1
D
+1.8VS
R19 100_0402_1%
2
1
1
C40 0.1U_0402_16V4Z
R21 100_0402_1%
1
C145 0.1U_0402_16V4Z
1
+MVREFD_0 (15mils)
2
C
2
2
2
+1.8VS
M31 M30 L31 L30 H30 G31 G30 F31 M27 M29 L28 L27 J27 H29 G29 G27 M26 L26 M25 L25 J25 G28 H27 H26 F26 G26 H25 H24 H23 H22 J23 J22 E23 D22 D23 E22 E20 F20 D19 D18 B19 B18 C17 B17 C14 B14 C13 B13 D17 E18 E17 F17 E15 E14 F14 D13 H18 H17 G18 G17 G15 G14 H14 J14
+MVREFD_0 (15mils) +MVREFS_0 (15mils)
2
R18 100_0402_1% (15mils)
DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63
MEMORY A
MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15
D26 F28 D28 D25 E24 E26 D27 F25 C26 B26 D29 B27 B25 C25 E27 E29 H31 J29 J26 G23 E21 B15 D14 J17 J31 K29 K25 F23 D20 B16 D16 H15 K31 K28 K26 G24 D21 C16 D15 J15 F29 D24 D31 E31 B30 B28 C29 B31 B29 C28
<8,9> DQSA[0..7] <8,9> DQSA#[0..7] <8,9> DQMA#[0..7] <8,9> MAA[0..12] <8,9> A_BA[0..1]
DQMA#_0 DQMA#_1 DQMA#_2 DQMA#_3 DQMA#_4 DQMA#_5 DQMA#_6 DQMA#_7 QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 QSA_0# QSA_1# QSA_2# QSA_3# QSA_4# QSA_5# QSA_6# QSA_7# ODTA0 ODTA1 CLKA0 CLKA0# CKEA0 RASA0# CASA0# WEA0# CSA0#_0 CSA0#_1 CLKA1 CLKA1# CKEA1 RASA1#
+1.8VS
R61 100_0402_1%
+MVREFD_1 (15mils) R62 100_0402_1%
2
+1.8VS
B12 C12 B11 C11 C8 B7 C7 B6 F12 D12 E11 F11 F9 D8 D7 F7 G12 G11 H12 H11 H9 E7 F8 G8 G6 G7 H8 J8 K8 L8 K9 L9 K5 L4 K4 L5 N5 N6 P4 R4 P2 R2 T3 T2 W3 W2 Y3 Y2 T4 R5 T5 T6 V5 W5 W6 Y4 R8 T8 R7 T7 V7 W7 W8 W9 B3 C3
2
R57 100_0402_1% (15mils) R58 1 4.7K_0402_5% R55 1 4.7K_0402_5% R60 1 4.7K_0402_5% R15 1 243_0603_1%
DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63
MEMORY B
MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15
G4 E6 E4 H4 J5 G5 F4 H6 G3 G2 D4 F2 H2 H3 F5 D5 B8 D9 G9 K7 M5 V2 W4 T9 B9 D10 H10 K6 N4 U2 U4 V8 B10 E10 G10 J7 M4 U3 V4 V9 D6 J4 B4 B5 C2 E2 D3 B2 D2 E3 N2 P3 L3 J2 L2 M2 K2 K3
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 A_BA0 A_BA1 MAA12
D
DQMB#_0 DQMB#_1 DQMB#_2 DQMB#_3 DQMB#_4 DQMB#_5 DQMB#_6 DQMB#_7 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 QSB_0# QSB_1# QSB_2# QSB_3# QSB_4# QSB_5# QSB_6# QSB_7# ODTB0 ODTB1 CLKB0 CLKB0# CKEB0 RASB0# CASB0# WEB0# CSB0#_0 CSB0#_1 CLKB1 CLKB1# CKEB1
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 DQSA0 DQSA1 DQSA2 DQSA3 DQSA4 DQSA5 DQSA6 DQSA7 DQSA#0 DQSA#1 DQSA#2 DQSA#3 DQSA#4 DQSA#5 DQSA#6 DQSA#7
1
1
C
ODTA0 <8> ODTA1 <9> MCLKA0 MCLKA0# MCKEA0 MRASA0# MCASA0# MWEA0# MCSA0#0 MCLKA0 <8> MCLKA0# <8> MCKEA0 <8> MRASA0# <8> MCASA0# <8> MWEA0# <8> MCSA0#0 <8>
1
1
B
1
C31 C30
MVREFD_0 MVREFS_0
B20 C19 C22
0.1U_0402_16V4Z
MVREFD_1 MVREFS_1 DRAM_RST TEST_MCLK TEST_YCLK MEMTEST
MCLKA1 MCLKA1# MCKEA1 MRASA1# MCASA1# MWEA1# MCSA1#0
MCLKA1 <9> MCLKA1# <9> MCKEA1 <9> MRASA1# <9> MCASA1# <9> MWEA1# <9> MCSA1#0 <9>
B
1
1
C147 R59 100_0402_1%
1
C39 0.1U_0402_16V4Z R20 100_0402_1%
2 2 2
MEM_RST AA3
B24 B22 B21 B23 C23
RASB1# CASB1# WEB1# CSB1#_0 CSB1#_1
2
2
CASA1# WEA1# CSA1#_0 CSA1#_1
M52-P
2
2
AA5 AA2
MEMTEST AA7 2 (15mil)
M52-P
A
GDDR2
Security Classification Issued Date 2005/12/22
A
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
M52-P Memory Interface
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:18
6
of
13
5
4
3
2
1
+PCIE_PVDD12 +1.8VS C118 1 1000mA for GDDR1 2400mA for GDDR3 C106 1 2 22U_0805_6.3V6M C62 +1.8VS U2E 1U_0402_6.3V4Z 2 C46 1U_0402_6.3V4Z C47 L13 1 2 BLM18PG121SN1D_0603 C53 1U_0603_10V6K +PCIE_VDDR12B L14 1 2 BLM18PG121SN1D_0603 C51 1U_0402_6.3V4Z +1.2VS
C37
2
2
C35 22U_0805_6.3V6M
2
1
2
2
0.1U_0402_16V4Z C54
0.1U_0402_16V4Z C67
1
2
1
2
1
2
0.1U_0402_16V4Z
D
0.1U_0402_16V4Z C71
22U_0805_6.3V6M C148 1
C149 1
2
1
2
2
0.1U_0402_16V4Z C117 1
0.1U_0402_16V4Z C60
0.1U_0402_16V4Z C112 1
2
1
2
2
0.1U_0402_16V4Z C107 1
0.1U_0402_16V4Z C86
0.1U_0402_16V4Z C74
2
1
2
1
2
0.1U_0402_16V4Z C131 1
0.1U_0402_16V4Z C82
0.1U_0402_16V4Z C124 1
2
1
2
2
0.1U_0402_16V4Z C122 1
0.1U_0402_16V4Z C98
0.1U_0402_16V4Z C120 1
2
1
2
2
0.1U_0402_16V4Z C36
0.1U_0402_16V4Z C126 1
0.1U_0402_16V4Z C123 1
1
C
2
2
2
0.1U_0402_16V4Z C103 1
0.1U_0402_16V4Z C128 1
0.1U_0402_16V4Z C116 1
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z +3VS C84
0.1U_0402_16V4Z +3VS
C1 J1 M1 R1 V1 AA1 A3 P9 J10 N9 P10 A9 Y10 P8 R9 Y9 J11 A21 M10 N10 Y8 J18 J19 K21 A12 H13 A15 J20 J13 K11 K19 A18 L23 K20 K24 L24 H19 A24 K13 J32 A30 C32 F32 L32
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
POWER PCIE_PVDD_12
PCIE_PVDD_12 PCIE_PVDD_12 PCIE_PVDD_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDD25 VDD25 VDD25
V23 100mA N23 P23 U23
1
1
1
1
Close to U2.N26
P CI EXPRESS
N29 2000mA 22U_0805_6.3V6M N28 2 2 N27 C59 C193 N26 1U_0603_10V6K N25 1 1 AL31 AM31 AM30 AL32 AL30 AM28 AL29 AM29 AM27 AC11 AC12 P14 U15 W14 W15 R17 R15 V15 V16 T16 U16 T17 U17 V14 R18 T18 V18 P18 P19 R19 W19 AD11
22U_0805_6.3V6M 2 C34 Close to U2.AL29
+1.2VS
D
2
1
2
C194
2
C42 1U_0402_6.3V4Z
2
+PCIE_VDDR12A L15 1 2 BLM18PG121SN1D_0603 C45 1U_0402_6.3V4Z
+1.2VS
1
MEMORY I/O
1 1U_0603_10V6K
1
1
+VGA_CORE C61 1
2
VDDC+VDDCI=18A C72 1
2
+VGA_CORE C70 1
+VGA_CORE C87
2
1
2
22U_0805_6.3V6M C56
0.1U_0402_16V4Z C89
0.1U_0402_16V4Z C94
0.1U_0402_16V4Z C97
1
2
1
2
1
2
1
2
22U_0805_6.3V6M C113 1
0.1U_0402_16V4Z C104 1
0.1U_0402_16V4Z C119 1
0.1U_0402_16V4Z C44
2
2
2
2
+
1
330U_D2E_2.5VM_R9
C
CO RE
22U_0805_6.3V6M C115 1
0.1U_0402_16V4Z C83
0.1U_0402_16V4Z C69
2
1
2
1
2
22U_0805_6.3V6M C68
0.1U_0402_16V4Z C102 1
0.1U_0402_16V4Z C99
1
2
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z +VDD25 22U_0805_6.3V6M 2 2 L1 1 2 CHB1608U301_0603
C140 1
2
1
2
C156 1
2
50mA
0.1U_0402_16V4Z +VDDRH L10 +1.8VS
0.1U_0402_16V4Z C63
22U_0805_6.3V6M C146 1
1
0.1U_0402_16V4Z 2 2 C159 C154 C153
2
2
I/O INTERNAL
1 2 BLM18PG121SN1D_0603
22U_0805_6.3V6M
0.1U_0402_16V4Z C127 1
0.1U_0402_16V4Z C136 1 50mA
AB9 AB10 AA9 AC19 AD18 AC20 AD19 AD20 AJ5 AM5 AL5 AK5 AE2 AE3 AE4 AE5
2
VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR4 VDDR4 VDDR4 VDDR4 VDDR5 VDDR5 VDDR5 VDDR5
AC13 50mA AC16 AC18 AC15 20mA W10 500mA T14 W17 P16 T23 K14 U19 2
+2.5VS
+VDDPLL L2
2
C108
C80
VDDPLL VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI
1 2 +1.2VS 2 BLM15AG102SN1D_0402
C101 1U_0402_6.3V4Z
1
1 1 0.1U_0402_16V4Z
C93 0.1U_0402_16V4Z
2
2
C267 1 1 22U_0805_6.3V6M
1
1
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z C64
0.1U_0402_16V4Z C139 1
0.1U_0402_16V4Z 2 2 C88 C135 2
+VDDCI L4 0.1U_0402_16V4Z 1 2 2 2 BLM18PG121SN1D_0603 C105 C75 C95
I/O
+VGA_CORE
B
+1.8VS
C270 22U_0805_6.3V6M
C271
C272 +VDDRH0 +VDDRH 400mA A27 F1
LVDS PLL, I/O
+VDDRH0 L16 0.1U_0402_16V4Z 1 2 BLM18PG121SN1D_0603 2 2 2
1
2
2
50mA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LPVDD/VDDL0 LVDDR/VDDL0 LVDDR/VDDL0 LVDDR/VDDL0 LVDDR/VDDL1 LVDDR/VDDL1 LVDDR/VDDL1 LVDDR/VDDL2 LVDDR/VDDL2 LVDDR/VDDL2 TPVDD
AE19 AF20 AE20 AF19 AC21 AC22 AD22 AE21 AD21 AE22
+LPVDD 20mA 200mA
1
1
0.1U_0402_16V4Z
1 1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
B
1
1
1 0.1U_0402_16V4Z
VDDRH0 VDDRH1 VSSRH0 VSSRH1
MEM I/O CLOCK
2
0.1U_0402_16V4Z 2 2 C55 C85
0.1U_0402_16V4Z 2 2 C65 C58 C57
+2.5VS
2
C73 0.1U_0402_16V4Z
BLM15AG102SN1D_0402 L5 1 2 +2.5VS 1 C268 + @ 330U_V_6.3VM_R25
+AVDD
A28 E1
1 1 1 22U_0805_6.3V6M 0.1U_0402_16V4Z
1
1 1 0.1U_0402_16V4Z
+LPVDD
22U_0805_6.3V6M 2 2 C125 C129 +A2VDD
2
1 1 0.1U_0402_16V4Z
L9 1 2 BLM15AG102SN1D_0402
TV
NC_A2VDDQ VDD2DI
M52-P
PLL
+2.5VS
1
C269 + @ 330U_V_6.3VM_R25
2
A
65mA AL25 L6 AM25 +VDDID BLM15AG102SN1D_0402 20mA AM23 1 2 +2.5VS 2 1 C132 0.1U_0402_16V4Z 130mAAM16 22U_0805_6.3V6M AL16 2 2 AL14 C144 C143 20mA AJ16 +VDDID 1 1 2 0.1U_0402_16V4Z C142 0.1U_0402_16V4Z
TM DS
AVDD AVDD
AM8 20mA AJ6 150mA AK6 AL6 AM6 AJ14 100mA A6
20mA +MPVDD L8 22U_0805_6.3V6M 2 2 C155 C134
1
+2.5VS
L7 1 2 BLM15AG102SN1D_0402
+2.5VS
VDD1DI A2VDD A2VDD
TXVDDR TXVDDR TXVDDR TXVDDR PVDD MPVDD
C RT
2
0.1U_0402_16V4Z C133
2
C141 0.1U_0402_16V4Z +PVDD L3
1
1 1 0.1U_0402_16V4Z 2
C96
1 2 +2.5VS 2 BLM15AG102SN1D_0402
C100 0.1U_0402_16V4Z
2
C138
1 2 +VGA_CORE 2 BLM15AG102SN1D_0402
C137 0.1U_0402_16V4Z
1
1 22U_0805_6.3V6M
1
1 22U_0805_6.3V6M
1
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
M52-P Power
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:19
7
of
13
5
4
3
2
1
MCLKA0# MCLKA0
<6,9> MDA[0..63] <6,9> DQSA[0..7] <6,9> DQSA#[0..7] <6,9> DQMA#[0..7]
MDA[0..63] DQSA[0..7] DQSA#[0..7] DQMA#[0..7] MAA[0..12] A_BA[0..1]
2
2
R37 56_0402_1% @
R38 56_0402_1% @
<6,9> MAA[0..12] <6,9> A_BA[0..1]
Default VRAM chip is SAM: SA00000YC00.
D
1
1
D
1
C92 470P_0402_50V7K @
U8 A_BA0 A_BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 MCLKA0# MCLKA0 MCKEA0
U9
L2 L3 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 K2
BA0 BA1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK CKE
2
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDD1 VDD2 VDD3 VDD4 VDD5 VDDL VSSDL
B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 J1 J7
MDA8 MDA9 MDA11 MDA10 MDA12 MDA13 MDA14 MDA15 MDA2 MDA1 MDA0 MDA3 MDA5 MDA7 MDA6 MDA4
A_BA0 A_BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0 MCLKA0# MCLKA0 +1.8VS MCKEA0
L2 L3 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 K2
BA0 BA1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK CKE
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDD1 VDD2 VDD3 VDD4 VDD5 VDDL VSSDL
B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 J1 J7
MDA29 MDA28 MDA31 MDA30 MDA27 MDA24 MDA26 MDA25 MDA19 MDA18 MDA17 MDA16 MDA20 MDA23 MDA22 MDA21
<6> MCLKA0# <6> MCLKA0 <6> MCKEA0
+1.8VS
+1.8VS +1.8VS
2
C
<6> MCSA0#0 <6> MWEA0# <6> MRASA0# <6> MCASA0#
MCSA0#0 MWEA0# MRASA0# MCASA0# DQMA#0 DQMA#1
L8 K3 K7 L7 F3 B3 K9 F7 E8
CS WE RAS CAS LDM UDM ODT
MCSA0#0 R108 0_0402_5% 64@ MWEA0# MRASA0# MCASA0# DQMA#2 DQMA#3
2
L8 K3 K7 L7 F3 B3 K9 F7 E8
CS WE RAS CAS LDM UDM ODT
C
R109 0_0402_5% 64@ +VDDL1
1
+VDDL0
+1.8VS <6> ODTA0 ODTA0 DQSA0 DQSA#0
1
2
C234 C235 0.1U_0402_16V4Z 64@ 1U_0603_10V6K 1 64@
+1.8VS ODTA0
1
1
2 R98 10K_0402_5% 64@
2 LDQS LDQS VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSS1 VSS2 VSS3 VSS4 VSS5 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 A3 E3 J3 N1 P9
1
2 R99 10K_0402_5% 64@
2
DQSA2 DQSA#2
C236 C237 0.1U_0402_16V4Z 64@ 1U_0603_10V6K 1 64@
LDQS LDQS
R42 64@ 1K_0402_1%
DQSA1 DQSA#1 (25mil) +VR_VREF_0
B7 A8 J2 A2 E2 L1 R3 R7 R8
SAM64@
UDQS UDQS VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8
R100 64@ 1K_0402_1%
DQSA3 DQSA#3 +VR_VREF_1
B7 A8 J2 A2 E2 L1 R3 R7 R8
UDQS UDQS VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8
R47 64@ 1K_0402_1%
B
1
C114 0.1U_0402_16V4Z 2 64@
R101 64@ 1K_0402_1%
1
C231 0.1U_0402_16V4Z 64@
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSS1 VSS2 VSS3 VSS4 VSS5
1
1
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 A3 E3 J3 N1 P9
1
2
2
1
1 2
B
2
K4N56163QF-ZC33_FBGA84
2
2
SAM64@ K4N56163QF-ZC33_FBGA84
+1.8VS 64@ 10U_0805_10V4Z
As close as ppossible to related pin
64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z
+1.8VS 64@ 10U_0805_10V4Z 64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z 64@ 0.1U_0402_16V4Z
1
C49
1
C48
1
C90
1
C77
1
C78
1
C111
1
C76
1
C110
1
C109
1
C91
1
C167
1
C166
1
C151
1
C161
1
C163
1
C162
1
C152
1
C164
1
C158
1
C157
1
C150
2
A
2
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
10U_0805_10V4Z 64@
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
2
2
0.1U_0402_16V4Z 64@
A
10U_0805_10V4Z 64@
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
External GDDR2 A0
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:19
8
of
13
5
4
3
2
1
MCLKA1# MCLKA1 <6,8> MDA[0..63] <6,8> DQSA[0..7] <6,8> DQSA#[0..7] <6,8> DQMA#[0..7] R113 @ 56_0402_1% <6,8> MAA[0..12] <6,8> A_BA[0..1] MDA[0..63] DQSA[0..7] DQSA#[0..7] DQMA#[0..7] MAA[0..12] A_BA[0..1]
2
R112 @ 56_0402_1%
2
1
1
C266 @ 470P_0402_50V7K U10 B1_A_BA0 B1_A_BA1 B1_MAA12 B1_MAA11 B1_MAA10 B1_MAA9 B1_MAA8 B1_MAA7 B1_MAA6 B1_MAA5 B1_MAA4 B1_MAA3 B1_MAA2 B1_MAA1 B1_MAA0 MCLKA1# MCLKA1 MCKEA1 U11
1
D
Default VRAM chip is SAM: SA00000YC00.
L2 L3 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 K2 BA0 BA1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK CKE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDD1 VDD2 VDD3 VDD4 VDD5 VDDL VSSDL ODT LDQS LDQS B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 J1 J7 1
MDA38 MDA32 MDA39 MDA34 MDA35 MDA36 MDA33 MDA37 MDA45 MDA41 MDA46 MDA40 MDA43 MDA44 MDA42 MDA47 B1_A_BA0 B1_A_BA1 B1_MAA12 B1_MAA11 B1_MAA10 B1_MAA9 B1_MAA8 B1_MAA7 B1_MAA6 B1_MAA5 B1_MAA4 B1_MAA3 B1_MAA2 B1_MAA1 B1_MAA0 MCLKA1# MCLKA1 +1.8VS MCKEA1
D
2
L2 L3 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 K2
BA0 BA1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK CKE
A_BA0 A_BA1 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0
C
R115 1 R116 1 R117 1 R118 1 R119 1 R120 1 R121 1 R122 1 R123 1 R124 1 R125 1 R126 1 R127 1 R128 1 R129 1
128@ 0_0402_5% B1_A_BA0 2 128@ 0_0402_5% B1_A_BA1 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 128@ 2 0_0402_5% B1_MAA12 0_0402_5% B1_MAA11 0_0402_5% B1_MAA10 0_0402_5% B1_MAA9 0_0402_5% B1_MAA8 0_0402_5% B1_MAA7 0_0402_5% B1_MAA6 0_0402_5% B1_MAA5 0_0402_5% B1_MAA4 0_0402_5% B1_MAA3 0_0402_5% B1_MAA2 0_0402_5% B1_MAA1 0_0402_5% B1_MAA0
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDD1 VDD2 VDD3 VDD4 VDD5 VDDL VSSDL
B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 J1 J7
MDA57 MDA59 MDA56 MDA58 MDA61 MDA62 MDA60 MDA63 MDA53 MDA50 MDA55 MDA49 MDA51 MDA52 MDA48 MDA54
<6> MCLKA1# <6> MCLKA1 <6> MCKEA1
+1.8VS
+1.8VS +1.8VS
C
2
<6> MCSA1#0 <6> MWEA1# <6> MRASA1# <6> MCASA1#
MCSA1#0 MWEA1# MRASA1# MCASA1# DQMA#5 DQMA#4
L8 K3 K7 L7 F3 B3 K9 F7 E8
CS WE RAS CAS LDM UDM
MCSA1#0 R110 128@ 0_0402_5% MWEA1# MRASA1# MCASA1# DQMA#6 DQMA#7
L8 K3 K7 L7 F3 B3 K9 F7 E8
CS WE RAS CAS LDM UDM ODT LDQS LDQS
2
R111 128@ 0_0402_5% +VDDL3
1
+VDDL2
+1.8VS <6> ODTA1 ODTA1 DQSA5 DQSA#5
2
+1.8VS ODTA1
1
C240 128@ 2 0.1U_0402_16V4Z
2 R102 128@ 10K_0402_5% 1
1
C238 C239 128@ 0.1U_0402_16V4Z 128@ 2 1 1U_0603_10V6K
R104 128@ 1K_0402_1%
DQSA4 DQSA#4 (25mil) +VR_VREF_2
B7 A8 J2 A2 E2 L1 R3 R7 R8
UDQS UDQS VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8
B
R106 128@ 1K_0402_1%
1
C232 128@ 0.1U_0402_16V4Z
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSS1 VSS2 VSS3 VSS4 VSS5
1
1
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 A3 E3 J3 N1 P9
2 R103 128@ 10K_0402_5% 1
1
DQSA6 DQSA#6
R105 128@ 1K_0402_1%
DQSA7 DQSA#7 +VR_VREF_3
B7 A8 J2 A2 E2 L1 R3 R7 R8
UDQS UDQS VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8
R107 128@ 1K_0402_1%
1
C233 128@ 0.1U_0402_16V4Z 2
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSS1 VSS2 VSS3 VSS4 VSS5
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 A3 E3 J3 N1 P9
B
2
2
SAM128@ K4N56163QF-ZC33_FBGA84
2
2
2
SAM128@ K4N56163QF-ZC33_FBGA84
+1.8VS 128@ 10U_0805_10V4Z
As close as ppossible to related pin
128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z
+1.8VS 128@ 10U_0805_10V4Z 128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z 128@ 0.1U_0402_16V4Z
1
C242
1
C243
1
C244
1
C245
1
C246
1
C247
1
C248
1
C249
1
C250
1
C251
1
C252
1
C253
1
C254
1
C255
1
C256
1
C257
1
C258
1
C259
1
C260
1
C261
1
1 2
C241 128@ 1 1U_0603_10V6K
C262
1
C263
2
A
2
2
0.1U_0402_16V4Z 128@
2
2
0.1U_0402_16V4Z 128@
2
2
0.1U_0402_16V4Z 128@
2
2
2
2
2
2
2
0.1U_0402_16V4Z 128@
2
2
0.1U_0402_16V4Z 128@
2
2
0.1U_0402_16V4Z 128@
2
2
2
2
0.1U_0402_16V4Z 128@
A
128@ 10U_0805_10V4Z
128@ 0.1U_0402_16V4Z
128@ 0.1U_0402_16V4Z
128@ 10U_0805_10V4Z
128@ 0.1U_0402_16V4Z
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
External GDDR2 A0
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:19
9
of
13
5
4
3
2
1
+5VALW +LCDVDD +3VS CHB2012U121_0805 L11 1 2
LCD/PANEL BD. CONN.
JP2
1
R81 300_0402_5%
1
R82 100K_0402_5%
1
C227 4.7U_0805_10V4Z B+
2
D
2
2
R83 Q3
L12 1 2 CHB2012U121_0805 +3VS I2C_CLK I2C_DAT VGA_LVDSB0VGA_LVDSB0+ VGA_LVDSB1+ VGA_LVDSB1VGA_LVDSB2+ VGA_LVDSB2VGA_LVDSBCVGA_LVDSBC+ LCD_ID#
D Q2
3
S
2N7002_SOT23
1
1
0.01U_0402_16V7K
D
1
C228
<5> VGA_ENVDD
VGA_ENVDD 2 G Q4 S 2N7002_SOT23
1
3
2
R84
2
10K_0402_5%
C
+3VS_D
+3VS Delay
PJ6 +3VS
1
1
2
2 2
C225 @ 22U_0805_6.3V6M
JUMP_43X79
2
C226 @ 10U_0805_10V4Z
1
1
1
1
1
1
8 7 6 5
D D D D
S S S G
1 2 3 4
R130 3VS_DELAY
1
2
B+
SI4800DY_SO8
2
@ 1K_0402_5% @ 0.1U_0402_25V4K Q5 @ BSS84_SOT23-3 susp#
C274 @ 10U_1206_16V4Z
1
2
3
1
C273
Those are at button side
2
susp# <3,11>
CF2 CF3 @ SMD40M80 @ SMD40M80
B
B
1
+1.8VS Delay
+1.8VS_D PJ7 +1.8VS
2
2
1
1
JUMP_43X79 U13
1
For IC FIXED
S S S G 1 2 3 4
R131 @ 1K_0402_5% 1 2
8 7 6 5
D D D D
1.8VS_DELAY
B+
FD1 @ FIDUCAL
FD2 @ FIDUCAL
FD3 @ FIDUCAL
1
FD4 @ FIDUCAL
FD5 @ FIDUCAL
FD6 @ FIDUCAL
SI4800DY_SO8
2
1
1
1
1
1
2
@ 10U_1206_16V4Z
1
@ 0.1U_0402_25V4K susp#
For Board FIXED
2
Q6 @ BSS84_SOT23-3
A
1
C276
3
1
C275
1
U12
1
1
1
5
4
D
10K_0402_5%
G
2 G
1
2
2
<4> I2C_CLK <4> I2C_DAT AOS3401_SOT23 +LCDVDD <5> VGA_LVDSB0<5> VGA_LVDSB0+ <5> VGA_LVDSB1+ <5> VGA_LVDSB1-
1
C229 4.7U_0805_10V4Z
1
C230 0.1U_0402_16V4Z
<5> VGA_LVDSB2+ <5> VGA_LVDSB2<5> VGA_LVDSBC<5> VGA_LVDSBC+ <3> LCD_ID#
2
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DAC_BRIG INVT_PWM DISPOFF#
DAC_BRIG <3> INVT_PWM <3> DISPOFF# <3> +LCDVDD AT LEAST 60 MIL
D
1
3
S
VGA_LVDSA0VGA_LVDSA0+ VGA_LVDSA1VGA_LVDSA1+ VGA_LVDSA2+ VGA_LVDSA2VGA_LVDSACVGA_LVDSAC+
VGA_LVDSA0- <5> VGA_LVDSA0+ <5> VGA_LVDSA1- <5> VGA_LVDSA1+ <5> VGA_LVDSA2+ <5> VGA_LVDSA2- <5> VGA_LVDSAC- <5> VGA_LVDSAC+ <5>
ACES_88326-4000
C
H1 H4 @ H_C236B276D157 @ H_C315D157
H5 @ H_C315D157
H2 @ H_C315D122
H3 @ H_C315D122
H6 @ H_C315D122
H7 @ H_C315D122
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Compal Electronics, Inc.
Title LVDS Conn/ Screw Hole Size Document Number Custom Date: 12/23/05 14:40:19
LVDS Connector & Screw
EFL50 LS-2766P
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Rev 1.0 10 of 13
5
4
3
2
1
PJ1
2
2
1
1
JUMP_43X118 PJ2 +VGA_COREP
D
PJ3
2
2
1
1
+VGA_CORE
ISL6227B+
2
2
1
1
B+
1
1
JUMP_43X118 PC1 10U_1206_25VAK PJ5 +1.2VSP
1
JUMP_43X118
1
2
2
PC2 10U_1206_25VAK
PR1 51_1206_5%
1
D
2
2
+5VALW
2
PC3 4.7U_1206_25V6K
PC4 4.7U_1206_25V6K
PL3
1
2
FBMA-L11-322513-151LMA50T_1210
2
2
1
1
+1.2VS PC5 4.7U_0805_6.3V6K
JUMP_43X79
1
1
1
2
2
+VGA_CORE
+VGA_COREP PL1 1.4UH_CEP125-1R4_15.5A_20% 1 2 PR24 4.7_1206_5% 1
8 7 6 5
3
1
PD1 DAP202U_SOT323
2
D D D D
BST_1.2V PQ1 IRF7821_SO8 BST_VGA
14
S S S G
VIN
D D D D
4 3 2 1
C
+ PC12 220U_6.3VM_R15
PQ3 IRF7832_SO8
+VGA_CORE
PR25 0_0402_5% 2 1
PR3 0_0603_5% DH_VGA
BOOT1
BOOT2
G S S S
8 7 6 5
1 3
PC10 0.1U_0402_16V7K 2 1
0.01U_0402_25V7K
0.01U_0402_25V7K
1
2BST_VGA-1 6
23
BST_1.2V-1 1 2 PR4 0_0603_5% DH_1.2V LX_1.2V
PC11 0.1U_0402_16V7K 2 1
D D D D
SOFT1
VCC
1 2 3 4
PC8 2
1
12
SOFT2
17
1
PQ2 SI4800BDY_SO8
5 6 7 8
PU1
28
PC9 2
2
PC6 0.1U_0603_25V7K
PR2 2.2_0603_5%
1
PC7 2.2U_0805_10V6K
2
+1.2V
PL2 +1.2VSP
C
2
2
1
5 4
UGATE1 PHASE1
UGATE2 PHASE2
24 25
PC19 @ 680P_0402_50V7K 2 1
1 2 3 4
PR23 @ 0_0402_5%
@
S S S G
LX_VGA PR7 1.27K_0402_1% 1 2 ISE_VGA DL_VGA
1
PR8 1.27K_0402_1% 1 2
2 1
+ PC14 220U_6.3VM_R15
1
PR6 0_0402_5%
2
ISEN1 LGATE1
ISEN2 LGATE2
D D D D
7 2
22 27
ISE_1.2V DL_1.2V
5 6 7 8
3UH_SPC-07040-3R0_5A_30% PQ4 SI4810BDY-T1_SO8
1
1
PC13 0.01U_0402_25V7K
PR5 2 1 1.15K_0402_1%
4 3 2 1
2
@
PR9 0_0402_5%
2
G S S S
1
1
PC15 0.01U_0402_25V7K PR10
2
2
PGND1 VOUT1 VSEN1 EN1 PG1 OCSET1
PGND2 VOUT2 VSEN2 EN2 PG2/REF OCSET2
VSE_VGA +3VS_D
10K_0402_5%
POWER_SEL
<4>
19.6K_0402_1% 2 1
PR16 20K_0402_1%
PR27
PR13
GND
DDR
1
68K_0402_1%
1
1
1
1 2
0.1U_0402_16V7K
RHU002N06_SOT323
0_0402_5%
B
RHU002N06_SOT323
2
PR26 10K_0402_5% 1 2 2 G PC20 2 1 D 0.01U_0402_25V7K
13
1
1
1
D
<3,10> susp#
2
2
@ 0_0402_5%
2
@
0_0402_5%
PR19 75K_0402_1%
1
2
susp# <3,10>
B
3
PR20 @ 0_0402_5% 1 2
2
2 G 3
S
PC18 0.1U_0402_16V7K
1
1
PQ6
W/O POWER PLAY
@
POWER_SEL
Low
2
S PQ5
With POWER PLAY
High
@
+VGA_CORE
1.0V
0.95V
PR5=1.15K,PR16=20K,PR13=19.6K
PR5=1.15K,PR16=20K
A
2
1
2
ISL6227CA-T_SSOP28
PR18 100K_0402_1%
2
PR17
PR21
0.1U_0402_16V7K
PC17
1
11
18
PC16 PR22
PR15 @ 0_0402_5%
1
PR14 10K_0402_1%
1 2 PR11 10K_0402_1%
9 10 8 15
20 19 21 16
VSE_1.2V
2
1
1 PR12
2 +3VS_D
2
+5VALW
2
3
26
3.4K_0402_1%
PJ3,PJ1,PJ2,PJ4 short
PJ3,PJ1,PJ2,PJ4 short
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title Power
Compal Electronics, Inc.
Power
EFL50 LS-2766P
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom Date: 12/23/05 14:40:19
Rev 1.0 11 of 13
5
4
3
2
1
Version change list (P.I.R. List)
=========== 2005/12 R0.2 ==================
D D
01. Reserve +3VS and +1.8VS delay circuit and reserve Jump. == To meet ATI PWR sequence. Reserve PJ6, PJ7, U12, U13, C273, C274, C275, C276, Q5, Q6, R130 and R131. 02. Change C42, C45, C46, C47 and C51, from 0.1U to 1U. == For 3D hang issue. 03. Change C101, from 0.1U to 1U. 04. Add C44 as 330U 05. Delete R63, 10K_0402_5% == For 3D hang issue. == For 3D hang issue. == PCIE TX power saving.
C
C
B
B
A
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
P.I.R.
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:19
12
of
13
5
4
3
2
1
ZZZ
U8
DA800005F10 --PCB ZKD LS-2766P REV1 VGA/B
D
DA800005F10
SA00000JW00 --S IC D2 16M16/600 HY5PS561621AFP-33 FBGA
HYN64@ SA00000JW00 U9
D
SA00000JW00 --S IC D2 16M16/600 HY5PS561621AFP-33 FBGA
HYN64@ SA00000JW00 U10
SA00000JW00 --S IC D2 16M16/600 HY5PS561621AFP-33 FBGA
HYN128@ SA00000JW00 U11
C
SA00000JW00 --S IC D2 16M16/600 HY5PS561621AFP-33 FBGA
HYN128@ SA00000JW00
C
B
B
A
A
Security Classification Issued Date 2005/12/22
Compal Secret Data
Deciphered Date 2006/12/22
Title
Compal Electronics, Inc.
For BOM
Rev 1.0 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom EFL50 LS-2766P Date:
12/23/05 14:40:19
13
of
13