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TITLE
COVER SHEET BLOCK DIAGRAM RESET&CLK MAP
D
SHEET
1 2 3 4 5,6,7,8,9 10 11 12 13,14,15 16,17,18,19 20 21 22 23 24 25 26 27 28 29 30 31 32
B D
SPEC&CHANGE LIST PROCESSOR K8 754 DDR 1 DDR 2 DDR ADD/CTL/VTT TERMINATI NORTH BRIDGE(C51G) SOURTH BRIDGE(MCP51G) PCI 1&2 FRONT PANEL HEADER PCI EXPRESS X16 & X1
CRU51G+MCP51G VER:1.3A
C
C
IDE CONN POWER CONN & FAN CONTROL FLOOPY / KB / MOUSE / CMOS VGA CONN & TV OUT USB DEVICE SERIAL & PARALLEL
AUDIO CODEC AUDIO CONN VCORE POWER SUPPLY MEM_VREG/MEM_VTT
B
LPC SUPER IO(IT8712) FLASH ROM & H/W MON POWER SEQUENCING LAN 10/100/1000 OVER VOLTAGE C51 CORE BOM
33 34 35 36 37 38 39
A
A
Title
COVER SHEET
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 1 of 39
Monday, April 10, 2006
5
4
3
2
1
D
POWER SUPPLY CONN
VREG
AMD K8 SOCKET 754
MEMORY
DDR DIMM(2) 128-BIT 200/266/333/400 MHZ
D
HT 16X16 1GHZ
PEX X16 (1)
PEX X1 (1)
NFORCE CRUSH 51G 468BGA
ATA 133 HT 4X4 800MHZ PCI 33MHZ
VGA
CONN
TV OUT
(C51PV ONLY)
PRIMARY IDE
C
SECONDARY IDE
NFORCE MCP 51G 508BGA
PCI SLOT (2)
AZALILA/AC97
C
SATA CONN(X4)
INTEGRATED SATA 1/2 LPC BUS 33MHZ
AUDIO CODEC USB2.0 (X8) USB2 PORTS 5-4 DOUBLE STACK USB2 PORTS 3-2 LAN RJ45 BACK PANEL CONN
FLOPPY CONN PS2/KBRD CONN PARALLEL CONN
B
SIO IT8712
SERIAL CONN H/W MON RGMII 4MB FLASH
USB2 PORTS 1-0 USB2 PORTS 7-6
FRONT PANEL HDR
B
MII/RGMII
A
A
Title
SYSTEM BLOCK
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 2 of 39
Monday, April 10, 2006
5
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3
2
1
K8 754 CPU
HT_CPU_TXCLK0 HT_CPU_TXCLK0* HT_CPU_RXCLK0 HT_CPU_RXCLK0*
D
K8 SKT 754
CHANNEL A1 0-63
MEMORY_A1_CLK[2:0] MEMORY_A1_CLK[2:0]* MEMORY_B1_CLK[2:0]
CPU RST* DIMM 0
CPU_RST* CPU_PWRGD
RESET MAP
CRUSH 51
PE_RESET*
CPU PWRGD
DIMM 1 HT_CPU_TXCLK1 HT_CPU_TXCLK1* HT_CPU_RXCLK1 HT_CPU_RXCLK1* CPUCLK_IN* CPUCLK_IN MEMORY_B1_CLK[2:0]*
CHANNEL B1 64-127
D
HT CPU PWRGD HT CPU RST*
HT_CPU_PWRGD HT_CPU_RST* HT_MCP_PWRGD HT_MCP_RST*
MEMORY_A2_CLK[2:0] MEMORY_A2_CLK[2:0]* MEMORY_B2_CLK[2:0] MEMORY_B2_CLK[2:0]*
CHANNEL A2 0-63
PEX X16 DIMM 2 /NI
OPTIONAL
PEX X1
HT MCP PWRGD HT MCP RST*
DIMM 3 /NI
CHANNEL B2 64-127
OPTIONAL
PEX X1 /NI
CRUSH 51
CLKOUT_200MHZ CLKOUT_200MHZ* HT_CPU_RXCLK1* HT_CPU_RXCLK1 HT_CPU_TXCLK1* HT_CPU_TXCLK1 HT_CPU_RXCLK0* PE2_REFCLK HT_CPU_RXCLK0 HT_CPU_TXCLK0* HT_CPU_TXCLK0 HT_MCP_TXCLK0 HT_MCP_TXCLK0* HT_MCP_RXCLK0 HT_MCP_RXCLK0* CLKIN_25MHZ XTAL_OUT CLKIN_200MHZ* CLKIN_200MHZ XTAL_IN PE2_REFCLK* PEX X1 /NI PE1_REFCLK PEX X1 PE1_REFCLK* PS ON PWR GOOD
C
MCP 51
HT_MCP_RST* HT MCP RST* PWR BUTTON HT MCP PWRGD HT_MCP_PWRGD PCIRST_SLOT1* PCIRST_SLOT2* PCIRST_SLOT3-4* PCIRST_IDE* LPCRST_FLASH* LPCRST_SIO* PRI IDE PCI SLOT 3 /NI PCI SLOT2 PCI SLOT1
C
PE0_REFCLK PEX X16 PE0_REFCLK*
PWR SWTCH
8712
PWRBT ON* PWR BUTTON* SLP_S3* PS ON PCI RST1* POWER_GOOD PWRGD PCI RST2* PCI RST3* PWRGD_SB PWRGD SB CIRCUIT GPIO_AUX* PWRGD_SB LPC_RST* AC_RESET* PWRBTN* SLP_S3* SLP S3* PCI RST0*
PWR CONN
CLOCK DISTRIBUTION
27 MHZ (TV OUT ONLY)
SIO LAN_PHY RESET* AUDIO_PHY RESET*
FLASH SEC IDE PCI SLOT4 /NI
MCP 51
B
PCI SLOT2 14MHZ OR 24MHZ BUF_SIO SUSCLK LPC_CLK0 SIO PCI SLOT1
B
MCPCLK_OUT MCPCLK_OUT* 25MHZ_CLKOUT HT_MCP_RXCLK0* HT_MCP_RXCLK0 HT_MCP_RXCLK0* HT_MCP_RXCLK0 RTC_XTAL 32.0 KHZ
PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK_FB
PCI SLOT 3 /NI PCI SLOT4 /NI
FLASH LPC_CLK1 XTAL_IN AC_97CLK 25 MHZ XTAL_OUT AC_BITCLK BUF_25MHZ LAN PHY AC97/AZALIA LINK AC97 CODEC LPC HEADER
A
A
Title
RESET&CLOCK MAP
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 3 of 39
Monday, April 10, 2006
5
4
3
2
1
CPU VID TABLE
VID [4..0] 0X00000
D
PCI INTERRUPT/IDSEL MAP
VDD 1.150V 1.125V 1.100V 1.075V 1.050V 1.025V 1.000V 0.975V 0.950V 0.925V 0.900V 0.875V 0.850V 0.825V 0.800V OFF BACK PANEL SLOT 1 2 3 4 5 6 01 01 01 01 01 01 0X05 0X06 0X07 0X08 0X09 0X0A 27 26 25 24 23 22 PCI BUS# DEVICE# IDSEL PIN PCI SLOT INTA* P_INTZ* P_INTY* P_INTX* P_INTW* P_INTZ* P_INTY* PCI SLOT INTB* P_INTW* P_INTZ* P_INTY* P_INTX* P_INTW* P_INTZ* PCI SLOT INTC* P_INTX* P_INTW* P_INTZ* P_INTY* P_INTX* P_INTW* PCI SLOT INTD* P_INTY* P_INTX* P_INTW* P_INTZ* P_INTY* P_INTX* 5/5 4/4 3/3 2/2 1/1 0/0 REQ/GNT
N51IGP-A7
1. CPU --- AMD Socket 754(3-Phase Power) 2. CHIPSET --- NF C51 IGP + NF MCP51 3. MEMORY --- DDR SDRAM X 2 (Max. 2GB) 4. SLOTS --- PEX X16 (x1),PEX X1 (x1),PCI (x2) 5. CODEC --- Realtek ALC655 5.1 Channel Audio 6. LAN PHY --- RTL8201 7. LPC/SIO --- IT8712F 8. SATA -- INTEGRATED 9. PCB Size --- 24.4cmx24.4cm, 4-Layer
D
VDD 1.550V 1.525V 1.500V 1.475V 1.450V 1.425V 1.400V 1.375V 1.350V 1.325V 1.300V 1.275V 1.250V 1.225V 1.200V 1.175V
VID [4..0] 0X10000 0X10001 0X10010 0X10011 0X10100 0X10101 0X10110 0X10111 0X11000 0X11001 0X11010 0X11011 0X11100 0X11101 0X11110 0X11111
0X00001 0X00010 0X00011 0X00100 0X00101 0X00110 0X00111 0X01000 0X01001 0X01010 0X01011 0X01100 0X01101 0X01110 0X01111
PCI DEVICE MAP
DEVICE PCI BUS# MCP51 LOGICAL PCI BUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 FUNCTION 0X01-0X0F XA X9 X8 X8 X6 X4 X4 X2 X2 X1 X0 X1 ? X1 ? IDSEL PIN -0 0 0 0 0 1 0 1 0 2 0 1 ? 0 ? DEVICE ID -0X56/57 0X005C 0X0055 0X0054 0X0053 0X0058 0X0059 0X005B 0X005A 0X005F 0X005E 0X0052 0X00D3 0X0050/51 ?
CHANGE LIST
MCP51
MAC /MAC PCI-PCI BRIDGE SATA1 SATA0 IDE MODEM CODEC
C
C
SMBUS ADDRESS MAP
DEVICE SLOT SMBUS # ADDRESS
AUDIO CODEC USB 2.0 DIMM 0 DIMM 1 DIMM 2 DIMM 3 SIO PCI SLOT 1 PCI SLOT 2 PCI SLOT 3 PCI SLOT 4 DDC BUS DDC BUS
B
0 0 0 0 1 1 1 1 1 A B
1010 000 = 0X50 USB 1.1 1010 001 = 0X51 SHAPE TRIM 1010 010 = 0X52 LDT 1010 011 = 0X53 SMBUS2 0101 101 = 0X2D LEGACY SLAVE ARP LPC ARP LOGICAL PCI BUS ARP PCI SLOT 1 ARP PCI SLOT 2 ? PCI SLOT 3 ? PCI SLOT 4 PCI SLOT 5
B
22U/25DE 100U/16DE 220U/10DE 470U/16DE 1000U/10DE 1500U/16DE 3300U/25DE
5*7 mm 6.3*11 mm 6.3*11 mm 8*11 mm 8*14 mm 10*25 mm 10*25 mm
D D
O
A
D
C
KA
I GO G TO-263 PHB55N03 90N02 S G S A O I C SOT-23 LM431 R G SOT-23 2N7002 SI2303S SI2301S S B SOT-23 E A SOT-23 K TO-92 LM431 78L05-D LM432
E BC
ECB
TO-252
SOT-223
TO-92 2N2222A 2N2097A
TO-92 HSD882-D
20N03 AMS1117 TM3055TL-S PHD55N03
2N3904 BAT54C 2N3906 BAT54S MMBT2907A 2N2222A
A
A
Title
SPEC&CHANGE LIST
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 4 of 39
Monday, April 10, 2006
5
4
3
2
1
D
CPU1A +1.2V_HT D29 D27 D25 C28 C26 B29 B27 13 HTCPU_UP[15..0] HTCPU_UP[15..0] HTCPU_UP15 HTCPU_UP-15 HTCPU_UP14 HTCPU_UP-14 HTCPU_UP13 HTCPU_UP-13 HTCPU_UP12 HTCPU_UP-12 HTCPU_UP11 HTCPU_UP-11 HTCPU_UP10 HTCPU_UP-10 HTCPU_UP9 HTCPU_UP-9 HTCPU_UP8 HTCPU_UP-8 HTCPU_UP7 HTCPU_UP-7 HTCPU_UP6 HTCPU_UP-6 HTCPU_UP5 HTCPU_UP-5 HTCPU_UP4 HTCPU_UP-4 HTCPU_UP3 HTCPU_UP-3 HTCPU_UP2 HTCPU_UP-2 HTCPU_UP1 HTCPU_UP-1 HTCPU_UP0 HTCPU_UP-0 HTCPU_UP-[15..0] HTCPU_UPCLK1 HTCPU_UPCLK-1 HTCPU_UPCLK0 HTCPU_UPCLK-0 49.9 1% CTLIP1 49.9 1% CTLIN1 HTCPU_UPCNTL HTCPU_UPCNTLT25 R25 U27 U26 V25 U25 W27 W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25 T27 T28 V29 U29 V27 V28 Y29 W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28 VLDT_A6 VLDT_A5 VLDT_A4 VLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 VLDT0_B6 VLDT0_B5 VLDT0_B4 VLDT0_B3 VLDT0_B2 VLDT0_B1 VLDT0_B0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 +1.2V_HT_CPU AH29 +1.2V_HT_CPU AH27 AG28 AG26 AF29 AE28 AF25 N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29
LAYOUT: Place HT bypass caps on topside near unconnected Clawhammer HT Link
+1.2V_HT
D
C101 C97 1UF 16V 0805 Y5V 0.1UF 25V Y5V C180 C181 C233 C320 1UF 16V 0805 Y5V 1UF 16V 0805 Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V
C
13 HTCPU_UP-[15..0] 13 HTCPU_UPCLK1 13 HTCPU_UPCLK-1 13 HTCPU_UPCLK0 13 HTCPU_UPCLK-0 +1.2V_HT_CPU R45 R44
HTCPU_DWN[15..0] HTCPU_DWN[15..0] 13 HTCPU_DWN15 HTCPU_DWN-15 HTCPU_DWN14 HTCPU_DWN-14 HTCPU_DWN13 HTCPU_DWN-13 HTCPU_DWN12 HTCPU_DWN-12 HTCPU_DWN11 HTCPU_DWN-11 HTCPU_DWN10 HTCPU_DWN-10 HTCPU_DWN9 HTCPU_DWN-9 HTCPU_DWN8 HTCPU_DWN-8 HTCPU_DWN7 HTCPU_DWN-7 HTCPU_DWN6 HTCPU_DWN-6 HTCPU_DWN5 HTCPU_DWN-5 HTCPU_DWN4 HTCPU_DWN-4 HTCPU_DWN3 HTCPU_DWN-3 HTCPU_DWN2 HTCPU_DWN-2 HTCPU_DWN1 HTCPU_DWN-1 HTCPU_DWN0 HTCPU_DWN-0 HTCPU_DWN-[15..0] HTCPU_DWN-[15..0] 13 HTCPU_DWNCLK1 HTCPU_DWNCLK-1 HTCPU_DWNCLK0 HTCPU_DWNCLK-0 HTCPU_DWNCLK1 HTCPU_DWNCLK-1 HTCPU_DWNCLK0 HTCPU_DWNCLK-0 13 13 13 13
C
Y25 W25 Y27 Y28 R27 R26 T29 R29
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0
L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0
J26 J27 J29 K29 N25 P25 P28 P27
13 HTCPU_UPCNTL 13 HTCPU_UPCNTLB
HTCPU_DWNCNTL HTCPU_DWNCNTL-
HTCPU_DWNCNTL 13 HTCPU_DWNCNTL- 13
B
BGA754S-DIP
A
A
Title
K8 HT
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 5 of 39
Wednesday, April 12, 2006
5
4
3
2
1
CPU1B AE13 AG12 D14 C14 VTT_SENSE MEMVREF1 MEMZN MEMZP VTT_A4 VTT_A1 VTT_A2 VTT_A3 VTT_B1 VTT_B2 VTT_B3 VTT_B4 MEMRESET_L A16 B15 A12 B11 A17 A15 C13 A11 A10 B9 C7 A6 C11 A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2 L2 M1 W1 W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5 AJ6 AJ7 AH9 AG5 AH5 AJ9 AJ10 AH11 AJ11 AH15 AJ15 AG11 AJ12 AJ14 AJ16 R1 A13 A7 C2 H1 AA1 AG1 AH7 AH13 T1 A14 A8 D1 J1 AB1 AJ2 AJ8 AJ13 MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0 MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0 MEMCKEA MEMCKEB MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0 MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0 MEMRASA_L MEMCASA_L MEMWEA_L MEMBANKA1 MEMBANKA0 D17 A18 B17 C17 AF16 AG16 AH16 AJ17 AG10
D
+1.25VTT
+1.25VREF_CLAW +2.5VDIMM R78 R79 33 1% MEMZN 33 1% MEMZP
D
LAYOUT: 10/5/10 LAYOUT: PLACE WITHIN 1 INCH OF CPU
12 MD[63:0]
C
B
MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
AE8 AE7 D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4 D8 C8 E8 E7 D6 E6 C4 E5 H5 D4 G5 K3 H3 DCLK7+ DCLK7DCLK6+ DCLK6DCLK5+ DCLK5DCLK4+ DCLK4-
CKE0 CKE1 DCLK7+ DCLK7DCLK6+ DCLK6DCLK5+ DCLK5DCLK4+ DCLK4-
10,11,12 10,11,12 10,12 10,12 11,12 11,12 10,12 10,12 11,12 11,12
Clawhammer DDR Interface
+1.25VREF_CLAW
DCLK1+ DCLK1DCLK0+ DCLK0-
DCLK1+ DCLK1DCLK0+ DCLK0-
11,12 11,12 10,12 10,12
+2.5VDIMM
+1.25VREF_CLAW R30 110 1% -CS3 -CS2 -CS1 -CS0 -CS3 -CS2 -CS1 -CS0 -SRASA -SCASA -SWEA MEMBAA1 MEMBAA0 11,12 11,12 10,12 10,12 10,12 10,12 10,12 10,12 10,12 C54 0.01UF 50V X7R
Change to 1%
R29 110 1%
C53 C51 C60 C50 C52 C57 0.01UF 50V X7R 33P 50V NPO 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 1000P 50V X7R /NI
C
LAYOUT: Place on the bottom of the board.
LAYOUT: Place 39pF LAYOUT: Locate caps EMI cap near output close to socket.
RSVD_MEMADDA15 RSVD_MEMADDA14 MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10 MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0 MEMRASB_L MEMCASB_L MEMWEB_L MEMBANKB1 MEMBANKB0 RSVD_MEMADDB_B15 RSVD_MEMADDB_B14 MEMADDB_B13 MEMADDB_B12 MEMADDB_B11 MEMADDB_B10 MEMADDB_B9 MEMADDB_B8 MEMADDB_B7 MEMADDB_B6 MEMADDB_B5 MEMADDB_B4 MEMADDB_B3 MEMADDB_B2 MEMADDB_B1 MEMADDB_B0 MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0 BGA754S-DIP
E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5 H4 F5 F4 L5 J5 E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3 N3 N1 U3 V1 N2 P1 U1 U2
MAA13 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4 MAA3 MAA2 MAA1 MAA0
MAA[13:0]
10,12
-SRASB -SCASB -SWEB MEMBAB1 MEMBAB0
11,12 11,12 11,12 11,12 11,12
B
12
DQS[17:0]
DQS17 DQS16 DQS15 DQS14 DQS13 DQS12 DQS11 DQS10 DQS9 DQS8 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0
MAB13 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 MECC7 MECC6 MECC5 MECC4 MECC3 MECC2 MECC1 MECC0
MAB[13:0]
11,12
MECC[7:0]
12
A
A
Title
K8 CNTL/STRAPS
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 6 of 39
Wednesday, April 12, 2006
5
4
3
2
1
LAYOUT: Route +2.5VDDA approx. 50mil wide and 500mils long.(Reference to ground)
+3.3V_STBY U2 C69 CPU1C 2200P 50V X7R /NI +2.5VDDA
D
1 2 3 4 R36
VDD SMB_CL D+ SMB_DA DALERT# T_CRIT_A# VSS
8 7 6 5
SMB_SCL SMB_SDA SMB_ALLERT-
SMB_SCL 18,20,22,37 SMB_SDA 18,20,22,37 SMB_ALLERT- 33
C84 47P 50V NPO /NI HTCPU_RST13 HTCPU_RSTHTCPU_PWRGD 13 HTCPU_PWRGD HTCPU_STOP13 HTCPU_STOP-
AH25 AJ25 AF20 AE18 AJ27
VDDA1 VDDA2 RESET_L PWROK LDTSTOP_L L0_REF1 L0_REF0 COREFB_H COREFB_L CORE_SENSE VDDIOFB_H VDDIOFB_L VDDIO_SENSE CLKIN_H CLKIN_L NC NC NC NC VTT_A5 VTT_B5 DBRDY
THERMTRIP_L THERMDA THERMDC VID4 VID3 VID2 VID1 VID0 NC NC NC NC
A20 A26 A27 AG13 AF14 AG14 AF15 AE15 AG18 AH18 AG17 AJ18 VID4 VID3 VID2 VID1 VID0
R276 R42 R40
LM90 MSOP8 /NI 0 /NI CHIP_THERM- 18,33 CPU_THERMTRIP- 16 680 +2.5VDDA 0 CPU_THERMDA 33 0 CPU_THERMDC 33,34 37 37 37 37 37
D
ROUTING : 10/10/10
PLACE WITHIN 1 INCH +1.2V_HT_CPU 10/5/10
R49 R48
44.2 1% LVREF1 AF27 44.2 1% LVREF0 AE26 CPU_CORE_FB CPU_CORE_FBA23 A24 B23 AE12 AF12 AE11 AJ21 AH21 AJ23 AH23 AE24 AF24
31 CPU_CORE_FB 31 CPU_CORE_FB-
K8_VID4 K8_VID3 K8_VID2 K8_VID1 K8_VID0
ROUTE AS DIFF PAIR 10/5/10 10
32 VDDIO_SENSE 13 13 CPU_CLK CPU_CLKC75 C83 SNS_+2.5VDIMM
BP1 BP0
ROUTE AS DIF 20/5/5/5/20 LAYOUT: PLACE 169 OHM WITHIN 0.5INCH OF CPU
CPUCK+ 3900P 50V X7R R50 169 1% CPUCK3900P 50V X7R BPSCLK+ BPSCLK-
80.6 1%-->82 1%
G_FBCLKOUT_H G_FBCLKOUT_L AH19 AJ19 FBCLKOUT+ R53 FBCLKOUT80.6 1%
+1.25VTT
C
C16 AG15 DBRDY AH17 C15 TMS TCK -TRST TDI SINCHN -BRN E20 E17 B21 A21 C18 A19 A28 AJ28 CLAW_ANALOG3 CLAW_ANALOG2 CLAW_ANALOG1 CLAW_ANALOG0 AE23 AF23 AF22 AF21 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9
LAYOUT: Route differentially with 20/8/5/8/20
LAYOUT: PLACE WITHIN 0.5 INCH OF CPU
AE19 D20 C21 D18 C19 B19 -DBREQ SCANCLK1 SCANCLK2 SCANEN SCANSHENB SCANSHENA SCANSHENA SCANSHENB SCANCLK1 SCANCLK2 1 3 5 7
RN37 2 4 6 8 680 8P4R RN9 SCANEN BP1 BP0 8 6 4 2 7 5 3 1 680 8P4R +2.5VDDA +2.5VDIMM
C
DBREQ_L NC TMS TCK TRST_L TDI NC NC KEY1 KEY0 NC NC NC NC FREE29 FREE31 FREE33 FREE35 FREE1 FREE37 FREE4 FREE38 FREE41 FREE7 FREE11 FREE12 FREE13 FREE14 FREE40 RSVD_SCL RSVD_SDA NC NC NC NC NC
TDO NC
A22 AF18
TDO R31 0 /NI +2.5VDIMM
RN38 680 8P4R 8 6 4 2 +2.5VDIMM
D22 C22
BPSCLK+ BPSCLK-
R51 R52
820 820
TDI -TRST TMS TDO
B
FREE26 FREE28 FREE30 FREE32 FREE34 FREE36 FREE10 FREE18 FREE19 FREE42 FREE24 FREE25 FREE27
B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9
LVREF0 C77 LVREF1 C78
1000P 50V X7R 1000P 50V X7R
7 5 3 1
B
+2.5VDDA
Modify circuit
0.01UF 50V X7R /NI SINCHN -BRN R76 R75 680 680
+2.5VDDA
C68
BGA754S-DIP +2.5VDDA RN11 680 8P4R 1 2 3 4 5 6 7 8 RN12 1 3 5 7 2 HTCPU_STOP4 6 8 HTCPU_RST680 8P4R HTCPU_PWRGD -DBREQ DBRDY TCK
CLAW_ANALOG3 CLAW_ANALOG2 CLAW_ANALOG1 CLAW_ANALOG0
8 6 4 2
7 5 3 1 RN15 680 8P4R
A
+2.5VDDA
A
Title
K8 DDR MEM 0-63
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 7 of 39
Wednesday, April 12, 2006
5
4
3
2
1
CPU1E VCORE CPU1D +2.5VDIMM B2 AH20 AB21 W22 M23 L24 AG25 AG27 D2 AF2 W6 Y7 AA8 AB9 AA10 J12 B14 Y15 AE16 J18 G20 R20 U20 W20 AA20 AC20 AE20 AG20 AJ20 D21 F21 H21 K21 M21 P21 T21 V21 Y21 AD21 AG21 B22 E22 G22 J22 L22 N22 R22 U22 AG29 AA22 AC22 AG22 AH22 AJ22 D23 F23 H23 K23 P23 T23 V23 Y23 AB23 AD23 AG23 E24 G24 J24 N24 R24 U24 W24 AA24 AC24 AG24 AJ24 B25 C25 B26 D26 H26 M26 T26 Y26 AD26 AF26 AH26 C27 B28 D28 G28 F15 H15 AB17 AD17 B16 G18 AA18 AC18 D19 F19 H19 K19 Y19 AB19 AD19 AF19 J20 L20 N20 VSS1 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS187 VSS188 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 BGA754S-DIP
5 4 3 2
D
C
B
L7 AC15 H18 B20 E21 H22 J23 H24 F26 N7 L9 V10 G13 K14 Y14 AB14 G15 J15 AA15 H16 K16 Y16 AB16 G17 J17 AA17 AC17 AE17 F18 K18 Y18 AB18 AD18 AG19 E19 G19 AC19 AA19 J19 F20 H20 K20 M20 P20 T20 V20 Y20 AB20 AD20 G21 J21 L21 N21 R21 U21 W21 AA21 AC21 F22 K22 M22 P22 T22 V22 Y22 AB22 AD22 E23 G23 L23 N23 R23 U23 W23 AA23 AC23 B24 D24 F24 K24 M24 P24 T24 V24 Y24 AB24 AD24 AH24 AE25 K26 P26 V26
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92 BGA754S-DIP
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29 VDDIO30 VDDIO31 VDDIO32 VDDIO33 VDDIO34 VDDIO35 VDDIO36 VDDIO37 VDDIO38 VDDIO39 VDDIO40 VDDIO41 VDDIO42 VDDIO43 VDDIO44 VDDIO45 VDDIO46 VDDIO47 VDDIO48 VDDIO49 VDDIO50 VDDIO6 VDD96 VDD97 VDD98 VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133 VDD93 VDD94 VDD95
E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4 N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28
VCORE
A
VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS189 VSS190 VSS191 VSS192 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS223 VSS201 VSS202 VSS203 VSS204 VSS205
L28 R28 W28 AC28 AF28 AH28 C29 F2 H2 K2 M2 P2 T2 V2 Y2 AB2 AD2 AH2 B4 AH4 B6 G6 J6 L6 N6 R6 U6 AA6 AC6 AH6 F7 H7 K7 M7 P7 T7 V7 AB7 AD7 B8 G8 J8 L8 N8 R8 U8 W8 AC8 AH8 F9 H9 K9 M9 P9 T9 V9 Y9 AD9 B10 G10 J10 L10 N10 R10 U10 W10 AC10 AH10 F11 H11 K11 Y11 AB11 AD11 B12 G12 AA12 AC12 AH12 F13 H13 K13 Y13 AB13 AD13 AF17 G14 J14 AA14 AC14 AE14 D16 E15 K15 AB15 AD15 AH14 E16 G16 J16 AA16 AC16 AE29 AJ26 E18 F17 H17 K17 Y17
Clawhammer Power and Ground Connections
VCORE VCORE BC4 BC2 C147 10UF 10V 0805 Y5V C146 10UF 10V 0805 Y5V C132 10UF 10V 0805 Y5V BC8 10UF 10V 0805 Y5V /NI 10UF 10V 0805 Y5V 10UF 10V 0805 Y5V
D
LAYOUT: Place in uPGA socket cavity. LAYOUT: Place 6 EMI caps along bottom right side of CPU,2 in middle of HT link,and 12 along bottom left side of CPU. LAYOUT: Place 1000p caps between VRM & CPU.. LAYOUT: Place 1 cap every 1~1.5" along VCORE perimiter.
C
+2.5VDIMM VCORE BC5 BC3 10UF 10V 0805 Y5V /NI 10UF 10V 0805 Y5V +2.5VDIMM C159 0.1UF 25V Y5V
C141 1UF 16V 0805 Y5V /NI BC9 10UF 10V 0805 Y5V C86 0.1UF 25V Y5V
VCORE BC6 BC7 10UF 10V 0805 Y5V /NI 10UF 10V 0805 Y5V /NI +2.5VDIMM
C128 1UF 16V 0805 Y5V C170 1UF 16V 0805 Y5V VCORE
B
C194 1UF 16V 0805 Y5V
C137 1UF 16V 0805 Y5V /NI C142 1UF 16V 0805 Y5V /NI C131 10UF 10V 0805 Y5V C136 1UF 16V 0805 Y5V /NI
LAYOUT: Located close to socket
+1.25VTT
+2.5VDIMM C223 0.1UF 25V Y5V
A
Title
K8 DDR MEM 64-127
Size Document Number Custom Date: Monday, April 10, 2006
1
CRU51-M7
Sheet 8 of 39
Rev 1.3
5
4
3
2
1
2.5V/150mA
D
+3.3V D G S Q15 2N7002 SOT23 /NI
FB8 BEAD 60 0805 1A /NI +2.5VDDA C81 1UF 16V 0805 Y5V CT7 100UF 16V 5X11 2mm /NI
D
+ R32 R1 20 1% /NI R24 1K 1% /NI +12V -
C
R
Vout=Vref (2.5V) X ( 1+R1/R2 ) =2.55V
Change to 1%
R33
D5 LM431 SOT23 /NI A
R2
1K 1% /NI
C
C
B
B
A
A
Title
AMD-K8-POWER
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 9 of 39
Monday, April 10, 2006
5
4
3
2
1
+2.5VDIMM
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
7 38 46 70 85 108 120 148 168 VDD VDD VDD VDD VDD VDD VDD VDD VDD
DIMM1
D
DIMM1 MD_0 MD_1 MD_2 MD_3 MD_4 MD_5 MD_6 MD_7 MD_8 MD_9 MD_10 MD_11 MD_12 MD_13 MD_14 MD_15 MD_16 MD_17 MD_18 MD_19 MD_20 MD_21 MD_22 MD_23 MD_24 MD_25 MD_26 MD_27 MD_28 MD_29 MD_30 MD_31 MD_32 MD_33 MD_34 MD_35 MD_36 MD_37 MD_38 MD_39 MD_40 MD_41 MD_42 MD_43 MD_44 MD_45 MD_46 MD_47 MD_48 MD_49 MD_50 MD_51 MD_52 MD_53 MD_54 MD_55 MD_56 MD_57 MD_58 MD_59 MD_60 MD_61 MD_62 MD_63 MECC_0 MECC_1 MECC_2 MECC_3 MECC_4 MECC_5 MECC_6 MECC_7 R143 4.7K
6,12
MAA[13:0]
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MEMBAA0 MEMBAA1
48 43 41 130 37 32 125 29 122 27 141 118 115 167 59 52 113 157 158 71 163
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
6,12 6,12 6,12 6,12
MEMBAA0 MEMBAA1 -CS0 -CS1
CS0 CS1 NC/CS2 NC/CS3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE CAS RAS CKE0 CKE1 CK0/DNU CK0/DNU CK1 CK1 CK2/DNU CK2/DNU DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 SA1 SA2 VREF VDDID VDDSPD NC NC/RESET NC NC NC NC/FETEN
11,12 DQS_[17:0]
C
DQS_9 DQS_10 DQS_11 DQS_12 DQS_13 DQS_14 DQS_15 DQS_16 DQS_17 -SWEA -SCASA -SRASA CKE0 CKE1 DCLK5+ DCLK5DCLK0+ DCLK0DCLK7+ DCLK7DQS_0 DQS_1 DQS_2 DQS_3 DQS_4 DQS_5 DQS_6 DQS_7 DQS_8 SMBDT SMBCK
97 107 119 129 149 159 169 177 140 63 65 154 21 111 16 17 137 138 76 75 5 14 25 36 56 67 78 86 47 91 92 181 182 183 1 82 184 9 10 101 102 173 103
6,12 6,12 6,12 6,11,12 6,11,12 6,12 6,12 6,12 6,12 6,12 6,12
-SWEA -SCASA -SRASA CKE0 CKE1 DCLK5+ DCLK5DCLK0+ DCLK0DCLK7+ DCLK7-
11,12 DQS_[17:0]
B
11,18 SMB_MEM_SDA 11,18 SMBDT 11,18 SMBCK 11,18 SMB_MEM_SCL
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 90
MD_[63:0]
11,12
D
+2.5VDIMM
Change to 1%
R25 100 1%
C41 0.01UF 50V X7R
LAYOUT: Place 39pf EMI cap near output
+1.25VREF_MEM
C
+1.25VREF_MEM
Change to 1%
R26 100 1% C43 0.1UF 25V Y5V C44 33P 50V NPO C42
LAYOUT: Locate caps close to DIMMs.
C45 1000P 50V X7R /NI 0.1UF 25V Y5V /NI
B
+1.25VREF_MEM +2.5VDIMM
MECC_[7:0]
11,12
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
R38
0 /NI
FETEN
WP
+2.5VDIMM
11
FETEN
A
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
DDRAM184 NYLON LOTES B
A
Title
DDR DIMM1
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 10 of 39
Wednesday, April 12, 2006
5
4
3
2
1
+2.5VDIMM
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
7 38 46 70 85 108 120 148 168
DIMM2
DIMM2 MD_0 MD_1 MD_2 MD_3 MD_4 MD_5 MD_6 MD_7 MD_8 MD_9 MD_10 MD_11 MD_12 MD_13 MD_14 MD_15 MD_16 MD_17 MD_18 MD_19 MD_20 MD_21 MD_22 MD_23 MD_24 MD_25 MD_26 MD_27 MD_28 MD_29 MD_30 MD_31 MD_32 MD_33 MD_34 MD_35 MD_36 MD_37 MD_38 MD_39 MD_40 MD_41 MD_42 MD_43 MD_44 MD_45 MD_46 MD_47 MD_48 MD_49 MD_50 MD_51 MD_52 MD_53 MD_54 MD_55 MD_56 MD_57 MD_58 MD_59 MD_60 MD_61 MD_62 MD_63 MECC_0 MECC_1 MECC_2 MECC_3 MECC_4 MECC_5 MECC_6 MECC_7 R142 WWP MD_[63:0] 10,12
D
D
6,12
MAB[13:0]
MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MEMBAB0 MEMBAB1
48 43 41 130 37 32 125 29 122 27 141 118 115 167 59 52 113 157 158 71 163
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
6,12 6,12 6,12 6,12
MEMBAB0 MEMBAB1 -CS2 -CS3
CS0 CS1 NC/CS2 NC/CS3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE CAS RAS CKE0 CKE1 CK0/DNU CK0/DNU CK1 CK1 CK2/DNU CK2/DNU DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 SA1 SA2 VREF VDDID VDDSPD NC NC/RESET NC NC NC NC/FETEN
10,12 DQS_[17:0]
C
DQS_9 DQS_10 DQS_11 DQS_12 DQS_13 DQS_14 DQS_15 DQS_16 DQS_17 -SWEB -SCASB -SRASB CKE0 CKE1
97 107 119 129 149 159 169 177 140 63 65 154 21 111 16 17 137 138 76 75
6,12 6,12 6,12 6,10,12 6,10,12 6,12 6,12 6,12 6,12 6,12 6,12
-SWEB -SCASB -SRASB CKE0 CKE1 DCLK4+ DCLK4DCLK1+ DCLK1DCLK6+ DCLK6-
10,12 DQS_[17:0]
B
DQS_0 DQS_1 DQS_2 DQS_3 DQS_4 DQS_5 DQS_6 DQS_7 DQS_8 SMBDT SMBCK
5 14 25 36 56 67 78 86 47 91 92 181 182 183 1 82 184 9 10 101 102 173 103
10,18 10,18
SMBDT SMBCK +2.5VDIMM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 90
C
B
MECC_[7:0]
10,12
+1.25VREF_MEM +2.5VDIMM
10
FETEN
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
FETEN
WP
+2.5VDIMM
A
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
4.7K DDRAM184 NYLON LOTES B
A
Title
DDR DIMM2
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 11 of 39
Wednesday, April 12, 2006
5
4
3
2
1
D
C
MD0 MD4 MD5 MD1 MD2 MD6 MD7 MD3 MD14 MD15 MD10 MD11 MD20 MD16 MD17 MD21 MD18 MD22 MD19 MD23 MD24 MD28 MD25 MD29 MD26 MD30 MD27 MD31 MD32 MD36 MD33 MD37 MD34 MD38 MD39 MD35 MD40 MD44 MD45 MD41 MD48 MD49 MD52 MD53 MD54 MD50 MD55 MD51 MD60 MD56 MD61 MD57 MD62 MD58 MD63 MD59 MD8 MD9 MD12 MD13 MD42 MD43 MD46 MD47 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS9 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17
1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 R39 R54 R58 R65 R101 R106 R109 R130 R70 R41 R56 R59 R66 R102 R107 R108 R127 R74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8
RN8 10 8P4R RN13 10 8P4R RN19 10 8P4R RN22 10 8P4R RN25 10 8P4R RN27 10 8P4R RN31 10 8P4R RN39 10 8P4R RN43 10 8P4R RN45 10 8P4R RN51 10 8P4R RN55 10 8P4R RN59 10 8P4R RN64 10 8P4R RN16 10 8P4R RN48 10 8P4R
MD_0 MD_4 MD_5 MD_1 MD_2 MD_6 MD_7 MD_3 MD_14 MD_15 MD_10 MD_11 MD_20 MD_16 MD_17 MD_21 MD_18 MD_22 MD_19 MD_23 MD_24 MD_28 MD_25 MD_29 MD_26 MD_30 MD_27 MD_31 MD_32 MD_36 MD_33 MD_37 MD_34 MD_38 MD_39 MD_35 MD_40 MD_44 MD_45 MD_41 MD_48 MD_49 MD_52 MD_53 MD_54 MD_50 MD_55 MD_51 MD_60 MD_56 MD_61 MD_57 MD_62 MD_58 MD_63 MD_59 MD_8 MD_9 MD_12 MD_13 MD_42 MD_43 MD_46 MD_47 DQS_0 DQS_1 DQS_2 DQS_3 DQS_4 DQS_5 DQS_6 DQS_7 DQS_8 DQS_9 DQS_10 DQS_11 DQS_12 DQS_13 DQS_14 DQS_15 DQS_16 DQS_17
B
MD_0 1 MD_4 3 MD_5 5 MD_1 7 DQS_0 1 DQS_9 3 MD_2 5 MD_6 7 MD_11 7 MD_10 5 MD_15 3 MD_14 1 CKE1 1 MD_20 3 MD_16 5 MD_17 7 CKE0 1 MAB12 3 MAA12 5 MAB11 7 MD_21 1 MAA11 3 MAA9 5 MAB9 7 MD_30 1 MAA3 3 MD_27 5 MAB2 7 MAB4 1 MAA4 3 MAB3 5 MD_26 7 MD_33 1 MD_37 3 DQS_4 5 DQS_13 7 MD_34 1 MD_38 3 MEMBAB0 5 MD_39 7 MD_46 1 MD_47 3 MD_48 5 MD_49 7 -SCASB 1 -CS1 3 -CS2 5 -CS3 7 DQS_15 1 DQS_6 3 MD_54 5 MD_50 7 MD_55 1 MD_51 3 MD_60 5 MD_56 7 MD_62 1 MD_58 3 MD_63 5 MD_59 7 MD_61 1 MD_57 3 DQS_16 5 DQS_7 7 MECC_7 1 MEMBAB1 3 MD_32 5 MD_36 7 MECC_2 1 MECC_6 3 MECC_3 5 MEMBAA1 7 MD_7 1 MD_3 3 MD_8 5 MD_9 7 -SWEB 1 -CS0 3 MD_41 5 -SCASA 7 DQS_8 R71 DQS_2 1 DQS_11 3 MD_18 5 MD_22 7 MD_52 1 MD_53 3 MAB13 5 MAA13 7 DQS_17 R85
+1.25VTT 2 RN5 4 47 8P4R 6 8 2 RN6 4 47 8P4R 6 8 8 RN14 6 47 8P4R 4 2 2 RN17 4 47 8P4R 6 8 2 RN18 4 47 8P4R 6 8 2 RN20 4 47 8P4R 6 8 2 RN30 4 47 8P4R 6 8 2 RN29 4 47 8P4R 6 8 2 RN42 4 47 8P4R 6 8 2 RN44 4 47 8P4R 6 8 2 RN57 4 47 8P4R 6 8 2 RN52 4 47 8P4R 6 8 2 RN62 4 47 8P4R 6 8 2 RN65 4 47 8P4R 6 8 2 RN70 4 47 8P4R 6 8 2 RN68 4 47 8P4R 6 8 2 RN41 4 47 8P4R 6 8 2 RN40 4 47 8P4R 6 8 2 RN7 4 47 8P4R 6 8 2 RN50 4 47 8P4R 6 8 47 2 RN21 4 47 8P4R 6 8 2 RN60 4 47 8P4R 6 8 47
DDR Termination
+1.25VTT 6 6 MD[63:0] DQS[17:0] MAB2 MAA2 MAB1 MAA1 MAB5 MAA5 MAB6 MAA6 MAB11 MAA11 MAA9 MAB9 MAA0 MAA10 MAB0 MAB10 MAB4 MAA4 MAB3 MAA3 MAB7 MAA7 MAB8 MAA8 MEMBAA1 MEMBAB1 MEMBAB0 MEMBAA0 -CS1 -CS3 MAB13 MAA13 -SRASA -SRASB -SWEA -SWEB -CS0 -SCASA -SCASB -CS2 CKE1 CKE0 MAB12 MAA12 MECC_5 MAA1 MECC_0 MECC_1 MAB7 MAA7 MAB8 MAA8 MD_24 MD_28 MAB6 MAA6 MD_12 MD_13 DQS_1 DQS_10 MD_31 MAA2 MECC_4 MAB1 MD_25 MD_29 DQS_3 DQS_12 MD_19 MD_23 MAB5 MAA5 DQS_5 DQS_14 MD_42 MD_43 MAA0 MAA10 MAB0 MAB10 MEMBAA0 MD_35 MD_40 MD_44 -SRASA -SRASB -SWEA MD_45 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 RN34 47 8P4R RN23 47 8P4R RN26 47 8P4R RN10 47 8P4R RN32 47 8P4R RN28 47 8P4R RN24 47 8P4R
+1.25VTT
+2.5VDIMM
+1.25VTT
C213 0.1UF 25V Y5V C158 0.1UF 25V Y5V
D
10,11 MD_[63:0] 10,11 DQS_[17:0] 6,10 6,11 MAA[13:0] MAB[13:0]
C85
0.1UF 25V Y5V
C297 0.1UF 25V Y5V
C269 0.1UF 25V Y5V
6,10 6,11 6,11 6,10 6,10 6,11 6,10 6,11 6,10 6,11 6,10 6,10 6,11 6,11 6,10,11 6,10,11
MEMBAA1 MEMBAB1 MEMBAB0 MEMBAA0 -CS1 -CS3 -SRASA -SRASB -SWEA -SWEB -CS0 -SCASA -SCASB -CS2 CKE1 CKE0
C165 0.1UF 25V Y5V RN53 47 8P4R
C94
0.1UF 25V Y5V
C
RN35 47 8P4R RN46 47 8P4R RN47 47 8P4R C231 0.1UF 25V Y5V
C277 0.1UF 25V Y5V C149 0.1UF 25V Y5V C143 0.1UF 25V Y5V
C61
0.1UF 25V Y5V
C205 0.1UF 25V Y5V +1.25VTT +1.25VTT C253 0.1UF 25V Y5V +1.25VTT C116 0.1UF 25V Y5V C108 0.1UF 25V Y5V
C125 0.1UF 25V Y5V C234 0.1UF 25V Y5V C82 1UF 16V 0805 Y5V C133 0.1UF 25V Y5V
LAYOUT: Place alternating caps to GND and +2.5VDIMM in a single line along VTT island. LAYOUT: Place a cap every 1 inch on VTT trace between Clawhammer and DDR.
B
C197 0.1UF 25V Y5V +2.5VDIMM C100 0.1UF 25V Y5V C175 0.1UF 25V Y5V C246 0.1UF 25V Y5V +1.25VTT +2.5VDIMM +1.25VTT
C257 0.1UF 25V Y5V
LAYOUT: Add 100pF and 1000pF VTT fill near Clawhammer and near DIMMs (Both Sides)
C74
0.1UF 25V Y5V C238 0.1UF 25V Y5V
C33
0.1UF 25V Y5V
+2.5VDIMM CT17 1000UF 6.3V 8X12
LAYOUT: Place on backside, evenly spaced around VTT fill.
C235 0.1UF 25V Y5V C214 0.1UF 25V Y5V
A
6
MECC[7:0]
MECC2 MECC6 MECC3 MECC7 MECC4 MECC5 MECC0 MECC1
1 3 5 7 1 3 5 7
2 4 6 8 2 4 6 8
MECC_2 MECC_6 MECC_3 MECC_7 MECC_4 MECC_5 MECC_0 MECC_1
MECC_[7:0] RN36 10 8P4R RN33 10 8P4R
10,11 6,10 6,11 6,10 6,11 6,11 6,10 DCLK7DCLK6DCLK5DCLK4DCLK1DCLK0R82 R77 R47 R46 R60 R61 120 120 120 120 120 120 DCLK7+ DCLK6+ DCLK5+ DCLK4+ DCLK1+ DCLK0+ 6,10 6,11 6,10 6,11 6,11 6,10
A
1000UF 6.3V 8X12
Title
DDR TERMINATION
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 12 of 39
Wednesday, April 12, 2006
5
4
3
2
1
D
D
5 HTCPU_DWN[15..0]
5 HTCPU_DWN-[15..0]
C
HTCPU_DWN[15..0] HTCPU_DWN0 HTCPU_DWN1 HTCPU_DWN2 HTCPU_DWN3 HTCPU_DWN4 HTCPU_DWN5 HTCPU_DWN6 HTCPU_DWN7 HTCPU_DWN8 HTCPU_DWN9 HTCPU_DWN10 HTCPU_DWN11 HTCPU_DWN12 HTCPU_DWN13 HTCPU_DWN14 HTCPU_DWN15 HTCPU_DWN-[15..0] HTCPU_DWN-0 HTCPU_DWN-1 HTCPU_DWN-2 HTCPU_DWN-3 HTCPU_DWN-4 HTCPU_DWN-5 HTCPU_DWN-6 HTCPU_DWN-7 HTCPU_DWN-8 HTCPU_DWN-9 HTCPU_DWN-10 HTCPU_DWN-11 HTCPU_DWN-12 HTCPU_DWN-13 HTCPU_DWN-14 HTCPU_DWN-15 HTCPU_DWNCLK0 HTCPU_DWNCLK-0 HTCPU_DWNCLK1 HTCPU_DWNCLK-1 HTCPU_DWNCNTL HTCPU_DWNCNTL-
U8A Y23 W24 V24 U22 R24 P24 P22 N22 Y21 V21 W21 T21 R18 P16 N20 M17 Y22 W23 V23 U21 R23 P23 P21 N21 Y20 W20 W22 U20 R19 P17 N19 N18 T23 T22 R21 R20 M23 M22 W19 Y19 N16 T13 HT_CPU_RXD+0 HT_CPU_RXD+1 C51 HT_CPU_RXD+2 HT_CPU_RXD+3 1 OF HT_CPU_RXD+4 HT_CPU_RXD+5 CPU HT_CPU_RXD+6 HT_CPU_RXD+7 HT_CPU_RXD+8 HT_CPU_RXD+9 HT_CPU_RXD+10 HT_CPU_RXD+11 HT_CPU_RXD+12 HT_CPU_RXD+13 HT_CPU_RXD+14 HT_CPU_RXD+15 HT_CPU_RXD-0 HT_CPU_RXD-1 HT_CPU_RXD-2 HT_CPU_RXD-3 HT_CPU_RXD-4 HT_CPU_RXD-5 HT_CPU_RXD-6 HT_CPU_RXD-7 HT_CPU_RXD-8 HT_CPU_RXD-9 HT_CPU_RXD-10 HT_CPU_RXD-11 HT_CPU_RXD-12 HT_CPU_RXD-13 HT_CPU_RXD-14 HT_CPU_RXD-15 HT_CPU_RX_CLK+0 HT_CPU_RX_CLK-0 HT_CPU_RX_CLK+1 HT_CPU_RX_CLK-1 HT_CPU_RXCTL+ HT_CPU_RXCTLHT_CPU_CAL_1P2V HT_CPU_CAL_GND +1.2V_PLLHTCPU +1.2V_PLLHTMCP HT_CPU_TXD+0 HT_CPU_TXD+1 HT_CPU_TXD+2 6 HT_CPU_TXD+3 HT_CPU_TXD+4 HT_CPU_TXD+5 HT_CPU_TXD+6 HT_CPU_TXD+7 HT_CPU_TXD+8 HT_CPU_TXD+9 HT_CPU_TXD+10 HT_CPU_TXD+11 HT_CPU_TXD+12 HT_CPU_TXD+13 HT_CPU_TXD+14 HT_CPU_TXD+15 HT_CPU_TXD-0 HT_CPU_TXD-1 HT_CPU_TXD-2 HT_CPU_TXD-3 HT_CPU_TXD-4 HT_CPU_TXD-5 HT_CPU_TXD-6 HT_CPU_TXD-7 HT_CPU_TXD-8 HT_CPU_TXD-9 HT_CPU_TXD-10 HT_CPU_TXD-11 HT_CPU_TXD-12 HT_CPU_TXD-13 HT_CPU_TXD-14 HT_CPU_TXD-15 HT_CPU_TX_CLK+0 HT_CPU_TX_CLK-0 HT_CPU_TX_CLK+1 HT_CPU_TX_CLK-1 HT_CPU_TXCTL+ HT_CPU_TXCTLCLKOUT0_200MHZ+ CLKOUT0_200MHZCLKOUT1_200MHZ+ CLKOUT1_200MHZHT_CPU_REQ* HT_CPU_STOP* HT_CPU_RESET* HT_CPU_PWRGD +2.5V_PLLHTCPU C51G_PBGA_468 C23 D23 E22 F23 H22 J21 K21 K23 D21 F19 F21 G20 J19 L17 L20 L18 C24 D24 E23 F24 H23 J22 K22 K24 D22 E20 E21 G19 J18 K17 K19 L19 G23 G24 G22 G21 L23 L24 B24 B23 A22 B21 F18 G18 D20 E19 L16
HTCPU_UP[15..0] HTCPU_UP0 HTCPU_UP1 HTCPU_UP2 HTCPU_UP3 HTCPU_UP4 HTCPU_UP5 HTCPU_UP6 HTCPU_UP7 HTCPU_UP8 HTCPU_UP9 HTCPU_UP10 HTCPU_UP11 HTCPU_UP12 HTCPU_UP13 HTCPU_UP14 HTCPU_UP15 HTCPU_UP-[15..0] HTCPU_UP-0 HTCPU_UP-1 HTCPU_UP-2 HTCPU_UP-3 HTCPU_UP-4 HTCPU_UP-5 HTCPU_UP-6 HTCPU_UP-7 HTCPU_UP-8 HTCPU_UP-9 HTCPU_UP-10 HTCPU_UP-11 HTCPU_UP-12 HTCPU_UP-13 HTCPU_UP-14 HTCPU_UP-15 HTCPU_UPCLK0 HTCPU_UPCLK-0 HTCPU_UPCLK1 HTCPU_UPCLK-1 HTCPU_UPCNTL HTCPU_UPCNTLCPU_CLK CPU_CLK-
HTCPU_UP[15..0] 5 16 HTMCP_UP[7..0] HTMCP_UP[7..0] HTMCP_UP0 HTMCP_UP1 HTMCP_UP2 HTMCP_UP3 HTMCP_UP4 HTMCP_UP5 HTMCP_UP6 HTMCP_UP7 AD6 AC7 AA8 AA9 AD10 AD11 AC12 AC13 AA6 W7 Y8 V9 Y10 AA11 V11 W12 AC6 AB7 AB8 AB9 AC10 AC11 AB12 AB13 Y6 Y7 AA7 W9 W10 Y12 W11 V13 AD9 AC9 U10 T10 AD14 AC14 AB5 AA5 AC5 AD5 AC4 Y5 W5
U8B
C51
HT_MCP_TXD+0 HT_MCP_RXD+0 HT_MCP_RXD+1 2 OF 6 HT_MCP_TXD+1 HT_MCP_TXD+2 HT_MCP_RXD+2 HT_MCP_RXD+3 HT_MCP HT_MCP_TXD+3 HT_MCP_TXD+4 HT_MCP_RXD+4 HT_MCP_TXD+5 HT_MCP_RXD+5 HT_MCP_TXD+6 HT_MCP_RXD+6 HT_MCP_TXD+7 HT_MCP_RXD+7 HT_MCP_TXD+8 HT_MCP_RXD+8 HT_MCP_TXD+9 HT_MCP_RXD+9 HT_MCP_TXD+10 HT_MCP_RXD+10 HT_MCP_TXD+11 HT_MCP_RXD+11 HT_MCP_TXD+12 HT_MCP_RXD+12 HT_MCP_TXD+13 HT_MCP_RXD+13 HT_MCP_TXD+14 HT_MCP_RXD+14 HT_MCP_TXD+15 HT_MCP_RXD+15 HT_MCP_RXD-0 HT_MCP_RXD-1 HT_MCP_RXD-2 HT_MCP_RXD-3 HT_MCP_RXD-4 HT_MCP_RXD-5 HT_MCP_RXD-6 HT_MCP_RXD-7 HT_MCP_RXD-8 HT_MCP_RXD-9 HT_MCP_RXD-10 HT_MCP_RXD-11 HT_MCP_RXD-12 HT_MCP_RXD-13 HT_MCP_RXD-14 HT_MCP_RXD-15 HT_MCP_RX_CLK+0 HT_MCP_RX_CLK-0 HT_MCP_RX_CLK+1 HT_MCP_RX_CLK-1 HT_MCP_RXCTL+ HT_MCP_RXCTLHT_MCP_TXD-0 HT_MCP_TXD-1 HT_MCP_TXD-2 HT_MCP_TXD-3 HT_MCP_TXD-4 HT_MCP_TXD-5 HT_MCP_TXD-6 HT_MCP_TXD-7 HT_MCP_TXD-8 HT_MCP_TXD-9 HT_MCP_TXD-10 HT_MCP_TXD-11 HT_MCP_TXD-12 HT_MCP_TXD-13 HT_MCP_TXD-14 HT_MCP_TXD-15 HT_MCP_TX_CLK+0 HT_MCP_TX_CLK-0 HT_MCP_TX_CLK+1 HT_MCP_TX_CLK-1 HT_MCP_TXCTL+ HT_MCP_TXCTLAC24 AD23 AC22 AC20 AB18 AA17 AB16 AC16 AB21 AB20 AB19 W18 W15 AA15 Y14 W13 AC23 AD22 AC21 AD20 AC18 AB17 AB15 AD16 AB22 AA20 AA19 V17 V15 Y15 W14 Y13 AC19 AD19 Y17 W17 AC15 AD15 B22 A20 B20 AB23 AB24
HTMCP_DWN[7..0] HTMCP_DWN0 HTMCP_DWN1 HTMCP_DWN2 HTMCP_DWN3 HTMCP_DWN4 HTMCP_DWN5 HTMCP_DWN6 HTMCP_DWN7
HTMCP_DWN[7..0] 16
HTCPU_UP-[15..0] 5 16 HTMCP_UP-[7..0] HTMCP_UP-[7..0] HTMCP_UP-0 HTMCP_UP-1 HTMCP_UP-2 HTMCP_UP-3 HTMCP_UP-4 HTMCP_UP-5 HTMCP_UP-6 HTMCP_UP-7
HTMCP_DWN-[7..0] HTMCP_DWN-0 HTMCP_DWN-1 HTMCP_DWN-2 HTMCP_DWN-3 HTMCP_DWN-4 HTMCP_DWN-5 HTMCP_DWN-6 HTMCP_DWN-7
HTMCP_DWN-[7..0] 16
C
5 5 5 5
HTCPU_DWNCLK0 HTCPU_DWNCLK-0 HTCPU_DWNCLK1 HTCPU_DWNCLK-1
HTCPU_UPCLK0 HTCPU_UPCLK-0 HTCPU_UPCLK1 HTCPU_UPCLK-1
5 5 5 5
16 HTMCP_UPCLK0 16 HTMCP_UPCLK-0
HTMCP_UPCLK0 HTMCP_UPCLK-0
HTMCP_DWNCLK0 HTMCP_DWNCLK-0
HTMCP_DWNCLK0 16 HTMCP_DWNCLK-0 16
5 HTCPU_DWNCNTL 5 HTCPU_DWNCNTL+1.2V_HT BR1 R112
HTCPU_UPCNTL 5 HTCPU_UPCNTL- 5 CPU_CLK CPU_CLK7 7 16 HTMCP_UPCNTL 16 HTMCP_UPCNTL16 16 16 16 HTMCP_REQHTMCP_STOPHTMCP_RSTHTMCP_PWRGD
150 1%HTCPUCAL_1P2V 150 1%HTCPUCAL_GND
HTMCP_UPCNTL HTMCP_UPCNTLHTMCP_REQHTMCP_STOPHTMCP_RSTHTMCP_PWRGD MCPOUT_25MHZ MCPOUT_200MHZ MCPOUT_200MHZ-
HTMCP_DWNCNTL HTMCP_DWNCNTLCLKOUTCTERM R123
HTMCP_DWNCNTL 16 HTMCP_DWNCNTL- 16 2.37K 1%
14,15 1P2VPLL_PWR
BFB4 1P2VPLL_FILT BEAD 60 0805 1A
B
PLACE ON CHIP BACK SIDE
BC18 BC17 10UF 10V 0805 Y5V 1UF 10V Y5V
HTCPU_REQ- R133 HTCPU_STOPHTCPU_RSTHTCPU_PWRGD
10K 1% /NI +3.3V HTCPU_STOP- 7 HTCPU_RST- 7 HTCPU_PWRGD 7 14,15
2P5V_PLLHTCPU BFB1 2P5V_PWR BEAD 60 0805 1A BC10 BC11 1UF 16V 0805 Y5V /NI 1UF 10V Y5V
16 MCPOUT_25MHZ 16 MCPOUT_200MHZ 16 MCPOUT_200MHZ-
HT_MCP_REQ* CLKOUT_CTERM HT_MCP_STOP* SCLKIN_MCLKOUT_200MHZ+ HT_MCP_RESET*SCLKIN_MCLKOUT_200MHZHT_MCP_PWRGD HT_MCP_CAL_1P2V CLKIN_25MHZ HT_MCP_CAL_GND CLKIN_200MHZ+ CLKIN_200MHZC51G_PBGA_468
FOR VER 1.0
HTMCPCAL_1P2V R113 HTMCPCAL_GND R114
150 1% 150 1%
+1.2V
B
A
A
Title
C51 (1&2) OF 6
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 13 of 39
Wednesday, April 12, 2006
5
4
3
2
1
PLACE ON CLOSE CHIP < 600 mil
U8C 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 PE0_IN0 PE0_IN1 PE0_IN2 PE0_IN3 PE0_IN4 PE0_IN5 PE0_IN6 PE0_IN7 PE0_IN8 PE0_IN9 PE0_IN10 PE0_IN11 PE0_IN12 PE0_IN13 PE0_IN14 PE0_IN15 PE0_IN-0 PE0_IN-1 PE0_IN-2 PE0_IN-3 PE0_IN-4 PE0_IN-5 PE0_IN-6 PE0_IN-7 PE0_IN-8 PE0_IN-9 PE0_IN-10 PE0_IN-11 PE0_IN-12 PE0_IN-13 PE0_IN-14 PE0_IN-15 PE0_PRSNTPE1_IN PE1_INPE1_PRSNTPE0_IN0 PE0_IN1 PE0_IN2 PE0_IN3 PE0_IN4 PE0_IN5 PE0_IN6 PE0_IN7 PE0_IN8 PE0_IN9 PE0_IN10 PE0_IN11 PE0_IN12 PE0_IN13 PE0_IN14 PE0_IN15 J8 J6 K9 L6 L7 M9 N8 N6 R6 P3 R8 U6 T8 U7 V4 Y3 J7 J5 J9 L5 L8 M8 N7 N5 R5 P4 R7 U5 T9 U8 V3 AA3 D1 G6 H6 E2 J4 K3 E3 D3 E4 AC3 AB3 13,15 1P2VPLL_PWR BFB5 0 0805 1P2V_PLLPE BC27 T11 PE0_RX+0 PE0_RX+1 PE0_RX+2 PE0_RX+3 PE0_RX+4 PE0_RX+5 PE0_RX+6 PE0_RX+7 PE0_RX+8 PE0_RX+9 PE0_RX+10 PE0_RX+11 PE0_RX+12 PE0_RX+13 PE0_RX+14 PE0_RX+15 PE0_RX-0 PE0_RX-1 PE0_RX-2 PE0_RX-3 PE0_RX-4 PE0_RX-5 PE0_RX-6 PE0_RX-7 PE0_RX-8 PE0_RX-9 PE0_RX-10 PE0_RX-11 PE0_RX-12 PE0_RX-13 PE0_RX-14 PE0_RX-15 PE0_PRSNT* PE1_RX+ PE1_RXPE1_PRSNT* PE2_RX+ PE2_RXPE2_PRSNT* PE1_CLKREQ* PE2_CLKREQ* PE_REFCLK+ PE_REFCLK+12V_PLLPE C51G_PBGA_468
C51 3 OF 6 PE
26 DAC_HSYNC 26 DAC_VSYNC
DAC_HSYNC DAC_VSYNC R151 124 1%DACRSET C276 DACVREF 0.01UF 50V X7R
B7 C7 D8 D9 C8
DAC_HSYNC DAC_VSYNC DAC_RSET DAC_VREF DAC_IDUMP
VGA
Q21 2N7002 SOT23 /NI
D
D
PE0_TX+0 PE0_TX+1 PE0_TX+2 PE0_TX+3 PE0_TX+4 PE0_TX+5 PE0_TX+6 PE0_TX+7 PE0_TX+8 PE0_TX+9 PE0_TX+10 PE0_TX+11 PE0_TX+12 PE0_TX+13 PE0_TX+14 PE0_TX+15 PE0_TX-0 PE0_TX-1 PE0_TX-2 PE0_TX-3 PE0_TX-4 PE0_TX-5 PE0_TX-6 PE0_TX-7 PE0_TX-8 PE0_TX-9 PE0_TX-10 PE0_TX-11 PE0_TX-12 PE0_TX-13 PE0_TX-14 PE0_TX-15
L1 L3 L4 M4 P1 R1 R3 R4 U4 V1 W1 W3 AA1 AB1 AC1 AD2 L2 M2 M3 N3 P2 R2 T2 T3 U3 V2 W2 Y2 AA2 AB2 AC2 AD3 K1 K2 G4 G5 G2 G3 H4 J3 H2 H3 F1 F2 G1 D2
PE0_OUT[15..0] PE0_OUT0 PE0_OUT1 PE0_OUT2 PE0_OUT3 PE0_OUT4 PE0_OUT5 PE0_OUT6 PE0_OUT7 PE0_OUT8 PE0_OUT9 PE0_OUT10 PE0_OUT11 PE0_OUT12 PE0_OUT13 PE0_OUT14 PE0_OUT15 PE0_OUT-[15..0] PE0_OUT-0 PE0_OUT-1 PE0_OUT-2 PE0_OUT-3 PE0_OUT-4 PE0_OUT-5 PE0_OUT-6 PE0_OUT-7 PE0_OUT-8 PE0_OUT-9 PE0_OUT-10 PE0_OUT-11 PE0_OUT-12 PE0_OUT-13 PE0_OUT-14 PE0_OUT-15 PE0_REFCLK PE0_REFCLKPE1_OUT PE1_OUTPE1_REFCLK PE1_REFCLK-
PE0_OUT[15..0] 22
RN72 8 6 4 2 26 DAC_RED 26 DAC_GREEN 26 DAC_BLUE
150 8P4R 7 5 3 1 A5 B6 A6
DACRSET
U8D DAC_RED DAC_GREEN DAC_BLUE IFPA_TXC+ IFPA_TXCIFPA_TXD+0 IFPA_TXD+1 IFPA_TXD+2 IFPA_TXD+3 IFPA_TXD-0 IFPA_TXD-1 IFPA_TXD-2 IFPA_TXD-3 IFPB_TXC+ IFPB_TXCIFPB_TXD+4 IFPB_TXD+5 IFPB_TXD+6 IFPB_TXD+7 IFPB_TXD-4 IFPB_TXD-5 IFPB_TXD-6 IFPB_TXD-7 IFPAB_PROBE IFPAB_RSET C14 B13 A15 D15 A14 F14 B15 C15 B14 E14 A10 B10 B11 E13 D13 B12 A11 F13 C13 C12 A16 F15 E16 H12 D17 C17 C18 B19 C19 B18 A19
R149 301 1% /NI
C51 4 OF 6
D
G S
RGB/TV
16,20
+3.3V PE0_OUT-[15..0] 22
3P3V_DAC FB15 A9 +3.3V_DAC BEAD 60 0805 1A C274 1UF 16V 0805 Y5V /NI C275 1UF 10V Y5V
13,15 2P5V_PWR
2P5V_PLLGPU H13 BFB2 +2.5V_PLLGPU BEAD 60 0805 1A BC14 1UF 16V 0805 Y5V /NI BC15 1UF 10V Y5V C9 B9 F12 E11 E17 F17 G17 XTAL_IN XTAL_OUT NC1-DDC_CLK NC2-DDC_DATA NC3-HPDET NC4-EE_CLK NC5-EE_DATA +1.2V_PLLGPU +1.2V_PLLCORE +1.2V_PLLIFP
IFPAB_PROBE C267 0.1UF 25V Y5V /NI
+2.5V_PLLIFP +2.5V_PLLCORE PKG_TEST TEST_MODE_EN JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST*
2P5V_PLLCORE BFB3 BEAD 60 0805 1A BC23 BC24 1UF 16V 0805 Y5V /NI 1UF 10V Y5V TEST_MODE_EN R136 1K 1% JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TRSTRN61 JTAG_TCK JTAG_TMS JTAG_TRSTJTAG_TDI 1 3 5 7 2 4 6 8 10K 8P4R /NI
2P5V_PWR
13,15
22 PE0_PRSNTC
PE0_REFCLK+ PE0_REFCLKPE1_TX+ PE1_TXPE1_REFCLK+ PE1_REFCLKPE2_TX+ PE2_TXPE2_REFCLK+ PE2_REFCLKPE_TSTCLK+ PE_TSTCLKPE_RST* PE_CTERM_GND
PE0_REFCLK 22 PE0_REFCLK- 22 PE1_OUT PE1_OUTPE1_REFCLK PE1_REFCLK22 22 22 22 13,15 1P2VPLL_PWR 1P2VPLL_PWR
C
22 PE1_IN 22 PE1_IN22 PE1_PRSNT22 PE2_PRSNT-
PE2_PRSNT-
BC30 BC28 1UF 10V Y5V C51G_PBGA_468 1UF 10V Y5V /NI
R9 P9 H16
TP_PECLK_TEST1 TP_PECLK_TEST-1 R179 PE_RESETPE_COMP R161
2P5V_PWR
13,15
100 /NI 22 26 DAC_RED 26 DAC_GREEN 26 DAC_BLUE DAC_VSYNC BC78 C495 C496 10P 50V NPO /NI 10P 50V NPO /NI 10P 50V NPO /NI
PE_RESET2.37K 1%
1UF 10V Y5V
500mils close to c51 5:5
R315 1K 1%
PLACE ON BACK SIDE
B
B
A
A
Title
C51 (3&4) OF 6
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 14 of 39
Wednesday, April 12, 2006
5
4
3
2
1
U8F U8E
D
C51 DECOUPLING
C51 6 OF 6 GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V19 T14 C20 R17 AB14 U12 G13 Y16 H21 C22 AB6 F22 L22 R22 V22 AA22 A23 AA23 AA24 L11 M11 N11 P11 M12 N12 P12 M13 N13 P13 M14 N14 P14 L12
D
BFB7 BFB8
0 0805 0 0805
+1.2V 1P2VPEA_PWR
+1.2V
B5 C6 D7 E8 E9 E10 F10 F11 G11 H11 J11 J12 J13 J14 T15 U13 U11 Y9 AB11 AA18 W16 U16 U15 B4 C5 D6 E7
+1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_CORE +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_HTMCP +1.2V_PED +1.2V_PED +1.2V_PED +1.2V_PED +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +3.3V +3.3V
C51 5 OF 6 PWR
+1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PEA +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +1.2V_PLL +2.5V_CORE +2.5V_CORE +2.5V_IFPA +2.5V_IFPA
A3 B3 C4 D5 E6 F7 F8 F9 A2 B2 C2 C3 D4 E5 F6 G7 G8 G9 H10 J10 C16 B16 G15 H15
BFB6
BEAD 60 0805 1A
+1.2V 1P2VPLL_PWR 13,14
2P5V_PWR
2P5V_PWR
13,14
C
+1.2V_HT
K16 M16 R16 M21 J20 T16 U17 C21 H17 D18 C10
C1 AA21 AA13 U14 H14 C11 AB4 AA4 J15 E12 AB10 Y18 E18 U18 E15 Y11 U19 N17 F16 J17 L13 B1 T17 D11 T12 J16 D19 H19 L21 M19 P19 T19 L14
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
13,14 2P5V_PWR
C262 1UF 10V Y5V /NI C266 1UF 10V Y5V
PLACE ON BACK SIDE CENTER OF CHIPSET
+1.2V BC21 10UF 10V 0805 Y5V BC26 10UF 10V 0805 Y5V BC25 0.1UF 25V Y5V
13,14 1P2VPLL_PWR
BC35 1UF 16V 0805 Y5V /NI BC31 1UF 16V 0805 Y5V /NI BC20 1UF 10V Y5V C314 1UF 10V Y5V BC29 1UF 10V Y5V
1P2VPEA_PWR
BC43 1UF 16V 0805 Y5V /NI BC45 1UF 10V Y5V /NI BC38 1UF 10V Y5V /NI BC40 1UF 10V Y5V
+1.2V_HT
BC19 1UF 10V Y5V C245 0.1UF 25V Y5V BC16 0.1UF 25V Y5V
C
+3.3V
C51G_PBGA_468
F3 L9 P8 N9 K4 N4 T4 W4 Y4 U9 H9
PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND C51G_PBGA_468
PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND PE_GND
K6 M6 P6 T6 W6 W8 H8 K8 V6 F4 V8
+3.3V
C244 0.1UF 25V Y5V /NI
+1.2V
BC32 1UF 16V 0805 Y5V /NI BC34 0.1UF 25V Y5V C305 1UF 10V Y5V
C51 2.5V
B
+2.5VDDA
C304 0.1UF 25V Y5V /NI BC12 0.1UF 25V Y5V
2.5V @ 500MA AMPS MAX
R145 0 0805
B
+5V
2P5V_PWR CT14 C374 100UF 16V 5X11 2mm /NI 1UF 16V 0805 Y5V /NI I O A
13,14
R1
R122 49.9 1%
CT18 C278 100UF 16V 5X11 2mm 1UF 16V 0805 Y5V /NI
Q20 AZ1117H-ADJ SOT-223
R2
R116 54.9 1%
Vout=Vref (1.25V) X ( 1+R2/R1 ) =2.5V
A A
Title
C51 (5&6) OF 6
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 15 of 39
Wednesday, April 12, 2006
5
4
3
2
1
D
D
20 PCI_AD[31..0] 13 HTMCP_DWN[7..0] HTMCP_DWN[7..0] HTMCP_DWN0 HTMCP_DWN1 HTMCP_DWN2 HTMCP_DWN3 HTMCP_DWN4 HTMCP_DWN5 HTMCP_DWN6 HTMCP_DWN7 HTMCP_DWN-[7..0] HTMCP_DWN-0 HTMCP_DWN-1 HTMCP_DWN-2 HTMCP_DWN-3 HTMCP_DWN-4 HTMCP_DWN-5 HTMCP_DWN-6 HTMCP_DWN-7 HTMCP_DWNCLK0 HTMCP_DWNCLK-0 HTMCP_DWNCNTL HTMCP_DWNCNTLHTMCP_REQHTMCP_STOPR200 R199 35 31 38 31 +3.3V HT_VLD CPU_VLD +2.5VDIMM HTVDD_EN CPUVDD_EN 150 1% 49.9 1% U12A K1 L1 M1 N1 R1 T1 U1 V1 K2 L2 M2 N2 R2 T2 U2 V2 P1 P2 W1 W2 AD1 AA5 AB1 AB2 F22 N26 M24 F23 N25 M6 M5 HT_MCP_RXD+0 HT_MCP_RXD+1 HT_MCP_RXD+2 HT_MCP_RXD+3 HT_MCP_RXD+4 HT_MCP_RXD+5 HT_MCP_RXD+6 HT_MCP_RXD+7 HT_MCP_RXD-0 HT_MCP_RXD-1 HT_MCP_RXD-2 HT_MCP_RXD-3 HT_MCP_RXD-4 HT_MCP_RXD-5 HT_MCP_RXD-6 HT_MCP_RXD-7 HT_MCP_RX_CLK+ HT_MCP_RX_CLKHT_MCP_RXCTL+ HT_MCP_RXCTLHT_MCP_REQ* HT_MCP_STOP* HT_MCP_COMP_GND1 HT_MCP_COMP_GND2 HT_VLD CPU_VLD MEM_VLD HTVDD_EN CPUVDD_EN +1.5V_PLL_CPU_HT +3.3V_PLL_CPU_HT HTMCP_UP[7..0] HTMCP_UP0 HTMCP_UP1 HTMCP_UP2 HTMCP_UP3 HTMCP_UP4 HTMCP_UP5 HTMCP_UP6 HTMCP_UP7 HTMCP_UP-[7..0] HTMCP_UP-0 HTMCP_UP-1 HTMCP_UP-2 HTMCP_UP-3 HTMCP_UP-4 HTMCP_UP-5 HTMCP_UP-6 HTMCP_UP-7 HTMCP_UPCLK0 HTMCP_UPCLK-0 HTMCP_UPCNTL HTMCP_UPCNTLMCPOUT_200MHZ MCPOUT_200MHZ25MHZ_R R201 22 HTMCP_PWRGD HTMCP_UP[7..0] 13
MCP51
1 OF 7 HT
HT_MCP_TXD+0 HT_MCP_TXD+1 HT_MCP_TXD+2 HT_MCP_TXD+3 HT_MCP_TXD+4 HT_MCP_TXD+5 HT_MCP_TXD+6 HT_MCP_TXD+7 HT_MCP_TXD-0 HT_MCP_TXD-1 HT_MCP_TXD-2 HT_MCP_TXD-3 HT_MCP_TXD-4 HT_MCP_TXD-5 HT_MCP_TXD-6 HT_MCP_TXD-7 HT_MCP_TX_CLK+ HT_MCP_TX_CLKHT_MCP_TXCTL+ HT_MCP_TXCTLCLKOUT_200MHZ+ CLKOUT_200MHZCLKOUT_25MHZ HT_MCP_PWRGD
AA1 Y1 AA3 W5 U5 T5 R5 P5 AA2 Y2 AA4 W6 U6 T6 R6 P6 V5 V6 N5 N6 AC1 AC2 Y5 AD2
13 HTMCP_DWN-[7..0]
HTMCP_UP-[7..0] 13
C
13 HTMCP_DWNCLK0 13 HTMCP_DWNCLK-0 13 HTMCP_DWNCNTL 13 HTMCP_DWNCNTL13 HTMCP_REQ13 HTMCP_STOP-
HTMCP_UPCLK0 13 HTMCP_UPCLK-0 13 HTMCP_UPCNTL 13 HTMCP_UPCNTL- 13 MCPOUT_200MHZ 13 MCPOUT_200MHZ- 13 MCPOUT_25MHZ 13 HTMCP_PWRGD 13 20 PCI_C/BE-[3..0]
HT_VLD CPU_VLD HTVDD_EN CPUVDD_EN +3.3V_PLL_CPU_HT
HT_MCP_RST* THERMTRIP*/GPIO CLK200MHZ_TERM_GND JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST*
HTMCP_RSTAE1 HTMCP_RST- 13 J6 CPU_THERMTRIP- 7 K6 TERM_GNDR191 562 1% H22 H21 H23 D26 F25 MCP51_TCK MCP51_TDI MCP51_TMS MCP51_TRSTMCP51_TDI MCP51_TMS MCP51_TCK MCP51_TRST1 3 5 7 RN98 10K 8P4R 2 4 6 8 20 20 20 20 20 20 20 20 20 20 PCI_FRAMEPCI_IRDYPCI_TRDYPCI_STOPPCI_DEVSELPCI_PAR PCI_PERRPCI_SERRPCI_PMEPCI_CLKRUN-
PCI_AD[31..0] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE-[3..0] PCI_C/BE-0 PCI_C/BE-1 PCI_C/BE-2 PCI_C/BE-3 PCI_FRAMEPCI_IRDYPCI_TRDYPCI_STOPPCI_DEVSELPCI_PAR PCI_PERRPCI_SERRPCI_PMEPCI_CLKRUN-
U12B AF19 AB21 AC19 AA20 AA19 AF20 AE19 AE20 AB20 AB19 AA18 AB18 AE18 AF18 AC17 AA17 AB15 AF15 AE15 AF14 AE14 AA14 AB14 AC13 AB13 AE13 AA12 AF13 AB12 AF12 AE12 AF11 AD19 AB17 AA15 AA13 AC15 AD15 AB16 AE16 AA16 AE17 AF16 AF17 AD11 AF25 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE*0 PCI_CBE*1 PCI_CBE*2 PCI_CBE*3 PCI_FRAME* LPC_AD0 PCI_IRDY* LPC_AD1 PCI_TRDY* LPC_AD2 PCI_STOP* LPC_AD3 PCI_DEVSEL* PCI_PAR LPC_FRAME* PCI_PERR*/GPIO LPC_DRQ0* PCI_SERR* LPC_DRQ1*/LPC_CS* PCI_PME*/GPIO LPC_SERIRQ PCI_CLKRUN*/GPIO K24 H26 H25 K22 G25 K21 K23 L22 H24 F26 G26 LPC_CLK0 R257 22
B
MCP51
2 OF 7 PCI
PCI_REQ*0 PCI_REQ*1 PCI_REQ*2 PCI_REQ*3/GPIO PCI_REQ*4/GPIO PCI_GNT*0 PCI_GNT*1 PCI_GNT*2 PCI_GNT*3/GPIO PCI_GNT*4/GPIO PCI_TNTW* PCI_TNTX* PCI_TNTY* PCI_TNTZ* PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLKIN
AA22 AE22 AF21 AF22 AE23 AE21 AC21 AA21 AB24 AB22 AE11 AB11 AC11 AA11 AE24 AF24 AD23 AF23 AB23 AC23
PCI_REQ-0 PCI_REQ-1 PCI_REQ-2 PCI_REQ-3 PCI_REQ-4 PCI_GNT-0 PCI_GNT-1 PCI_GNT-2 PCI_GNT-3 PCI_GNT-4 PCI_INTWPCI_INTXPCI_INTYPCI_INTZPCI_CLK0 R230 PCI_CLK1 R229 PCI_CLK4 PCI_CLKIN PCI_CLK0 PCI_CLK1 PCI_CLK4 PCI_GNT-3 PCI_GNT-4 R228 22 22 22
PCI_REQ-0 PCI_REQ-1 PCI_REQ-2 PCI_REQ-3 PCI_REQ-4 PCI_GNT-0 PCI_GNT-1 PCI_GNT-2 PCI_GNT-3 PCI_GNT-4 PCI_INTWPCI_INTXPCI_INTYPCI_INTZ-
20 20 20 20 20 20 20 20 14,20 20 20 20 20 20
PCI_CLKSLOT1 20 PCI_CLKSLOT2 20
C
C448 10P 50V NPO C442 10P 50V NPO C438 10P 50V NPO RGB/TV GPIO_LOAD 14,20 20
+1.5V FB21 BEAD 60 0805 1A
LPC_AD[3..0] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAMELPC_DRQ0LPC_DRQ1-R245 LPC_SERIRQ
LPC_AD[3..0]
33,34
C377 C384 C390 C395 0.1UF 25V Y5V /NI 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 0.01UF 50V X7R /NI +1.2V_HT VCORE R154 R10 0 /NI HTVDD_EN 2K /NI CPUVDD_EN
MCP51G_PBGA_508
+3.3V
LPC_FRAMELPC_DRQ08.2K +3.3V LPC_SERIRQ
33,34 33 33
B
HTMCP_RSTHTMCP_PWRGD HTMCP_STOPHTMCP_REQ-
1 3 5 7
RN76 680 8P4R 2 4 6 8
R238
+3.3V
23 20 20 34
PCIRST_IDEPCIRST_SLOT2PCIRST_SLOT1LPCRST_FLASH-
33 LPCRST_SIO-
PCI_RESET0AE25 PCI_RESET*0 LPC_PWRDWN*/GPIO PCI_RESET1AD24 PCI_RESET*1 PCI_RESET2 33 1% AE26 PCI_RESET*2 LPC_CLK0 PCI_RESET3W22 PCI_RESET*3 LPC_RESETL26 LPC_RESET*4 LPC_CLK1 RN89 MCP51G_PBGA_508 PCI_RESET31 2 PCI_RESET13 4 PCI_RESET05 6 LPC_RESET7 8 33 8P4R R260 33 1% LPC_RESET-
LPCCLK_SIO
33
LPC_CLK1 R256 22 C473 10P 50V NPO C474 10P 50V NPO
LPCCLK_FLASH 34
A
A
Title
MCP51 (1&2) OF 7
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 16 of 39
Wednesday, April 12, 2006
5
4
3
2
1
D
H1 JSATA1 1 SATA_A0_TX_P_C 2 SATA_A0_TX_N_C 3 4 SATA_A0_RX_N_C 5 SATA_A0_RX_P_C 6 7 H2 SATA CONNECTOR H1 JSATA2 1 SATA_A1_TX_P_C 2 SATA_A1_TX_N_C 3 4 SATA_A1_RX_N_C 5 SATA_A1_RX_P_C 6 7 H2 SATA CONNECTOR
D
U12C C441 0.01UF 50V X7R C453 0.01UF 50V X7R C437 0.01UF 50V X7R C423 0.01UF 50V X7R SATA_A0_TX_P B20 SATA_A0_TX_N A20 SATA_A0_RX_N A19 SATA_A0_RX_P B19 SATA_A0_TX+ SATA_A0_TXSATA_A0_RXSATA_A0_RX+
MCP51
IDE SATA
IDE_DATA_P0 IDE_DATA_P1
3 OF 7 IDE_DATA_P2 IDE_DATA_P3
IDE_DATA_P4 IDE_DATA_P5 IDE_DATA_P6 IDE_DATA_P7 IDE_DATA_P8 IDE_DATA_P9 IDE_DATA_P10 IDE_DATA_P11 IDE_DATA_P12 IDE_DATA_P13 IDE_DATA_P14 IDE_DATA_P15 IDE_ADD_P0 IDE_ADD_P1 IDE_ADD_P2
C411 0.01UF 50V X7R C421 0.01UF 50V X7R C410 0.01UF 50V X7R C408 0.01UF 50V X7R
SATA_A1_TX_P B18 SATA_A1_TX_N A18 SATA_A1_RX_N A17 SATA_A1_RX_P B17
SATA_A1_TX+ SATA_A1_TXSATA_A1_RXSATA_A1_RX+
F8 D8 A9 E9 A10 E10 C10 E11 F11 D10 F10 B10 F9 B9 E8 A8 A6 D6 B6 A5 B5 B7 F7 E6 B8 E7 A7 C6 E4 D1 D4 C2 B2 C3 A3 A4 B4 B3 A2 B1 C1 D2 E3 E5 G4 G6 G2 G1 G3 F5 E1 F6 E2 F2 F1 G5
IDE_PDD[15..0] IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_ADDR_P0 IDE_ADDR_P1 IDE_ADDR_P2 IDE_CS1_PIDE_CS3_PIDE_DACK_PIDE_IOW_PIDE_INTR_P IDE_DREQ_P IDE_IOR_PIDE_IORDY_P CBLE_DET_P IDE_SDD[15..0] IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 IDE_ADDR_S0 IDE_ADDR_S1 IDE_ADDR_S2 IDE_CS1_SIDE_CS3_SIDE_DACK_SIDE_IOW_SIDE_INTR_S IDE_DREQ_S IDE_IOR_SIDE_IORDY_S CBLE_DET_S
IDE_PDD[15..0]
23
B15 A15 A16 B16
C
IDE_ADDR_P0 23 IDE_ADDR_P1 23 IDE_ADDR_P2 23 IDE_CS1_PIDE_CS3_PIDE_DACK_PIDE_IOW_PIDE_INTR_P IDE_DREQ_P IDE_IOR_PIDE_IORDY_P CBLE_DET_P IDE_SDD[15..0] 23 23 23 23 23 23 23 23 23 23
SATA_B0_TX+ SATA_B0_TXSATA_B0_RXSATA_B0_RX+
B13 A13 A14 B14
IDE_CS1_P* IDE_CS3_P* IDE_DACK_P* IDE_IOW_P* IDE_INTR_P IDE_DREQ_P IDE_IOR_P* IDE_IORDY_P CBLE_DET_P IDE_DATA_S0 IDE_DATA_S1 IDE_DATA_S2 IDE_DATA_S3 IDE_DATA_S4 IDE_DATA_S5 IDE_DATA_S6 IDE_DATA_S7 IDE_DATA_S8 IDE_DATA_S9 IDE_DATA_S10 IDE_DATA_S11 IDE_DATA_S12 IDE_DATA_S13 IDE_DATA_S14 IDE_DATA_S15 IDE_ADD_S0 IDE_ADD_S1 IDE_ADD_S2 IDE_CS1_S* IDE_CS3_S* IDE_DACK_S* IDE_IOW_S* IDE_INTR_S IDE_DREQ_S IDE_IOR_S* IDE_RDY_S CABLE_DET_S/GPIO IDE_COMP_3P3 IDE_COMP_GND
C
SATA_B1_TX+ SATA_B1_TXSATA_B1_RXSATA_B1_RX+
21 SATA_HDLEDBR6 100 /NI
SATA_HDLEDTP_SATA_TSTCLK_P TP_SATA_TSTCLK_N SATA_TERMP
C20 D14 C14 F13 F14
SATA_LED*/GPIO SATA_TSTCLK+ SATA_TSTCLKSATA_TEST SATA_TERM+ SATA_TERM+1.5V_PLL_SP_VDD
BR5 +1.5V
B
2.49K 1% SATA_TERMN E14 +1.5V_PLL_SP_VDD F18
IDE_ADDR_S0 23 IDE_ADDR_S1 23 IDE_ADDR_S2 23 IDE_CS1_SIDE_CS3_SIDE_DACK_SIDE_IOW_SIDE_INTR_S IDE_DREQ_S IDE_IOR_SIDE_IORDY_S CBLE_DET_S 120 120 +3.3V 23 23 23 23 23 23 23 23 23
FB24 BEAD 60 0805 1A
C457 C456 C455 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 0.01UF 50V X7R /NI 18 +3.3V_PLL_SP_SS +3.3V FB25 0 +1.5V +3.3V_PLL_SP_SS F19 D20 +1.5V_PLL_SP_SS +3.3V_PLL_SP_SS
B
B11 IDE_COMP_3P3V R205 A11 IDE_COMP_GND R213
MCP51G_PBGA_508 C463 C462 C375 C464 0.1UF 25V Y5V 10UF 10V 0805 Y5V 0.1UF 25V Y5V 0.01UF 50V X7R /NI
A
A
Title
MCP51 (3) OF 7
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 17 of 39
Wednesday, April 12, 2006
5
4
3
2
1
+3.3V_DUAL
R253 10K 1% /NI AC_RSTR254 10K 1%
D
AC_RST* 1 = *RGMII 0 = MII SPDIF0 (SIO CLK) 1 = 24MHZ 0 = *14.318MHZ * = DEFAULT
29 AUD_14MHZ_IN 29 AC_BITCLK 29 AC_SDOUT 29 AC_SDIN_0 AUD_14MHZ_IN AC_BITCLK AC_SDOUT AC_SDIN_0 AC_SDATA_IN1 AC_SDATA_IN2 AC_RSTAC_SYNC SPDIF DDC_CLK DDC_DATA R22 U26 T25 R26 T24 U21 U25 R21
U12D AC97_CLK MCP51 AC_BITCLK AC_SDATA_OUT0/GPIO AC_SDATA_IN0/GPIO 4 OF 7 AC_SDATA_IN1/GPIO AC_SDATA_IN2/GPIO USB AC_RESET* AC_SYNC/GPIO USB+0 USB-0 USB+1 USB-1 USB+2 USB-2 USB+3 USB-3 USB+4 USB-4 USB+5 USB-5 USB+6 USB-6 USB+7 USB-7 USB_OC0*/GPIO USB_OC1*/GPIO USB_OC2*/GPIO USB_OC3*/GPIO USB_RBIAS_GND A20GATE/GPIO INTRUDER* EXT_SMI*/GPIO RI*/GPIO SPKR PWRBTN* SIO_PME*/GPIO KBRDRSTIN*/GPIO PE_WAKE* SMB_CLK0/GPIO SMB_DATA0/GPIO SMB_CLK1/GPIO SMB_DATA1/GPIO SMB_ALERT*/GPIO +3.3V_VBAT BUF_SIO_CLK SUS_CLK/GPIO THERM*/GPIO RSTBTN* SLP_S5* SLP_S3* PWRGD_SB PWRGD FANRPM/GPIO FANCTL0/GPIO FANCTL1/GPIO TEST_MODE_EN AC26 AC25 AB26 AB25 AA26 AA25 Y26 Y25 W26 W25 V24 V23 V26 V25 T22 T23 Y24 Y23 U22 V22 AD25 J22 A24 M26 M25 E26 D23 M23 J21 AC3 H1 H2 M21 L25 M22 A23 J26 N21 K25 F21 C26 F24 B26 N22 L21 J25 K26 D25 USB_0 USB_0USB_1 USB_1USB_2 USB_2USB_3 USB_3USB_4 USB_4USB_5 USB_5USB_6 USB_6USB_7 USB_7USB_BKPNL_3_2_OCUSB_BKPNL_5_4_OCUSB_FNTPNL_7_6_OCUSB_FNTPNL_1_0_OC732 1% USB_GND R242 A20GATE INTRUDEREXTSMISER_RISPEAKER PWBTOUTIO_PMESIO_KBRSTPE_WAKESMB_MEM_SCL SMB_MEM_SDA SMB_SCL SMB_SDA SMB_ALERT+3.3V_VBAT BUF_SIO_CLK_R SUS_CLK_R CHIP_THERMFP_RESETSLP_S5SLP_S3PWRGD_SB MCP51_PWRGD CPUFAN_TACH CPUFAN_CNTL SYSFAN_CNTL SB_TEST RN92 1 2 3 4 5 6 7 8 10K 8P4R /NI USB_0 USB_0USB_1 USB_1USB_2 USB_2USB_3 USB_3USB_4 USB_4USB_5 USB_5USB_6 USB_6USB_7 USB_727 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
D
29 R308 29,30 SPDIFO 0 /NI 26 26 29
AC_RSTAC_SYNC DDC_CLK DDC_DATA
AC97 GPIO
+3.3V
1 3 5 7
RN102 2 4 6 8
SPDIF TP_CPUVID5 AC_SDATA_IN2 AC_SDATA_IN1 36 RGMII_RESET34 FLASH_RECOVERY-
+3.3V_DUAL
C
1 3 5 7
10K 8P4R RN103 2 LLB4 LID6 8 10K 8P4R
T26 AE10 AF10 AA10 AB10 AF9 C24 D24 C25 J4 J3 J5 RGMII_RESETAE2 K5 J2 FLASH_RECOVERY- J1 AC9 AB9 AA9 P24 P25 P22 P26 R25 TP_CPUVID5 P23 B25 B24 E22 G22 A25
SPDIF0/GPIO DDC_CLK0/GPIO DDC_DATA0/GPIO DDC_CLK1/GPIO DDC_DATA1/GPIO HPLUG_DET0/GPIO LCD_BKL_CTL/GPIO LCD_BKL_PWR/GPIO LCD_BKL_ON/GPIO GPIO_1/SLAVE_READY GPIO_2/CPU_SLP* GPIO_3/CPU_CLKRUN* GPIO_4/AGPSTP*/SUS_STAT* GPIO_5/SYS_SHUTDOWN* GPIO_6/NFERR*/SYS_PERR* GPIO_7/FERR*/SYS_SERR* GPIO_8/CR_VID0 GPIO_9/CR_VID1 GPIO_10/CR_VID2 GPIO_11/CPU_VID0 GPIO_12/CPU_VID1 GPIO_13/CPU_VID2 GPIO_14/CPU_VID3 GPIO_15/CPU_VID4 GPIO_16/CPU_VID5 LID*/GPIO SLP_DEEP* V3P3_DEEP LLB* RTC_RST* +1.5V_PLL_LEG +3.3V_PLL_LEG +1.5V_PLL_USB +3.3V_PLL_USB MCP51G_PBGA_508
USB_BKPNL_3_2_OC- 27 USB_BKPNL_5_4_OC- 27 USB_FNTPNL_7_6_OC- 27 USB_FNTPNL_1_0_OC- 27 A20GATE EXTSMISER_RISPEAKER PWBTOUTIO_PMESIO_KBRST33 +3.3V_DUAL +2.5VDIMM RN105 2.7K 8P4R 2 4 6 8
21,33 28 21 R193 R144 33 10K 1% 2.7K 33 33
R194 2.7K
1 3 5 7
+3.3V_DUAL
C
PE_WAKE22 SMB_MEM_SCL 10,11 SMB_MEM_SDA 10,11 SMB_SCL 7,20,22,37 SMB_SDA 7,20,22,37 R247 R255 CHIP_THERM- 7,33 FP_RESET21,37 SLP_S521,32 SLP_S324,33 PWRGD_SB 35 MCP51_PWRGD 35 22 22 +3.3V_VBAT 25,33,37 BUF_SIO_CLK 33 SUSCLK 33 C467 0.1UF 25V Y5V
C55 25,33,37 +3.3V_VBAT 1 R246 51K +3.3V_DUAL JCMOS1 2 HEADER 1X3 3 C80
LID0.1UF 25V Y5V LLB1UF 10V Y5V RTC_RST-
C469 C468 10P 50V NPO /NI 10P 50V NPO /NI R249 R244 10K 1% /NI +3.3V_DUAL 10K 1%
SUSCLK 1 = SLAVE 0 = *NORMAL * = DEFAULT
+1.5V 17 +3.3V_PLL_SP_SS +1.5V
B22 +3.3V_PLL_SP_SS A22 Y21 AD26
+3.3V
FB26 BEAD 60 0805 1A
+3.3V_PLL_USB_CORE
R248
1K 1%
CLEAR CMOS CONTROL
B
1-2 2-3
NORMAL CLEAR CMOS
C376 C380 C459 BC70 C460 C461 0.1UF 25V Y5V /NI 0.01UF 50V X7R /NI 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V 0.01UF 50V X7R /NI
+3.3V
+3.3V +3.3V
B
CMOS CLEAR JUMPER
USB_1USB_1 USB_0USB_0 USB_3USB_3 USB_2USB_2 USB_5USB_5 USB_4USB_4 USB_6USB_6 USB_7USB_7
1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7
2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8
RN94 15K 8P4R SPEAKER RN96 15K 8P4R RN97 15K 8P4R RN95 15K 8P4R 2 25,33,37 +3.3V_VBAT R243 1M INTRUDERJCI1 HEADER 1X2
R250 10K 1% /NI
R6 4.7K
CHIP_THERMR261 10K 1%
A
1
A
Title
MCP51 (4) OF 7
Size Document Number Custom Date:
5 4 3 2
CRU51-M7
Sheet
1
Rev 1.3 18 of 39
Wednesday, April 12, 2006
5
4
3
2
1
U12G
D
RN77 36 36 36 36 36 36 RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3 RGMII_TXCLK RGMII_TXCTL 36 36 36 36 36 36 7 5 3 1
BR3 BR4
0 8P4R 8 6 4 2 0 0 RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3 RGMII_RXCLK RGMII_RXCTL RGMII_VREF
U12E AE7 AF6 AB6 AA6 AA7 AB7 AF7 AF8 AD7 AB8 AC7 AE8 AF4 AF5 AE6 AD3 AC4 AF2 AE5 AA8 AC5 RGMII_TD0/MII_TD0 RGMII_TD1/MII_TD1 RGMII_TD2/MII_TD2 RGMII_TD3/MII_TD3 RGMII_TXC/MII_TXCLK RGMII_TX_CTL/MII_TXEN RGMII_RD0/MII_RXD0 RGMII_RD0/MII_RXD1 RGMII_RD0/MII_RXD2 RGMII_RD0/MII_RXD3 RGMII_RXC/MII_RXCLK RGMII_RX_CTL/MII_RXDV MII_VREF MII_MDC MII_MDIO MII_RXER/GPIO MII_COL MII_CRS MII_PWRDWN/GPIO MII_INTR/GPIO BUF_25MHZ XTALIN_RTC +1.2V_PLL_MAC_DUAL +3.3V_PLL_MAC_DUAL MCP51G_PBGA_508 XTALOUT_RTC X3 C22 B23 XTALIN_RTC XTALOUT_RTC 32.768KHZ 12.5PF 20PPM C470 C472 15P 50V NPO 15P 50V NPO
MCP51
5 OF 7 LAN CLOCK
NC NC NC NC NC
E19 D12 E12 E25 AE9 X2
+3.3V_DUAL R203
1K 1%
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3 RGMII_RXCLK RGMII_RXCTL
XTALIN XTALOUT
E21 D22
XTALIN XTALOUT 25MHZ 20PF 30PPM C465 C466 15P 50V NPO 15P 50V NPO
R204 1K 1% C400 0.1UF 25V Y5V
36 36 36 36 36
RGMII_MDC RGMII_MDIO MII_RXER MII_COL MII_CRS R202 R192
RGMII_MDC RGMII_MDIO
+3.3V_DUAL +3.3V_DUAL 36 BUF_25M
10K 1% 22 BUF_25MHZ_R
C
FB22 BEAD 60 0805 1A
+1.5V_DUAL
AE4 +3.3V_PLL_MAC_DUAL AB5
C335 C381 C394 C382 C393 C383 0.1UF 25V Y5V /NI 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V 0.01UF 50V X7R /NI 0.01UF 50V X7R /NI
AF26 AF1 AD22 AD20 AD18 AD16 AD14 AD12 AD10 AD8 AD6 AD4 AC24 AB3 AA24 Y3 W24 V3 U24 U14 U13 T16 T15 T14 T13 T12 T11 T3 R24 R16 R15 R14 R13 R12 R11 P17 P16 P15 P14 P13 P12 P11 P10 P3 N24 N17 F20 E18 D18 D16 E20 C18 C16 B21 A21
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
MCP51
7 OF 7 GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
N16 N15 N14 N13 N12 N11 N10 M16 M15 M14 M13 M12 M11 M3 L24 L16 L15 L14 L13 L12 L11 K14 K13 K3 J24 H3 G24 F3 E24 D3 C23 C11 C9 C7 C5 A26 A1 H5 H6 U4 R4 N4 L4 W4 L5 L6 C21 C19 C17 C15 C13 E13 B12 A12
D
TOP SIDE CAP
+3.3V C454 BC77 BC62 BC52 BC51
0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V /NI
BACK SIDE CAP
+1.5V
BC73 1UF 16V 0805 Y5V /NI BC65 0.1UF 25V Y5V BC49 BC53 BC72 BC57 BC55 BC50 BC63 BC74 BC54 BC64 BC61 BC75 BC60 BC56 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
+1.2V
BACK SIDE CAP
+1.5V_DUAL C392 0.1UF 25V Y5V /NI C391 0.1UF 25V Y5V /NI +5V
TOP SIDE CAP
TOP SIDE CAP
BC59 0.1UF 25V Y5V BC58 0.1UF 25V Y5V /NI
C
SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND
SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND SATA_GND
+3.3V
+1.5V + CT37 100UF 16V 5X11 2mm
MCP51G_PBGA_508
B
1A
Q35 U12F +1.2V +3.3V_DUAL +1.5V_DUAL + CT35 100UF 16V 5X11 2mm Q34 I O A AZ1117H-ADJ SOT-223 U17 U16 U15 U12 U11 U10 T17 T10 R17 R10 M17 M10 L17 L10 K17 K16 K15 K12 K11 K10 U3 R3 N3 L3 W3 +1.5V_DUAL AE3 AF3 +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2_DUAL +1.2_DUAL +5V +5V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Y22 F12 AD21 AD17 AD13 AD9 AD5 C12 C8 C4 Y6 T21 P21 G21 W21 V21 F17 E17 F16 E16 E15 F15 +5V +3.3V I O A
R1
R195 1K 1% +
1.5V_SP_A 440mA 1.5V_SP_D 164mA 1.5V_PLL_SP_DVDD 20mA 1.5V_PLL_SP_AVDD 160mA 1.5V_PLL_CPU_HT 71mA 1.5V_PLL_SP_SS 10mA 1.5V_PLL_LEG 4mA 1.5V_PLL_USB_CORE 16mA
B
MCP51
6 OF 7 PWR
CT41 100UF 16V 5X11 2mm
AZ1117H-ADJ SOT-223
R2
R197 200 1%
+1.2V_DUAL @ 145MA AMPS MAX
R189 100 1% + CT38 100UF 16V 5X11 2mm R190 20 1%
R1
R2
A
R1 NI 1K 1% 1K 1%
R2 0 40.2 1% 82 1%
+1.2V +1.25V +1.3V +1.35V
+3.3V_DUAL +3.3V_DUAL +3.3V_DUAL +3.3V_DUAL +3.3V_USB_DUAL +3.3V_USB_DUAL +1.5V_SP_A +1.5V_SP_A +1.5V_SP_A +1.5V_SP_A +1.5V_SP_D +1.5V_SP_D
+3.3V_DUAL
Vout=Vref (1.25V) X ( 1+R2/R1 ) =1.5V
+1.5V_SP_A
BFB9 BEAD 60 0805 1A
+1.5V
A
Vout=Vref (1.25V) X ( 1+R2/R1 ) =1.25V
+1.5V C389 BC71 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V BC67 BC66 BC76 0.1UF 25V Y5V /NI 0.1UF 25V Y5V 1UF 16V 0805 Y5V /NI
MCP51G_PBGA_508 C332 0.1UF 25V Y5V
Title
MCP51 (5&6&7) OF 7
Size Document Number Custom Date: Wednesday, April 12, 2006
1
CRU51-M7
Sheet 19 of 39
Rev 1.3
5
4
3
2
5
4
3
2
1
+3.3V +5V
-12V B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
PCI1 PCI SLOT 120PIN U TRST_L -12V +12V TCK TMS GND TDI TDO 5V 5V INTA_L 5V INTC_L INTB_L 5V INTD_L PRSNT1_L RSRVD +Vio RSRVD PRSNT2_L RSRVD GND GND GND GND RSRVD RSRVD RST_L GND +Vio CLK GNT_L GND GND REQ_L RSRVD +Vio AD30 AD31 3.3V AD29 AD28 GND AD26 AD27 GND AD25 AD24 3.3V IDSEL C/BE3_L 3.3V AD23 AD22 GND AD20 AD21 GND AD19 AD18 3.3V AD16 AD17 3.3V C/BE2_L FRAME_L GND GND IRDY_L TRDY_L 3.3V GND DEVSEL_L STOP_L GND 3.3V LOCK_L SDONE PERR_L SBO_L 3.3V GND SERR_L PAR 3.3V AD15 C/BE1_L 3.3V AD14 AD13 GND