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Foxconn Precision Co. Inc. 848M02 Schematic
PAGE INDEX
01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Index Page Topology Rest Map Clock Distribution Power Delivery Map ClockGen ICS952603 Voltage Regulator Down 10 2.5V Power and 5V_DUAL 1.5V Power VTT_DDR Power LGA775 -1 LGA775 -2 Springdale-GMCH-1 Springdale-GMCH-2 Springdale-GMCH-3 DDR Channel A AGP Connector ICH5-1 ICH5-2 & IDE Connecter 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. ICH5-3 LAN RTL8101L & USB LAN_POWER LAN Connector FWH USB Connectors AC'97 Codec Power/MISC Connectors PCI Slots 1,2 PCI Slot 3 Super IO ITE8712 Keyboard/Mouse/FAN Serial/Print Ports GPIO Summary Jumper Setting Summary Modify list
Fab A Date: 2004/6/25
D
C
C
B
B
A
A
FOXCONN PCEG
Title
Index Page
Doc ument Number
Size C Dat e:
848M02
S heet
1
Rev F 1 of 34
Friday , A ugus t 27, 2004
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VRD 9/10
D
Intel Prescott processor
LGA775 ZIP Socket
D
3 Phase PWM
400/533/800 FSB
CK-409 Clock
AGP 4X / 8X AGP Solt
4x/8x AGP
DDR 400/333/266
Channel A DDR DIMM1
GMCH
848P
DDR 400/333/266
932 Pin FC-BGA
Channel B DDR DIMM1
C
C
Back Panel USB2.0 Port 1 USB2.0 Port 2 USB2.0 Port 3
uATX Form Factor
USB2.0 Port 4 Front Panel USB2.0 Port 5 USB2.0 Port 6 USB2.0 Port 7 USB2.0 Port 8
460 Pin mBGA
PCI Interface
ICH5
PCI Slot 1 PCI Slot 2 PCI Slot 3 10/100 BT LAN
RTL8100C
B
B
IDE CONN 1 IDE CONN 2
S-ATA0 S-ATA1
Super I/O ITE8712F
PS2 Keyboard / Mouse
A
Parallel Serial
Floppy Drive Connector
Firmware HUB
2MB
AC 97 Code 2.3
ALC 655
A
FOXCONN PCEG
Title Size Doc ument Number Cus t om Dat e:
Topology
848M02
S heet
1
Rev F 2 of 34
Friday , A ugus t 27, 2004
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CPU
CPU_PWRGD
D
CPURSTJ
D
ATX Power
PSON PWRGD_ATX PS_On
GMCH
PWRGD_3V CPURSTJ
C
PCIRSTJ
C
ICH5
AGP 4X / 8X
ICH_PWRGD PCIRSTJ KBRST PWRGD_3V Buffer uATX Form Factor
AGP Solt
PCI Slot 1 PCI Slot 2 PCI Slot 3
B
Front Panel
SLP_S3#
B
RSMRST#
PWRBTN#
FR_RST SW_ON
System_RST SW_ON#
Buffer
IDE CONN 1 IDE CONN 2
PANSWH# POWBTN PSIN
FWH
Super IO
KBRST PWR_ON# RSMRST# PSON
A
A
FOXCONN PCEG
Title
Reset Map
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 3 of 34
Friday , A ugus t 27, 2004
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14.318MHz
CPU
100/133/200 MHz Diff Pair
D D
100/133/200 MHz Diff Pair
66 MHz
AGP 4x/8x
Channel A DDR
SpringDale
DIMM1
48 MHz 48 MHz
Channel B DDR DIMM1
66 MHz
C C
CK409-ICS952603
14.318Mhz
66 MHz 33 MHz 48 MHz
33 MHz
FWH
ICH5
B
33 MHz
PCI LAN RTL8101L
B
33 MHz 33 MHz 33 MHz
PCI Slot 1
32.768KHz
PCI Slot 2 PCI Slot 3 Super I/O
AC'97
33 MHz 100 MHz Diff Pair SRC
A
A
FOXCONN PCEG
Title
Clock Distribution
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 4 of 34
Friday , A ugus t 27, 2004
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SPD
D D
5V_SYS
>
1.5V REGULATOR
VCCQ
> >
DDR 2 DIMMS:
5V _D UAL
VCC, CORE LOG, 1.5V 2.46A
ATX SPS
5 V S B 5 V 3 . 3 V + 1 2 V 1 2 V
ATX 12V P/S
+ 1 2 V
SPD
VCCAGP, AGP I/O 1.5V 1.5A
>
V TTFSB 0.8375V~1.6V 2.4A
> 2.6V
6.00A
2D 6V _STR
> >
3D 3V_SYS
VCCDAC, DAC I/O 1.5V 65mA
M PG A 478 12V _VRM
>
VRD 10
C O R E _C PU_SYS
>
C
M IC5258
VCCVID
> >
C O R E _C PU_SYS 0.8375V~1.6V 60A V CC_VID 1.2V 30mA
>
2D 6V _STR
2.6V REGULATOR
VCCSM, DDR I/O 2.6V 2.8A
D D R _V TT_STR
VCCGPIO
DDR VTT
ICH 5
P W R G _A TX 5V _D UAL V CC3_3: 3D 3V_SYS V _C PU _IO 1.1V~1.85V 45mA
>
1.3V REGULATOR
> 1.3V
2.1A
>
3.3V 30mA
C
3.3V 610mA
5V _SB
A M S1086
3D 3V_SB
>
V C C SUS3_3 R E SUME: 3.3V 70mA
V CC1_5: C ORE LOGIC: 1.5V 970mA
3 VOLTS B A TTERY
> OR >
V C C _RTC
>
V CCRTC 3D 3V_SYS
3D 3V_SYS 5V_SYS 12V_SYS -12V_SYS
B
3D 3V_SB
> > > > >
PCI PER SLOT:
3.3V 5V 12V -12V 3.3Vaux 0.375A
7.6A 5.0A 0.5A 0.1A
5V _SB
A M S1086
3D 3V_SB
A
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5
4
>
3
>
>
3D 3V_SYS
CLK_GEN
> > > > >
5V _D UAL
PWRG_ATX
3.3V 250mA
5V _SB 5V_SYS 3D 3V_SYS
SUPER I/O 5V 3.3V
FWH CORE 3.3V 24mA USB POWER 5V PS2 KB/MS POWER
B
5V_SYS
5V _SB
5V _D UAL
> >
5V
12V_SYS 3D 3V_SYS
AUDIO VREG
5V _A U DIO
> >
AC' 97 AUDIO CODEC A5V 70mA 3.3V 10mA
A
FOXCONN PCEG
Title
Power Delivery Map
Size C Dat e:
2
Doc ument Number
848M02
S heet
1
Rev F 5 of 34
Friday , A ugus t 27, 2004
5
4
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2
1
D
D
3D3V_SYS
3D3V_SYS
3D3V_SYS
1
1
FB1 FB L0805 300 Ohm
FB2 FB L0805 300 Ohm
1
FB3 FB L0805 300 Ohm
2
2
3D3V_CLK
3 10 16 40 27 34
U1
VDD_REF VDD_PCI0 VDD_PCI1 VDD_CPU VDD_3V66 VDD_SRC
VDD_A VDD_48
48 24
2
BC11 4.7uF BC12 0.1uF BC13 4.7uF
1
BC1 10nF
BC2 1uF
BC3 10nF
BC5 10nF
BC7 10nF
3D3V_CLK
CPU0 CPU0# CPU1 CPU1# CPU_ITP CPU_ITP# SRC SRC# RST#/PD#
BC9 10nF
BC10 0.1uF R5 1K
BC14 0.1uF
DUMMY
DUMMY
39 38 42 41 45 44 36 35
166_P _GMCH 166_N_GMCH 166_P _CPU 1 66_N_CP U 166_P _ITP 166_N_ITP 100_P _ICH 1 0 0_N_ICH
R1 R2 R3 R4
1 1 1 1
2 33 2 33 2 33 2 33
CK _166M_P _GMCH 13 CK _166M_N_GMCH 13 CK _200M_P _CPU 11 CK _200M_N_CPU 11
C
C
R8 R9
1 1
2 33 2 33 1 1 1 1 1 1 1 1
R10 49.9 R11 49.9 R12 49.9 R13 49.9 R14 R15 R16 49.9 R17 49.9
2
20
CK _100M_P _ICH 18 CK _100M_N_ICH 18
VCCP
3D3V_CLK
2
2
2
2
2
2
2
1
1
16, 31 S MB _DA TA _MAIN 16, 31 S MB _CLK _MAIN
2
2
32 31
SDATA SCLK
33
Q1
VTT_PWRGD# XTAL_IN XTAL_OUT IREF VSS_REF VSS_PCI0 VSS_PCI1 VSS_48 VSS_3V66 VSS_SRC VSS_CPU VSS_A
4 5 46
MMB T3904 X1 XTA L-14.318MHz
1
2 1
6 11 17 23 28 37 43 47
3V66_0 3V66_1 *3V66_2/MODE 3V66_3/VCH DOT48 USB48 **FS_A/REF_1 **FS_B/REF_0
30 29 26 25 21 22 1 2
66_0 66_1 66_2 3V 66_3-V CH
R 23 R 24 R 25 R 26
1 1 1 1 1 1 1 1
48_DOT 48_USB
R 27 R 28
FS_A FS_B
R 29 R 31
2
B
* 150K Internal Pull-up **150K Internal Pull-down ICS 952603
SM Bus Address :1101-0010
3D3V_CLK
2 4 6 8
1 3 5 7
*
R N712 1K 8P 4R0603 +/-5%
1
2
12, 13 12, 13 12
FS B SEL0 FS B SEL1 FS B SEL2
R 36 R 37
1 1
1
3V 66_3-V CH
A
2
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*
*FS_C/PCIIF0 *FS_D/PCIIF1 *FS_E/PCIIF2 PCI0 PCI1 PCI2 PCI3 PCI4 PCI5
7 8 9 12 13 14 15 18 19
33M_LAN DISCONNECT THE 1394CLK FS_D 33M_P CI1 33M_P CI2 33M_P CI3 33M_FWH 33_4 33_5
R 20 RN1
1
2 33
CK _33M_LAN
21
7 5 3 1
8 6 4 2
R 21 R 22
33
1 1
2 33 2 33
CK _33M_P CI1 CK _33M_P CI2 CK _33M_P CI3 CK _33M_FWH CK _33M_ICH CK _33M_SIO
28 28 29 24 20 30
2 2 2 2
33 33 33 33
CK _66M_GMCH 13 CK _66M_AGP 17 CK _66M_ICH 18 CK _48M_SIO 30
2 33 2 33 2 33 2 33
BC943 0.1uF
CK _48M_GMCH 13 CK _48M_ICH 18
CK _14M_ICH A DU14MCLK
18 26
2
DUMMY DUMMY
R18 220
R19 10K R30 475 27pF BC15 27pF BC16
B
D UMMY
R35 10K
2 10K 2 10K
FS_A FS_B
R38 1K
A
FOXCONN PCEG
Title
Clock Generator CK-409
Doc ument Number
Size C Dat e:
2
848M02
S heet
1
Rev F 6 of 34
Friday , A ugus t 27, 2004
5
4
3
2
1
5V _SYS
*
D
R 501 4.7 +/-5% R 0603
*
U 51 IS L6566CR 11, 30 V ID4 11, 30 V ID3 11, 30 V ID2 11, 30 V ID1 11, 30 V ID0 11, 30 V I D5 V RM_EN
B C501 4. 7uF 10V , X7R, +/-10% C1206
12V _S YS
V IN
D
D
* *
R509
ISEN1
*
D
32 34
R 506 1K R 0603 +/-5% R508 0 +/-5% R0603
2
B C670 0. 1uF 16V , X7R, +/-10% C0603
PHASE1
29
P HA SE1
Q103
*
Q104 DUMMY
* *
note: 7/6-chang PWRGD_VRM pullup VCCP to 12V add R601 to 330 7/7 del Power Good VRM for timing
R0603
B C508 1K +/-5% C0603 B C509
S
5. 6nF 50V , X7R, +/-10%
8
LGATE1 COMP
*
G
A OD412
+/-1% R0603 2.2 R 507 B C510 1nF 50V , X7R, +/-10% C0603 V IN
*
38 39 40 1 2 3 35 37
VCC
VID4 VID3 VID2 VID1 VID0 DACSEL/VID5 PGOOD ENLL
R0603
*
PVCC1 BOOT1
33 30 R503
2.2 +/-1%
*
B C505 0. 1uF
*
B C504 1 uF 16V , X7R, +/-10% C 0805
D
*
Q101
D
B C503 4. 7uF 16V , X5R, +/-10% C 1206
7
Q102 D UMMY
G
A OD412
UGATE1
*
S
1
31
C0603 25V , X7R, +/-10%
G S
A OD412 L31 Chok e Coil 1. 0uH
V CCP
R504 1 +/-1% R 0603
R719 10K
E C101
E C102
E C103
E C104
E C105
G S
DUMMY 10pF 50V , NP O, +/-5%
12V _S YS
A OD412
*
* 3300uF 3300uF 3300uF 3300uF 3300uF ** ** ** ** *
DUMMY D UMMY B C514 4. 7uF 16V , X5R, +/-10% C1206
*
TC3 100uF
*
TC4 E C119 E C120 100uF
* *
C TD D UMMY
C TD DUMMY
560uF 560uF
C0603
9 10
FB VDIFF PVCC2/EN_PH3 BOOT2/NC 24
DUMMY D UMMY
*
560pF B C511 R512 C0603 50V , X7R, +/-10%
*
*
R0603
*
Q105 DUMMY
D
26 R511
2.2 +/-1%
B C515 0. 1uF
*
D
R 510 1K R 0603 +/-5%
B C512 1 uF 16V , X7R, +/-10% C 0805
*
Q106
C
*
VSEN PHASE2/NC RGND ISEN2/ISEN3 OFST LGATE2/NC 28 25 23
R 516 1K R 0603 +/-5%
S
12 11
5V _S YS R 518 200K +/-5%
UGATE2/PWM3
*
1
V CCP
750
+/-5% R0603 D UMMY
27
C0603 25V , X7R, +/-10%
G
R514 1 +/-1% R 0603 A OD412 R717 10K
G S
A OD412 L32 P HA SE2 +/-1% R0603 2.2 R 517 Chok e Coil 1. 0uH
C
D
*
Q107 R519 0 +/-5% R0603
Q108 DUMMY
* *
D
2
E C106
E C107
E C108
TC5
*
R0603
*
*
6
R 520 0 R0603 +/-5% DUMMY
G
A OD412
* ** ** *
3300uF 3300uF 3300uF D UMMY
* *
TC6 100uF
G S
A OD412 B C518 1nF 50V , X7R, +/-10% C0603
C TD C TD D UMMY 100uF D UMMY
12V _SYS
*
5V _S YS R 523 1K R 0603 +/-5%
36
R 521 150K +/-5% R 0603
FS PVCC3 18
V IN
2.2 21 R522 BOOT3 R 0603 +/-1%
*
4
R 524 R 0603 2.2K +/-5%
VRM10 OCSET ICOMP ISUM IREF UGATE3 PHASE3 ISEN3 LGATE3 20 22
*
B C523 0. 1uF
*
*
D
*
Q109
D
B C519 5 REF 10nF 25V , X7R, +/-10% C0603
B C520 1uF 16V , X7R, +/-10% C0805
S
Q110
*
B C522 4. 7uF 16V , X5R, +/-10% C 1206
*
*
1
13 14
S
C0603 1 25V , X7R, +/-10% R525 +/-1% R0603
G
R718 10K
D UMMY A OD412
G S
A OD412 L33 P HA SE3 Chok e Coil 1. 0uH
GND
R526 0 +/-5% R0603
R 527 R0603
33K +/-5%
*
*
*
15 16
19 R528 17
1K R0603 +/-5% R 530 0 +/-5% R0603
Q111
*
Q112 DUMMY A OD412
*
T
S
R T1 R0603
10K R 531 0 +/-5% +/-5% R0603 DUMMY DUMMY
*
B C524 10nF 25V , X7R, +/-10% C 0603
*
G
A OD412
+/-1% R0603 2.2 R529
D
*
E C115 560uF
* *
E C116 560uF
*
TC1 100uF
*
TC2 100uF
D
2
G
C TD D UMMY DUMMY DUMMY
C TD DUMMY
* * * * * *
3300uF 3300uF E C117 560uF DUMMY
E C109
E C100
E C118 560uF
*
B C525 1nF 50V , X7R, +/-10% C0603
*
41
S
D UMMY UMMY D
B
B
R 533 R0603 R534 R0603
* * *
B C526 C0603
22nF 25V , X7R, +/-10%
R 532 R0603
39K +/-5% 39K +/-5% 39K +/-5%
*
P HA SE1
P HA SE2
P HA SE3 V IN B C921 0. 1uF
12V _VRM V TT_OUT_RIGHT R 39 680 V TT_P W RGD R 0603 5V _S B _SYS V TT_P W RGD 12
12V _SYS
B C925
0. 1uF
5
C N 100 A TX12V _P1_2X2 P W R4NW P 1
+/-5%
*
C
R 43 1K +/-5% R 0603
*
R515 10.7K +/-1% R0603
2
4
For EMI
V RM_EN
1
3
*
E C111
*
E C114
*
E C112
*
E C113
B C528
*
*
change bc527 from 10u to 0.1u 0704
1500uF
1500uF
1500uF
1500uF
3. 3uF
*
R 58 22. 1K +/-1% R0603
E
B C527 0. 1uF 25V , X7R, +/-10% C0603
*
L4
Chok e Coil 1. 2uH V IN R 52
V RM_EN Q2 MMBT3904 S OT23_BEC
B
*
2. 74K R 0603 +/-1%
D
Q3
G
2N7002
*
S
R535 1.4K +/-1% R0603
A
A
FOXCONN PCEG
Title
VRD10.1
Doc ument Number
Size C Dat e:
848M02
S heet
1
Rev F 7 of 34
Saturday, August 28, 2004
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4
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2
5
4
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2
1
2D5V_STR Regulator
D
3D3V _S YS
12V _SYS
5V _S B_SYS
D
*
5V _S B_SYS 12V _S YS
E C20 470uF 10V , +/-20% CE 35D80H200
D5 B A T54C Q18
G
3D3V _SB
3
D
N TD40N03R
1
Q19 D6 B120
D
C
S
*
5V _S B _SYS
D
R 94 220 +/-5% R0603
*
G
2N7002 R 96
R 95 220 +/-5% R0603
2
1
E
2
R 97 47K +/-5% R0603
Q21
G D
N TD40N03R Q22
(2.64V)
2D5V _S TR
1
G C
R 99
LM431A CZ
3
U6
1
R 98
S
2N7002
S
*
18
S LP _S4J
2
B E
Q23 MMB T3904
C
5V_DUAL Circuit
B
5V _DUA L U7 12V _SYS 5V _S B _SYS 5V _S YS Q24 5V _S B_SYS R101
8
D1
1
S1
7 6 5
2 3 4
D1
G1
D2
S2
D2
G2
2N7002
Q26 P W RG_A TX P W RG_ATX 27
BC57
VIN
ADJ/GND
A O4600 Q27
R 103 301
1
5 6 7 8
D4 D3 D2 D1
G S3 S2 S1
4 3 2 1
R 104 499
S i4410DY
A
+ E C25 1000uF BC58 0.1uF
FDS8958A 7A,30V. 28mohm @Vgs=10V for N-Channel -5A,-30V. 80mohm @Vgs=-4.5 for P-Channel
220uF
2N7002
1uF
2
EC24
1
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5
*
1K R0603 +/-5%
560 R 100 10K
*
E C21 1000uF 10V , +/-20% CE 35D80H200
*
E C22 1000uF 10V , +/-20% CE 35D80H200
1.5K PWOK+ Q25 P W OKJ
4
*
Q20 MMB T3904 R 102 1K
R 92 10K R0402 +/-5%
2
R 93 47K +/-5% R 0402
2
1
S
*
1K R 0402 +/-5%
B
P W RG_ATX
27
5V _DUAL
*
3
B C922 0. 1uF
C
3D3V _S YS
5V _SYS
B C923
0. 1uF
B C924
0. 1uF
For EMI
3D3V_SV Regulator
SB3.3V
5V _DUAL
Vref=1.25V
3D3V _SB
B
Vin 4 4 Vout ADJ
A IC1086
3 2 1
IF USE 1086 DUMMY R103CHANGE THE R104 TO 0 OHM
D UMMY U8 A ME 1085
3
VOUT
2
Vout=Vref(1+R2/R1)+IadjR2 R1 is Up Resister. Iadj=50uA Vref=1.25V
A
FOXCONN PCEG
Title
Power 2.5V-5VDUAL-3.3SB
Doc ument Number
Size C Dat e:
2
848M02
S heet
1
Rev F 8 of 34
Friday , A ugus t 27, 2004
5
4
3
2
1
3D3V _S YS 12V _S YS
1D5V_CORE Regulator
D
3D3V _SB
1
EC26 220uF
BC59 0.1uF
1
B C60 0. 1uF 12V _SYS R 105 910 U 9A LM358M
2
D
8
D
Q28
2
3
note: 7/6-chang del D7 reg
+ -
1
G
N TD40N03R
2
4
1
R 107 1K
2
change R105&R108 to 910 ohm 080204
B C61 0. 1uF
S
1
B C62 10nF DUMMY R 108 DUMMY
B C63 0. 1uF
DUMMY
BC64 2.2uF
2
910 DUMMY BC65 1uF
12V _SYS
U 9B LM358M
8
D
Q29
5 6
C
+ -
7
G
N TD40N03R
1D5V _CORE
4
S
2
1
R 109 1K
2 1 1
C
R 110 1. 54K
1
2
2
B C66 0. 1uF D UMMY
BC67 0.1uF
EC27 1000uF
EC28 1000uF
D UMMY D UMMY DUMMY
BC68
B C69 10nF
B C70 0. 1uF
PROCHOTJ Signal
B B
A
A
FOXCONN PCEG
Title
Power 1.5V
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 9 of 34
Friday , A ugus t 27, 2004
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5
4
3
2
5
4
3
2
1
PSC=1.2V
D D
FSB_VTT Regulator
GMCH VTT Source 1.6A and Sink 600mA
change Q30 2N3904 to MMBT3904 FOR FOOTPRINT 0705
del Q30 0707 1 D5V _CORE FS B _VTT 12V _SYS 3D3V _SB RN2 BC71 0.1uF BC72 0.1uF V CCP
2 4 6 8
D UMMY -12V _SYS
Y 5V + 20%~-80% D UMMY
C
Q31
0 +/-5% 8P 4R0603
8
U 10A LM358M
8
3 2
R 113 523 +/-1% R 0603
+ -
U10B LM358M 1K
R 112 G N TD40N03R BC920 0.1uF
+ -
7
R 114 220
1 1 2 B
2
4
E
6
S
1
5
D
4
change R113from 562 ohm to 523ohm 0707
C
2N2907A
1
Q32
-12V _SYS -12V _SYS
2
DUMMY Y 5V + 20%~-80%
B
1 3 5 7
change R111 from 1k ohm to 910 ohm 0707
R 111 910 +/-1% R 0603
*
DEL THE BOOTSELECT CIRCUIT FOR ADAPTING TO THE 775CPU DESIGNGUIDE 0705
7/7:DEl CAP
1
2
BC73 1uF BC76 0.1uF C1 0. 1uF
C
VTT_DDR Regulator
EC29 220uF
BC75 4.7uF
B
2D5V _S TR
3D3V _S YS
V TT_DDR
+ E C30 U 11 DUMMY
1
R115 10K
VIN
A
VCNTL1 VCNTL2 VCNTL3 VCNTL4 VOUT
5 6 7 8 4 1 2
7/7:change EC33 1000uf to 470uf C2 0. 1uF
A
3
R116 10K
REFEN
RT9173
GND
1
E C32 470uF
1
E C33 470uF Title
D UMMY B C78
2
FOXCONN PCEG Power 1.25V-GMCH VTT
Doc ument Number Size C Dat e:
2
7/7:DEl 1uf CAP
2
848M02
S heet
1
Rev F 10 of 34
Friday , A ugus t 27, 2004
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5
4
3
2
5
4
3
2
1
HDJ[ 63. . 0]
HDJ[ 63. . 0]
13
13
HA J[ 31. . 3]
HA J[ 31. . 3]
U12B HDJ0 HDJ1 HDJ2 HDJ3 HDJ4 HDJ5 HDJ6 HDJ7 HDJ8 HDJ9 H D J10 H D J11 H D J12 H D J13 H D J14 H D J15 13 13 13 H D B IJ0 H D S TB NJ0 HDS TB P J0 H D J16 H D J17 H D J18 H D J19 H D J20 H D J21 H D J22 H D J23 H D J24 H D J25 H D J26 H D J27 H D J28 H D J29 H D J30 H D J31 13 13 13 H D B IJ1 H D S TB NJ1 HDS TB P J1
2 OF 7 H A J3 H A J4 H A J5 H A J6 H A J7 H A J8 H A J9 H A J10 H A J11 H A J12 H A J13 H A J14 H A J15 H A J16 13 HRE QJ[ 4. . 0]
U 12A
D
B4 C5 A4 C6 A5 B6 B7 A7 A10 A11 B10 C11 D8 B12 C12 D11 H D B IJ0 A8 C8 B9 G9 F8 F9 E9 D7 E10 D10 F11 F12 D13 E13 G13 F14 G14 F15 G15 H D B IJ1 G11 G12 E12
D00# D01# D02# D03# D04# D05# D06# D07# D08# D09# D10# D11# D12# D13# D14# D15# DBI0# DSTBN0# DSTBP0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DBI1# DSTBN1# DSTBP1#
CP U_S oc ket
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DBI2# DSTBN2# DSTBP2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBI3# DSTBN3# DSTBP3#
G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D19 G20 G19 D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 A19 A22 B22 C20 A16 C17
H D J32 H D J33 H D J34 H D J35 H D J36 H D J37 H D J38 H D J39 H D J40 H D J41 H D J42 H D J43 H D J44 H D J45 H D J46 H D J47 H D B IJ2
H D B IJ2 H D S TB NJ2 HDS TB P J2
13 13 13 13 HA J[ 31. . 3]
H R E QJ0 H R E QJ1 H R E QJ2 H R E QJ3 H R E QJ4 13 HA DS TB J0
HA J[ 31. . 3]
H D J48 H D J49 H D J50 H D J51 H D J52 H D J53 H D J54 H D J55 H D J56 H D J57 H D J58 H D J59 H D J60 H D J61 H D J62 H D J63 H D B IJ3
L5 P6 M5 L4 M4 R4 T5 U6 T4 U5 U4 V5 V4 W5 N4 P5 K4 J5 M6 K6 J6 R6 G5 AB6 W6 Y6 Y4 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 AG4 AG5 AH4 AH5 AJ5 AJ6 AC4 AE4 AD5
H D B IJ3 H D S TB NJ3 HDS TB P J3
13 13 13
H A J17 H A J18 H A J19 H A J20 H A J21 H A J22 H A J23 H A J24 H A J25 H A J26 H A J27 H A J28 H A J29 H A J30 H A J31 TP11 TP12 TP13 TP14 V TT_OUT_RIGHT FS B _VTT 13 R118 100 +/-1% R0603 GTLREF voltage 12 mils width, divider should caps should be should be 0.67*FSB_VTT 15 mils spacing be within 1.5" of the GTLREF pin placed near CPU pin R 117 100 +/-1% R0603 HA DS TB J1 TP _LA G775_P IN_AH4 TP _LA G775_P IN_AH5 TP _LA G775_P IN_AJ5 TP _LA G775_P IN_AJ6
C
TBD
Pin CRB Pin CRB D23 0.7: test point TP_VCCPLL AM5 0.7: test point TP_VID6
TBD
Pin AL2 PROCHOT# CRB 0.7: pull up to VTT_OUT_RIGHT DG/611A: example VR thermal monitor circuit
A03# ADS# A04# BNR# A05# HIT# A06# RSP# A07# BPRI# A08# DBSY# A09# DRDY# A10# HITM# A11# IERR# A12# INIT# A13# LOCK# A14# TRDY# A15# BINIT# A16# DEFER# RSVD1 EDRDY# RSVD2 MCERR# REQ0# REQ1# AP0# REQ2# AP1# REQ3# REQ4# BR0# ADSTB0# TESTHI08 PCREQ# TESTHI09 TESTHI10 A17# A18# DP0# A19# DP1# A20# DP2# A21# DP3# A22# A23# GTLREF A24# A25# RESET# A26# A27# RS0# A28# RS1# A29# RS2# A30# A31# A32# A33# A34# A35# RSVD3 RSVD4 ADSTB1#
1 OF 7
D2 C2 D4 H4 G8 B2 C1 E4 AB2 P3 C3 E3 AD3 G7 F2 AB3 U2 U3 F3 G3 G4 H5 J16 H15 H16 J17 H1 G23 B3 F5 A3
TP _RS PJ
H A DS J H B N RJ H I TJ TP1 H B P RIJ HDB SYJ H DRDY J H I TMJ I N I TJ H L OCK J H TR D Y J TP2
13 13 13 13 13 13 13 18, 24 13 13
D
H I E R RJ
T P _B INITJ TP _E DRDY J TP _MCE RRJ TP _A PJ0 TP _A PJ1 H B R0J TE S THI_8 TE S THI_9 TE S THI_10 TP _DP J0 TP _DP J1 TP _DP J2 TP _DP J3 H GTLRE F
H D E FE RJ 13 TP3 TP4 TP5 TP6 H B R0J 13
TP7 TP8 TP9 TP 10
H C P URS TJ 13 H R S J0 H R S J1 H R S J2 13 13 13
TBD
HBR0J CRB 0.7: 220 ohm, 5% DG 0.51: 62 ohm, 5%
C
GTLREF voltage should be 0.67*FSB_VTT 12 mils width, 15 mils space caps should be placed near MCH pin H GTLRE F_MCH H GTLRE F_MCH 12, 13
CP U_S oc ket
H GTLRE F
*
R120 210 +/-1% R0603
*
B C79 1uF 10V , Y 5V , + 80%/-20% C0603
*
B C80 220pF 50V , X7R, +/-10% C0603
*
R 121 210 +/-1% R0603
*
B C711 1uF C0603
10V, X5R, +/-10%
*
B C712 220pF 50V , X7R, +/-10% C0603
Place at CPU end of route
FS B _VTT R 122 R 0603 R 123 R 0603 62 +/-5% 62 +/-5%
**
TE S THI_0 TE S THI_2_7
TE S THI_0
12
U 12C 18 18 18 18 18 18 18 12 12 12 S MIJ A 20MJ F E R RJ I N TR N MI I G N NE J S TP CLKJ H V CCA HV S SA TP 15 H V CCIOP LL V ID0 V ID1 V ID2 V ID3 V ID4 V ID5 TP _V ID6
3 OF 7
TP _V CCP LL
A23 B23 D23 C23 AM2 AL5 AM3 AL6 AK4 AL4 AM5 F28 G28
VCCA VSSA RSVD5 VCCIOPLL VID0 VID1 VID2 VID3 VID4 VID5 RSVD6 BCLK0 BCLK1 SKTOCC# THERMDA THERMDC VCCSENSE VSSSENSE VCC_MB_REG VSS_MB_REG
Changed pin name
TE S THI_2_7 RS V D_AK6 RS V D_G6 CP US LP J C P U_P W RG P R OCHOTJ THE RMTRIP J HCOMP 0 HCOMP 1 HCOMP 2 HCOMP 3 18 18 13 18
R 124 R0603
62 +/-5%
*
H I E R RJ
6 CK _200M_P _CPU 6 CK _200M_N_CPU 30 S K TOCCJ S K TOCCJ
COMP0 COMP1 COMP2 COMP3 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24
A13 T1 G2 R1 N5 AE6 C9 G10 D16 A20 E23 E24 F23 H2 J2 J3 Y1 V2 AA2
R 225 1 R 226 1
2 62 2 62
T HE RMTRIP J F E RRJ
***
7,30 7,30 7,30 7,30 7,30 7,30
V ID0 V ID1 V ID2 V ID3 V ID4 V ID5 TP 16
SLP# RSVD12 PWRGOOD PROCHOT# THERMTRIP#
L2 AH2 N1 AL2 M2
R 722 FS B _VTT
* *
R 129
DUMMY +/-5% 130 +/-1% R0603
RS V D_AK6
P R OCHOTJ
1 3 5 7
R134 R0603 R135 R0603 R136
*
62
* *
B
P2 K3 R3 K1 L1 N2 M3
SMI# A20M# FERR#/PBE# LINT0 LINT1 IGNNE# STPCLK#
TESTHI00 TESTHI01 TESTHI11 TESTHI12 TESTHI02 TESTHI03 TESTHI04 TESTHI05 TESTHI06 TESTHI07 RSVD10 RSVD11
F26 W3 P1 W2 F25 G25 G27 G26 G24 F24 AK6 G6
TE S THI_0 TE S THI_1 TE S THI_11 TE S THI_12
TBD
Pin AK6, G6 refer to CRB 0.7
V TT_OUT_RIGHT V TT_OUT_LEFT Place at CPU end of route H B R0J 62 +/-5% Place at CPU end of route C P U_P W RG R128 100 +/-1% R0603 R N601 R125 R0603
B
2 4 6 8
TE S THI_9 TE S THI_8 TE S THI_10 TE S THI_1
V TT_OUT_LEFT
8P 4R0603 62 +/-5% 62 +/-5% DUMMY +/-5% +/-5% 62 +/-5%
TE S THI_11 TE S THI_12 RS V D_G6
AE8 AL1 AK1
TBD
Pin N5 ~ Pin J3 CRB 0.7: connections ok?
30 30
THE RMDA THE RMDC TP 17 TP 18 V CC_S E NSE V S S _SENSE TP _V CCS E NSE TP _V SSSENSE
R137 R0603 R138 R0603
10 mils width 7 mils spacing 100 +/-1% 100 +/-1%
R 126 R0603 HCOMP 2 HCOMP 3 V TT_OUT_RIGHT
AN3 AN4 AN5 AN6
F29 from RSV RSVD9
TP _RS V D_CP U_N5 TP _RS V D_CP U_AE6 TP _RS V D_CP U_C9 TP _RS V D_CP U_G10 TP _RS V D_CP U_D16 TP _RS V D_CP U_A20
TP19 TP20 TP21 TP22 TP23 TP24
**
H C P URS TJ B C81 2 2pF 50V , NP O,+/-5% C 0603
*
*
*
R139 RN3
680 +/-5%
V ID0
A
TP25 HCOMP 1
**
BOOTSELECT LL_ID0 LL_ID1
L L_ID0 TP _LL_ID1
L L_ID0
HCOMP 0
R140 R0603 R142 R0603
60. 4 +/-1% 60. 4 +/-1%
680 R 141 +/-5%
CP U_S oc k et
10 mils width 7 mils spacing
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* *
8 6 4 2
7 5 3 1
V ID3 V ID2 V ID4 V ID1
680 +/-5%
V ID5
A
FOXCONN PCEG
Title
LGA775 -1
Size Doc ument Number
848M02
S heet
1
Rev A 11 of 34
Dat e:
2
Friday , A ugus t 27, 2004
5
4
3
2
1
V CCP U12E 5 OF 7
V CCP V CCP U 12G U 12F 6 OF 7 7 OF 7
D
R148
**
R147
49. 9 49. 9
C
B
C10 D12 AM7 C24 K2 C22 AN1 B14 K7 AE16 B11 AL10 AK23 H12 AF7 AK7 H7 E14 L28 Y5 E11 AL16 AL24 AK13 AL3 D21 AL20 D18 AN2 AK16 AK20 AM27 AM1 AL13 AL17 C19 E28 AH7 AK30 D24
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40
7 5 3 1
*
R 149 49. 9 +/-1% R 0603
8 6 4 2
GTLRE F_SEL
R N 711 51 8P 4R0603 +/-5% HTMS H TD I HB P M2J H TCK
place TDO termination near XDP connector
RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36
V1 F6 T2 Y3 AE3 W1 E7 B13 D14 E6 D1 E5
place TRSTJ termination anywhere on route
CP U_S oc ket FS B _VTT PLL Supply Filter
CP U_S oc k et
1
CP U_S oc k et 12V _SYS V CCP L0805 10uH
125mA L8 0805 +/-10%
1
For supporting to LGA775 P4EE CPU
FS B _VTT U 1 2D H TCK H TD I H T DO HTMS H T RS TJ
AE1 AD1 AF1 AC1 AG1 AJ2 AJ1 AD2 AG2 AF2 AG3
TCK TDI TDO TMS TRST#
HB P M0J HB P M1J HB P M2J HB P M3J HB P M4J HB P M5J 6, 18, 27 I C H_S Y S _RS TJ
I C H_S Y S _RS TJ AC2
A
6,13 6,13 6
FS B SEL0 FS B SEL1 FS B SEL2
FS B SEL0 FS B SEL1 FS B SEL2
D
AK3 AJ3 G29 H30 G30
VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 BPM0# VTT8 BPM1# VTT9 BPM2# VTT10 BPM3# VTT11 BPM4# VTT12 BPM5# VTT13 VTT14 DBR# VTT15 VTT16 ITPCLKOUT0 VTT17 ITPCLKOUT1 VTT18 VTT19 BSEL0 VTT20 BSEL1 VTT21 BSEL2 VTT22 VTT23 VTT24 VTTPWRGD VTT_OUT1 VTT_OUT2 VTT_SEL
CP U_S oc ket
A29 B25 B29 B30 C29 A26 B27 C28 A25 A28 A27 C30 A30 C25 C26 C27 B26 D27 D28 D25 D26 B28 D29 D30 AM6 AA1 J1 F27
V TT_OUT_RIGHT V TT_OUT_LEFT R 155 1
D
4 OF 7
R745 10K R0603 +/-5%
*
R 746 619 +/-1% R 0603
2
11
H V CCIOP LL
H V CCIOP LL B C102 1uF 10V , X5R, +/-10% C0603
*
*
Q120
R 154 0 +/-1% R0603
2
G
2N7002 11 11 H V CCA HV S SA
S
H V CCA HVSSA
H GTLRE F_MCH 11, 13 3D3V _S YS
*
GTLRE F_SEL
R 751 249 +/-1% R0603
*
Q121
R 752 110 +/-1% R 0603
A
G
2N7002 V TT_P W RGD 7 V TT_OUT_RIGHT V TT_OUT_LEFT 3D3V _S YS 11 TE S THI_0 TE S THI_0
S
*
BC440 0.1uF Place at CPU end of route
2
DUMMY
R 753 62 +/-5% R 0603 Title
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*
AG22 K29 AM26 AL8 AE12 AE11 W23 W24 W25 T25 Y28 AL18 AC25 W30 Y30 AN14 AD28 Y26 AC29 M29 U24 J23 AC27 AM18 AM19 AB8 AC26 J8 J28 T30 AM9 AF15 AC8 AE14 N23 W29 U29 AC24 AC23 Y23 AN26 AN25 AN11 AN18 Y27 Y25 AD24 AE23 AE22 AN19 V8 K8 AE21 AM30 AE19 AC30 AE15 M30 K27 M24 AN21 T8 AC28 N25 AE18 W26 AD25 M8 N30 AD26 AJ26 AM29 M25 M26 L8 U25 Y8 AJ12 AD27 U23 M23 AG29 N27 AM22 U28 K28 U8 AK18 AD8 K24 AH28 AH21
VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24 VCCP25 VCCP26 VCCP27 VCCP28 VCCP29 VCCP30 VCCP31 VCCP32 VCCP33 VCCP34 VCCP35 VCCP36 VCCP37 VCCP38 VCCP39 VCCP40 VCCP41 VCCP42 VCCP43 VCCP44 VCCP45 VCCP46 VCCP47 VCCP48 VCCP49 VCCP50 VCCP51 VCCP52 VCCP53 VCCP54 VCCP55 VCCP56 VCCP57 VCCP58 VCCP59 VCCP60 VCCP61 VCCP62 VCCP63 VCCP64 VCCP65 VCCP66 VCCP67 VCCP68 VCCP69 VCCP70 VCCP71 VCCP72 VCCP73 VCCP74 VCCP75 VCCP76 VCCP77 VCCP78 VCCP79 VCCP80 VCCP81 VCCP82 VCCP83 VCCP84 VCCP85 VCCP86 VCCP87 VCCP88 VCCP89 VCCP90 VCCP91 VCCP92
VCCP93 VCCP94 VCCP95 VCCP96 VCCP97 VCCP98 VCCP99 VCCP100 VCCP101 VCCP102 VCCP103 VCCP104 VCCP105 VCCP106 VCCP107 VCCP108 VCCP109 VCCP110 VCCP111 VCCP112 VCCP113 VCCP114 VCCP115 VCCP116 VCCP117 VCCP118 VCCP119 VCCP120 VCCP121 VCCP122 VCCP123 VCCP124 VCCP125 VCCP126 VCCP127 VCCP128 VCCP129 VCCP130 VCCP131 VCCP132 VCCP133 VCCP134 VCCP135 VCCP136 VCCP137 VCCP138 VCCP139 VCCP140 VCCP141 VCCP142 VCCP143 VCCP144 VCCP145 VCCP146 VCCP147 VCCP148 VCCP149 VCCP150 VCCP151 VCCP152 VCCP153 VCCP154 VCCP155 VCCP156 VCCP157 VCCP158 VCCP159 VCCP160 VCCP161 VCCP162 VCCP163 VCCP164 VCCP165 VCCP166 VCCP167 VCCP168 VCCP169 VCCP170 VCCP171 VCCP172 VCCP173 VCCP174 VCCP175 VCCP176 VCCP177 VCCP178 VCCP179 VCCP180 VCCP181 VCCP182 VCCP183 VCCP184
AK12 AH22 T29 AM14 AM25 AE9 Y29 AK25 AK19 AG15 J22 T24 AG21 AM21 J25 U30 AL21 AG25 AJ18 J19 AH30 J15 AG12 AJ22 J20 AH18 AH26 W27 AL25 AN8 AH14 U27 T23 R8 AK22 AN29 AG11 AK26 J10 AJ15 AG26 AN9 AH15 AF18 AL15 J26 J18 J21 AG27 AK15 AF11 AD23 AM15 AF8 AK21 AG30 AJ21 AM11 AL11 AJ11 K30 AL14 AN30 AH25 AL12 AJ9 AK11 AG14 N29 AL30 AJ25 AH9 J29 J11 K25 P8 K23 AL19 AM8 T26 N28 AH12 AL22 AN15 AJ8 U26 AJ19 T27 AK8 AN12 AG9 N26
AF9 AF22 AH11 AJ14 AH19 AH29 AH27 AG28 AL26 AM12 J24 J13 T28 W28 J12 J27 AG19 AL9 AD30 AF21 Y24 AK14 J9 M27 AF14 J30 AG18 AA8 AG8 AL29 AD29 W8 AH8 N24 AN22 J14 K26 AF19 N8 AF12 M28 AK9
VCCP185 VCCP186 VCCP187 VCCP188 VCCP189 VCCP190 VCCP191 VCCP192 VCCP193 VCCP194 VCCP195 VCCP196 VCCP197 VCCP198 VCCP199 VCCP200 VCCP201 VCCP202 VCCP203 VCCP204 VCCP205 VCCP206 VCCP207 VCCP208 VCCP209 VCCP210 VCCP211 VCCP212 VCCP213 VCCP214 VCCP215 VCCP216 VCCP217 VCCP218 VCCP219 VCCP220 VCCP221 VCCP222 VCCP223 VCCP224 VCCP225 VCCP226
VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125
AL23 A12 L25 J7 AE28 AE29 K5 J4 AE30 AN20 AF10 AE24 AM24 AN23 H9 H8 H13 AC6 AC7 AH6 C16 AM16 AE25 AE27 AJ28 AJ7 F19 AH13 AD7 AH16 AK17 E17 AH17 AH20 AE5 AH23 AE7 AM13 AH24 AJ30 AJ10 AF3 AK5 AJ16 AF6 AK29 AJ17 F22 AH3 AK10 AM10 F16 AJ23 F13 AG7 F10 L26 AD4 H11 L24 L23 AM23 A15 AH10 H29 B24 L3 H27 A21 AE2 AJ29 A24 AK27 AK28 B20 AM20 H26 B17 H25 H24 AA3 AA7 H23 AA6 H10
H22 H21 H20 H19 H18 AB7 H17 AJ24 AM17 AC3 H14 P28 V6 AK2 P27 P26 AM28 AJ13 W4 P25 AJ20 W7 P23 AG13 AG16 AG17 C7 Y2 L30 L29 D15 AL27 Y7 L27 AA29 N6 N7 AA28 AN13 AA27 AA26 P4 AA25 AA24 P7 E26 V30 R2 V29 V28 R5 V27 R7 E20 AN10 V25 T3 V24 V23 T6 AL7 E25 U1 R29 R28 R27 R26 R25 U7 R24 R23 P30 V3 P29 AF16 AE10 AF13 H6 A18 A2 E2 D9 C4 A6 D6
VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210
VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276
D5 A9 D3 B1 B5 B8 AJ4 AE26 AH1 E29 V7 C13 AK24 AB30 L6 L7 AB29 M1 AB28 E8 AG20 AN17 AB27 AB26 AN16 M7 AB25 AB24 AB23 N3 AA30 F4 AG10 AE13 AF30 H28 F7 AF29 AF28 G1 AF27 AF26 AF25 AN28 AN27 AF24 AF23 AG24 AF17 AN24 H3 AN7 P24 AE20 AE17 E27 T7 R30 AJ27 AB1 AM4 V26 AA23 AL28 AF20 AG23
V CCP Place these caps. inside CPU socket 10uF/SDK caps. co-layout C1206 6.3V,X5R,+/-10% C1206 BC82 6.3V,X5R,+/-10% 10uF C1206 BC83 6.3V,X5R,+/-10% 10uF C1206 BC84 6.3V,X5R,+/-10% 10uF C1206 BC85 6.3V,X5R,+/-10% 10uF C1206 BC86 6.3V,X5R,+/-10% 10uF C1206 BC87 6.3V,X5R,+/-10% 10uF C1206 BC88 6.3V,X5R,+/-10% 10uF C1206 BC89 6.3V,X5R,+/-10% 10uF C1206 BC90 6.3V,X5R,+/-10% 10uF C1206 BC91 6.3V,X5R,+/-10% 10uF 51 C1206 BC92 6.3V,X5R,+/-10% 10uF C1206 BC93 6.3V,X5R,+/-10% 10uF C1206 BC94 6.3V,X5R,+/-10% 10uF C1206 BC95 6.3V,X5R,+/-10% 10uF C1206 BC96 6.3V,X5R,+/-10% 10uF C1206 BC97 6.3V,X5R,+/-10% 10uF C1206 BC98 6.3V,X5R,+/-10% 10uF BC99 10uF
* * * * * * * * * * * * * * * * * *
D
VTT_OUT_RIGHT
note: 7/6-change termination 49.9 to RN702 47
Place BPM termination near CPU 8P 4R0603 H T DO +/-5% 7 HB P M4J 5 HB P M3J 3 HB P M5J 1 +/-1% +/-1% HB P M1J HB P M0J
R N 702
8 6 4 2
C
VTT_OUT_RIGHT
B C100
B C101 0. 1uF
*
H T RS TJ
0. 1uF
place TCK/TDI/TMS terminations near CPU within 1.5 inch
B
125mA L9 L0805 10uH 0805 +/-10% Notes: 1. Cap. should be within 600 mils of the VCCA and VSSA pins 2. VCCA route should be parallel and next to VSSA route 3. Min. 12 mils trace from the filter to the processor pins 4. The inductors should be close to the cap.
*
E C34 33uF 25V , +/-20% CE 20D50H110 ESL <= 5 nH, ESR < 0.3 ohm
*
FOXCONN PCEG
LGA775 -2
Size Doc ument Number
848M02
S heet
1
Rev A 12 of 34
Dat e:
Friday , A ugus t 27, 2004
5
4
3
2
1
U 1 3D
D
17 G CB E J0 17 G CB E J1 17 G CB E J2 17 G CB E J3 11 HA J[ 31. . 3] H A J3 H A J4 H A J5 H A J6 H A J7 H A J8 H A J9 H A J10 H A J11 H A J12 H A J13 H A J14 H A J15 H A J16 H A J17 H A J18 H A J19 H A J20 H A J21 H A J22 H A J23 H A J24 H A J25 H A J26 H A J27 H A J28 H A J29 H A J30 H A J31 11 HRE QJ[ 4. . 0] U13A HDJ[ 63. . 0] HDJ[ 63. . 0] 11 GS W ING_GMCH A GP RE F_GMCH 17 6 17 17 17 17 17 17 17 GFRA MEJ CK _66M_GMCH GDE V S ELJ G IRDYJ G TR DY J GS TOPJ GP A R G RE QJ G GNTJ
GCB E J0 GCB E J1 GCB E J2 GCB E J3 GFRA MEJ GDE V S ELJ G IRD YJ G TR DY J GS TOPJ GP A R G RE QJ G GNTJ GRCOMP
Y7 W5 AA3 U2 U6 H4 AB4 V11 AB5 W11 AB2 N6 M7 AC2 AC3 AD2 R10 R9 M4 M5
GCBE0 GCBE1 GCBE2 GCBE3 GFRAME GCLKIN GDEVSEL GIRDY GTRDY GSTOP GPAR/ADD_DETECT GREQ GGNT
GADSTBF0 GADSTBS0 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GADSTBF1 GADSTBS1 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GSBSTBF GSBSTBS GSBA0# GSBA1# GSBA2# GSBA3# GSBA4# GSBA5# GSBA6# GSBA7# DDCA_DATA DDCA_CLK RED RED# GREEN GREEN# BLUE BLUE# HSYNC VSYNC REFSET NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20
GMCH 848P
AC6 AC5 AE6 AC11 AD5 AE5 AA10 AC9 AB11 AB7 AA9 AA6 AA5 W10 AA11 W6 W9 V7 V4 V5 AA2 Y4 Y2 W2 Y5 V2 W3 U3 T2 T4 T5 R2 P2 P5 P4 M2 U11 T11 R6 P7 R3 R5 U9 U10 U5 T7 H3 F2
A D_S TB0 A D_S TB 0J GA D0 GA D1 GA D2 GA D3 GA D4 GA D5 GA D6 GA D7 GA D8 GA D9 GA D10 GA D11 GA D12 GA D13 GA D14 GA D15 A D_S TB1 A D_S TB 1J GA D16 GA D17 GA D18 GA D19 GA D20 GA D21 GA D22 GA D23 GA D24 GA D25 GA D26 GA D27 GA D28 GA D29 GA D30 GA D31 SB_STB S B _S TBJ SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
A D_S TB0 A D_S TB 0J
17 17 GA D[ 31. .0]
D
17
D26 D30 L23 E29 B32 K23 C30 C31 J25 B31 E30 B33 J24 F25 D34 C32 F28 C34 J27 G27 F29 E28 H27 K24 E32 F31 G30 J26 G26 B29 J23 L22 C29 J21 B30 D28 B7 C7 B19 C19 C17 L19 K19 L17 G9 F9 L14 D12 E12 C15 F27 D24 G24 L21 E23 K21 E25 B24 B28 B26 E27 G22 C27 B27 E8 AE14 E24 C25 F23
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HADSTB0# HADSTB1#
C
H R E QJ0 H R E QJ1 H R E QJ2 H R E QJ3 H R E QJ4 HA DS TB J0 HA DS TB J1
11 11
FSB
6 CK _166M_P _GMCH 6 CK _166M_N_GMCH 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 HDS TB P J0 H DS TB NJ0 H D B IJ0 HDS TB P J1 H DS TB NJ1 H D B IJ1 HDS TB P J2 H DS TB NJ2 H D B IJ2 HDS TB P J3 H DS TB NJ3 H D B IJ3 H A DS J H TR D Y J HDRDY J H D E FE RJ H ITMJ H I TJ H L OCK J H B R0J H B N RJ H B P RIJ HDBSYJ H R S J0 H R S J1 H R S J2 H C P URS TJ
HCLKP HCLKN HDSTBP0# HDSTBN0# DINV0# HDSTBP1# HDSTBN1# DINV1# HDSTBP2# HDSTBN2# DINV2# HDSTBP3# HDSTBN3# DINV3# ADS# HTRDY# DRDY# DEFER# HITM# HIT# HLOCK# BREQ0# BNR# BPRI# DBSY# RS0# RS1# RS2# CPURST# PWROK# HDRCOMP HDSWING HDVREF
H D B IJ0
H D B IJ1
H D B IJ2
H D B IJ3
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
1
1
B23 E22 B21 D20 B22 D22 B20 C21 E18 E20 B16 D16 B18 B17 E16 D18 G20 F17 E19 F19 J17 L18 G16 G18 F21 F15 E15 E21 J19 G14 E17 K17 J15 L16 J13 F13 F11 E13 K15 G12 G10 L15 E11 K13 J11 H10 G8 E9 B13 E14 B14 B12 B15 D14 C13 B11 D10 C11 E10 B10 C9 B9 D8 B8 L20 L13 L12
HDJ0 HDJ1 HDJ2 HDJ3 HDJ4 HDJ5 HDJ6 HDJ7 HDJ8 HDJ9 H D J10 H D J11 H D J12 H D J13 H D J14 H D J15 H D J16 H D J17 H D J18 H D J19 H D J20 H D J21 H D J22 H D J23 H D J24 H D J25 H D J26 H D J27 H D J28 H D J29 H D J30 H D J31 H D J32 H D J33 H D J34 H D J35 H D J36 H D J37 H D J38 H D J39 H D J40 H D J41 H D J42 H D J43 H D J44 H D J45 H D J46 H D J47 H D J48 H D J49 H D J50 H D J51 H D J52 H D J53 H D J54 H D J55 H D J56 H D J57 H D J58 H D J59 H D J60 H D J61 H D J62 H D J63
AGP
BC104 10nF BC103 0.1uF
BC106 10nF BC105 0.1uF
1D5V_CORE
17 GS W ING_GMCH 17 A GP RE F_GMCH 17 17 17 17 17 17 17 18 ST0 ST1 ST2 HI[ 10. . 0] R B FJ W B FJ P IP E J DB I_LO ST0 ST1 ST2 HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 H I 10 HI_S TB F HI_S TBS H I_RCOMP _MCH H I_V S W ING H I_V RE F BC112 10nF
GRCOMP GVSWING GVREF GRBF GWBF DBI_HI DBI_LO GST0 GST1 GST2 HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HISTRF HISTRS
R 156 226
A D_S TB1 A D_S TB 1J
17 17 GA D[ 31. .0] 17
1
0.8V
1
BC107 0.1uF D UMMY
W IS W ING_S P D
N3 N5 N2 AF5 AG3 AK2 AG5 AK5 AL3 AL2 AL4 AJ2 AH2 AJ3 AH5 AH4 AD4 AE3 AE2 AK7 AH7 AD11 AF7 AD7 AC10 AF8 AG7 AE9 AH9 AG6 AJ6 AJ5
2
R 157 147 BC108 10nF
HUB
2
H I_V S W ING H I_V RE F
D UMMY BC109 10nF BC110 10nF
C
0.35V
1
BC111 0.1uF D UMMY
W IV RE F_S PD
18 HI_S TB F 18 HI_S TBS
R 158 113
HI_RCOMP HI_SWING HI_VREF CI0 CI1 CI2 CI3 CI4 CI5 CI6 CI7 CI8 CI9 CI10 CISTRF CISTRS
SB_STB S B _STBJ S B A [ 7..0]
17 17 17
2
D UMMY
1D5V_CORE
R 159 1
2 52.3
W IS W ING_S P D W IV RE F_S PD 6 CK _48M_GMCH
AG2 AF2 AF4 G4 AP8 AJ8 AK4 AG10 AG9 AN35 AP34 AR1
CI_RCOMP CI_SWING CI_VREF DREFCLK EXTTS# ICH_SYNC# RSTIN# RESERVED_1 RESERVED_2 RESERVED_3 RESERVED_4 RESERVED_5
VGA
CSA
pull low the VGA signal pin according to the 848p demo sch 0703
F4 E4 H6 G5 H7 G6 G3 E2 D2 A3 A33 A35 AF13 AF23 AJ12 AN1 AP2 AR3 AR33 AR35 B2 B25 B34 C1 C23 C35 E26 M31 R25
FS B SEL0 FS B SEL1
6,12 6,12
TP 26 20, 24,30 I C H _P CIRS TJ
1D5V_CORE
R 161 2K R 162 1 B C113 12pF
PROCHOT# BSEL0 BSEL1
P R OCHOTJ
11
R 160 2K
2 51. 1 2 43. 2
H I_RCOMP _MCH
B
B
2
P W RGD_3VG H D_RCOMP H D _S W ING
2
R 163 1
GRCOMP
11, 12 HGTLRE F_MCH
R 164 2. 49K
R 165 2. 49K
GMCH 848P R 166 20
1 2 3 4 5 6 7 8
1
1
POST1 POST2 POST3 POST4 POST5 POST6 POST7 POST8
2
1
2
2
BC114 0.1uF
U13_1 V CCP Ver A to Ver B HD_SWING update GMCH_VTT replace with VCCP
18, 24,27 P W RGD_3V note: 7/6-del u17 and gate ;R169 0
P W RGD_3VG
1D5V_CORE
1
1
U13_A R 168 226
U 13_C
2
2
R 167 301 H D _S W ING
R 171 100
2
A
2
B C116 0. 1uF
Pin Name Pin # Decouping cap VTTFSB A15 0.22uF VTTFSB A21 0.47uF VCC_DDR E35 0.47uF VCC_DDR R35 0.22uF VCCA_DDR AL35 0.1uF VCCA_DDR AA35 0.1uF VCC_DDR AR31 0.1uf VCC_DDR AR21 0.22uF VCC_DDR AR15 0.1uF VCC_AGP AG1 0.1uF VCC_AGP Y1 0.1uF BaseOn Intel WW29 Update
4 3
H I_V S W ING
18
1
Clip_2P N/A
Clip_2P N/A Heat s ink grant s dale1210
R 170 147
1
BC115 0.1uF H I_V RE F 18
R e s erved
A
1
R 172 113 BC117 0.1uF
FOXCONN PCEG
Title
GMCH-1
Doc ument Number
2
Size C Dat e:
848M02
S heet
1
Rev F 13 of 34
Friday , A ugus t 27, 2004
PDF created with pdfFactory trial version www.pdffactory.com
5
2
5
4
3
2
1
U 13C U13B 16 M_MA A _A[12..0] M_MAA_A0 M_MAA_A1 M_MAA_A2 M_MAA_A3 M_MAA_A4 M_MAA_A5 M_MAA_A6 M_MAA_A7 M_MAA_A8 M_MAA_A9 M_MAA_A10 M_MAA_A11 M_MAA_A12 M_MAB_A1 M_MAB_A2 M_MAB_A3 M_MAB_A4 M_MAB_A5 M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
D
AJ34 AL33 AK29 AN31 AL30 AL26 AL28 AN25 AP26 AP24 AJ33 AN23 AN21 AL34 AM34 AP32 AP31 AM26 AB34 Y34 AC33
SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 SMAA_A12 SMAB_A1 SMAB_A2 SMAB_A3 SMAB_A4 SMAB_A5 SWE_A# SCAS_A# SRAS_A# SBA_A0 SBA_A1 SCS_A0# SCS_A1# SCS_A2# SCS_A3# SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3
SDQS_A0 SDM_A0 SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7 SDQS_A1 SDM_A1 SDQ_A8 SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQS_A2 SDM_A2 SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23 SDQS_A3 SDM_A3 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQS_A4 SDM_A4 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQS_A5 SDM_A5 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQS_A6 SDM_A6 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQS_A7 SDM_A7 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63
AN11 AP12 AP10 AP11 AM12 AN13 AM10 AL10 AL12 AP13 AP15 AP16 AP14 AM14 AL18 AP19 AL14 AN15 AP18 AM18 AP23 AM24 AP22 AM22 AL24 AN27 AP21 AL22 AP25 AP27 AM30 AP30 AP28 AP29 AP33 AM33 AM28 AN29 AM31 AN34 AF34 AF31 AH32 AG34 AF32 AD32 AH31 AG33 AE34 AD34 V34 W33 AC34 AB31 V32 V31 AD31 AB32 U34 U33 M32 M34 T34 T32 K34 K32 T31 P34 L34 L33 H31 H32 J33 H34 E33 F33 K31 J34 G34 F34
M_DQS_A0 M_DQM_A0 M_DA TA_A0 M_DA TA_A1 M_DA TA_A2 M_DA TA_A3 M_DA TA_A4 M_DA TA_A5 M_DA TA_A6 M_DA TA_A7 M_DQS_A1 M_DQM_A1 M_DA TA_A8 M_DA TA_A9 M_DA TA_A10 M_DA TA_A11 M_DA TA_A12 M_DA TA_A13 M_DA TA_A14 M_DA TA_A15 M_DQS_A2 M_DQM_A2 M_DA TA_A16 M_DA TA_A17 M_DA TA_A18 M_DA TA_A19 M_DA TA_A20 M_DA TA_A21 M_DA TA_A22 M_DA TA_A23 M_DQS_A3 M_DQM_A3 M_DA TA_A24 M_DA TA_A25 M_DA TA_A26 M_DA TA_A27 M_DA TA_A28 M_DA TA_A29 M_DA TA_A30 M_DA TA_A31 M_DQS_A4 M_DQM_A4 M_DA TA_A32 M_DA TA_A33 M_DA TA_A34 M_DA TA_A35 M_DA TA_A36 M_DA TA_A37 M_DA TA_A38 M_DA TA_A39 M_DQS_A5 M_DQM_A5 M_DA TA_A40 M_DA TA_A41 M_DA TA_A42 M_DA TA_A43 M_DA TA_A44 M_DA TA_A45 M_DA TA_A46 M_DA TA_A47 M_DQS_A6 M_DQM_A6 M_DA TA_A48 M_DA TA_A49 M_DA TA_A50 M_DA TA_A51 M_DA TA_A52 M_DA TA_A53 M_DA TA_A54 M_DA TA_A55 M_DQS_A7 M_DQM_A7 M_DA TA_A56 M_DA TA_A57 M_DA TA_A58 M_DA TA_A59 M_DA TA_A60 M_DA TA_A61 M_DA TA_A62 M_DA TA_A63
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
AG31 AJ31 AD27 AE24 AK27 AG25 AL25 AF21 AL23 AJ22 AF29 AL21 AJ20 AE27 AD26 AL29 AL27 AE23 W27 W31 W26
SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 SMAB_B1 SMAB_B2 SMAB_B3 SMAB_B4 SMAB_B5 SWE_B# SCAS_B# SRAS_B# SBA_B0 SBA_B1 SCS_B0# SCS_B1# SCS_B2# SCS_B3# SCKE_B0 SCKE_B1 SCKE_B2 SCKE_B3 SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B1 SCMDCLK_B1# SCMDCLK_B2 SCMDCLK_B2# SCMDCLK_B3 SCMDCLK_B3# SCMDCLK_B4 SCMDCLK_B4# SCMDCLK_B5 SCMDCLK_B5# SMVREF_B SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL
SDQS_B0 SDM_B0 SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7 SDQS_B1 SDM_B1 SDQ_B8 SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 SDQS_B2 SDM_B2 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQS_B3 SDM_B3 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQS_B4 SDM_B4 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQS_B5 SDM_B5 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQS_B6 SDM_B6 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55 SDQS_B7 SDM_B7 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63
AF15 AG11 AJ10 AE15 AL11 AE16 AL8 AF12 AK11 AG12 AG13 AG15 AE17 AL13 AK17 AL17 AK13 AJ14 AJ16 AJ18 AG21 AE21 AE19 AE20 AG23 AK23 AL19 AK21 AJ24 AE22 AH27 AJ28 AK25 AH26 AG27 AF27 AJ26 AJ27 AD25 AF28 AD29 AC31 AE30 AC27 AC30 Y29 AE31 AB29 AA26 AA27 U30 U31 AA30 W30 U27 T25 AA31 V29 U25 R27 L27 M29 P29 R30 K28 L30 R31 R26 P25 L32 J30 J31 K30 H29 F32 G33 N25 M25 J29 G32
D
16 M_MA B _A[5..1]
16 16 16 16
M_W E_AJ M_CA S _AJ M_RA S _AJ M_B S _A[1..0]
DDR Channel A
M_BS_A0 M_BS_A1
AE33 AH34 AA34 Y31 Y32 W34
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
Y25 AA25 U26 T29 V25 W25 AK19 AF19 AG19 AE18 AG29 AG30 AF17 AG17 N27 N26 AJ30 AH29 AK15 AL15 N31 N30
GMCH_V RE F_B S MY RCOMP S MY RCOMP VOH S MY RCOMPVOL
16 16 16 16 16
M_S CS _A0J M_S CS _A1J M_S CS _A2J M_S CS _A3J M_S CK E _A[3..0]
M_S CKE_A0 M_S CKE_A1 M_S CKE_A2 M_S CKE_A3
AL20 AN19 AM20 AP20 AK32 AK31 AP17 AN17 N33 N34 AK33 AK34 AM16 AL16 P31 P32
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
C
16 16 16 16 16 16 16 16 16 16 16 16
CK _M_133M_P _DDR0_A CK _M_133M_N_DDR0_A CK _M_133M_P _DDR1_A CK _M_133M_N_DDR1_A CK _M_133M_P _DDR2_A CK _M_133M_N_DDR2_A CK _M_133M_P _DDR3_A CK _M_133M_N_DDR3_A CK _M_133M_P _DDR4_A CK _M_133M_N_DDR4_A CK _M_133M_P _DDR5_A CK _M_133M_N_DDR5_A GMCH_V RE F_A S MXRCOMP S MXRCOMPVOH S MXRCOMPVOL
SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A1 SCMDCLK_A1# SCMDCLK_A2 SCMDCLK_A2# SCMDCLK_A3 SCMDCLK_A3# SCMDCLK_A4 SCMDCLK_A4# SCMDCLK_A5 SCMDCLK_A5# SMVREF_A SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL
DDR Channel B
C
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
E34 AK9 AN9 AL9
AP9 AA33 R34 R33
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
GMCH 848P
B
Subject: New DDR Tuning Requirement > The following are the updated DDR tuning guidelines for DQ/DQM to DQS. DQ > & DQM is matched to DQS in EACH byte lane: > From GMCH pad to DIMM-0 pin +/-25mils. > From GMCH pad to DIMM-1 pin +/-25mils. > From DIMM-1 pin to Rtt no tuning required. Form Intel WW32 update
GMCH 848P
B
M_DQS _A [ 7..0] 16 M_DQM_A [7..0] 16 M_DA TA _A [63..0] 16
2D5V _S TR
2D5V _S TR
2D5V _S TR V _S MY RCOMP V _S MY RCOMPVO V _S MY RCOMPVO 2D5V _S TR
1
1
1
1
1
1
R173 42.2 R 179 10K
R174 10K
R175 30.1K
1
R 176 150
R 177 42.2
R178 30.1K
2
2
2
2
2
2
A
2
A
S MY RCOMP S MXRCOMPVOH GMCH_V RE F_A
S MY RCOMP VOH
S MY RCOMPVOL
GMCH_V RE F_B
S MXRCOMP
S MXRCOMPVOL
1
1
1
1
1
1
R180 42.2 R 186 30.1K BC123 1uF BC124 2.2uF BC125 0.1uF
R181 30.1K BC118 1uF
R182 10K BC119 1uF
1
R 183 150 BC120 2.2uF BC121 0.1uF
R 184 42.2
R185 10K BC122 1uF
2
2
2
2
D UMMY
DUMMY
FOXCONN PCEG
Title
2
2
2
D UMMY
GMCH-2
note: 7/6-change BC118 and BC119 to Dummy
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 14 of 34
Friday , A ugus t 27, 2004
PDF created with pdfFactory trial version www.pdffactory.com
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FS B _VTT
1D5V _CORE
U13E V CCP _DCA P 1 V CCP _DCA P 2
U 13F
U13G
D
V _S MY RCOMPVO
V _S MY RCOMP V _S MY RCOMP 2D5V _S TR
A15 A21 A4 A5 A6 B5 B6 C5 C6 D5 D6 D7 E6 E7 F7 AA35 AL6 AL7 AM1 AM2 AM3 AM5 AM6 AM7 AM8 AN2 AN4 AN5 AN6 AN7 AN8 AP3 AP4 AP5 AP6 AP7 AR15 AR21 AR31 AR4 AR5 AR7 E35 R35 G1 G2 AG1 Y11 A31 B4 B3 C2 AL35 AB25 AC25 AC26
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DAC VCC_DAC VCCA_AGP VCCA_AGP VCCA_FSB VCCA_FSB VCCA_DPLL VCCA_DAC VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR
GMCH 848P
V 2P 5_DCAP5 V 2P 5_DCAP4 V _S MY RCOMPVO
V 2P 5_DCAP1
C
3D3V _S YS 1D5V _CORE V CORE _DCA P 1
V CCP _DCA P 3 V _1P 5_V CCA_FSB V CCA _DP LL V _1P 7_DAC V 2P 5_DCAP2
VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VSSA_DAC
J1 J2 J3 J4 J5 K2 K3 K4 K5 L1 L2 L3 L4 L5 Y1 D3
GND
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
J6 J7 J8 J9 K6 K7 K8 K9 L6 L7 L9 L10 L11 M8 M9 M10 M11 N9 N10 N11 P10 P11 R11 T16 T17 T18 T19 T20 U16 U17 U20 V16 V18 V20 W16 W19 W20 Y16 Y17 Y18 Y19 Y20
V CORE _DCA P 2
V _1P 5_V CCA_SM
1D5V _CORE
2D5V _S TR FS B _VTT
7/7:DEl 1psc CAP BC129 BC130 BC131
+ 1000uF
+ D UMMY
B
3D3V _S YS
D UMMY 0.1uF 1uF
D UMMY
DUMMY DUMMY
B C133 0. 1uF
AR32 AR29 AR27 AR25 AR23 AR20 AR16 AR13 AR11 AR9 AN32 AN30 AN28 AN26 AN24 AN22 AN20 AN18 AN16 AN14 AN12 AN10 AM35 AM29 AM27 AM25 AM23 AM21 AM19 AM17 AM15 AM13 AM11 AM9 AL32 AL1 AK28 AK26 AK24 AK22 AK20 AK18 AK16 AK14 AK12 AK10 AK8 AK3 AJ35 AJ32 AJ9 AJ4 AJ1 AH33 AH30 AH24 AH22 AH20 AH18 AH16 AH14 AH12 AH10 AH6 AH3 AG35 AG32 AG28 AG26 AG24 AG22 AG20 AG18 AG16 AG14 AG8 AG4 AF33 AF30 AF25 AF24 AF22 AF20 AF18 AF16 AF14 AF11 AF9 AF6 AF3 AE35 AE32 AE26 AE25 AE13 AE12
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GMCH 848P
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE11 AE10 AE4 AE1 AD33 AD30 AD28 AD10 AD9 AD8 AD6 AD3 AC35 AC32 AC4 AC1 AB33 AB30 AB28 AB27 AB26 AB10 AB9 AB8 AB6 AB3 AA32 AA4 AA1 Y35 Y33 Y30 Y28 Y27 Y26 Y10 Y9 Y8 Y6 Y3 W32 W18 W17 W4 V33 V30 V28 V27 V26 V19 V17 V10 V9 V8 V6 V3 U32 U19 U18 U4 T35 T33 T30 T28 T27 T26 T10 T9 T8 T6 T3 T1 R32 R4 R1 P33 P30 P28 P27 P26 P9 P8 P6 P3 N35 N32 N4 N1 M33 M30 M28 M27 M26 M6 M3 L35
L31 L26 L25 L24 K33 K29 K27 K25 K22 K20 K18 K16 K14 K12 K11 J35 J32 J28 J22 J20 J18 J16 J14 J12 J10 H33 H30 H26 H24 H22 H20 H18 H16 H14 H12 H9 H8 H5 H2 G35 G31 G28 F26 F24 F22 F20 F18
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F16 F14 F12 F10 F8 F5 F3 F1 E3 E1 D35 D33 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D1 C28 C26 C24 C22 C20 C18 C16 C14 C12 C10 C8 C4 A32 A29 A27 A25 A23 A20 A16 A13 A11 A9 A7
D
POWER
GND
1D5V _CORE
C3 0.22uF L10 L0603 0. 1uH BC126 10uF
C4 0.1uF EC36 EC35 1D5V _CORE BC127 L11 L0603 0. 82uH BC128
C
GMCH 848P
B
1D5V _CORE
1D5V _CORE
*
R187 0 +/-1% R0603 L12 L0603 0. 1uH
V CORE _DCA P 1 V CORE _DCA P 2 V CCP _DCA P 1 V CCP _DCA P 2 V CCP _DCA P 3 V 2P 5_DCAP2 V 2P 5_DCAP5 V 2P 5_DCAP4 V 2P 5_DCAP1
D UMMY
A
V _1P 7_DAC
V _1P 5_V CCA_FSB
V _1P 5_V CCA_SM
V CCA _DP LL
Subject: GMCH Vtt VR Clarification The GMCH VTT regulator is required to be capable of sinking 600mA of current in addition to sourcing 1.6A of current in normal operation. Sinking 600mA of current is a new requirement for the Springdale platform regardless if a Northwood or Prescott processor is installed. The reason why the GMCH VTT VR must be able to sink 600mA is because there will be times when the GMCH VTT VR's output will be set to a voltage lower than the VRD 10's output. The difference in voltage will cause current to be driven from the VRD to the GMCH VTT regulator. If the GMCH VTT VR doesn't have the capability to sink the current, damage to the GMCH can occur. In order to meet this requirement, Intel is using a P-FET in an SOT-23 footprint on the GMCH VTT voltage regulator. The back driven current will be sunk into the ground plane through this P-FET without causing damage to the Springdale GMCH. Update from Intel WW34 MOV
C5 0.47uF
C6 0.22uF
C7 0.1uF
C8 0.1uF
C9 0.1uF
C10 0.47uF
C11 0.47uF
C12 0.47uF
C13 0.47uF
A
1
1
1
1
DUMMY DUMMY EC40 100uF BC138 0.1uF EC37 100uF
2
2
2
D UMMY BC134 10nF BC135 0.1uF EC38 470uF EC39 100uF BC136 0.1uF BC137 0.1uF
2
FOXCONN PCEG
Title
GMCH-3
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 15 of 34
Friday , A ugus t 27, 2004
PDF created with pdfFactory trial version www.pdffactory.com
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VTT_DDR RN4 2 4 6 8 M_ D ATA_A0 M_ D ATA_A4 M_ D ATA_A5 M_ D ATA_A1
1 3 5 7
*
M_ D ATA_ A[63..0] 14
1 3 5 7
*
56 RN5 2 4 6 8 RN6 2 4 6 8 RN7 2 4 6 8 RN8 2 4 6 8 RN9 2 4 6 8 RN10 2 4 6 8 M_ D QS_A2 M_ D QM_A2 M_ D ATA_A18 M_ D ATA_A22 M_ D ATA_A20 M_ D ATA_A16 M_ D ATA_A17 14 M_ MAA_ A[1 2..0] 14 M_ D ATA_ A[63..0] M_ D QM_A1 M_ D ATA_A14 M_ D ATA_A15 M_ D ATA_A10 M_ D ATA_A9 M_ D ATA_A12 M_ D QS_A1 M_ D ATA_A13
D
M_ D QS_A0 M_ D QM_A0 M_ D ATA_A2 M_ D ATA_A6
14 M_ MAB_ A[5..1]
56
D
1 3 5 7
*
56
M_ D ATA_A7 M_ D ATA_A3 M_ D ATA_A8
1 3 5 7
*
56
1 3 5 7
*
56
Updated DDR Termination Resistor (Rtt) Values The recommended termination resistor (Rtt) value for DQ/DQM/DQS is changed to 56 ohms.The previous recommendation was 110 ohms. Form Intel FAE WW32
DIMM2
14 M_ MAA_ A[1 2..0] M_ MAA_A0 M_ MAA_A1 M_ MAA_A2 M_ MAA_A3 M_ MAA_A4 M_ MAA_A5 M_ MAA_A6 M_ MAA_A7 M_ MAA_A8 M_ MAA_A9 M_ MAA_A10 M_BS_A0 M_BS_A1 M_ MAA_A11 M_ MAA_A12 M_ D ATA_A0 M_ D ATA_A1 M_ D ATA_A2 M_ D ATA_A3 M_ D ATA_A4 M_ D ATA_A5 M_ D ATA_A6 M_ D ATA_A7 M_ D ATA_A8 M_ D ATA_A9 M_ D ATA_A10 M_ D ATA_A11 M_ D ATA_A12 M_ D ATA_A13 M_ D ATA_A14 M_ D ATA_A15 M_ D ATA_A16 M_ D ATA_A17 M_ D ATA_A18 M_ D ATA_A19 M_ D ATA_A20 M_ D ATA_A21 M_ D ATA_A22 M_ D ATA_A23 M_ D ATA_A24 M_ D ATA_A25 M_ D ATA_A26 M_ D ATA_A27 M_ D ATA_A28 M_ D ATA_A29 M_ D ATA_A30 M_ D ATA_A31 M_ D ATA_A32 M_ D ATA_A33 M_ D ATA_A34 M_ D ATA_A35 M_ D ATA_A36 M_ D ATA_A37 M_ D ATA_A38 M_ D ATA_A39 M_ D ATA_A40 M_ D ATA_A41 M_ D ATA_A42 M_ D ATA_A43 M_ D ATA_A44 M_ D ATA_A45 M_ D ATA_A46 M_ D ATA_A47 M_ D ATA_A48 M_ D ATA_A49 M_ D ATA_A50 M_ D ATA_A51 M_ D ATA_A52 M_ D ATA_A53 M_ D ATA_A54 M_ D ATA_A55 M_ D ATA_A56 M_ D ATA_A57 M_ D ATA_A58 M_ D ATA_A59 M_ D ATA_A60 M_ D ATA_A61 M_ D ATA_A62 M_ D ATA_A63 CN3 48 43 41 130 37 32 125 29 122 27 141 103 59 52 113 118 115 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 154 65 63 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A13 BA0 BA1 BA2 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 /RAS /CAS /WE D D R 3 33_DIMM /CS0 /CS1 CKE0 CKE1 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 VDDID CK0 /CK0 CK1 /CK1 CK2 /CK2 SCL SDA SA0 SA1 SA2 WP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VSDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDSPD NC/FETEN NC/CS2 NC/CS3 NC NC NC NC NC 157 158 21 111 5 14 25 36 56 67 78 86 47 97 107 119 129 149 159 169 177 140 82 137 138 16 17 76 75 92 91 181 182 183 90 108 120 148 70 85 168 38 7 46 54 96 62 128 104 136 30 143 77 112 156 164 172 180 15 22 1 3 145 18 58 50 100 160 139 132 152 116 11 34 26 66 93 124 74 176 42 81 89 184 167 71 163 10 9 101 102 173 M_ SCKE_A0 M_ SCKE_A1 M_ D QS_A0 M_ D QS_A1 M_ D QS_A2 M_ D QS_A3 M_ D QS_A4 M_ D QS_A5 M_ D QS_A6 M_ D QS_A7 M_ D QM_A0 M_ D QM_A1 M_ D QM_A2 M_ D QM_A3 M_ D QM_A4 M_ D QM_A5 M_ D QM_A6 M_ D QM_A7 M_ SC S_A0J M_ SC S_A1J 14 14 M_ MAA_A0 M_ MAB_A1 M_ MAB_A2 M_ MAB_A3 M_ MAB_A4 M_ MAB_A5 M_ MAA_A6 M_ MAA_A7 M_ MAA_A8 M_ MAA_A9 M_ MAA_A10 M_BS_A0 M_BS_A1 M_ MAA_A11 M_ MAA_A12 M_ D ATA_A0 M_ D ATA_A1 M_ D ATA_A2 M_ D ATA_A3 M_ D ATA_A4 M_ D ATA_A5 M_ D ATA_A6 M_ D ATA_A7 M_ D ATA_A8 M_ D ATA_A9 M_ D ATA_A10 M_ D ATA_A11 M_ D ATA_A12 M_ D ATA_A13 M_ D ATA_A14 M_ D ATA_A15 M_ D ATA_A16 M_ D ATA_A17 M_ D ATA_A18 M_ D ATA_A19 M_ D ATA_A20 M_ D ATA_A21 M_ D ATA_A22 M_ D ATA_A23 M_ D ATA_A24 M_ D ATA_A25 M_ D ATA_A26 M_ D ATA_A27 M_ D ATA_A28 M_ D ATA_A29 M_ D ATA_A30 M_ D ATA_A31 M_ D ATA_A32 M_ D ATA_A33 M_ D ATA_A34 M_ D ATA_A35 M_ D ATA_A36 M_ D ATA_A37 M_ D ATA_A38 M_ D ATA_A39 M_ D ATA_A40 M_ D ATA_A41 M_ D ATA_A42 M_ D ATA_A43 M_ D ATA_A44 M_ D ATA_A45 M_ D ATA_A46 M_ D ATA_A47 M_ D ATA_A48 M_ D ATA_A49 M_ D ATA_A50 M_ D ATA_A51 M_ D ATA_A52 M_ D ATA_A53 M_ D ATA_A54 M_ D ATA_A55 M_ D ATA_A56 M_ D ATA_A57 M_ D ATA_A58 M_ D ATA_A59 M_ D ATA_A60 M_ D ATA_A61 M_ D ATA_A62 M_ D ATA_A63 48 43 41 130 37 32 125 29 122 27 141 103 59 52 113 118 115 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 154 65 63
DIMM1
CN2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A13 BA0 BA1 BA2 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 /RAS /CAS /WE D D R 3 33_DIMM /CS0 /CS1 CKE0 CKE1 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 VDDID CK0 /CK0 CK1 /CK1 CK2 /CK2 SCL SDA SA0 SA1 SA2 WP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VSDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDSPD NC/FETEN NC/CS2 NC/CS3 NC NC NC NC NC 157 158 21 111 5 14 25 36 56 67 78 86 47 97 107 119 129 149 159 169 177 140 82 137 138 16 17 76 75 92 91 181 182 183 90 108 120 148 70 85 168 38 7 46 54 96 62 128 104 136 30 143 77 112 156 164 172 180 15 22 1 3 145 18 58 50 100 160 139 132 152 116 11 34 26 66 93 124 74 176 42 81 89 184 167 71 163 10 9 101 102 173 M_ SCKE_A2 M_ SCKE_A3 M_ D QS_A0 M_ D QS_A1 M_ D QS_A2 M_ D QS_A3 M_ D QS_A4 M_ D QS_A5 M_ D QS_A6 M_ D QS_A7 M_ D QM_A0 M_ D QM_A1 M_ D QM_A2 M_ D QM_A3 M_ D QM_A4 M_ D QM_A5 M_ D QM_A6 M_ D QM_A7 M_ SC S_A2J M_ SC S_A3J 14 14 M_ SC KE_ A[3..0] 14
M_ SC KE_ A[3..0] 14
14 M_ BS_ A[1..0]
M_ D QS_ A[7..0] 14
1 3 5 7
*
56
1 3 5 7
*
56
M_ MAA_ A[1 2..0] 14 M_ BS_ A[1..0] 14 M_ SC KE_ A[3..0] 14 M_ D QM_ A[7..0] 14 M_ D QS_ A[7..0] 14
M_ D QM_ A[7..0] 14 C K_ M_ 133M_P_DDR0_A C K_ M_ 1 33M_N_DDR0_A C K_ M_ 133M_P_DDR1_A C K_ M_ 1 33M_N_DDR1_A C K_ M_ 133M_P_DDR2_A C K_ M_ 1 33M_N_DDR2_A SMB_ C L K_MAIN 6,31 SMB_ D ATA_MAIN 6,31 14 14 14 14 14 14
SMB_ C L K_MAIN SMB_ D ATA_MAIN
C K_ M_ 133M_P_DDR3_A C K_ M_ 133M_N_DDR3_A C K_ M_ 133M_P_DDR4_A C K_ M_ 133M_N_DDR4_A C K_ M_ 133M_P_DDR5_A C K_ M_ 133M_N_DDR5_A
14 14 14 14 14 14
*
R851
C
56
M_ D ATA_A24 VTT_DDR
C
**** * **** *
1 3 5 7
*
56
RN12 2 4 6 8 RN13 2 4 6 8 RN14 2 4 6 8 RN16 2 4 6 8 RN18 2 4 6 8 M_ D ATA_A39 M_ D ATA_A35 M_ D ATA_A44 M_ D ATA_A40 M_ D QS_A4 M_ D ATA_A34 M_ D QM_A4 M_ D ATA_A38 M_ D ATA_A32 M_ D ATA_A36 M_ D ATA_A33 M_ D ATA_A37 M_ D ATA_A30 M_ D ATA_A26 M_ D ATA_A31 M_ D ATA_A27 R192 M_ D ATA_A25 M_ D ATA_A29 M_ D QM_A3 M_ D QS_A3 R188 R189 R854 R190 R191 47 56.2 56 56 47 47 47 47 47 47 M_ D QM_A5 M_ D QS_A5 M_ R AS_AJ M_ WE_AJ M_BS_A0 M_ MAA_A6 M_ MAA_A9 M_ MAA_A11 M_ MAA_A12 14 14 M_ SC S_A0J 14
1 3 5 7
*
56
1 3 5 7
*
56
R193 R194 R195 R196
2D5V_STR
2D5V_STR
1 3 5 7
*
RN15 2 4 6 8 M_ C AS_AJ M_ SC S_A2J M_ SC S_A1J M_ SC S_A3J 14 14 14 14
1 3 5 7
*
56
1 3 5 7
*
56 RN17 2 4 6 8 M_ MAA_A0 M_ MAA_A10 M_BS_A1
SMVR EF_A
SMVR EF_A
1 3 5 7
*
56
1 3 5 7
*
47 RN19 2 4 6 8 M_ MAA_A7 M_ MAA_A8
**
R852 R853
B
56 56
M_ D ATA_A45 M_ D ATA_A41
1 3 5 7 R855 R857 R858 R859 R860 R861 R862 R863
*
47 RN21 2 4 6 8 56 47 56 56 56 47 47 56 RN24 2 4 6 8 RN26 2 4 6 8 M_ MAA_A4 M_ MAB_A4 M_ MAB_A3 M_ MAA_A3 M_ SCKE_A3 M_ SCKE_A0 M_ SCKE_A2 M_ D ATA_A21 M_ SCKE_A1 M_ D ATA_A23 M_ D ATA_A11 M_ D ATA_A19 M_ MAA_A5 M_ MAB_A5 M_ D ATA_A28 M_ MAA_A2 M_ MAB_A2 M_ MAA_A1 M_ MAB_A1
B
******* *
1 3 5 7
*
56
RN22 2 4 6 8 RN23 2 4 6 8 RN25 2 4 6 8 RN27 2 4 6 8 RN28 2 4 6 8 RN29 2 4 6 8 M_ D ATA_A62 M_ D ATA_A63 M_ D ATA_A59 M_ D ATA_A58 M_ D ATA_A56 M_ D ATA_A57 M_ D QM_A7 M_ D QS_A7 2D5V_STR VTT_DDR M_ D ATA_A50 M_ D ATA_A51 M_ D ATA_A60 M_ D ATA_A61 47 M_ D QM_A6 M_ D QS_A6 M_ D ATA_A54 M_ D ATA_A55 M_ D ATA_A48 M_ D ATA_A49 M_ D ATA_A52 M_ D ATA_A53 M_ D ATA_A42 M_ D ATA_A43 M_ D ATA_A46 M_ D ATA_A47 47
2D5V_STR
2D5V_STR
1 3 5 7
*
56
1 3 5 7
*
56
1 3 5 7
* *
47
14 M_ R AS_AJ 14 M_ C AS_AJ 14 M_ WE_AJ
M_ R AS_AJ M_ C AS_AJ M_ WE_AJ
1 3 5 7
2 D 5 V_STR
1 3 5 7
*
56
*
1 3 5 7
*
56
R197 75 +/-1% R0603 SMVR EF_A
A
BC141
BC151
BC152
BC153
BC154
BC155
BC156
BC157
BC170
B C143
B C144
B C145
B C146
B C147
B C148
B C149
B C150
B C158
B C159
B C160
B C161
B C162
B C163
B C164
B C165
B C166
B C167
B C168
B C169
B C171
BC172
B C173
B C174
B C175
B C176
B C177
B C178
B C179
B C180
B C181
B C182
B C183
B C184
B C185
B C186
1 3 5 7
*
56
*
R198 75 +/-1% R0603
*
BC139 0.1uF 2 5 V, X7 R, +/-10% BC140 C0603 0.1uF
A
D U MMY
*
0 . 1uF D U MMY
*** *****
0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF
**** **
0 .1uF 0 .1uF 0 .1uF 0 .1uF 0 .1uF 0 .1uF
*
0 . 1uF
*
* *** **** ***
0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF
* ****** ** * **
0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF 0 . 1uF
*****
1 uF 1 uF 1 uF 1 uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
1 uF
FOXCONN PCEG
Title
D U MMY D U MMY
D U MMY D U MMY
D U MMY D U MMY D U MMY D U MMY
D U MMY
D U MMY D U MMY
D U MMY D U MMY D U MMY
D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY
D U MMY
D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY
DDR Channel A Termination
Size D o cu ment Number Custom D a te:
848M02
Sheet 16 of 34
1
R ev C
Fri d a y, Au g ust 27, 2004
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AGP CONN.
1D5V _CORE 12V _SYS
D
1D5V _CORE
3D3V _SB 5V _SYS 3D3V _S YS CN4
D
B9 B16 B25 B28 A9 A16 A25 A28 A34 B34 B40 B47 B52 B58 B64 A40 A52 A58 A64 B2 B3 A1 A2 B1 A4 B4 A6 B6 A7 A8 B7 B8 A12 A14 B12 A48 A50 B41 B46 B48 B50 A41 A46 A47 B5 B13 B19 B23 B31 B37 B49 B55 B61 A5 A13 A19 A23 A31 A37 A49 A55 A61
1.5 AGP 8X
VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 5.0V 5.0V 12V TYPEDET# OVRCNT# USBUSB+ INTA# INTB# RST# GNT# CLK REQ# PIPE#/DBI_HI WBF# RBF# PME# PAR IRDY# DEVSEL# PERR# SERR# FRAME# TRDY# STOP# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC1 NC2 NC3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 SB_STB SB_STB# AD_STB0# AD_STB1# AD_STB0 AD_STB1 C/BE0# C/BE1# C/BE2# C/BE3# ST0 ST1 ST2 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 DBI_LO RESERVED 3.3V_AUX VREFCG GC_DET MB_DET RESERVED RESERVED RESERVED
GA D[ 31. .0]
13
R 199
1
6.8K
C
20, 28 20, 28 19, 20, 21, 28,29 13 6 13 13 13 13 20, 21, 28,29 13 13 13
I N TA J I N TB J I CH_P _P CIRE S TJ G GNTJ CK _66M_AGP G RE QJ P IP E J W B FJ R B FJ PMEJ GP A R G IRDYJ GDE V S ELJ
13 GFRA MEJ 13 G TR DY J 13 GS TOPJ
I N TA J I N TB J I CH_P _P CIRE S TJ G GNTJ CK _66M_AGP G RE QJ P IP E J W B FJ R B FJ PMEJ GP A R G IRD YJ GDE V S ELJ G P E RRJ G S E RRJ GFRA MEJ G TR DY J GS TOPJ
A65 B65 A63 B63 A62 B62 A60 B60 B57 A56 B56 A54 B54 A53 B53 A51 A39 B38 A38 B36 A36 B35 A35 B33 A30 B30 A29 B29 A27 B27 A26 B26 B18 A18 A59 A32 B59 B32 A57 B51 B39 A33 B10 A10 B11 B15 A15 B17 A17 B20 A20 B21 A21 B14 B22 B24 B66 A3 A11 A22 A24 A66
GA D0 GA D1 GA D2 GA D3 GA D4 GA D5 GA D6 GA D7 GA D8 GA D9 GA D10 GA D11 GA D12 GA D13 GA D14 GA D15 GA D16 GA D17 GA D18 GA D19 GA D20 GA D21 GA D22 GA D23 GA D24 GA D25 GA D26 GA D27 GA D28 GA D29 GA D30 GA D31 SB_STB S B _S TBJ A D_S TB 0J A D_S TB 1J A D_S TB0 A D_S TB1 GCB E J0 GCB E J1 GCB E J2 GCB E J3
2
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 DB I_LO
SB_STB S B _S TBJ A D_S TB 0J A D_S TB 1J A D_S TB0 A D_S TB1 GCB E J0 GCB E J1 GCB E J2 GCB E J3 ST0 ST1 ST2
13 13 13 13 13 13 13 13 13 13 13 13 13
C
S B A [ 7..0] D B I_LO
13 13
A GP RE F_GMCH G C_DE TJ
B
1 2 3
B
R e s erved
DECUBLE CAP. AGPREF & AGPSWING CIRCUIT
5V _S YS 3D3V _S YS 12V _SYS 1D5V _CORE 3D3V _SB 1D5V _CORE
1
1D5V _CORE 12V _SYS 1D5V _CORE 7/6 Update from PBSS4320T to 3904 add R702 2.2K R 200 60. 4 BC187 R e s erved 0.1uF BC188 R e s erved 0.1uF BC189 0.1uF BC190 0.1uF BC191 R e s erved 0.1uF B C192 0. 1uF e s erved R
1
2
R e s ervedR e s erved
R202 8.2K
R 203 8.2K
R 201 8.2K
GS W ING_GMCH 13
1
1
1
R 204 39. 2
2 2 2
G P E RRJ R 205 39. 2
C
R 702
*
C
E
R 207 100
E
Q34 MMB T3904
+/-1%
1
1
G C_DE TJ
B
2.2K
E
C
R 0603
B
Q35 MMB T3904
*
B
Q33 MMB T3904
2
A
A
+/-1% R0603
A GP RE F_GMCH 13
R 206 100
2
2
FOXCONN PCEG
Title
AGP Connector
Size C Dat e: Doc ument Number
848M02
S heet
1
Rev F 17 of 34
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U15B 13 HI[ 10. . 0] U 1 5D HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 H I 10
D
R208 1 13 HI_S TB F 13 HI_S TBS
2 61. 9
HI_S TB F HI_S TBS H I _ RCOMP _ICH H I _ V S W ING_ICH H I _ V RE F_ICH
H20 H21 J20 H23 M23 M21 N21 M20 L22 J22 K21 G22 K23 J24 N24 L20 L24 N22 C10 C9 C11 D9 E9 B12 D10 E10 AA1 B11 B10 A12 B9
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HI11 HI_STBF HI_STBS HIRCOMP HI_VSWING HIREF CLK66 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_RSTSYNC LAN_CLK LAN_RST# EE_DIN EE_CS EE_SHCLK EE_DOUT AC_SYNC AC_RST# AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_BIT_CLK
ICH5
USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBP4P USBP4N USBP5P USBP5N USBP6P USBP6N USBP7P USBP7N OC0# OC1# OC2# OC3# OC4#/GPI9 OC5#/GPI10 OC6#/GPI14 OC7#/GPI15 USBRBIAS USBRBIAS# CLK48
C23 D23 A22 B22 C21 D21 A20 B20 C19 D19 A18 B18 C17 D17 A16 B16 C15 D15 D14 C14 B14 A14 D13 C13 A24 B24 F24
US B P0P US B P 0N US B P1P US B P 1N US B P2P US B P 2N US B P3P US B P 3N US B P4P US B P 4N US B P5P US B P 5N US B P6P US B P 6N US B P7P US B P 7N R N30
US B P0P US B P 0N US B P1P US B P 1N US B P2P US B P 2N US B P3P US B P 3N US B P4P US B P 4N US B P5P US B P 5N US B P6P US B P 6N US B P7P US B P 7N
25 25 25 25 23 23 23 23 25 25 25 25 25 25 25 25
30 11 11 11 11 11, 24 11 11 30 30 11 11 CN5 SATA
A 20GATE A 20MJ C P US LP J F E R RJ I G N NE J I N I TJ I N TR NM I K B RS TJ S E RIRQ S MIJ S TP CLK J
T22 V23 P22 U24 R21 R23 U23 R22 P23 F23 V24 T24 P20 R24 AA8 AB8 AD7 AC7 AA10 AB10 AD9 AC9 Y11 Y9 AC5 AD5
R N31
A20GATE A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI RCIN# SERIRQ SMI# STPCLK# DPRSLPVR DPSLP# SATA0TXP SATA0TXN SATA0RXN SATA0RXP SATA1TXP SATA1TXN SATA1RXN SATA1RXP
13 H I_V S W ING 13 H I_V RE F 6 CK _66M_ICH
8
1 3 5 7
*
0 +/-5% 8P 4R0603
2 4 6 8
US B _OC3 US B _OC
25 23 CN6 SATA
9
1 2 3 4 5 6 7 1 2 3 4 5 6 7
6 CK _100M_P _ICH 6 C K _100M_N_ICH 24, 30 L_A D0 24, 30 L_A D1 24, 30 L_A D2 24, 30 L_A D3
TP32 S A TA _TXP0 S A TA _TXN0 S A TA _RXN0 S A TA _RXP0
AGPBUSY#/GPI6 GPI7 GPI8 SMBALERT#/GPI1