Text preview for : 845EIClient_guide.pdf part of some brands - algumas marcas some schematic motherboards notebooks downloaded from www.freeservicemanuals.net. alguns esquemas placa-mae e notebook baixados de www.freeservicemanuals.net.
Back to : Notebook_MB schematic.par | Home
Intel® 845E Interactive Client Reference Design
User's Guide
October 2002
Order Number: 273782-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 845E chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © Intel Corporation, 2002
2
Intel® 845E Reference Design User's Guide
Contents
Contents
1 Term Definitions .............................................................................................................................. 5 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 Abbreviations ........................................................................................................................ 5 Text Conventions .................................................................................................................. 7 About this Manual ................................................................................................................. 9 Manual Organization............................................................................................................. 9 Reference Design Features................................................................................................10 Technical Support...............................................................................................................12 Product Literature ...............................................................................................................13 Related Documents ............................................................................................................14 Reference Design Kit Contents ..........................................................................................15 Before You Begin................................................................................................................15 Initial Setup .........................................................................................................................15 Configuring the System Board............................................................................................16 Headless Operation ............................................................................................................18 System Overview................................................................................................................19 Block Diagram ....................................................................................................................20 Hardware Reference...........................................................................................................20 4.3.1 System Board ........................................................................................................20 4.3.2 Processor...............................................................................................................21 4.3.2.1 Intel® Pentium® 4 Processor-M .............................................................21 4.3.2.2 Intel® Pentium® 4 Processor with 512 KB L2 Cache on 0.13 Micron Process .........................................................................22 4.3.3 Chipset................................................................................................................... 23 4.3.4 Memory Controller Hub..........................................................................................24 4.3.4.1 System Memory .....................................................................................24 4.3.4.2 Accelerated Graphics Port Interface ......................................................24 4.3.5 I/O Controller Hub ..................................................................................................25 4.3.5.1 Hub Interface to MCH ............................................................................25 4.3.5.2 Dual-Channel Ultra ATA-100 Bus Master IDE Controller ......................25 4.3.5.3 Six USB 2.0/1.1 Ports ............................................................................25 4.3.5.4 Advanced Configuration Power Interface ..............................................25 4.3.5.5 System Management Bus 2.0 Controller ...............................................25 4.3.5.6 Firmware Hub ........................................................................................25 4.3.5.7 Super IO.................................................................................................26 4.3.5.8 AC¶97 2.3 ...............................................................................................26 4.3.5.9 PCI 2.2 Interface ....................................................................................26 4.3.6 Clocking .................................................................................................................26 4.3.7 Real-Time Clock ....................................................................................................26 4.3.8 SMI Cougar3DR16* AGP Graphics .......................................................................26 Thermal Solution.................................................................................................................27 Power Supply......................................................................................................................27
Introduction...................................................................................................................................... 9
Getting Started ..............................................................................................................................15
Technical Reference......................................................................................................................19
4.4 4.5
Intel® 845E Reference Design User's Guide
3
Contents
4.6 A
Port 80h Progress and Error Codes ................................................................................... 28
Schematics .................................................................................................................................... 33
Figures
1 2 Connector Locations................................................................................................................... 17 System Block Diagram ............................................................................................................... 20
Tables
1 2 3 4 Intel Literature Centers ............................................................................................................... 13 Related Documents .................................................................................................................... 14 Jumper Settings.......................................................................................................................... 16 Port 80h Progress and Error Codes ........................................................................................... 28
Revision History
Date September 2002 Revision 001 Description First Release of Document
4
Intel® 845E Reference Design User's Guide
Term Definitions
Term Definitions
1.1 Abbreviations
AC'97 ACPI AGP AGTL ASF ATA ATM ATX BGA BIOS BOM CD CM CMOS CPU DDR DIMM DVI-I ECC EHCI EmbATX EMS FC FWH GTL I/O, IO ICH IDE Audio Codec 97 Advanced Configuration Power Interface Accelerated Graphics Port Assisted GTL Alerting Standard Format Advanced Technology Attachment Automatic Teller Machine a motherboard form factor and standard for power supplies (not an acronym) Ball-Grid Array Basic Input/Output System Battery-Optimized Mode Compact Disk Contract Manufacturer Complementary Metal Oxide Semiconductor Central Processing Unit Double Data Rate Dual Inline Memory Module Digital Video Interface (łI´ refers to digital and analog support) Error Correcting Code, Error Checking and Correcting Enhanced Host Controller Interface EmbeddedATX motherboard interface specification Electronic Manufacturing Service Flip-Chip Firmware Hub Gunning Transceiver Logic Input/Output I/O Controller Hub Integrated Device/Drive Electronics
1
Intel® 845E Reference Design User's Guide
5
Term Definitions
IR ITP JEDEC KB/M L2 LAN LED LPC LVDS MCH MIDI mPGA MPM ODM OEM PCI PCM PGA PIO POS POST PSB RAM ROM RTC SDRAM SIMD SIO SSE SST UHCI USB VRM
Infrared In-Target Probe Joint Electron Device Engineering Council (electronics trade association) Keyboard/Mouse Level 2 Local Area Network Light-Emitting Diode Low Pin Count Low-Voltage Differential Signaling Memory Controller Hub Musical Instrument Digital Interface Micro-PGA Maximum Performance Mode Original Design Manufacturer Original Equipment Manufacturer Peripheral Component Interconnect Pulse Code Modulation Pin-Grid Array Programmed Input/Output Point-of-Sale Power-On Self-Test Processor System Bus Random Access Memory Read-Only Memory Real-Time Clock Synchronous Dynamic RAM Single Instruction Multiple Data Super I/O Streaming SIMD Extensions Source-Synchronous Transfer Universal Host Controller Interface Universal Serial Bus Voltage Regulator Module
6
Intel® 845E Reference Design User's Guide
Term Definitions
ZIF
Zero Insertion Force
1.2
Text Conventions
# Variables Instructions The pound symbol (#) appended to a signal name indicates that the signal is active low. Variables are shown in italics. Variables must be replaced with correct values. Instruction mnemonics are shown in uppercase. When you are programming, instructions are not case-sensitive. You may use either uppercase or lowercase. Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H or h. A zero prefix is added to numbers that begin with A through F. For example, FF is shown as 0FFH. Decimal and binary numbers are represented by their customary notations. That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity. Signal names are shown in uppercase. When several signals share a common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0). Units of measure are listed below.
Amps (Amperes) Gigabytes Gigahertz
Numbers
Signal Names
Units of Measure A GB, Gbyte GHz Hz KB, Kbytes k, mA MB, Mbyte MHz ms mW ns s, sec
Hertz
Kilobytes (1 KB = 1024 bytes; also kB, kbytes) Kilo ohms Milliamps Megabytes Megahertz Milliseconds Milliwatts Nanoseconds
Seconds Ohms
Intel® 845E Reference Design User's Guide
7
Term Definitions
pF W V
µA µF µs µW
Picofarads Watts Volts Microamps Microfarads Microseconds Microwatts
8
Intel® 845E Reference Design User's Guide
Introduction
2.1 About this Manual
2
This document describes the features of the Intel® 845E Interactive Client Reference Design and guides the reader in use of the reference board. Read this document in its entirety before applying power to the motherboard. The Intel 845E Interactive Client Reference Design will help OEMs and CMs quickly bring products to market by presenting a standard space platform. This platform allows for flexible development of interactive client applications such as POS devices, ATMs, kiosks, gaming terminals, and other display-centric embedded clients. The utilization of the EmbATX specification ensures a small profile for the Intel 845E Interactive Client Reference Design. With the capability of servicing a large variety of applications, the EmbATX specification allows OEMs, ODMs, EMSs and CMs to reuse design elements and reduce cost while incorporating innovative features of a highly competitive market for hardware building blocks. At the same time, EmbATX allows OEMs to standardize a consistent form factor for enclosures, display housings, and external chassis, which will reduce the cost to develop new systems and upgrade systems. More information on the Intel® 845E Chipset is available at the following website: http://developer.intel.com/design/intarch/platforms/iaclient/refconfig/845e/845e.htm
2.2
Manual Organization
Chapter 2, "Introduction" introduces the features of the Intel 845E Interactive Client Reference Design and provides information on related literature and customer support. Chapter 3, "Getting Started" provides instructions for configuring the system board and provides information about connectors on the board. Chapter 4, "Technical Reference" describes the component features and specifications of the reference design. It also provides information about the chipset, cache memory and main memory system. This chapter includes reference information for connectors on the board. Appendix A, "Schematics," includes the schematics for the system included in the kit.
Intel® 845E Reference Design User's Guide
9
Introduction
2.3
Reference Design Features
The major features of this reference design include:
· Intel® Pentium® 4 Processor
-- Scalable performance supporting either the Intel® Pentium® 4 processor with 512 KB L2 cache on 0.13 micron process (desktop) or the Intel® Pentium® 4 Processor-M. -- mPGA478B socket for mFC-PGA and mFC-PGA2 packages
· 82845E Memory Controller Hub
-- 593-ball FCBGA package -- 400 and 533 MHz processor system bus support -- 200/266 MHz DDR SDRAM -- Up to 2GByte with 2 DIMM slots -- AGP 4x graphics (1.5 V)
· Advanced Graphics Controller
-- Silicon Motion* Cougar3DR16* Graphics Chip · LVDS for integrated flat-panel support · S-Video for TV output · Dual independent display (two digital or one digital/one analog) -- DVI-I for digital and analog monitor support
· Intel® 82801DB I/O Controller Hub 4 (ICH4)
-- 421-ball mBGA package -- 32-bit/33 MHz PCI · Mini-PCI slot for 802.11 wireless LAN · One PCI riser slot for low-profile PCI expansion · Supports either the Intel® 82551QM Fast Ethernet Card/Bus Controller with ASF or the Intel® 82540EM Gigabit Ethernet Controller with ASF -- Dual-channel ATA-100 for up to four devices -- SMBus 2.0 -- Socketable FWH (Flash BIOS) -- Six USB 2.0/1.1 ports · Two onboard headers · Four external connectors, two of which are PoweredUSB* ports -- Integrated AC¶97 support · Amplified audio output · Mini-jack audio connectors for line in, mic in, headphone out -- Four 16550C-compatible serial ports
· Form Factor: EmbATX
-- 9.6´ x 9.6´ x 2´ overall dimensions
10
Intel® 845E Reference Design User's Guide
Introduction
Intel® 845E Reference Design User's Guide
11
Introduction
2.4
Technical Support
The Intel Developer website (http://developer.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it. For a commercially available product based on this reference design, contact Kontron* at: http://www.kontron.com/. The BIOS is created and supported by Phoenix Technologies*. For more information, visit: http://www.phoenix.com. Support for the SMI Cougar3DR16* AGP Graphics chip is provided by Silicon Motion, Inc. For more information, visit: http://www.siliconmotion.com/. Technical questions for this reference design can be sent to Intel at [email protected].
12
Intel® 845E Reference Design User's Guide
Introduction
2.5
Table 1.
Product Literature
Product literature can be ordered from the following Intel literature centers: Intel Literature Centers
1-800-548-4725 708-296-9333 44(0)1793-431155 44(0)1793-421333 44(0)1793-421777 81(0)120-47-88-32 U.S. and Canada U.S. (from overseas) Europe (U.K.) Germany France Japan (fax only)
Intel® 845E Reference Design User's Guide
13
Introduction
2.6
Table 2.
Related Documents
Related Documents
Document Title Intel® Intel® Pentium® Pentium® 4 Processor with 512 KB L2 Cache on 0.13 Micron Process Datasheet 4 Processor in the 478-Pin Package Thermal Design Guidelines Order Number 298643 249889 290728 250686 290742 290744 298653 298651 290658 251319 273704 273729 298652 249205 Intel Confidential document Register to download at developer.intel.com
Mechanical Enabling for the Intel® Pentium® 4 Processor in the 478-pin Package Intel® Intel® Intel® Pentium® 4 Processor-M Datasheet
82845 Memory Controller Hub (MCH) for DDR Datasheet 82801DB I/O Controller Hub 4 (ICH4) Datasheet
Intel® 845E Chipset: Intel® 82845 Thermal and Mechanical Design Guidelines Intel® Intel® Intel® 82801DB I/O Controller Hub (ICH4): Thermal and Mechanical Design Guidelines 82802AB/AC Firmware Hub (FWH) Datasheet Pentium®
4 Processor and Intel® 845E Chipset Platform Design Guide Addendum for Embedded Applications Intel® Pentium® 4 Processor for Embedded Applications Thermal Design Guide Intel® Pentium® 4 Processor-M for Applied Computing Thermal Design Guide Intel® Pentium® 4 Processor in 478-Pin Package and Intel® 845E Chipset Platform for DDR Design Guide VRM 9.0 DC-DC Converter Design Guidelines IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide
EmbeddedATX Motherboard Interface Specification
14
Intel® 845E Reference Design User's Guide
Getting Started
3.1 Reference Design Kit Contents
The following components are included in the kit: · Intel® 845E Interactive Client Reference Design system board
3
· · · · · ·
1.7 GHz Intel® Pentium® 4 Processor-M VRM for Intel Pentium 4 Processor-M Active thermal solution for Intel Pentium 4 Processor-M BIOS from Phoenix Technologies* One 256 MByte non-ECC DIMM Collateral CD with instructions describing how to download the electronic design file
3.2
Before You Begin
To prevent damage to the system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from static electricity discharge:
· When handling the board, use a grounded wrist strap designed for static discharge elimination. · Touch a grounded metal object before removing the board from the antistatic bag. · Handle the board by its edges only; do not touch its components, peripheral chips, memory
modules or gold contacts.
· When handling processor chips or memory modules, avoid touching their pins or gold edge
fingers. Put the system board and peripherals back into the antistatic bag when they are not in use or not installed in a chassis. Warning: This guide is for technically qualified personnel who have experience installing and configuring system boards. Disconnect the system board power supply from its power source before connecting or disconnecting cables or installing or removing any system board components. Failure to do this can result in personal injury and/or equipment damage. Avoid short-circuiting the lithium battery; this can cause it to overheat and cause burns if touched. Although the Intel® Pentium® 4 Processor-M has built-in thermal management features, do not operate the processor without a thermal solution; otherwise damage may occur.
Warning: Warning:
3.3
Initial Setup
To set up the system for operation: 1. If not already installed, install the system memory DIMM(s) into the DIMM socket(s).
Intel® 845E Reference Design User's Guide
15
Getting Started
2. If not already installed, attach the active thermal solution for the processor following the instructions in the Thermal Design Guide, ensuring it is plugged into its power supply at the CPU fan connector (see CN33 in Figure 1 on page 17). 3. Connect an ATX12V power supply to the board and to any desired drives to be powered. Make sure to connect both the standard ATX power connector and the additional 4-pin 12 V connector to the board. 4. Install desired peripheral devices such as a hard drive, CD-ROM, floppy drive, keyboard, mouse, and monitor. 5. Turn on the external power supply. The reference board will power up automatically because the system power signal is tied high. If the system does not power up, short the reset and ground pins (pins 5 and 7) on the power/LED header (connector CN34, see Appendix A, "Schematics"). Note: Ensure that the power supply is configured for the proper AC voltage based on the geographic location where this board is used.
3.4
Configuring the System Board
Configuring the jumpers is not required for standard operation. The table below shows the jumper settings. More information can be found in Appendix A, "Schematics". The jumper locations as well as the major components and connectors on the board are shown in Figure 1 on page 17.
Table 3.
Jumper Settings
Jumper JP1 JP2 JP3 JP4 Setting 1-2 normal (default) 2-3 clear CMOS not populated not populated and functionality not used photodiode header
Changing the BIOS default settings is not recommended. For custom BIOS configuration, enter the BIOS setup utility as the system boots. This can be accomplished in standard (with keyboard and monitor attached to the system) or headless operation (without keyboard and monitor attached). For more details on running headless, see "Headless Operation" on page 18.
16
Intel® 845E Reference Design User's Guide
Getting Started
Figure 1. Connector Locations
(CN12) Mic/line-in/ headphone connector (CN29) Stacked RJ45LAN0/USB (CN40) (CN30,31) S-Video connector [0,1] PoweredUSB* [2,3] port
(CN16) RJ45 connector
(CN18) DVI-I connector
(CN8) COM1, COM2 serial ports and LPT parallel port
(CN20) LVDS flat-panel header
(CN14) Analog audio planar header (CN13) CDROM audio plug (CN33) CPU fan connector (CN37) VRM socket
(CN23) Single-slot PCI riser connector
(U22) Cougar3DR16* Graphics Controller
(JP4) Photodiode header
(CN36) ATX12V power supply connector (U1) CPU socket (CN1) ITP header (CN19) Backlight controller header (U2) 845E MCH
(CN41) MiniPCI analog phone line header (CN24) MiniPCI connector
(CN25) ditional PCI ru-holes for 3 slot risers
(U4) ICH4
(CN2) DIMM 0 socket (CN32) USB header [4,5] (CN26/28) Pri/Sec IDE (CN3) DIMM 1 socket
(CN4) CPU boot speed transition logic header
(CN7) FIR port
(U36) FWH socket
(CN35) Chassis fan connector (BUZ1) Speaker
(CN11) PS/2 KB/mouse header
(CN5) IR port
(BAT1) Battery (JP1) CMOS clear
(CN34) Power/ LED header
(CN9) COM3 Serial header
(CN10) COM4 Serial header
(U9,U8) Port 80 LED display
(CN38) ATX power supply connector
(CN6) Game/ MIDI port
(CN27) Standard floppy drive connector
*Other names and brands may be claimed as the property of others.
Intel® 845E Reference Design User's Guide
17
Getting Started
3.5
Headless Operation
This platform was designed with the capability of running headless: without a monitor, keyboard, and mouse. If the system is headless, console redirection can be implemented by changing an option in the BIOS in order to monitor the board's status and change its settings. Note: If the board is built without the graphics chip, then the BIOS default shall be set for console redirection. To connect through the serial port: 1. Connect a host computer to the reference design board with a cable between their respective serial ports. 2. Run a remote access program such as HyperTerminal*. 3. Boot the reference design board.
18
Intel® 845E Reference Design User's Guide
Technical Reference
4.1 System Overview
4
Utilizing the Intel® Pentium® 4 processor, this reference design employs best-in-class multimedia, advanced thermal management, an Intel® architecture development environment and scalable performance. Best of all, one design is able to provide multiple options for processor and usage. The features of this design are outlined in Section 2.3, "Reference Design Features" on page 10. Developers are able to design products that meet customer needs by utilizing next-generation POS/ kiosk features:
· · · ·
Wireless connectivity Dual independent display Advanced remote manageability EmbATX form factor for low-profile and small footprints
Utilization of the design provides a variety of price/performance capabilities and takes advantage of reduced investment in enclosure design. Together these attributes provide reduced time-tomarket and lower total cost for development.
Intel® 845E Reference Design User's Guide
19
Technical Reference
4.2
Block Diagram
Figure 2. System Block Diagram
Processor
400/533 MT/s PSB
DVI-I S-Video LVDS
Cougar3DR16*
4x AGP
845E MCH
DDR200 or DDR 266
HI 1.1
6 USB 2.0/1.1 (2 PoweredUSB*) 2 x ATA-100 ICH4
SMBus 2.0
LM87 82551 LAN miniPCI 802.11
32-bit/33 MHz PCI
AC'97 FWH
SIO PCI slot (riser)
*Other names and brands may be claimed as the property of others.
4.3
Hardware Reference
This section describes the devices and connectors on the board.
4.3.1
System Board
· The system board is an 8-layer PCB composed of industry-standard FR4 material. · The system board is 9.6´ x 9.6´, in compliance with the EmbATX specification. · The system board includes an mBGA478B socket for mFC-PGA and mFC-PGA2 packages,
supporting both the Intel® Pentium® 4 Processor with 512 KB L2 Cache on 0.13 Micron Process and the Intel® Pentium® 4 Processor-M.
20
Intel® 845E Reference Design User's Guide
Technical Reference
· The VRM supplied in this kit supports only the Intel Pentium 4 Processor-M. More
information about voltage regulations for mobile processors can be found in the IMVP-III Specification. A different VRM must be used with a desktop Intel Pentium 4 Processor which requires compliance to the VRM 9.0 specification. More information can be found in the Intel® Pentium® 4 Processor and Intel® 845E Chipset Platform Design Guide Addendum for Embedded Applications as well as in the VRM 9.0 DC-DC Converter Design Guide. For more information on obtaining these documents, see Table 2, "Related Documents" on page 14.
· 12 V active thermal solutions are required, and one supporting the Intel Pentium 4 Processor M is included in the kit.
· An ATX12V-compliant power supply is required to provide power to this system board.
4.3.2
Processor
The Intel® 845E Interactive Client Reference Design was designed with platform scalability in mind. To that end, this platform supports both the Intel Pentium Processor and the Intel Pentium 4 Processor-M, for the 478-pin socket. The Mobile Intel® Pentium® 4 Processor-M features enhanced Intel SpeedStep® technology, which allows the processor to switch between two core frequencies. The mobile processor operates in two modes, the high frequency MPM or the low frequency BOM. By default, the mobile processor will boot to the lower frequency. Certain mobile chipsets, such as the mobile Intel® 845MZ or 845MP chipset, can control the transition between the two modes; however, the Intel® 845E chipset is not capable of controlling the transition. Therefore, when designing a system based on the Intel 845E chipset, additional logic is required to transition the mobile processor from BOM to MPM. The reference design kit comes equipped with a Intel Pentium 4 Processor-M operating at 1.7GHz in MPM. Accordingly, the VRM included in the kit is designed for the mobile processor. A different VRM must be used when using a desktop processor. More information about this implementation can be found in the Intel® Pentium® 4 Processor and Intel® 845E Chipset Platform Design Guide Addendum for Embedded Applications (see Table 2, "Related Documents" on page 14). The following sections describe the features of the different processors supported on this platform. In addition, future processors may be drop-in compatible with this design. Please contact Intel Support for further information. Contact information is listed in Section 2.4, "Technical Support" on page 12. This system only supports uni-processor configurations.
4.3.2.1
Intel® Pentium® 4 Processor-M
The Intel Pentium 4 Processor-M is the first Intel mobile processor with the Intel® NetBurstTM microarchitecture. The processor utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (MicroFCPGA) package, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The processor maintains full compatibility with IA-32 software. The Intel® NetBurstTM microarchitecture features include hyper-pipelined technology, a rapid execution engine, a 400-MHz system bus, and an execution trace cache. The hyper-pipelined technology doubles the pipeline depth in the Intel Pentium 4 Processor-M allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute
Intel® 845E Reference Design User's Guide
21
Technical Reference
in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main execution path, thereby increasing performance. Additional features within the Intel NetBurst microarchitecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multimedia unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2 (L2) cache. A new floating point and multimedia unit has been implemented which provides superior performance for multimedia and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep have been incorporated. The Streaming SIMD Extensions 2 (SSE2) enable breakthrough levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The processor's 400-MHz Intel NetBurst Micro-architecture system bus utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 processor. This system bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst Microarchitecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/sec. Note: Intel Speedstep technology is not supported by the Embedded Intel Architecture Division. The processor default is to initialize to BOM, but an additional logic chip in this design transitions the CPU to MPM while the system boots, and it stays at this speed until reset, and the same transition occurs. The processor system bus uses a variant of GTL+ signaling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology. The Intel Pentium 4 Processor-M included in this kit runs at a core frequency of 1.7 GHz in Maximum Performance Mode.
4.3.2.2
Intel® Pentium® 4 Processor with 512 KB L2 Cache on 0.13 Micron Process
The Intel Pentium 4 processor with 512 KB L2 cache on 0.13 micron process is a follow-on to the Pentium 4 processor in the 478-pin package with Intel Netburst microarchitecture. The Pentium 4 processor with 512 KB L2 cache on 0.13 micron process utilizes Flip-Chip Pin Grid Array (FCPGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Pentium 4 processor with 512 KB L2 cache on 0.13 micron process, like its predecessor, the Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.
22
Intel® 845E Reference Design User's Guide
Technical Reference
The Intel NetBurst Micro-architecture features include hyper-pipelined technology, a rapid execution engine, a 400-MHz or a 533-MHz system bus, and an execution trace cache. The hyperpipelined technology doubles the pipeline depth in the Intel Pentium 4 processor with 512 KB L2 cache on 0.13 micron process, allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz or 533-MHz system bus is a quad-pumped bus running off a 100-MHz or 133-MHz system clock making 3.2 GB/sec and 4.3 GB/sec data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main execution path, thereby increasing performance. Additional features within the Intel NetBurst Micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multimedia unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2 (L2) cache. A new floating point and multimedia unit has been implemented which provides superior performance for multimedia and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep have been retained. The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. Intel Pentium 4 processor with 512 KB L2 cache on 0.13 micron process Intel NetBurst microarchitecture system bus utilizes a split-transaction, deferred reply protocol like the Pentium 4 processor in the 478-pin package. This system bus is not compatible with the P6 processor family bus. The Intel NetBurst microarchitecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4.3 GB/sec. The processor system bus uses a variant of GTL+ signaling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology.
4.3.3
Chipset
The Intel 845E Interactive Client Reference Design utilizes the Intel 845E chipset. The Intel 845E chipset consists of two components: the Intel® 82845E Memory Controller Hub (845E MCH) and the Intel® 82801DB I/O Controller Hub 4 (ICH4). These components are interconnected via an Intel proprietary interface called Hub Interface. Hub Interface 1.1 is designed into the 845E chipset to provide efficient communication between these two components. This chipset supports platform hardware features including AGP 4x, DDR SDRAM system memory, Ultra ATA/100, Low Pin Count (LPC) interface, integrated LAN, and Universal Serial Bus (USB). The platform is also ACPI compliant and supports Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-off power management states. Through the use of an appropriate LAN controller, the platform supports ASF for remote administration and troubleshooting.
Intel® 845E Reference Design User's Guide
23
Technical Reference
4.3.4
Memory Controller Hub
The 845E MCH component provides the processor interface, system memory interface, AGP interface, and hub interface to ICH4 in an 845E chipset platform. The MCH is in a 593-ball FCBGA package and has the following functionality:
· Supports a single processor with a processor system bus speed of either 400 MHz or 533 MHz. · Supports up to 2 GB of DDR 200/266 SDRAM (in two unbuffered DIMMs), with or without
ECC. More information is in the "System Memory" section below.
· AGTL+ bus driver technology with integrated termination resistors supporting 32-bit host
addressing.
· 1.5 V AGP interface supporting 1x/2x/4x devices. More information is in the "Accelerated
Graphics Port Interface" section below.
· 8-bit, 4x 66 MHz Hub Interface 1.1 to ICH4, operating at 1.5 V. 4.3.4.1 System Memory · Supports one DDR-SDRAM channel, 64 bits wide (72 bits with ECC). · Supports 200 MHz or 266 MHz DDR devices. · Supports 64 Mbit, 128 Mbit, 256 Mbit and 512 Mbit technologies for x8 and x16 devices (no
support for double sided x16 devices).
· Supports page sizes of 2 KByte, 4 KByte, 8 KByte and 16 KByte (must have four banks).
Page size is individually selected for every row. Supports JEDEC DIMM configurations defined in the JEDEC specification.
4.3.4.2
Accelerated Graphics Port Interface
AGP is a high performance, component-level interconnect that is designed for 3D graphical display applications. AGP is based on a set of performance extensions and enhancements to the PCI bus. The 845E chipset employs an AGP interface that is optimized for a point-to-point topology using 1.5 V signaling in 4x mode. The 4x mode provides a peak bandwidth of 1066 MB/sec. The Intel® 845E Interactive Client Reference Design incorporates an SMI Cougar3DR16* Graphics chip, connected on AGP. For more information about this device, please see "SMI Cougar3DR16* AGP Graphics" on page 26. AGP features supported by the 845E MCH include:
· Support for AGP 2.0 including 1x/2x/4x AGP data transfers and 2x/4x Fast Write protocol. · Support for a single Accelerated Graphics Port (AGP) device (either via a connector or
mounted directly on the motherboard). This reference design incorporates an SMI Cougar3DR16 Graphics chip directly on the motherboard.
· Support for AGP 1.5 V connector. No support for 3.3 V or Universal AGP connectors. Serious
damage may occur if a 3.3 V AGP Card is plugged in an 845E chipset based platform.
· Support for high priority access. · Support for delayed transaction for AGP reads that cannot be serviced immediately.
24
Intel® 845E Reference Design User's Guide
Technical Reference
4.3.5
I/O Controller Hub
The ICH4 provides the I/O subsystem with access to the rest of the system and integrates many I/O functions.
4.3.5.1
Hub Interface to MCH
The Hub Interface (version 1.1) connects the 845E MCH to the ICH4. All communication between the MCH and the ICH4 occurs over this interface. The 8-bit hub interface runs at 66 MHz quadpumped for a bandwidth of 266 MBytes/sec.
4.3.5.2
Dual-Channel Ultra ATA-100 Bus Master IDE Controller
The ICH4 supports dual-channel Ultra ATA-100/66/33, Bus Master IDE and PIO modes and independent timing of up to four drives with separate IDE connections for primary and secondary cables. Additionally, "Native Mode" Register and Interrupt support is included. The reference design board uses 44-pin IDE connectors (typically used for 2.5´ "laptop" hard drives).
4.3.5.3
Six USB 2.0/1.1 Ports
The ICH4 contains three UHCI Host Controllers supporting six external USB 2.0/1.1 ports and an EHCI 2.0 Host Controller that supports all six ports. The reference design board has four external connectors, two of which are PoweredUSB*, plus two on-board headers for a total of six supported USB 2.0/1.1 ports.
4.3.5.4
Advanced Configuration Power Interface
The ICH4 supports ACPI, which enables the OS to control the system's power management. The ACPI spec supports six power modes, S0 (working), S1-S3 (sleep states), S4 (soft off), and S5 (mechanical off).
4.3.5.5
System Management Bus 2.0 Controller
This controller integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. System management functions are designed to report errors, diagnose the system and recover from system lockups. SMBus 2.0 provides an interface to manage peripherals such as Serial Presence Detection (SPD) on DIMMs. The SMBus has a 32-byte buffer, conducts hardware packet error checking and is compatible with most two-wire components that are also I2C compatible. A host interface allows the processor to communicate via SMBus, while a slave interface allows an external microcontroller to access system resources.
4.3.5.6
Firmware Hub
The reference board implements an Intel 82802AC FWH for its system BIOS storage. The 82802AC is a socketed, 8 Mbit 32-pin PLCC device. All BIOS programming is controlled via software. The FWH resides on the LPC bus.
Intel® 845E Reference Design User's Guide
25
Technical Reference
4.3.5.7
Super IO
Super I/O is supported on the ICH4's LPC interface and provides customary system I/O functions. I/O hardware installed on the motherboard includes a single parallel port, four serial ports, a standard floppy disk drive connector, FIR port, and headers for legacy (PS/2) keyboard and mouse.
4.3.5.8
AC¶97 2.3
This chipset supports 20 bit/16 bit audio capability with support for up to six channels of PCM audio output. In addition, its three codecs with independent PCI functions for audio and modem are supported. Microphone input and left and right audio channels are supported for a high quality twospeaker audio solution. The reference design board has headers for line-out and analog CD-ROM input, as well as three mini-jack connectors on the IO panel for line-in, microphone, and headphone.
4.3.5.9
PCI 2.2 Interface
The reference board supports three PCI slots for add-in devices. The PCI bus is compliant to the PCI Rev. 2.2 specification for 32-bit data at 33 MHz, supporting 3.3Vaux and PME# pins. This design accommodates an Intel® 82551QM Fast Ethernet PCI/Card Bus Controller (or an Intel® 82540EM Gigabit Ethernet Controller), one PCI riser slot at 5 V for low-profile PCI riser and one mini-PCI slot for wireless LAN (802.11). The reference design board is populated with an 82540EM Gigabit Ethernet Controller.
4.3.6
Clocking
The CK-408 clock generator provides reference timing for the system; please see the schematics for complete signaling details.
4.3.7
Real-Time Clock
An onboard battery maintains power to the RTC when in a mechanical off state. A CR2032 battery is installed.
4.3.8
SMI Cougar3DR16* AGP Graphics
The SMI Cougar3DR16* AGP Graphics chip provides the system with high-performance graphics capability. Features include:
· · · · · ·
16 MByte internal memory S-Video output 128-bit robust drawing engine for 2D graphics Full-featured 3D graphics rendering engine LVDS for integrated flat-panel support Dual Independent Video (two digital or one digital and one analog)
26
Intel® 845E Reference Design User's Guide
Technical Reference
4.4
Thermal Solution
The CPU in this system requires an active thermal solution for it to operate properly. The reference design kit includes a fan-sink that should be used whenever the board is powered. The following options are available for platform designers:
· For designs incorporating the Intel Pentium 4 Processor that are not height-constrained to fit
the EmbATX form-factor, please see Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guidelines and/or Intel® Pentium® 4 Processor for Applied Computing Thermal Design Guide.
· For designs incorporating the Intel Pentium 4 Processor that are height-constrained to fit either
the EmbATX form-factor or in 1U chassis, one possible solution is offered by Sanyo-Denki; see http://www.sanyodenki.com.
· For designs incorporating the Intel Pentium 4 Processor-M, please see Intel® Pentium® 4
Processor-M for Applied Computing Thermal Design Guide.
4.5
Power Supply
This system requires an ATX12V-compliant power supply. Be sure to connect the standard ATX power connector and the additional 12 V 4-pin connector to the system board before applying power.
Intel® 845E Reference Design User's Guide
27
Technical Reference
4.6
Port 80h Progress and Error Codes
The BIOS writes progress and error codes to I/O port 80 during POST. These codes can be displayed by using either on-board LEDs (as in this reference design) or a Port 80 card that plugs into a PCI slot. Some errors are also indicated by a beep code. The table below defines the POST codes written to Port 80 in hexadecimal and the corresponding beep codes. If for some reason the board fails, this will help the user identify the problem. For more information, see the Phoenix Technologies* website at http://www.phoenix.com. Unless otherwise noted, these codes are valid for PhoenixBIOS 4.0 Release 6.x.
Table 4.
Port 80h Progress and Error Codes (Sheet 1 of 5)
Codes 02h 03h 04h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 16h 17h 18h 1Ah 1Ch 20h 22h 24h 28h 29h 2Ah 2Ch Beeps 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1-2-2-3 0 0 0 0 1-3-1-1 1-3-1-3 0 0 0 0 1-3-4-1 Verify Real Mode Disable Non-Maskable Interrupt (NMI) Get CPU type Initialize system hardware Disable shadow and execute code from the ROM Initialize chipset with initial POST values Set IN POST flag Initialize CPU registers Enable CPU cache Initialize caches to initial POST values Initialize I/O component Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore CPU control word during warm boot Initialize PCI Bus Mastering devices Initialize keyboard controller BIOS ROM checksum Initialize cache before memory Auto size 8254 timer initialization 8237 DMA controller initialization Reset Programmable Interrupt Controller Test DRAM refresh Test 8742 Keyboard Controller Set ES segment register to 4 GB Auto size DRAM Initialize POST Memory Manager Clear 512 kB base RAM RAM failure on address line xxxx POST Routine Descriptions
28
Intel® 845E Reference Design User's Guide
Technical Reference
Table 4.
Port 80h Progress and Error Codes (Sheet 2 of 5)
Codes 2Eh 2Fh 32h 33h 36h 38h 3Ah 3Ch 3Dh 41h 42h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Eh 4Fh 50h 51h 52h 54h 55h 58h 59h 5Ah 5Bh 5Ch 60h 62h 64h 66h 67h 68h 69h Beeps 1-3-4-3 0 0 0 0 0 0 0 0 0 0 0 2-1-2-3 0 0 0 0 0 0 0 0 0 0 0 0 0 2-2-3-1 0 0 0 0 0 0 0 0 0 0 0 POST Routine Descriptions RAM failure on data bits xxxx of low byte of memory bus Enable cache before system BIOS shadow Test CPU bus-clock frequency Initialize Phoenix Dispatch Manager Warm start shut down Shadow system BIOS ROM Auto size cache Advanced configuration of chipset registers Load alternate registers with CMOS values Initialize extended memory for RomPilot Initialize interrupt vectors POST device initialization Check ROM copyright notice Initialize I20 support Check video configuration against CMOS Initialize PCI bus and devices Initialize all video adapters in system QuietBoot start (optional) Shadow video BIOS ROM Display BIOS copyright notice Initialize MultiBoot Display CPU type and speed Initialize EISA board Test keyboard Set key click if enabled Enable USB devices Test for unexpected interrupts Initialize POST display service Display prompt "Press F2 to enter SETUP" Disable CPU cache Test RAM between 512 and 640 KByte Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers Initialize Multi Processor APIC Enable external and CPU caches Setup System Management Mode (SMM) area
Intel® 845E Reference Design User's Guide
29
Technical Reference
Table 4.
Port 80h Progress and Error Codes (Sheet 3 of 5)
Codes 6Ah 6Bh 6Ch 6Eh 70h 72h 76h 7Ch 7Dh 7Eh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Fh 90h 91h 92h 93h 95h 96h 97h 98h 99h 9Ah 9Ch 9Dh 9Eh 9Fh Beeps 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1-2 0 0 0 0 0 0 POST Routine Descriptions Display external L2 cache size Load custom defaults (optional) Display shadow-area message Display possible high address for UMB recovery Display error messages Check for configuration errors Check for keyboard errors Set up hardware interrupt vectors Initialize Intelligent System Monitoring Initialize coprocessor if present Disable onboard Super I/O ports and IRQs Late POST device initialization Detect and install external RS232 ports Configure non-MCD IDE controllers Detect and install external parallel ports Initialize PC-compatible PnP ISA devices Re-initialize onboard I/O ports. Configure Motherboard Configurable Devices (optional) Initialize BIOS Data Area Enable Non-Maskable Interrupts (NMIs) Initialize Extended BIOS Data Area Test and initialize PS/2 mouse Initialize floppy controller Determine number of ATA drives (optional) Initialize hard-disk controllers Initialize local-bus hard-disk controllers Jump to UserPatch2 Build MPTABLE for multi-processor boards Install CD ROM for boot Clear huge ES segment register Fix up Multi Processor table Search for option ROMs. One long, two short beeps on checksum failure Check for SMART Drive (optional) Shadow option ROMs Set up Power Management Initialize security engine (optional) Enable hardware interrupts Determine number of ATA and SCSI drives
30
Intel® 845E Reference Design User's Guide
Technical Reference
Table 4.
Port 80h Progress and Error Codes (Sheet 4 of 5)
Codes A0h A2h A4h A8h AAh ACh AEh B0h B1h B2h B4h B5h B6h B7h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh D2h Beeps 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Set time of day Check key lock Initialize typematic rate Erase F2 prompt Scan for F2 key stroke Enter SETUP Clear Boot flag Check for errors Inform RomPilot about the end of POST POST done - prepare to boot operating system One short beep before boot Terminate QuietBoot (optional) Check password (optional) Initialize ACPI BIOS Prepare Boot Initialize SMBIOS Initialize PnP Option ROMs Clear parity checkers Display MultiBoot menu Clear screen (optional) Check virus and backup reminders Try to boot with INT 19 Initialize POST Error Manager (PEM) Initialize error logging Initialize error display function Initialize system error handler PnPnd dual CMOS (optional) Initialize note dock (optional) Initialize note dock late Force check (optional) Extended checksum (optional) Redirect Int 15h to enable remote keyboard Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk Redirect Int 10h to enable remote serial video Re-map I/O and memory for PCMCIA Initialize digitizer and display message Unknown interrupt POST Routine Descriptions
Intel® 845E Reference Design User's Guide
31
Technical Reference
Table 4.
Port 80h Progress and Error Codes (Sheet 5 of 5)
Codes Beeps POST Routine Descriptions The following are for boot block in Flash ROM E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initialize the chipset Initialize the bridge Initialize the CPU Initialize system timer Initialize system I/O Check force recovery boot Checksum BIOS ROM Go to BIOS Set Huge Segment Initialize Multi Processor Initialize OEM special code Initialize PIC and DMA Initialize Memory type Initialize Memory size Shadow Boot Block System memory test Initialize interrupt vectors Initialize Run Time Clock Initialize video Initialize System Management Manager Output one beep Clear Huge Segment Boot to Mini DOS Boot to Full DOS
32
Intel® 845E Reference Design User's Guide
Schematics
Schematics are listed on the following pages.
A
Intel® 845E Reference Design User's Guide
33
5
4
3
2
1
Intel (R) 845E Interactive Client Reference Design
D
Revision X2 Last Change : 2002-08-08
D
#
1 2 3 4 5 6 7 8 9 10 11
C
Schematic Page
COVER SHEET BLOCK DIAGRAM BLOCK-POWER MECH-ROUTE NOTES CPU-P4 BUS CPU-P4 POWER CPU-ITP MCH-SYSBUS & CLOCK MCH-AGP & DDR MCH-POWER CLK-ICS950201 DDR-DIMM 0 DDR-DIMM 1 ICH4-SYSBUS & PCI ICH4-LPC & IDE & USB ICH4-POWER GLUE LOGIC SIO0-LPC47M107 SIO1-LPC47N227 CONN-COM1/COM2/LPT CONN-COM3/COM4/KBC AC97-AD1885 LAN-10/100/1000 BUS LAN-10/100/1000 CONN VGA-COUGAR-01 VGA-COUGAR-02 VGA-COUGAR-03 CONN-PCI CONN-01 IDE-FLOPPY USB0-USB1-LAN0 USB2-USB5 SYSTEM CONTROL DDR-POWER POWER
Prefix
A_ AC_ APIC_ AUD_ CK_ EEn_ EN_ F_ FWH_ G_ GND_ GND H_ I2C_ IDE_ INT_ KB_ L_ LANn_ LP_ M_ MIDI_ MS_ P_ SPn_ USB_ V_ ZV_
Netobject
CRITICAL ANALOG TRACES AC97 SIGNAL APIC SIGNAL ANALOG AUDIO SIGNAL CLOCK SIGNAL SERIAL EEPROM LANn ENABLE FOR POWER SOURCES FLOPPY DISK SIGNAL FIRMWARE HUB SIGNAL AGP BUS SIGNAL GND SIGNAL DERIVED GND POWER P4 HOSTBUS SIGNAL I2C BUS SIGNAL IDE SIGNAL INTERRUPT SIGNAL KEYBOARD SIGNAL LPC BUS SIGNAL LAN CONTROLLER n SIGNAL LPT1284 SIGNAL MEMORY BUS SIGNAL MIDI SIGNAL MOUSE SIGNAL PCI BUS SIGNAL SERIAL PORT n SIGNAL USB PORT SIGNAL POWER ZV VIDEO PORT SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Changes from X1 to X2
All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity R712 changed from 10k to 15k to adjust voltage PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5) Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error PU R758 added at CN34.7 (SYS_RESET#) PU R759 added at U39.4 (VIDPWRGD) C717 changed from 4u7 to 1u R607 not populated R571 and R572 not populated (FWH Test Pins) R585 and R586 not populated (for LVDS 18 Bit) R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset R501 and R494 not populated due to PCI config of LAN 82540 U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25) R496 changed to 4k7 and set to GND (PD M66EN) R525 and R499 is now populated R530 not populated due to wrong V_2V5LAN voltage U20.G4 is now 51R Pulldown to GND U20.H4 is now 33R Pullup to V_3V3LAN AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4) Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R) R615 changed to 4K32 due to Cougar Bug HW Rev changed to 2 at Glue Logic R373 is now populated with 10M CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND PU R761-R765 added to VID[0:4] PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options) HD-LED-power connected to V_5V0 instead of V_5V0SB PD R768 added to PS_ON PU R769 added to U3.28 (PGOOD408#) PD R770, R771, R772 added to power enables (default off, if CPLD not configured) PD R773-R776 added to serial port shut down pins Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs Removed R383, R384, R385 Added D25 to avoid crossvoltages from VGA Monitor Added D26 to avoid crossvoltages LPT Port Alternative population of L7 to L12 with resistors (0R) PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING) V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25) Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection
12 13 14 15 16 17 18 19 20 21 22 23 24 25
C
B
26 27 28 29 30 31 32 33 34 35
B
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
A
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE OR THE MISUSE OF THIS INFORMATION. * Other names and brands may be claimed as the property of others.
4 3 2
A
Intel (R) 845E Interactive Client Reference Design
Title Size
General Note: All Parts marked 'XXX1' will not be assembled in V1. All Parts marked 'XXX2' will not be assembled in V2.
5
COVER SHEET
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
1 of 35
Wednesday, September 11, 2002
5
4
3
2
1
Block Diagram
D D
CPU VRM
Pg. 35
CPU
Clocking
ICS950201 CK 408
Pg. 12
Glue Logic
Xilinx * Coolrunner
Pg. 18 - Postcode decoding - Speedstep logic - Powerup sequencing
ITP
Pg. 8
Pentium(R) 4 Processor FCPGA478
Pg. 6, 7
FSB 133MHz x4, 64b (4.3 GB/s)
1280x1024 @ 18Bit
LVDS
Pg. 27 planar
C
max. 2 GB
DDR-DIMM
Cougar 3DR *
DVI/VGA
845E MCH
C
DVI-I
Pg. 27 I/O panel
BGA385 16 MB int. mem.
Pg. 26, 27, 28
AGP 1.5V, 66MHz x4, 32b (1.1 GB/s)
i82845-E BGA593
DDR SDRAM 2.5V, 266MHz, 64b (2.1 GB/s)
DDR VR
Pg. 34
TV-OUT
Pg. 27 I/O panel
Pg. 9, 10, 11
PHY RJ45
Pg. 31 I/O panel PCI, 33MHz, 32b (132 MB/s)
Pg. 13 Pg. 14 Hub Interface 66MHz x4, 8b (266 MB/s)
i82562
Pg. 31
ICH4
i82801 BGA421
LPC 3.3V, 33MHz
B
B
5V PCI-Slot
Pg. 29
miniPCI-Slot
Pg. 29
LAN
i82540 (optional i82551/i82559)
Pg. 24, 25 Pg. 15, 16, 17
SMB
SYSMON
LM87 Pg. 33 FAN PHOTO DIODE
FWH
8 Mbit i82802AC PLCC32 Pg. 33
SIO
LPC47N227
SIO
LPC47M107
RJ45
Pg. 25 I/O panel
ATA66/100
Pg. 20
Pg. 19
USB2.0
AC'97 Pg. 22 SERIAL2 SERIAL0 SERIAL1 FDD PARALLEL K/B MOUSE I/O panel I/O panel planar I/O panel planar planar Pg. 21 Pg. 21 Pg. 30 Pg. 21 Pg. 22 Pg. 22
A
IDE0
Pg. 30 planar
USB
Pg. 31, 32
AC97
AD1885
LINE-IN LINE-OUT HEADPHONE MICRO
I/O panel planar I/O panel I/O panel planar
Pg. 22 SERIAL3 Pg. 20 FIR 3 * planar
IDE1
Pg. 30 planar
A
2 * I/O panel 2 * I/O panel, powered 2 * planar
Pg. 23
CD-ROM
Intel (R) 845E Interactive Client Reference Design
Title Size
BLOCK-DIAGRAM
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
2 of 35
Wednesday, September 11, 2002
5
4
3
2
1
SLP_S3#
ATX POWER
D
ATX 12V
12V
D
12V
5V 5VSB 3V3
CPU VRM MODULE MIC5284
VCCP VCC_1V2VID
CLK
VCC_CLK
MCH
VTT
C
ISL6225 A LTC1117
VCC_1V5 VCC_1V8 VCC_DDR
C
DIMM ISL6225 A
SLP_S4# VCC_REF SLP_S3# VCC_DDR
B
VCC_TERM
B
ICH4
VCC_5V0SUS
B
LTC1117 LTC1117
VCC_3V3SUS VCC_1V5SUS VCC_1V8S VCC_1V5S VCC_3V3S VCC_5V0S
A
A
COUGAR *
ISL6225
B
V_3V3AGP
Intel (R) 845E Interactive Client Reference Design
Title Size
BLOCK-POWER
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
3 of 35
Wednesday, September 11, 2002
5
4
3
2
1
Mx
Mx
Mx
B1 BOHR4.0
B4 BOHR4.0
B7 BOHR4.0
M29
M10 M7
M1
Mx
Mx
1
2
3
MACADRESS B3 BOHR4.0 B9 BOHR4.0 82802AC M30 BRD1
BIOS IN Firmware-Hub
P4_RETENT M2 M23 SM02/RD M24 SM02/RD M25 SM02/RD M26 SM02/RD
Mx
Mx
MACADRESS XXX1 XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
B444B
PCB
M31
M E C H
DK1 DK2 DK3 DK4 DK5 DK204060 DK204060 DK204060 DK204060 DK204060 BAT_CR2032 M11 M32
V_CORE V_CORE V_CORE V_CORE V_CORE
M E C H
JMP_2mm54
HS_MCH_PIN_FIN XXX1 XXX2 M15 HS_MCH_LEVER XXX1 XXX2
HS_MCH_INTERFACE XXX1 XXX2 M16
1 2 3 4 5 6 7 8
BGA593A/COOL
M12
4
D
Mx
B2 BOHR4.0
B5 BOHR4.0
B8 BOHR4.0
FWH
B4441000.01
D
M17
DK6 DK7 DK8 DK9 DK10 DK204060 DK204060 DK204060 DK204060 DK204060
HS_MCH_CLIP HS_MCH_PORON XXX1 XXX1 XXX2 XXX2
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
C
C
DK11 DK12 DK13 DK14 DK15 DK204060 DK204060 DK204060 DK204060 DK204060
V_CORE
V_CORE
V_CORE
DK16 DK17 DK18 DK204060 DK204060 DK204060
MARKE1 MARKETOP MARKE2 MARKETOP MARKE3 MARKETOP
MRKF1 MARKFPIT
B
B
TP1
TP2
TP3
TP4
GND
GND
GND
GND
A
A
Intel (R) 845E Interactive Client Reference Design
Title 6..8,11,17,33,35 V_CORE
V_CORE
MECH-ROUTE
Document Number
Size
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
4 of 35
Wednesday, September 11, 2002
5
4
3
2
1
INPUT VOLTAGES V_12V0VRM V_12V0
D
DERIVED VOLTAGES --> V_12V0VRMF V_FAN1 V_FAN1S V_FAN1SF V_FAN2 V_FAN2S V_FAN2SF V_3V3SB V_1V5SB V_KB V_KBF V_DDR V_USB0 V_USB1 V_USB2 V_USB3 V_USB4 V_USB5 V_1V5 V_USB0X V_USB1X V_USB2X V_USB3X V_USB4X V_USB5X V_DDRVTT V_DDRREF V_12USB2 V_12USB2F V_12USB2S V_12USB3 V_12USB3F V_12USB3S V_12VAUD V_AUDOUT V_5VAUD V_BLI V_CORE V_VCCA V_VCCIOPLL
I2C DEVICES DEVICE CLOCK GENERATOR SO-DIMM0 SO-DIMM1 ICH4 SLAVE LAN CONTROLLER LM87 HW MONITOR ADDRESS 1101001x 1010000x 1010001x 1000100x N/A 0101110x BUS SM SM SM SM SM SM BUS BUS BUS LINK LINK BUS
D
V_5V0SB
V_3V3LAN V_3V3LAN0
V_1V5LAN V_2V5LAN
PCI/AGP DEVICES DEV 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 IDSEL AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 DEVICE COUGAR AGP LAN10/100/1000T IRQ A G REQ/GNT AGP 4
V_5V0
C
V_1V5A1 V_1V5A2 V_2V5_LVD
V_HVDD V_ICHPLL V_2V5_LVD1 V_PLLVDD V_2V5_LVD2 V_LVDD1 V_CVDD V_LVDD2 V_VDD1
INTERNAL LAN MINI PCI SLOT STD PCI SLOT RISER SLOT1 RISER SLOT2 RISER SLOT3
N/A E-F A-B-C-D B-C-D-A C-D-A-B D-A-B-C
N/A 3 0 0 1 2
C
V_3V3AGP
V_2V0_2V5 V_2V5_VDD V_VCC1 V_AVCC1 V_PVCC1 V_VREF_SII V_DBL V_5DVI V_PIDE V_SIDE V_FIR V_IR V_3V3 V_1V2VID V_1V8 V_CLK V_5V0CF V_5DVIF V_IOLAN V_GAME V_GAMEF V_AMP V_AMPIN V_AMPINX V_AMPOUT V_5V0REF V_DL_CL V_DL_CLF V_AVDD V_FPVDD V_TVDD V_VPVDD
ICH4 GPIOs V_VDD2 V_VDD3 GPIO GPI6 GPI7 GPI8 GPI12 GPI13 GPIO25 GPIO27 GPIO28 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 DEVICE SUPER I/O 0 SUPER I/O 1 SUPER I/O 0 SUPER I/O 1 CPLD LAN0 KINNERETH MINI PCI CPLD PRIMARY IDE SECONDARY IDE POWERED USB POWERED USB FIRMWARE HUB FIRMWARE HUB PCI RISER PCI RISER AUDIO AMPLIFIER PCI RISER PCI SLOT PCI SLOT SIGNAL NAME SIO0_SMI# SIO1_SMI# SIO0_PME# SIO1_PME# XC_GPIO2 LAN0_ENA MPCI_ACT# XC_GPIO1 IDE_PPDIAG# IDE_SPDIAG# USB_PWR2ENA# USB_PWR3ENA# FWH_WP# FWH_TBL# RISER_ID1 RISER_ID2 AMP_SHDN NOGO P_PRSNT1# P_PRSNT2#
B
B
V_3V3SB V_RTC V_BAT V_RTCBIAS V_-12V0 V_-5V0
POWER STATES
A A
ON IN STATE S5 (SOFT OFF) S3 (SUS. TO RAM) S0 (FULL ON)
5
POWER PLANE V_*SB, V_KB, V_*LAN, V_USB*
Intel (R) 845E Interactive Client Reference Design
V_DDR, V_DDRREF
Title
OTHERS
4 3 2
NOTES
Document Number
Size
C
Date
B444B-W
Sheet
1
Rev
2.00
5 of 35
Wednesday, September 11, 2002
5
4
3
2
1
H_D[0..63]
H_D[0..63]
9
U1A
9 H_A#[3..31] H_A#[3..31] SPAREPIN SPAREPIN SPAREPIN SP