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CH845G REV:2.0
Title
Cover Sheet Block Diagram Socket 478 DECOUPLING Clock Synthesizer GMCH DDR DIMMS & TERMINATION AGP CONNECTOR ICH4 FWH LPC PCI Connectors IDE Connectors USB Connectors Parallel Port Serial Ports KEYBOARD/MOUSE CNR GAME PORT VGA CONNECTOR AC97 CODEC AUDIO CONNECTORS PWM REGULATORS SYSTEM & POWER CONNECTORS DDR POWER REGULATORS
Page
1 2 3,4 5 6 7,8,9 10,11,12 13 14 ,15 ,16 17 18 19 ,20 21 22 23 24 25
M62 M63 5 4 3 2 MTHOLE 6 7 8 9 MTHOLE 5 4 3 2 6 7 8 9 MTHOLE M70 5 4 3 2 M1 6 7 8 9 MTHOLE 5 4 3 2 6 7 8 9 MTHOLE M2 5 4 3 2 6 7 8 9 MTHOLE M3 5 4 3 2 FH4 1 FIDUCIAL FH2 1 FIDUCIAL FH5 1 FIDUCIAL FH1 1 FIDUCIAL FH3 1 FIDUCIAL HH1 1 NPTH157 HH2 1 NPTH157 HH3 1 NPTH157
26 27 28 29 30 31 32 33 34
6 7 8 9
Size A3 Date:
Document Number COVER SHEET Monday, August 19, 2002 Sheet 1 of 34
Rev 01
Block Diagram
Intel Pentium 4 processor / Northwood 478-Pin Socket
400/533MHz System Bus
VRM9.0
AGP4X or 2 Muxed DVO Port
MCH
1.06GB/S
1.6GB/S \ 2.1GB/S
Brookdale G
760 / 788 FC-BGA 266MB/s Hub interface 1.5
2 DIMM Modules
DDR200/266
IDE Primary ATA66/100 IDE Secondary
PCI CNTRL
PCI CONN 1
PCI CONN 2
PCI CONN 3
ICH4
Hi-Speed USB 6 Ports 480Mb/s
421 mBGA
PCI ADDR/DATA
USB
LPC Bus
AC97 3 Codec support
AC'97 Link LAN
SIO
LAN interface
Flash Bios
Keyboard Mouse
Floppy
Serial 1
Parallel
Game Port
Size A3 Date:
Document Number BLOCK DIAGRAM Monday, August 19, 2002 Sheet 2 of 34
Rev 01
VCORE
A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9
U10A
DEP3 DEP2 DEP1 DEP0
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
L25 K26 K25 J26
H_D0 H_D1 H_D2 H_D3 H_D4 H_D5 H_D6 H_D7 H_D8 H_D9 H_D10 H_D11 H_D12 H_D13 H_D14 H_D15 H_D16 H_D17 H_D18 H_D19 H_D20 H_D21 H_D22 H_D23 H_D24 H_D25 H_D26 H_D27 H_D28 H_D29 H_D30 H_D31 H_D32 H_D33 H_D34 H_D35 H_D36 H_D37 H_D38 H_D39 H_D40 H_D41 H_D42 H_D43 H_D44 H_D45 H_D46 H_D47 H_D48 H_D49 H_D50 H_D51 H_D52 H_D53 H_D54 H_D55 H_D56 H_D57 H_D58 H_D59 H_D60 H_D61 H_D62 H_D63 7 7 7 H_RS0# H_RS1# H_RS2#
B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 F1 G5 F4
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 RS0 RS1 RS2
SOCKET 478
A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 VID0 VID1 VID2 VID3 VID4 REQ4 REQ3 REQ2 REQ1 REQ0 BPM5 BPM4 BPM3 BPM2 BPM1 BPM0 TESTHI12 TESTHI11 TESTHI10 TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0
AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 AE5 AE4 AE3 AE2 AE1 H3 J3 J4 K5 J1 AB4 AA5 Y6 AC4 AB5 AC6 AD25 A6 Y3 W4 U6 AB22 AA20 AC23 AC24 AC20 AC21 AA2 AD24
H_A31 H_A30 H_A29 H_A28 H_A27 H_A26 H_A25 H_A24 H_A23 H_A22 H_A21 H_A20 H_A19 H_A18 H_A17 H_A16 H_A15 H_A14 H_A13 H_A12 H_A11 H_A10 H_A9 H_A8 H_A7 H_A6 H_A5 H_A4 H_A3 CPUVID0 CPUVID1 CPUVID2 CPUVID3 CPUVID4 H_REQ4 H_REQ3 H_REQ2 H_REQ1 H_REQ0 H_BPRM5_PREQ# H_BPRM4_PRDY# H_BPM1 H_BPM0 VCORE R208 56 8 6 4 2 RN11 56 RN13 56 8 6 4 2 7 5 3 1 7 5 3 1 18,31 18,31 18,31 18,31 18,31 7 7 7 7 7
H1 VSS H4 VSS H23 VSS H26 VSS A11 VSS A13 VSS A15 VSS A17 VSS A19 VSS A21 VSS A24 VSS A26 VSS A3 VSS A9 VSS AA1 VSS AA11VSS AA13VSS AA15VSS AA17VSS AA19VSS AA23VSS AA26VSS AA4 VSS AA7 VSS AA9 VSS AB10VSS AB12VSS AB14VSS AB16VSS AB18VSS AB20VSS AB21VSS AB24VSS AB3 VSS AB6 VSS AB8 VSS AC11VSS AC13VSS AC15VSS AC17VSS AC19VSS AC2 VSS AC22VSS AC25VSS AC5 VSS AC7 VSS AC9 VSS AD1 VSS AD10VSS AD12VSS AD14VSS AD16VSS AD18VSS AD21VSS AD23VSS AD4 VSS AD8 VSS AE11VSS AE13VSS AE15VSS AE17VSS AE19VSS AE22VSS AE24VSS AE26VSS AE7 VSS AE9 VSS AF1 VSS AF10VSS AF12VSS AF14VSS AF16VSS AF18VSS AF20VSS AF26VSS AF6 VSS AF8 VSS B10 VSS B12 VSS B14 VSS B16 VSS B18 VSS B20 VSS B23 VSS B26 VSS B4 VSS B8 VSS C11 VSS C13 VSS C15 VSS C17 VSS C19 VSS C2 VSS
SOCKET478
1 3 5 7 RN17 56
2 4 6 8
7 7
H_D[63:0] H_A[31:3]
H_D[63:0] H_A[31:3]
Intel Require Change From 39 ohm To 51 ohm
H_BPRM5_PREQ# H_BPRM4_PRDY# H_BPM1 H_BPM0 R178 R176 R174 R171 51 51 51 51 VCORE
CLOSE TO CPU
Size A3 Date:
Document Number SOCKET478-Part 1 Monday, August 19, 2002 Sheet 3 of 34
Rev 01
CPU SIGNAL TERMINATION
R170 49.9/1% VCORE
VCORE
CLOSE TO CPU
H_BREQ0# H_PWRGD THERMTRIP# R212 R158 R215 51 300 62
R167 C160 220pF AA21 AA6 F20 F6 C147 100/1% 0.01uF
C146 0.1uF
VCORE TC2 L5 L4 4.7uH 4.7uH TC1
47uF/TANB +
U10B
C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 C22
GTLREF GENERATION CIRCUITS
H_TDI IERR MCERR FERR STPCLK BINIT INIT RSP DBSY DRDY TRDY ADS LOCK BR0 BNR HIT HITM BPRI DEFER TCK TDI TMS TRST TDO PROCHOT IGNNE SMI A20M SLP PWRGOOD RESET AC3 V6 B6 Y4 AA3 W5 AB2 H5 H2 J6 G1 G4 H6 G2 F3 E3 D2 E2 D4 C1 F7 E6 D5 C3 B2 B5 C6 AB26 AB23 AB25 B3 C4 A2 AD6 AD5 AC1 V5 AF4 AF3 C162 0.1uF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Y5 Y25 Y22 Y2 W6 W3 W24 W21 V4 V26 V23 V1 U5 U25 U22 U2 T6 T3 T24 T21 R4 C167 4.7uF(NI) H_TRST H_FERR# H_FERR# H_STPCLK# H_INIT# H_DBSY# H_DRDY# H_TRDY# H_ADS# H_LOCK# H_BREQ0# H_BNR# H_HIT# H_HITM# H_BPRI# H_DEFER# 14 14 14,17 7 7 7 7 7 7 7 7 7 7 7 R210 R213 150 680
VCORE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE23 AD20 + AD22
VCCIOPLL VCCA VSSA
GTLREF0 GTLREF1 GTLREF2 GTLREF3
CLOSE TO CPU
47uF/TANB R157 R154 7 7 7 7 7 7 H_DBI3 H_DBI2 H_DBI1 H_DBI0 H_A_STB1 H_A_STB0 51 51 AC26 AD26 V21 P26 G25 E21 R5 L5 AE25 E5 D1 AF23 AF22 R184 R183 51 51 P1 L24 W23 P23 J23 F21 W22 R22 K22 E22 TP1 TP2 TP TP A5 A4 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 F8 G21 G24 G3 ITP_CLK0 ITP_CLK1 DB#3 DB#2 DB#1 DB#0 ADSTB1 ADSTB0 DBRESET LINT1 LINT0 BCLK1 BCLK0 COMP1 COMP0 STBP3 STBP2 STBP1 STBP0 STBN3 STBN2 STBN1 STBN0 VCC_SENSE VSS_SENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ITP/TAP TERMINATION
VCORE H_TMS R211 39
H_BREQ0#
DBRESET#
R161
150(NI)
DBRESET#
14 14 6 6
H_NMI H_INTR CPUHCLK# CPUHCLK
H_TCK H_TDI H_TMS H_TRST H_TDO
H_CPURST#
R153
51
SOCKET 478
H_PWRGD H_CPURST#
H_IGNNE# H_SMI# H_A20M# H_SLP# H_PWRGD H_CPURST# THRMDP THRMDN THERMTRIP# CPUBSEL0#
14 14 14 14 14 7 18 18 15 6
H_TDO
R214
75
H_TCK
R216
27
7 7 7 7 7 7 7 7
H_D_STBP3 H_D_STBP2 H_D_STBP1 H_D_STBP0 H_D_STBN3 H_D_STBN2 H_D_STBN1 H_D_STBN0
THERMDA THERMDC THERMTRIP BSEL0 BSEL1 AP0 AP1 VCCVID VCCVIDPRG
R_THTRIP# R209 0 VCCVID
CLOSE TO ITP PORT
G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SOCKET478
Size A3 Date:
Document Number SOCKET478-Part 2 Monday, August 19, 2002 Sheet 4 of 34
Rev 01
Put on the North side of the processor
VCORE
C128 10uF(NI)
C129 10uF
C130 10uF(NI)
C131 10uF
C132 10uF(NI)
C133 10uF
C134 10uF(NI)
C135 10uF
C136 10uF(NI)
C137 10uF
Put in the processor cavity
VCORE
C172 10uF(NI)
C166 10uF(NI)
C165 10uF
C173 10uF(NI)
C163 10uF
C164 10uF(NI)
C177 10uF(NI)
C178 10uF(NI)
C179 10uF(NI)
C180 10uF
C161 0.1uF(NI)
C176 0.1uF(NI)
C181 0.1uF(NI)
Put on the Sourth side of the processor
VCORE
C204 10uF(NI)
C205 10uF(NI)
C206 10uF(NI)
C207 10uF(NI)
C208 10uF(NI)
C209 10uF(NI)
C210 10uF(NI)
C211 10uF(NI)
C212 10uF(NI)
C213 10uF(NI)
C214 10uF(NI)
C215 10uF(NI)
C216 10uF(NI)
C217 10uF(NI)
Size A3 Date:
Document Number DECOUPLING Monday, August 19, 2002 Sheet 5 of 34
Rev 01
Clock Synthesizer
VCC3CLK FB24
VCC3_3
+ CE17
BEAD120
10uF/16V VCC3_3 FB23
C89 0.1uF
C94 0.1uF
C81 0.1uF
C84 0.1uF
C91 0.1uF
C97 0.1uF
C103 0.1uF
C101 C108 0.1uF 0.1uF 10uF/16V + CE16 BEAD120
13
18
30
33
41
45
U7 C82 10pF Y2 C83 10pF 14.318MHz 3 X2 2 X1
VDDPCI
VDDPCI
AVDD48
VDDREF
VDDCPU
VDD3V66
VDD3V66
VDDCPU
VDDA
24
1
7
CPUCLK0 CPUCLK0#
47 46
R71 R75
27.4/1% 27.4/1%
CPUHCLK 4 CPUHCLK# 4 GMCHCLK 7 GMCHCLK# 7
18 PCICLK_LPC 14 PCICLK_ICH4 17 PCICLKFWH
R74 R78 R79
33 33 33
PCICLKF0 PCICLKF1 PCICLK0
FS0 FS1
5 6
PCICLKF0/FS0 PCICLKF1/FS1 PCICLKF2/WDEN PCICLK0/FS5 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
CPUCLK1 CPUCLK1#
44 43
R80 R84
27.4/1% 27.4/1%
WDEN 9 10 11 12
CPUCLK2 CPUCLK2#
40 39
20 PCICLK1 19 PCICLK2 19 PCICLK3 15 ICH4_3V66 13 AGPCLK_CONN 8 GMCH_3V66
C102 C100 C98
R88 R89 R92
33 33 33
15 16 17
VCC3CLK R94 R93 10K 475/1% R103 48MHz_USB/FS3 48MHz_DOT REF0/FS2 35 34 48 FS2 R69 R115 VTTPWRGD R114 R113 220 4.7K 33 4.7K(NI) FS3 R102 R108 R68 33 33 33 33
R85 R81 R76 R72 49.9/1% 49.9/1% 49.9/1% 49.9/1%
MULTISEL IREF
38 37
R101 R107 R111
33 33 33 FS4
20 21 22 31
3V66_1 3V66_2 3V66_3 3V66_0/VCH_48MHz/FS4
SIO_CLK48 18 USBCLK DOTCLK 15 8
ICH4_CLK14 15 AC97CLK 29
VCC3CLK
10pF(NI) 10pF(NI) 10pF(NI)
12,15,18,19,20,26 SMBDATA 12,15,18,19,20,26 SMBCLK
27 28
PD#/VTT_PWRGD SDATA SCLK GND GND GND GND GND GND GND GND GND RESET#
26
VRM_PWRGD 15,31,33
VCC3CLK
23
CLKRST# 33
FS3 FS2 RX3 RX4 4.7K 4.7K
14
19
25
29
32
36
W83194BR-B
VCC3_3
R73
10K(NI) FS0 VCC3_3
42 R90 1.5K
4
Watch dog Enable
R82 R83 WDEN 0 10K(NI) JP1
8
4 CPUBSEL0#
1 2 3 R104 FS4 10K Size A3 Date: Document Number CLOCK SYNTHESIZER Monday, August 19, 2002 Sheet 6 of 34 Rev 01
MCHBSEL0# 8
H_D[63:0] H_A[31:3]
H_D[63:0] H_A[31:3]
3 3
12 12 12 12 12 12
MEMCLK2# MEMCLK2 MEMCLK0# MEMCLK0 MEMCLK1# MEMCLK1 AL21 AK22 AN11 AP11 AM34 AL33 AP21 AN21 AP9 AN9 AP33 AN34
MEMCLK4 MEMCLK4# MEMCLK3 MEMCLK3# MEMCLK5 MEMCLK5#
12 12 12 12 12 12
U11A H_D0 H_D1 H_D2 H_D3 H_D4 H_D5 H_D6 H_D7 H_D8 H_D9 H_D10 H_D11 H_D12 H_D13 H_D14 H_D15 H_D16 H_D17 H_D18 H_D19 H_D20 H_D21 H_D22 H_D23 H_D24 H_D25 H_D26 H_D27 H_D28 H_D29 H_D30 H_D31 H_D32 H_D33 H_D34 H_D35 H_D36 H_D37 H_D38 H_D39 H_D40 H_D41 H_D42 H_D43 H_D44 H_D45 H_D46 H_D47 H_D48 H_D49 H_D50 H_D51 H_D52 H_D53 H_D54 H_D55 H_D56 H_D57 H_D58 H_D59 H_D60 H_D61 H_D62 H_D63 4 4 4 4 4 4 4 4 4 6 6 H_D_STBP0 H_D_STBP1 H_D_STBP2 H_D_STBP3 H_D_STBN0 H_D_STBN1 H_D_STBN2 H_D_STBN3 H_CPURST# GMCHCLK GMCHCLK# T30 R33 R34 N34 R31 L33 L36 P35 J36 K34 K36 M30 M35 L34 K35 H36 G34 G36 J33 D35 F36 F34 E36 H34 F35 D36 H35 E33 E34 B35 G31 C36 D33 D30 D29 E31 D32 C34 B34 D31 G29 C32 B31 B32 B30 B29 E27 C28 B27 D26 D28 B26 G27 H26 B25 C24 B23 B24 E23 C22 G25 B22 D24 G23 L31 J34 E29 E25 N31 G33 C30 D25 D22 K30 J31 D27 H24 H30 AD30 P30 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
BROOKDALE-G
HOST,HUB
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
W31 AA33 AB30 V34 Y36 AC33 Y35 AA36 AC34 AB34 Y34 AB36 AC36 AC31 AF35 AD36 AD35 AE34 AD34 AE36 AF36 AE33 AF34 AG34 AG36 AE31 AH35 AG33 AG31 AB35 AF30 P36 M36 T36 T34 M34 U33 U31 N36 U36 V30 T35 C26 B33 C35 N33 V36 AA31 W33 AA34 W35 AF2 AE2 AF3 AE5 AE4 AF4 AD8 AC5 AC7 AB8 AA7 AD4 AC4 P34 U34 R36
H_A3 H_A4 H_A5 H_A6 H_A7 H_A8 H_A9 H_A10 H_A11 H_A12 H_A13 H_A14 H_A15 H_A16 H_A17 H_A18 H_A19 H_A20 H_A21 H_A22 H_A23 H_A24 H_A25 H_A26 H_A27 H_A28 H_A29 H_A30 H_A31
H_A_STB0 H_A_STB1 H_HIT# H_HITM# H_ADS# H_BNR# H_BPRI# H_BREQ0# H_DBSY# H_DEFER# H_DRDY# H_TRDY# H_LOCK# H_DBI3 H_DBI2 H_DBI1 H_DBI0 H_REQ0 H_REQ1 H_REQ2 H_REQ3 H_REQ4 HI[10:0] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 14
U11B 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 DM_MD0 DM_MD1 DM_MD2 DM_MD3 DM_MD4 DM_MD5 DM_MD6 DM_MD7 DM_MD8 DM_MD9 DM_MD10 DM_MD11 DM_MD12 DM_MD13 DM_MD14 DM_MD15 DM_MD16 DM_MD17 DM_MD18 DM_MD19 DM_MD20 DM_MD21 DM_MD22 DM_MD23 DM_MD24 DM_MD25 DM_MD26 DM_MD27 DM_MD28 DM_MD29 DM_MD30 DM_MD31 DM_MD32 DM_MD33 DM_MD34 DM_MD35 DM_MD36 DM_MD37 DM_MD38 DM_MD39 DM_MD40 DM_MD41 DM_MD42 DM_MD43 DM_MD44 DM_MD45 DM_MD46 DM_MD47 DM_MD48 DM_MD49 DM_MD50 DM_MD51 DM_MD52 DM_MD53 DM_MD54 DM_MD55 DM_MD56 DM_MD57 DM_MD58 DM_MD59 DM_MD60 DM_MD61 DM_MD62 DM_MD63 AN4 AP2 AT3 AP5 AN2 AP3 AR4 AT4 AT5 AR6 AT9 AR10 AT6 AP6 AT8 AP8 AP10 AT11 AT13 AT14 AT10 AR12 AR14 AP14 AT15 AP16 AT18 AT19 AR16 AT16 AP18 AR20 AR22 AP22 AP24 AT26 AT22 AT23 AT25 AR26 AP26 AT28 AR30 AP30 AT27 AR28 AT30 AT31 AR32 AT32 AR36 AP35 AP32 AT33 AP34 AT35 AN36 AM36 AK36 AJ36 AP36 AM35 AK35 AK34 SDQ_0 SDQ_1 SDQ_2 SDQ_3 SDQ_4 SDQ_5 SDQ_6 SDQ_7 SDQ_8 SDQ_9 SDQ_10 SDQ_11 SDQ_12 SDQ_13 SDQ_14 SDQ_15 SDQ_16 SDQ_17 SDQ_18 SDQ_19 SDQ_20 SDQ_21 SDQ_22 SDQ_23 SDQ_24 SDQ_25 SDQ_26 SDQ_27 SDQ_28 SDQ_29 SDQ_30 SDQ_31 SDQ_32 SDQ_33 SDQ_34 SDQ_35 SDQ_36 SDQ_37 SDQ_38 SDQ_39 SDQ_40 SDQ_41 SDQ_42 SDQ_43 SDQ_44 SDQ_45 SDQ_46 SDQ_47 SDQ_48 SDQ_49 SDQ_50 SDQ_51 SDQ_52 SDQ_53 SDQ_54 SDQ_55 SDQ_56 SDQ_57 SDQ_58 SDQ_59 SDQ_60 SDQ_61 SDQ_62 SDQ_63 82845G/GL
SMAA12/BS0 SMAA11/DQS8 SMAA10/DQ31 SMAA9/SMA3 SMAA8/SMA4 SMAA7/SMA6 SMAA6/SDQ29 SMAA5/SMA8 SMAA4/SMA11 SMAA3/SMA7 SMAA2/SMA9 SMAA1/SDQ19 SMAA0/SMA12 SMAB5 SMAB4 SMAB2 SMAB1 SBA1 SBA0
AN15 AL15 AK26 AK16 AN17 AP17 AP19 AL17 AL19 AK20 AP23 AN25 AL25 AK18 AN19 AN23 AP25 AP27 AN27 AR2 AT7 AT12 AT17 AR24 AT29 AT34 AL36 AP4 AR8 AP12 AR18 AT24 AP28 AR34 AL34 AL13 AK14 AN13 AP13 AL29 AP31 AK30 AN31 AK28 AN29 AP29 AK24 AL23 AJ34 AD16 AM2 RDCLKO RDCLKI R204 R205
SCMD_CLK0 SCMD_CLK0# SCMD_CLK1 SCMD_CLK1# SCMD_CLK2 SCMD_CLK2# SCMD_CLK3 SCMD_CLK3# SCMD_CLK4 SCMD_CLK4# SCMD_CLK5 SCMD_CLK5#
RM_MAA12 RM_MAA11 RM_MAA10 RM_MAA9 RM_MAA8 RM_MAA7 RM_MAA6 RM_MAA5 RM_MAA4 RM_MAA3 RM_MAA2 RM_MAA1 RM_MAA0 RM_MAB5 RM_MAB4 RM_MAB2 RM_MAB1 RM_BS1 RM_BS0 DM_SDQS0 DM_SDQS1 DM_SDQS2 DM_SDQS3 DM_SDQS4 DM_SDQS5 DM_SDQS6 DM_SDQS7 DM_SDM0 DM_SDM1 DM_SDM2 DM_SDM3 DM_SDM4 DM_SDM5 DM_SDM6 DM_SDM7 RM_CKE3 RM_CKE2 RM_CKE1 RM_CKE0 RM_SCS0 RM_SCS1 RM_SCS2 RM_SCS3 RM_RAS# RM_CAS# RM_WE# SR1 0(NI) 60.4/1% 60.4/1% C199 0.1uF C202 0.1uF
11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12
BROOKDALE-G
DDR
HADSTB0# HADSTB1# HIT# HITM# ADS# BNR# BPRI# BREQ0# DBSY# DEFER# DRDY# HTRDY# HLOCK# DINV3 DINV2 DINV1 DINV0 HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HI10 HI9 HI8 HI7 HI6 HI5 HI4 HI3 HI2 HI1 HI0 HI_STBS HI_STBF RS2# RS1# RS0#
SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7 SCKE3/SCK#5 SCKE2/RSVD SCKE1/SDQ58 SCKE0/RSVD SCS#0/SCKE2 SCS#1/RSVD SCS#2/SCK#2 SCS#3/SCAS# SRAS#/SCKE0 SCAS#/RSVD SWE#/SDQ5 SRCVEN_OUT# SRCVEN_IN# SMY_RCOMP SMX_RCOMP SM_VREF
HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# CPURST# HCLK HCLK# HD_VREF2 HD_VREF1 HD_VREF0 HA_VREF HCC_VREF 82845G/GL
HI10 HI9 HI8 HI7 HI6 HI5 HI4 HI3 HI2 HI1 HI0
RDCLKI & RDCLKO 100mils LENGTH 5mils WIDTH
VCC2_5 DDRVREF C194 0.1uF 12
HI_STBS HI_STBF H_RS2# H_RS1# H_RS0# R173 24.9/1%
14 14 3 3 3 R187 24.9/1%
BGA824 R201 60.4/1% R203 60.4/1%
9 MCH_GTLREF
HX_RCOMP HY_RCOMP HX_SWING HY_SWING HI_VREF HI_RCOMP HI_SWING BGA824
B28 V35 H28 Y30 AD3 AC2 AD2
HX_RCOMP HY_RCOMP
H_XY_SWING 9 HUBREF_A HI_VSWING 9,14 VCC1_5 9,14 R195 68.1/1% 1 2
HS3 1 2 8 7 8 7 HS4 HS-RACK 6 5
3 4
3 4 MCHPAD(NI)
6 5
Size A3 Date:
Document Number GMCH PART1 Monday, August 19, 2002 Sheet 7 of 34
Rev 01
U11C VCC1_5 13 G_PIPE#
13 G_AD[31:0]
G_AD[31:0] G_SBA[7:0]
U11D W19 Y19 AA19 T20 W20 AB20 U21 W21 AA21 T22 V22 Y22 AB22 A9 B9 C9 D9 E9 B10 C10 D10 F10 H10 A11 B11 C11 D11 E11 G11 J11 B12 C12 D12 F12 H12 G13 J13 H14 P14 J15 P15 P18 P16 P17 AB16 Y16 V16 T16 AA17 W17 U17 AB18 W18 T18 V19 U19 K10 K12 K14 K16 B18 C18 D18 H18 B19 C19 D19 E19 G19 J19 B20 C20 D20 F20 H20 P20 P22 P24 T24 V24 AB24 F18 Y24 K18 K20 K22 K26 M28 T28 Y28 AD28 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
A3 A7 C1 D4 D6 G1 K6 L1 L9 P6 R1 R9 T14 V14 W9 Y14 V6 P10 V10 AB10
VCC2_5
BROOKDALE-G
POWER
1
+
CE31
1
VCORE
VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM
AH8 AK8 AG9 AJ9 AL9 AD22 AM22 AJ23 AL37 AU9 AK10 AD24 AJ11 AL11 AU25 AM26 AU13 AM14 AJ27 AJ1 AL1 AJ15 AP15 AU29 AH2 AJ2 AK2 AL2 AM30 AH3 AJ3 AK3 AL3 AH4 AJ4 AK4 AL4 AU17 AD18 AJ5 AL5 AU5 AM18 AJ19 AK32 AU33 AH6 AK6 AD20 AP20 AG7 AJ7 AL7 AP7 AH10 AH12 AH14 AH18 AH22 AH26 AG1 AG2
VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP VCCAGP
G_PIPE# G_SBA0 G_SBA1 G_SBA2 G_SBA3 G_SBA4 G_SBA5 G_SBA6 G_SBA7
H8 C3 C2 D3 D2 E4 E2 F3 F2 G5 G7
GPIPE# GSBA0/ADDIN0 GSBA1/ADDIN1 GSBA2/ADDIN2 GSBA3/ADDIN3 GSBA4/ADDIN4 GSBA5/ADDIN5 GSBA6/ADDIN6 GSBA7/ADDIN7 GWBF# GRBF# GST0 GST1 GST2
AGP/DVO
+
CE44 100uF(NI)
+
CE40 100uF(NI)
+
CE41 100uF(NI)
13 13 13 13 13
G_WBF# G_RBF# G_ST0 G_ST1 G_ST2
G_ST0 G_ST1 G_ST2
C4 B4 B3 V8 U7 M8 L7 F4 E5 M4 N7 N5 P2 N2 D5 P4 B5 H2 M2 N4 R4 L2 W2 B7 C6 D7 C7 B16
BROOKDALE-G
VCC3SBYM Add Two 22UF CAP
13 G_ADSTB0 13 G_ADSTB0# 13 G_ADSTB1 13 G_ADSTB1# 13 G_SBSTB 13 G_SBSTB# 13 13 13 13 13 13 13 13 13 13 13 13 G_FRAME# G_IRDY# G_TRDY# G_STOP# G_DEVSEL# G_REQ# G_PAR G_GNT# G_C_BE3 G_C_BE2 G_C_BE1 G_C_BE0
GAD_STB0/DVOBCLK GAD_STB0#/DVOBCLK# GAD_STB1/DVOCCLK GAD_STB1#/DVOCCLK# GSBSTB GSBSTB# G_FRAME#/MDVI DATA G_IRDY#/MI2CCLK G_TRDY#/MI2CDATA G_STOP#/MDDC CLK G_DEVSEL#/MDVI CLK G_REQ# G_PAR/ADD_DETECT G_GNT# GCBE3#/DVOC5 GCBE2# GCBE1#/DVOBBLANK# GCBE0#/DVOBD7
GAD0/DVOBHSYNC GAD1/DVOBVSYNC GAD2/DVOBD1 GAD3/DVOBD0 GAD4/DVOBD3 GAD5/DVOBD2 GAD6/DVOBD5 GAD7/DVOBD4 GAD8/DVOBD5 GAD9/DVOBD9 GAD10/DVOBD8 GAD11/DVOBD11 GAD12/DVOBD10 GAD13/DVOBCCLKINT GAD14/DVOBFLDSTL GAD15/MDDC DATA GAD16/DVOCVSYNC GAD17/DVOCHSYNC GAD18/DVOCBLANK# GAD19/DVOCD0 GAD20/DVOCD1 GAD21/DVOCD2 GAD22/DVOCD3 GAD23/DVOCD4 GAD24/DVOCD7 GAD25/DVOCD6 GAD26/DVOCD9 GAD27/DVOCD8 GAD28/DVOCD11 GAD29/DVOCD10 GAD30/DVOBCINTR# GAD31/DVOCFLDSTL GCLKIN RSTIN# DREFCLK PWROK PSBSEL BLUE BLUE# GREEN GREEN# RED RED# BGA824
V4 V2 W4 W5 U5 U4 U2 V3 T2 T3 T4 R2 R5 R7 T8 P3 P8 K4 K2 J2 M3 L5 L4 H4 G2 K3 J4 J5 J7 H3 K8 G4 AE7 AJ31 D14 E7 Y3 G15 H16 E15 F16 C15 D16
G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31
13 G_SBA[7:0]
1
1
2
2
2
1
R355 NC-0
13 VREF_AGP_MCH 28 28 L9 0.68uH R172 VCC1_5 R356 NC-0 R357 NC-0 121/1% R186 40.2/1% 28 DDCA_CLK 28 DDCA_DATA HSYNC VSYNC 2
AGP RCOMP/DVOBCRCOMP AGP_VREF HSYNC VSYNC DDCA_CLK DDCA_DATA REFSET 82845G/GL
R189 8.2K
GMCH_3V66 HPCIRST# DOTCLK PWROK MCHBSEL0# BLUE BLUE# GREEN GREEN# RED RED#
6 14,17,18,20,21 6 15,33 6 28 28 28 28 28 28
ANALOG DISPLAY
C184 0.1uF
R192 8.2K(NI)
1 C229 4.7uF R222 1 2 L10 L0603-31 L8 1uH C155 0.01uF 1 C156 0.1uF
VCCA_DAC
R163 VCC1_5 1 1
L7 10uH 2
VCCA_DPLL
VCORE
+ CE33
560uF/16V
R358 NC-0
C158 0.1uF
C144 0.1uF(NI)
C145 0.1uF(NI)
AU37NC AU36NC AT37NC AU2 NC AU1 NC AT1 NC AJ35 NC AH34NC B1 NC B37 NC A36 NC A2 NC
VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB VTTFSB
VCCA_SM VCCA_SM VCCQSM VCCQSM VCCQSM VTTDECAP VTTDECAP VTTDECAP VTTDECAP VTTDECAP VCCA_FSB VCCA_HI VCCA_HI VCCHI VCCHI VCCHI VCCHI VCCHI VCCA_DPLL VCCA_DAC VCCA_DAC VCCGPIO SMX_RCOMP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
22uF/10V(NI) 2 C224 C192 0.1uF 2 1
+
CE36 100uF/25V L6 0.82uH VCC1_5 1 2
2
AT20 AT21 AU21 A31 AC37 R37 L37 G37 A17 AD14 AD10 AD6 AC9 AB14 AC1 AE3 A13 B14 A15 B6 AF10
0.1uF
FSB ADDR & CNTL
VCCA_FSB
VCC1_5 VCORE CE30 C142 C153 0.1uF C218 0.1uF(NI) C143 0.1uF(NI) 0.1uF(NI)
VCCA_FSB C170 VCC1_5 0.1uF C174 0.1uF C183 0.1uF C187 0.1uF C149 0.1uF 22uF/10V
FSB DATA
VCCA_DPLL VCCA_DAC VCC3_3 R200 R202 0.1uF 60.4/1% 60.4/1% VCC2_5 C152
82845G/GL BGA824
A37 AB2 AB3 AA2 AA3 AA4 AA5 Y2 Y4 Y8 W7
Size A3 Date:
Document Number GMCH PART2 Thursday, August 29, 2002 Sheet 8 of 34
Rev 01
HI_VSWING N37 C16 A25 AM24 AC24 AA24 W24 U24 R24 F24 AU23 AR23 AM10 AR9 AR17 AJ17 AD17 AB17 Y17 AG4 AB4 AU3 AR3 AN3 AM3 AG3 AC3 C31 AH30 V17 T17 J17 G17 E17 R199 226/1% VCC1_5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BGA824 C17 B17 AM16 AA16 W16 U16 W3 U3 R3 D17 N3 L3 J3 G3 E3 AT2 F30 AR29 AJ29 AG29 AE29 AC29 AA29 W29 R29 U29 N29 L29 J29 C29 A29 AU15 AR15 AD15 D15 B2 AR1 AN1 AE1 AA1 U1 N1 J1 E1 AM28 F28 AU27 AR27 AL27 AC14 AA14 W14 U14 R14 F14 AR13 AJ13 J27 C27 A27 E13 D13 C13 B13 AM12 AK12 F26 AR25 AJ25 J25 AU11 AR11 AR37 AN37 C25 AJ37 AG37 AE37 AA37 U37 AH28 AF28 AB28 V28 P28 K28 K24 C188 0.01uF C232 0.01uF C219 0.1uF R198 100/1%
7,14
U11E U18 V18 Y18 AA18 AL31 AR31 AU31 F32 H32 K32 M32 P32 T32 V32 Y32 AB32 AD32 AF32 AH32 AM4 A5 C5 AG5 AN5 AR5 P19 T19 AB19 AD19 AR19 AM32 A33 C33 AJ33 AN33 AR33 F6 H6 M6 T6 Y6 AB6 AF6 AM6 U20 V20 Y20 AA20 AM20 A21 B21 C21 D21 E21 G21 J21 D34 W34 A35 E35 G35 J35 L35 AN7 AR7 AU7 B8 C8 D8 F8 P21 T21 V21 Y21 AB21 AD21 AJ21 AR21 F22 H22 M10 T10 Y10 AH16 AH20 AH24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
10 mil Trace, 7mil Space
HUBREF_A 7,14 R197 100/1% C186 0.1uF C230 0.01uF C191 0.01uF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
PLACE NOTE: CAP PLACE AT MIDPOINT OF THE BUS.
NEAR MCH
NEAR ICH
NEAR MCH
NEAR ICH
R160 49.9/1% VCORE C157 0.1uF
10 mil Trace, 7mil Space
MCH_GTLREF 7 R165 100/1% C140 0.1uF
BROOKDALE-G
VSS
NEAR MCH
C127 VCORE
0.01uF
10 mil Trace, 7mil Space
H_XY_SWING 7
R159 301/1%
R164 150/1%
VCC2_5
SYSTEM MEMORY DECOUPLING
C226 0.1uF(NI)
C221 0.1uF(NI)
C223 0.1uF(NI)
C220 0.1uF(NI)
C222 0.1uF(NI)
C225 0.1uF(NI)
C198 0.1uF(NI)
C197 0.1uF(NI)
VCC1_5
GMCH DECOUPLING
C141 0.1uF(NI) C154 0.1uF(NI) C169 0.1uF(NI) C182 0.1uF(NI) C201 0.1uF(NI) C151 0.1uF(NI) C185 0.1uF(NI) C171 0.1uF(NI)
82845G/GL
C14 VSSA_DAC B15 VSSA_DAC
U22 VSS W22 VSS AA22VSS N35 VSS R35 VSS U35 VSS AA35VSS AC35VSS AE35VSS AG35 VSS AL35VSS AN35VSS AR35VSS AU35VSS B36 VSS W36 VSS AF8 VSS AM8 VSS G9 VSS J9 VSS N9 VSS U9 VSS AA9 VSS AE9 VSS A23 VSS C23 VSS D23 VSS J23 VSS P23 VSS AD23VSS AH36VSS AT36VSS C37 VSS E37 VSS J37 VSS
Size A3 Date:
Document Number GMCH PART3 Monday, August 19, 2002 Sheet 9 of 34
Rev 01
RN24 10 11,12 11,12 11,12 11,12 RM_MD6 RM_MD2 RM_MD7 RM_MD3 1 3 5 7 RN23 10 11,12 11,12 11,12 11,12 RM_MD0 RM_MD4 RM_MD5 RM_MD1 1 3 5 7 RN25 10 11,12 RM_MD8 11,12 RM_MD9 11,12 RM_MD12 11,12 RM_MD13 1 3 5 7 RN26 10 11,12 11,12 11,12 11,12 RM_MD14 RM_MD15 RM_MD10 RM_MD11 1 3 5 7 RN27 10 11,12 11,12 11,12 11,12 RM_MD20 RM_MD16 RM_MD17 RM_MD21 1 3 5 7 RN28 10 11,12 11,12 11,12 11,12 RM_MD18 RM_MD22 RM_MD19 RM_MD23 1 3 5 7 RN29 10 11,12 11,12 11,12 11,12 RM_MD24 RM_MD28 RM_MD29 RM_MD25 1 3 5 7 RN30 10 11,12 11,12 11,12 11,12 RM_MD26 RM_MD30 RM_MD27 RM_MD31 1 3 5 7 2 4 6 8 DM_MD26 DM_MD30 DM_MD27 DM_MD31 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD60 RM_MD56 RM_MD61 RM_MD57 1 3 5 7 2 4 6 8 DM_MD24 DM_MD28 DM_MD29 DM_MD25 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD62 RM_MD58 RM_MD63 RM_MD59 1 3 5 7 2 4 6 8 DM_MD18 DM_MD22 DM_MD19 DM_MD23 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD48 RM_MD49 RM_MD52 RM_MD53 1 3 5 7 2 4 6 8 DM_MD20 DM_MD16 DM_MD17 DM_MD21 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD54 RM_MD55 RM_MD50 RM_MD51 1 3 5 7 2 4 6 8 DM_MD14 DM_MD15 DM_MD10 DM_MD11 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD42 RM_MD46 RM_MD43 RM_MD47 1 3 5 7 2 4 6 8 DM_MD8 DM_MD9 DM_MD12 DM_MD13 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD40 RM_MD44 RM_MD45 RM_MD41 1 3 5 7 2 4 6 8 DM_MD0 DM_MD4 DM_MD5 DM_MD1 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD34 RM_MD38 RM_MD39 RM_MD35 1 3 5 7 2 4 6 8 DM_MD6 DM_MD2 DM_MD7 DM_MD3 7 7 7 7 11,12 11,12 11,12 11,12 RM_MD32 RM_MD36 RM_MD33 RM_MD37 1 3 5 7
RN31 10 2 4 6 8 RN32 10 2 4 6 8 RN33 10 2 4 6 8 RN34 10 2 4 6 8 RN36 10 2 4 6 8 RN35 10 2 4 6 8 RN38 10 2 4 6 8 RN37 10 2 4 6 8 DM_MD60 DM_MD56 DM_MD61 DM_MD57 7 7 7 7 DM_MD62 DM_MD58 DM_MD63 DM_MD59 7 7 7 7 DM_MD48 DM_MD49 DM_MD52 DM_MD53 7 7 7 7 DM_MD54 DM_MD55 DM_MD50 DM_MD51 7 7 7 7 DM_MD42 DM_MD46 DM_MD43 DM_MD47 7 7 7 7 DM_MD40 DM_MD44 DM_MD45 DM_MD41 7 7 7 7 DM_MD34 DM_MD38 DM_MD39 DM_MD35 7 7 7 7 DM_MD32 DM_MD36 DM_MD33 DM_MD37 7 7 7 7
11,12 RM_SDQS0
R233
10
DM_SDQS0
7
11,12 RM_SDQS1
R234
10
DM_SDQS1
7
11,12 RM_SDQS2
R236
10
DM_SDQS2
7
11,12 RM_SDQS3
R238
10
DM_SDQS3
7
11,12 RM_SDQS4
R240
10
DM_SDQS4
7
11,12 RM_SDQS5
R243
10
DM_SDQS5
7
11,12 RM_SDQS6
R245
10
DM_SDQS6
7
11,12 RM_SDQS7
R247
10
DM_SDQS7
7
11,12 RM_SDM0
R232
10
DM_SDM0
7
11,12 RM_SDM1
R235
10
DM_SDM1
7
11,12 RM_SDM2
R237
10
DM_SDM2
7
11,12 RM_SDM3
R239
10
DM_SDM3
7
11,12 RM_SDM4
R241
10
DM_SDM4
7
11,12 RM_SDM5
R242
10
DM_SDM5
7
11,12 RM_SDM6
R244
10
DM_SDM6
7
11,12 RM_SDM7
R246
10
DM_SDM7
7
Size A4 Date:
Document Number DDR SERIES TERMINATION_1 Monday, August 19, 2002 Sheet 10 of 34
Rev 01
VTT_DDR
VTT_DDR
VTT_DDR
VTT_DDR
RN39 56 C281 0.1uF C0603 1 3 5 7 RN40 56 C279 0.1uF C0603 1 3 5 7 RN41 56 C280 0.1uF C0603 1 3 5 7 RN42 56 C297 0.1uF C0603 1 3 5 7 RN43 56 C284 0.1uF C0603 1 3 5 7 RN44 56 C268 0.1uF C0603 1 3 5 7 RN45 56 C293 0.1uF C0603 1 3 5 7 RN46 56 C291 0.1uF C0603 1 3 5 7 2 4 6 8 RM_MD17 RM_MD21 RM_SDQS2 RM_MAA11 10,12 10,12 10,12 7,12 C276 0.1uF C0603 1 3 5 7 1 1 2 4 6 8 RM_CKE0 RM_MAA12 RM_MD20 RM_MD16 7,12 7,12 10,12 10,12 C294 0.1uF C0603 1 3 5 7 1 1 2 4 6 8 RM_CKE3 RM_MD10 RM_MD11 RM_CKE2 7,12 10,12 10,12 7,12 C290 0.1uF C0603 1 3 5 7 1 1 2 4 6 8 RM_SDM1 RM_MD14 RM_CKE1 RM_MD15 10,12 10,12 7,12 10,12 1 1 C275 0.1uF C0603 2 4 6 8 RM_MD9 RM_MD12 RM_MD13 RM_SDQS1 10,12 10,12 10,12 10,12 C286 0.1uF C0603 1 3 5 7 56 56 56 56 1 1 2 4 6 8 RM_MD2 RM_MD7 RM_MD3 RM_MD8 10,12 10,12 10,12 10,12 C267 0.1uF C0603 1 3 5 7 1 1 2 4 6 8 RM_MD1 RM_SDM0 RM_SDQS0 RM_MD6 10,12 10,12 10,12 10,12 C277 0.1uF C0603 1 3 5 7 1 1 2 4 6 8 RM_MD0 RM_MD4 RM_MD5 10,12 10,12 10,12 C282 0.1uF C0603 1 3 5 7 1 1
RN47 56 2 4 6 8 RN48 56 2 4 6 8 RN49 56 2 4 6 8 RN50 56 2 4 6 8 R297 R298 R300 R302 RN52 56 2 4 6 8 RN53 56 2 4 6 8 RN54 56 2 4 6 8 RM_SDM4 RM_MD34 RM_MD38 RM_MD39 10,12 10,12 10,12 10,12 C295 0.1uF C0603 1 3 5 7 1 RM_MD36 RM_MD33 RM_MD37 RM_SDQS4 10,12 10,12 10,12 10,12 C292 0.1uF C0603 1 3 5 7 1 RM_MAA0 RM_MAA10 RM_BS1 RM_MD32 7,12 7,12 7,12 10,12 C278 0.1uF C0603 1 3 5 7 1 RM_MAA6 RM_SDQS3 RM_SDM3 RM_MD31 7,12 10,12 1 10,12 2 10,12 C271 0.1uF C0603 1 3 5 7 RM_MAA3 RM_MD26 RM_MD30 RM_MD27 7,12 10,12 10,12 10,12 C296 0.1uF C0603 1 3 5 7 1 RM_MD24 RM_MD28 RM_MD29 RM_MD25 10,12 10,12 10,12 10,12 C285 0.1uF C0603 1 3 5 7 1 RM_MD22 RM_MAA8 RM_MD23 RM_MD19 10,12 7,12 10,12 10,12 C272 0.1uF C0603 1 3 5 7 1 RM_SDM2 RM_MAA9 RM_MD18 RM_MAA7 10,12 7,12 10,12 7,12 C270 0.1uF C0603 1 3 5 7 1
RN55 56 2 4 6 8 RN56 56 2 4 6 8 RN57 56 2 4 6 8 RN58 56 2 4 6 8 RN59 56 2 4 6 8 RN60 56 2 4 6 8 RN61 56 2 4 6 8 RN51 33 2 4 6 8 RM_MAB2 RM_MAA2 RM_MAB1 RM_MAA1 7,12 7,12 7,12 7,12 RM_SDQS6 RM_MD54 RM_MD55 RM_MD50 10,12 10,12 10,12 10,12 RM_MD49 RM_MD52 RM_MD53 RM_SDM6 10,12 10,12 10,12 10,12 RM_MD46 RM_MD43 RM_MD47 RM_MD48 10,12 10,12 10,12 10,12 CE46 + + RM_SCS1 RM_SDM5 RM_SDQS5 RM_MD42 7,12 10,12 10,12 10,12 RM_MD41 RM_SCS2 RM_CAS# RM_SCS3 10,12 7,12 7,12 7,12 C266 0.1uF C0603 1 3 5 7 1 RM_RAS# RM_MD45 RM_WE# RM_SCS0 7,12 10,12 7,12 7,12 C283 0.1uF C0603 1 3 5 7 1 RM_BS0 RM_MD35 RM_MD40 RM_MD44 7,12 10,12 10,12 10,12 C265 0.1uF C0603 1 3 5 7 1
RN62 56 2 4 6 8 RN63 56 2 4 6 8 RN64 56 2 4 6 8 RM_MD58 RM_MD63 RM_MD59 10,12 10,12 10,12 RM_MD57 RM_SDM7 RM_SDQS7 RM_MD62 10,12 10,12 10,12 10,12 RM_MD51 RM_MD60 RM_MD56 RM_MD61 10,12 10,12 10,12 10,12
2
2
2
2
2
2
2
2
2
2
2
2
R295 1 C274 0.1uF C0603 R299 R296 R301
33 33 33 33
RM_MAA5 RM_MAA4 RM_MAB5 RM_MAB4
7,12 7,12 7,12 7,12
2
2
2
2
CE47
2
2
470uF/16V 470uF/16V
2
2
2
2
2
2
2
2
2
Size A4 Date:
Document Number DDR SERIES TERMINATION_2 Monday, August 19, 2002 Sheet 11 of 34
Rev 01
VCC2_5 VCC2_5
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
7 38 46 70 85 108 120 148 168 VDD VDD VDD VDD VDD VDD VDD VDD VDD
DIMM2
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
7 38 46 70 85 108 120 148 168
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DIMM1 RM_MAA0 RM_MAB1 RM_MAB2 RM_MAA3 RM_MAB4 RM_MAB5 RM_MAA6 RM_MAA7 RM_MAA8 RM_MAA9 RM_MAA10 RM_MAA11 RM_MAA12 RM_BS0 RM_BS1 RM_SCS2 RM_SCS3 48 43 41 130 37 32 125 29 122 27 141 118 115 103 59 52 113 157 158 71 163 97 107 119 129 149 159 169 177 140 63 65 154 21 111 16 17 137 138 76 75 5 14 25 36 56 67 78 86 47 91 92 181 182 183 1 82 184 R272 49.9/1% VCC2_5 9 10 101 102 173 167 C242 0.1uF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
7,11 RM_MAA0 7,11 RM_MAA1 7,11 RM_MAA2 7,11 RM_MAA3 7,11 RM_MAA4 7,11 RM_MAA5 7,11 RM_MAA6 7,11 RM_MAA7 7,11 RM_MAA8 7,11 RM_MAA9 7,11 RM_MAA10 7,11 RM_MAA11 7,11 RM_MAA12
RM_MAA0 RM_MAA1 RM_MAA2 RM_MAA3 RM_MAA4 RM_MAA5 RM_MAA6 RM_MAA7 RM_MAA8 RM_MAA9 RM_MAA10 RM_MAA11 RM_MAA12 RM_BS0 RM_BS1 RM_SCS0 RM_SCS1
48 43 41 130 37 32 125 29 122 27 141 118 115 103 59 52 113 157 158 71 163 97 107 119 129 149 159 169 177 140 63 65 154 21 111 16 17 137 138 76 75 5 14 25 36 56 67 78 86 47 91 92 181 182 183 1 82 184 9 10 101 102 173 167
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
7,11 7,11 7,11 7,11
RM_BS0 RM_BS1 RM_SCS0 RM_SCS1
CS0 CS1 NC/CS2 NC/CS3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE CAS RAS CKE0 CKE1 CK0/DNU CK0/DNU CK1 CK1 CK2/DNU CK2/DNU DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 SA1 SA2 VREF VDDID VDDSPD NC NC NC NC NC NC/FETEN
DIMM1
10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11
RM_SDM0 RM_SDM1 RM_SDM2 RM_SDM3 RM_SDM4 RM_SDM5 RM_SDM6 RM_SDM7 RM_WE# RM_CAS# RM_RAS# RM_CKE0 RM_CKE1 MEMCLK0 MEMCLK0# MEMCLK1 MEMCLK1# MEMCLK2 MEMCLK2# RM_SDQS0 RM_SDQS1 RM_SDQS2 RM_SDQS3 RM_SDQS4 RM_SDQS5 RM_SDQS6 RM_SDQS7
RM_SDM0 RM_SDM1 RM_SDM2 RM_SDM3 RM_SDM4 RM_SDM5 RM_SDM6 RM_SDM7 RM_WE# RM_CAS# RM_RAS# RM_CKE0 RM_CKE1 MEMCLK0 MEMCLK0# MEMCLK1 MEMCLK1# MEMCLK2 MEMCLK2# RM_SDQS0 RM_SDQS1 RM_SDQS2 RM_SDQS3 RM_SDQS4 RM_SDQS5 RM_SDQS6 RM_SDQS7 SMBDATA SMBCLK
7,11 7,11 7,11 7,11 7,11 7 7 7 7 7 7 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11
6,15,18,19,20,26 SMBDATA 6,15,18,19,20,26 SMBCLK VCC2_5
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 90
RM_MD0 RM_MD1 RM_MD2 RM_MD3 RM_MD4 RM_MD5 RM_MD6 RM_MD7 RM_MD8 RM_MD9 RM_MD10 RM_MD11 RM_MD12 RM_MD13 RM_MD14 RM_MD15 RM_MD16 RM_MD17 RM_MD18 RM_MD19 RM_MD20 RM_MD21 RM_MD22 RM_MD23 RM_MD24 RM_MD25 RM_MD26 RM_MD27 RM_MD28 RM_MD29 RM_MD30 RM_MD31 RM_MD32 RM_MD33 RM_MD34 RM_MD35 RM_MD36 RM_MD37 RM_MD38 RM_MD39 RM_MD40 RM_MD41 RM_MD42 RM_MD43 RM_MD44 RM_MD45 RM_MD46 RM_MD47 RM_MD48 RM_MD49 RM_MD50 RM_MD51 RM_MD52 RM_MD53 RM_MD54 RM_MD55 RM_MD56 RM_MD57 RM_MD58 RM_MD59 RM_MD60 RM_MD61
RM_MD62 RM_MD63
RM_MD0 RM_MD1 RM_MD2 RM_MD3 RM_MD4 RM_MD5 RM_MD6 RM_MD7 RM_MD8 RM_MD9 RM_MD10 RM_MD11 RM_MD12 RM_MD13 RM_MD14 RM_MD15 RM_MD16 RM_MD17 RM_MD18 RM_MD19 RM_MD20 RM_MD21 RM_MD22 RM_MD23 RM_MD24 RM_MD25 RM_MD26 RM_MD27 RM_MD28 RM_MD29 RM_MD30 RM_MD31 RM_MD32 RM_MD33 RM_MD34 RM_MD35 RM_MD36 RM_MD37 RM_MD38 RM_MD39 RM_MD40 RM_MD41 RM_MD42 RM_MD43 RM_MD44 RM_MD45 RM_MD46 RM_MD47 RM_MD48 RM_MD49 RM_MD50 RM_MD51 RM_MD52 RM_MD53 RM_MD54 RM_MD55 RM_MD56 RM_MD57 RM_MD58 RM_MD59 RM_MD60 RM_MD61 RM_MD62 RM_MD63
10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11
7,11 RM_MAB1 7,11 RM_MAB2 7,11 RM_MAB4 7,11 RM_MAB5
DIMM2
7,11 7,11
RM_SCS2 RM_SCS3
CS0 CS1 NC/CS2 NC/CS3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE CAS RAS CKE0 CKE1 CK0/DNU CK0/DNU CK1 CK1 CK2/DNU CK2/DNU DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 SDA SCL SA0 SA1 SA2 VREF VDDID VDDSPD NC NC NC NC NC NC/FETEN
RM_SDM0 RM_SDM1 RM_SDM2 RM_SDM3 RM_SDM4 RM_SDM5 RM_SDM6 RM_SDM7 RM_WE# RM_CAS# RM_RAS# 7,11 7,11 7 7 7 7 7 7 RM_CKE2 RM_CKE3 MEMCLK3 MEMCLK3# MEMCLK4 MEMCLK4# MEMCLK5 MEMCLK5# RM_CKE2 RM_CKE3 MEMCLK3 MEMCLK3# MEMCLK4 MEMCLK4# MEMCLK5 MEMCLK5# RM_SDQS0 RM_SDQS1 RM_SDQS2 RM_SDQS3 RM_SDQS4 RM_SDQS5 RM_SDQS6 RM_SDQS7 VCC2_5 SMBDATA SMBCLK
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 90
RM_MD0 RM_MD1 RM_MD2 RM_MD3 RM_MD4 RM_MD5 RM_MD6 RM_MD7 RM_MD8 RM_MD9 RM_MD10 RM_MD11 RM_MD12 RM_MD13 RM_MD14 RM_MD15 RM_MD16 RM_MD17 RM_MD18 RM_MD19 RM_MD20 RM_MD21 RM_MD22 RM_MD23 RM_MD24 RM_MD25 RM_MD26 RM_MD27 RM_MD28 RM_MD29 RM_MD30 RM_MD31 RM_MD32 RM_MD33 RM_MD34 RM_MD35 RM_MD36 RM_MD37 RM_MD38 RM_MD39 RM_MD40 RM_MD41 RM_MD42 RM_MD43 RM_MD44 RM_MD45 RM_MD46 RM_MD47 RM_MD48 RM_MD49 RM_MD50 RM_MD51 RM_MD52 RM_MD53 RM_MD54 RM_MD55 RM_MD56 RM_MD57 RM_MD58 RM_MD59 RM_MD60 RM_MD61
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD
RM_MD62 RM_MD63
7
DDRVREF
DDRVREF
DDRVREF
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176 Size A3 Date: Document Number DIMM1&2 Monday, August 19, 2002
WP
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
C243 0.1uF
WP
R273 49.9/1%
DIMM_184P
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176 VCC2_5 1
DIMM_184P
DIMM DECOUPLING +
CE42 100uF(NI) 2 2 1
+
CE37 100uF(NI)
C244 0.1uF(NI)
C245 0.1uF(NI)
C246 0.1uF(NI)
C247 0.1uF(NI)
C248 0.1uF(NI)
C249 0.1uF(NI)
C250 0.1uF(NI)
C251 0.1uF(NI)
C252 0.1uF(NI) Rev 01 Sheet 12 of 34
VCC3_3
+12V VCC1_5
VCC3_3SBY C110 +5V 0.1uF AGP C125 0.1uF(NI) 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 G_AD[31:0] G_SBA[7:0] G_C_BE0 G_C_BE1 G_C_BE2 G_C_BE3 G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# G_PIPE# G_ADSTB0 G_ADSTB0# G_ADSTB1 G_ADSTB1# G_SBSTB G_SBSTB# G_ST0 G_ST1 G_ST2 G_RBF# G_WBF# G_AD[31:0] G_SBA[7:0] G_C_BE0 G_C_BE1 G_C_BE2 G_C_BE3 G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# G_PIPE# G_ADSTB0 G_ADSTB0# G_ADSTB1 G_ADSTB1# G_SBSTB G_SBSTB# G_ST0 G_ST1 G_ST2 G_RBF# G_WBF# AGPCLK_CONN PIRQ#A PIRQ#B PCIRST# G_IRDY# PCI_PME# PIRQ#B AGPCLK_CONN G_REQ# G_ST0 G_ST2 G_RBF# C114 0.1uF(NI) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 OVRCNT# 5.0V 5.0V USB+ GND INTB# CLK REQ# VCC3.3 ST0 ST2 RBF# GND SPARE SBA0 VCC3.3 SBA2 SB_STB GND SBA4 SBA6 RESERVED GND 3.3Vaux VCC3.3 AD31 AD29 VCC3.3 AD27 AD25 GND AD_STB1 AD23 VDDQ1.5 AD21 AD19 GND AD17 C/BE2# VDDQ1.5 IRDY# 12V SPARE RESERVED USBGND INTA# RST# GNT# VCC3.3 ST1 RESERVED PIPE# GND SPARE SBA1 VCC3.3 SBA3 RESERVED GND SBA5 SBA7 RESERVED GND RESERVED VCC3.3 AD30 AD28 VCC3.3 AD26 AD24 GND RESERVED C/BE3# VDDQ1.5 AD22 AD20 GND AD18 AD16 VDDQ1.5 FRAME# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 7 5 3 1 PIRQ#A PCIRST# G_GNT# G_ST1 G_PIPE# G_WBF# G_SBA1 G_SBA3 G_SBSTB# G_SBA5 G_SBA7 R177 8.2K(NI) G_IRDY# R191 8.2K(NI) G_ADSTB0 G_AD30 G_AD28 G_AD26 G_AD24 G_ADSTB1# G_C_BE3 G_AD22 G_AD20 G_AD18 G_AD16 G_FRAME# R134 8.2K(NI) G_ST1 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 G_TRDY# R156 8.2K(NI) G_SBSTB R127 8.2K(NI) G_GNT# R132 8.2K(NI) G_ST0 R175 8.2K(NI) G_ADSTB1 R182 6.8K G_SERR_R# VCC1_5 7 5 3 1 RN16 8 6 4 2 8.2K(NI) RN9 8 6 4 2 8.2K(NI) R181 6.8K G_PERR_R# G_WBF# G_PIPE# G_RBF# G_ST2 G_STOP# G_TRDY# G_DEVSEL# G_FRAME#
AGP BUS
G_SBA0 G_SBA2 G_SBSTB G_SBA4 G_SBA6
G_AD31 G_AD29 G_AD27 G_AD25 G_ADSTB1 G_AD23 G_AD21 G_AD19 G_AD17 G_C_BE2
6 AGPCLK_CONN 14,20 14,20 19,20 PIRQ#A PIRQ#B PCIRST#
14,19,20 PCI_PME#
KEY 1.5V
G_DEVSEL# G_PERR_R# G_SERR_R# G_C_BE1 G_AD14 G_AD12 VCC1_5 G_AD10 G_AD8 G_ADSTB0 G_AD7 R207 1K/1% 8 VREF_AGP_MCH R206 1K/1% C200 0.1uF AGP124/1.5V G_AD1 VREF_AGP_MCH G_AD5 G_AD3 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 DEVSEL# VDDQ1.5 PERR# GND SERR# C/BE1# VDDQ1.5 AD14 AD12 GND AD10 AD8 VDDQ1.5 AD_STB0 AD7 GND AD5 AD3 VDDQ1.5 AD1 RESERVED TRDY# STOP# SPARE GND PAR AD15 VDDQ1.5 AD13 AD11 GND AD9 C/BE0# VDDQ1.5 RESERVED AD6 GND AD4 AD2 VDDQ1.5 AD0 RESERVED
G_STOP# PCI_PME#
G_PAR G_AD15 G_AD13 G_AD11 G_AD9 G_C_BE0 G_ADSTB0# G_AD6 G_AD4 G_AD2 G_AD0
R126 8.2K(NI) G_REQ# R185 8.2K(NI) R188 8.2K(NI) G_ADSTB0# R169 8.2K(NI) G_ADSTB1# R149 8.2K(NI) G_SBSTB#
G_PAR
VCC1_5
VCC3_3
C168 0.1uF(NI)
C148 0.1uF(NI)
C193 0.1uF(NI)
C159 0.1uF(NI)
1
+
CE34 100uF(NI)
C138 0.1uF(NI)
C126 0.1uF(NI)
C124 0.1uF(NI)
2
Size A3 Date:
Document Number AGP CONNECTOR Monday, August 19, 2002 Sheet 13 of 34
Rev 01
ICH4 PART1
VCC3_3 RN12 1 3 5 7 8.2K RN14 1 3 5 7 8.2K RN19 8 6 4 2 8.2K RN21 8 6 4 2 8.2K 7 5 3 1 P_REQ#A PIRQ#A PIRQ#H PIRQ#D 7 5 3 1 PREQ#3 PIRQ#F 2 4 6 8 STOP# 2 4 6 8
R263
68
H_A20M#
H_A20M#
4
R230
68
H_SLP#
H_SLP#
4
FRAME# IRDY# TRDY# DEVSEL#
U12A
R257 VCORE R253 R271 19,20 AD[31:0]
68
H_IGNNE#
H_IGNNE#
4
68
H_INIT#
H_INIT#
4,17
PERR# SERR# PLOCK#
AD[31:0]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
19,20 19,20 19,20 19,20 C_BE#0 C_BE#1 C_BE#2 C_BE#3 C_BE#0 C_BE#1 C_BE#2 C_BE#3 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR ICHRST# PLOCK# SERR# PERR# P_REQ#A C231 33pF(NI) H5 J3 H3 K1 G5 J4 H4 J5 K2 G2 L1 G4 L2 H2 L3 F5 F4 N1 E5 N2 E3 N3 E4 M5 E2 P1 E1 P2 D3 R1 D2 P4 J2 K4 M4 N4 M3 F1 L5 F2 F3 G1 U5 M2 K5 L4 W2 B5 E8 P5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3 DEVESLE# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR# PME# GPIO0/REQA# GPIO16/GNTA# PCICLK GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH# GPIO7 GPIO8 GPIO12 GPIO13 GPIO25 GPIO27 GPIO28 GP1O32 GP1O33 GP1O34 GP1O35 GP1O36 GP1O37 GP1O38 GP1O39 GP1O40 GP1O41 GP1O42 GP1O43
ICH4
A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD DPSLP# AB23 U21 AA21 W21 V22 AB22 V21 W23 V23 U22 Y22 Y23 U23
62
R264
68
H_INTR
H_INTR
4
PREQ#5 PREQ#4
RH_A20M# RH_SLP# H_FERR# RH_IGNNE# RH_INIT# RH_INTR RH_NMI RH_SMI# RH_STPCLK# RCIN# A20GATE RH_PWRGD
R254 H_FERR# 4 R258
68
H_NMI
H_NMI
4
68
H_SMI#
H_SMI#
4
CPU
R231 RCIN# A20GATE 18 18 R260
68
H_STPCLK#
H_STPCLK#
4
68
H_PWRGD
H_PWRGD
4
HI[10:0]
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HI11 HI_STB/HI_STBS HI_STB#/HI_STBF HICOMP HIREF HI_VSWING PIRQA# PIRQB# PIRQC# PIRQD# L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21 P21 N20 R23 M23 R22 D5 C2 B4 A3 AC13 AA19 J19 H19 K20 J22 HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 R224 HI_STBS HI_STBF HUBREF_A HI_VSWING PIRQ#A PIRQ#B PIRQ#C PIRQ#D
HI[10:0]
7 VCC1_5
Place R as close as possible to ICH2.
R225 68.1/1% 62 7 7 7,9 7,9
19,20 DEVSEL# 19,20 FRAME# 19,20 IRDY# 19,20 TRDY# 19,20 STOP# 19,20 PAR VCC3_3SBY 19,20 PLOCK# 19,20 SERR# 19,20 PERR# 13,19,20 PCI_PME#
HUB
PCI
PIRQ#A PIRQ#B PIRQ#C PIRQ#D IRQ14 IRQ15
13,20 13,20 20 20 21 21 PIRQ#E RCIN# A20GATE SERIRQ 18 SERIRQ
VCC3_3
IRQ
R255 R251 R252 R228
8.2K 8.2K 8.2K 8.2K
LAN_DISABLE GPIO12 GPIO13 LPC_PME#
IRQ14 IRQ15 APICCLK APICD0 APICD1 SERIRQ
R106 R227 R261 R223 R100 R87
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K
APICD0 APICD1 SERIRQ
6 19 19 19 19 18
PCICLK_ICH4 PIRQ#E PIRQ#F PIRQ#G PIRQ#H LPC_PME#
R220
PIRQ#C
10K
PIRQ#E PIRQ#F PIRQ#G PIRQ#H GPIO7 LPC_PME# GPIO12 GPIO13 C8 D7 C3 C4 R3 V4 V5 W3 V2 W1 LAN_DISABLE W4 J20 G22 F20 G20 F21 H20 F23 H22 G23 H21 F22 E23 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 GPIO1/REQB#/REQ#5 GNT#0 GNT#1 GNT#2 GNT#3 GNT#4 GPIO17/GNTB#/GNT#5 CLKRUN#/GPIO24 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_CLK LAN_RSTSYNC U13A B1 A2 B3 C7 B6 A6 C1 E6 A7 B7 D6 C5 AC2 A10 A9 A11 B10 C10 A12 C11 B11 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5 PGNT#0 PGNT#1 PGNT#2 PREQ#0 PREQ#1 PREQ#2 20 19 19 PIRQ#B
RN20 PGNT#0 PGNT#1 PGNT#2 20 19 19 PIRQ#G PREQ#0 PREQ#1 PREQ#2 1 3 5 7 8.2K RN22 15 CNR_RXD0 CNR_RXD1 CNR_RXD2 CNR_TXD0 CNR_TXD1 CNR_TXD2 26 26 26 26 26 26 15,18 GPIO6 LDRQ#0 GPIO6 GPIO7 LDRQ#0 2 4 6 8 2.7K 1 3 5 7 2 4 6 8
GPIO
15 LAN_DISABLE 17 GPIO32
VCC3_3 +5V R306 1K 14
LAN
PCI
CNR_CLK 26 CNR_RSTSYNC 26
82801DB BGA421
8,17,18,20,21 HPCIRST#
2
1
ICHRST#
C236
7407 10pF(NI)
7
Size A3 Date:
Document Number ICH4 PART1 Monday, August 19, 2002 Sheet 14 of 34
Rev 01
ICH4 PART2
VCC3_3
R277 R268
10K 2.7K 2.7K 4.7K
8.2K
VRMPG SMBCLK SMBDATA LPCPD# THERM# 33 RST_SW# R311 R276 0 0 SYSRST# VRMPG
R267 R266
R226
6,31,33 VRM_PWRGD
VCC3_3SBY
R265 R229 R256 R259
10K 8.2K 8.2K 4.7K
BATLOW# U12B LDRQ#1 SYSRST# LPCPWRON 17,18 LAD0/FWH0 17,18 LAD1/FWH1 17,18 LAD2/FWH2 17,18 LAD3/FWH3 14,18 LDRQ#0 17,18 LFRAME#/FWH4 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBP4P USBP4N USBP5P USBP5N OC#1 OC#2 OC#3 R217 22.6/1% T2 R4 T4 U2 U3 U4 T5 C20 D20 A21 B21 C18 D18 A19 B19 C16 D16 A17 B17 B15 C14 A15 B14 A14 D14 A23 B23 D10 D11 A8 C12 THERM# V1 W20 W18 Y4 Y2 AA2 AB6 Y3 AA1 Y1 AA6 AB3 AA4 AB4 AC4 AA5 Y5 T3 V19 R2 Y21 W19 AB2 Y20 J21 V20 W6 AC3 AB1 AC7 AC6 Y6 W7 H23 J23 F19 T21 C233 18pF(NI) LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LDRQ0# LDRQ1# LFRAME#/FWH4 USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBP4+ USBP4USBP5+ USBP5OC0# OC1# OC2# OC3# OC4# OC5# USBRBIAS USBRBIAS# EE_CS EE_DIN EE_DOUT EE_SHCLK THRM# THRMTRIP# SLP_S1#/GPIO19 SLP_S3# SLP_S4# SLP_S5# PWROK SYS_RESET# PWRBTN# RI# RSMRST# SUS_STAT#/LPCPD# SUSCLK SMBDATA SMBCLK GPIO11/SMBALERT# LAN_RST# C3_STAT#/GPIO21 VRMPWRGD/VGATE AGPBUSY#/GPIO6 STP_PCI#/GPIO18 STP_CPU#/GPIO20 BATLOW#/TP0 CPUPERF#/GPIO22 SSMUXSEL/GPIO23 DPRSLPVR INTRUDER# SMLINK0 SMLINK1 RTCX1 RTCX2 VIBAS RTCRST# SPKR CLK14 CLK48 CLK66 AC_SDIN2 AC_SDIN1 AC_SDIN0 AC_SDOUT AC_BIT_CLK AC_SYNC AC_RST# PDCS1# SDCS1# PDCS3# SDCS3# PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 B13 A13 D13 D9 B8 C9 C13 Y13 AB21 AB14 AC22 AA13 AB13 W13 AA20 AC20 AC21 AA11 AB18 Y12 AB19 AC12 Y18 W12 AA18 AB12 AC19 AB11 AC11 Y10 AA10 AA7 AB8 Y8 AA8 AB9 Y9 AC9 W9 AB10 W10 W11 Y11 W17 AB17 W16 AC16 W15 AB15 W14 AA14 Y14 AC15 AA15 Y15 AB16 Y16 AA17 Y17 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 AC_SDIN2 AC_SDIN1 AC_SDIN0 AC_SDOUT AC_BITCLK AC_SYNC AC_RST# 26 26 26,29 26,29 26,29 26,29 26
LDRQ#1
R270
22K
PWROK
AC97
LPC USB
PDCS#1 SDCS#1 PDCS#3 SDCS#3
21 21 21 21 21 21
5VSBY
VCCRTC
PDA0 PDA1 PDA2 SDA0 SDA1 SDA2
PDA[2:0] SDA[2:0]
R282 1K 1 R283 4.7K 1N4148 D17 2 C255 1uF
ICH4
EEPROM
26 CNR_EE_CS 26 CNR_EE_DIN 26 CNR_EE_DOUT 26 CNR_EE_SHCLK 18 THERM# 4 THERMTRIP# 2 8.2K R289 1K R284 C240 2.2uF D18 1N5817 R291 1K 1 C259 0.047uF BATLOW# BT1 CR2032 2 R292 10M 1 2 1K 18 24 18 LPCPWRON ICH_RI# RSMRST# 3 330K 8,33 PWROK PWROK SYSRST# LPCPWRON LPCPD# SMBDATA SMBCLK LAN_DISABLE VRMPG GPIO6 R290 18 SLP_S3#
PDREQ SDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD[15:0]
21 21 21 21 21 21 21 21 21 21 21
R269 1
JP8
18 SUSCLK 6,12,18,19,20,26 SMBDATA 6,12,18,19,20,26 SMBCLK 33 EXTSMI# 14 LAN_DISABLE 14 GPIO6
IDE
SDD[15:0]
21
18
VBAT
SYSTEM
R262 33 6 6 6 C256 32.768KHz 18pF 18pF ICH_SPKR ICH4_CLK14 USBCLK ICH4_3V66
VIBAS RTCRST#
10M Y3
C257
82801DB BGA421
Size A3 Date:
Document Number ICH4 PART2 Monday, August 19, 2002 Sheet 15 of 34
Rev 01
ICH4 PART3
VCC3_3 VCC3_3SBY
VCC1_5SBY
C241 0.1uF(NI)
VCC1_5 U12C K10 K12 K18 K22 P10 T18 U19 V14 E12 E13 E20 F14 G18 R6 T6 U6 A5 AC17 AC8 B2 H18 H6 J1 J18 K6 M10 P12 P6 U1 V10 V16 V18 E11 F10 F15 F16 F17 F18 K14 V7 V8 V9 A1 A16 A18 A20 A22 A4 AA12 AA16 AA22 AA3 AA9 AB20 AB7 AC1 AC10 AC14 AC18 AC23 AC5 B12 B16 B18 B20 B22 B9 C15 C17 C19 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
ICH4
C150 0.1uF(NI)
C196 0.1uF
+5V C258 0.1uF(NI)
C203 0.1uF
AA23V_CPU_IO P14 V_CPU_IO U18 V_CPU_IO E7 V5REF V6 V5REF E15 V5REF_SUS C22 VCCPLL
AB5 VCCRTC
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCCLAN1_5/VCCSUS1_5 VCCLAN1_5/VCCSUS1_5 VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3
L23 M14 P18 T22
VCCHI VCCHI VCCHI VCCHI
C21 C23 C6 D1 D12 D15 D17 D19 D21 D23 D4 D8 D22 E10 E14 E16 E17 E18 E19 E21 E22 F8 G19 G21 G3 G6 H1 J6 K11 K13 K19 K23 K3 L10 L11 L12 L13 L14 L21 M1 M11 M12 M13 M20 M22 N10 N11 N12 N13 N14 N19 N21 N23 N5 P11 P13 P20 P22 P3 R18 R21 R5 T1 T19 T23 U20 V15 V17 V3 W22 W5 W8 Y19 Y7
VCC3_3
+5V
D15
Distribute near the VCCSUS power pins of the ICH.
R193 1K
1 2
1N5817
ICH5VREF
C195 0.1uF
C189 1uF(NI)
82801DB BGA421
F6 F7 E9 F9
5VSBY VCORE VCC1_5 C239 0.1uF C238 0.1uF C234 0.1uF(NI) C227 0.01uF(NI)
VCCRTC
Size A3 Date:
Document Number ICH4 PART3 Monday, August 19, 2002 Sheet 16 of 34
Rev 01
FirmWare Hub (FWH) Socket
NOTE: This is a Socketed Implementation
6 PCICLKFWH 8,14,18,20,21 HPCIRST#
VCC3_3
VCC3_3
Distribute close to each power pin VCC3_3 C303 0.1uF(NI) RX5 NC-4.7K
VCC3_3 RX6 NC-4.7K
R344 32 31 470 U16 30 4 3 2 1
C301 0.1uF(NI)
VCC
VPP
RST#
CLK
FGPI2
21 S66DETECT 21 P66DETECT
R348
5 6 7
FGPI3
FGPI4
FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0 FWH1 FWH2 FWH3 GND RFU RFU RFU
IC GNDA VCCA
29 28 27 26 25 24 2 23 22 21 3904 3 3 Q17 1 2 Q22 1 3904 4.7K R350 R323 300 R349 4.7K VCC3_3 +5V
14
GPIO32
0(NI) R343 10K R341 10K
8 9 10 11 12 13
FWH
SST49LF002A
GND VCC INIT# FWH4 RFU RFU
H_INIT#
4,14
14
15
16
17
18
19
15,18 LAD0/FWH0 15,18 LAD1/FWH1 15,18 LAD2/FWH2 15,18 LAD3/FWH3 15,18 LFRAME#/FWH4
20
Size A4 Date:
Document Number FWH Monday, August 19, 2002 Sheet 17 of 34
Rev 01
IRRX IRTX 6,12,15,19,20,26 SMBDATA 6,12,15,19,20,26 SMBCLK R21 R20 220 220 -5VIN -12VIN +12VIN +3.3VIN +5.0VIN VCORE_IN HM_VREF VTIN3 +5V FB1 0 HMAVCC C8 R4 0.1uF FB2 15 VBAT LPCPWRON +5V MDAT MCLK 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 U2 25 25 15 0 HMAGND 10K VCC3_3SBY RSMRST# PWRBTN# 15 33 C93 470pF C90 470pF C80 0.1uF RI#1 DCD#1 TXD1 RXD#1 DTR#1 RTS#1 DSR#1 CTS#1 5VSBY SUSCLK SLP_S3# 5VSBY PSON# LPCPWROK 33 33 IRTX 15 15 IRRX 24 24 24 24 24 24 24 24 VCC3_3
IR 1 2 3 4 5
R2 R3
10K 10K
VTIN2 VTIN1 15 3,31 3,31 3,31 3,31 3,31 THERM# CPUVID4 CPUVID3 CPUVID2 CPUVID1 CPUVID0
FAN_TAC3 FAN_TAC2 FAN_TAC1
DRVDEN0 DRVDEN1 INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4
33 27 27 27 27 27 27 27 27 27 27
BEEP MIDI_IN MIDI_OUT J1BUTTON2 J2BUTTON2 JOY1Y JOY2Y JOY2X JOY1X J2BUTTON1 J1BUTTON1
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VTIN3 VREF VCOREA VCOREB +3.3VIN AVCC +12VIN -12VIN -5VIN AGND SCL/GP21 SDA/GP22 PLED/GP23 WDTO/GP24 IRRX/GP25 IRTX/GP26 VSS RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# VCC CASEOPEN# SUSCLKIN VBAT SUSCIN/GP30 PWRCTL#/GP31 PWROK/GP32 RSMRST#/GP33 CIRRX/GP34 PSIN# PSOUT# MDAT MCLK
VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10
W83627HF
SUSLED/GP35 KDAT KCLK VSB KBRST GA20M KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
Temperature Sensing
KDAT KCLK 5VSBY RCIN# A20GATE KEYLOCK# RI#0 DCD#0 TXD0 RXD#0 DTR#0 RTS#0 DSR#0 CTS#0 +5V STROBE# ALF# ERROR# PAR_INIT# SLCTIN# 23 23 23 23 23 14 14 33 24 24 24 24 24 24 24 24 FOR SYSTEM T¢X VTIN1 RT1 10K(THRM) HMAGND 25 25 R9 10K/1% HM_VREF
R10 FOR CPU 4 4 THRMDP THRMDN VTIN2 C4
30K 3300pF
HM_VREF HMAGND
R11 FOR OPTION VTIN3
10K/1%
HM_VREF HMAGND
1 W83627HF PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 ACK# BUSY PE SLCT# HPCIRST# +5V VCC3_3 VCORE VCC3_3 R1 R13 R12 R15 HMAGND 0.1uF(NI) 0.1uF(NI) 0.1uF(NI) -12V HM_VREF R16 R17 R19 HM_VREF D19 CHSFAN 1N4148 3 2 1 R303 1K R18 R14 23 23 23 23 23 23 23 23 23 23 23 23 8,14,17,20,21 RT2
FDD Signals Trace 8 or 10 mil FDC RWC# 1 2 3 4 DS1# 5 6 INDEX# 7 8 MOA# 9 10 DSB# 11 12 DSA# 13 14 MOB# 15 16 DIR# 17 18 STEP# 19 20 WD# 21 22 WE# 23 24 TRAK0# 25 26 WP# 27 28 RDATA# 29 30 HEAD# 31 32 DSKCHG# 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Voltage Sensing
10K/1% 10K/1% 10K/1% 28K/1% 10K/1% 232K/1% 56K/1% 120K/1% 56K/1% -5VIN -12VIN VCORE_IN +3.3VIN +5.0VIN +12VIN
+5V +5V 6 SIO_CLK48 14 LPC_PME# 6 PCICLK_LPC 14,15 LDRQ#0 14 SERIRQ 15,17 LAD3/FWH3 15,17 LAD2/FWH2 15,17 LAD1/FWH1 15,17 LAD0/FWH0 15,17 LFRAME#/FWH4 C73 +5V +12V 22pF(NI) +12V D5 CPUFAN 1 3 2 1 C88 0.1uF 1N4148 R77 1K PWRFAN +5V +12V D8 1N4148 3 2 1 C92 0.1uF 1 R95 1K +5V -5V +12V C29 C99 C175
2
2
FAN_TAC1
FAN_TAC2
2
FAN_TAC3
1
C264 0.1uF Size A3 Date: Document Number LPC&FDC Monday, August 19, 2002 Sheet 18 of 34 Rev 01
2
PCI CONNECTORS
1 AND 2
VCC3_3 -12V +5V +5V +12V VCC3_3 VCC3_3SBY -12V VCC3_3 +5V +5V +12V PCI2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# GND GND RESERVED GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V PCI_CON TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V RESERVED GND GND 3.3V AUX RST# +5V GNT# GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 C/BE0# +3.3V AD6 AD4 GND AD2 AD0 +5V REQ64# +5V +5V A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 VCC3_3 VCC3_3SBY
PCI1 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# GND GND RESERVED GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V PCI_CON TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V RESERVED GND GND 3.3V AUX RST# +5V GNT# GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 C/BE0# +3.3V AD6 AD4 GND AD2 AD0 +5V REQ64# +5V +5V A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
14 14
PIRQ#G PIRQ#E
PIRQ#G PIRQ#E
PIRQ#F PIRQ#H
PIRQ#F PIRQ#H
14 14
PIRQ#H PIRQ#F
PIRQ#G PIRQ#E
PCIRST#
6
PCICLK2
AD31 AD29 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 IRDY# C_BE#2
14 PREQ#1
PGNT#1
PCI_PME# AD30 AD28 AD26 AD24 R130 R_AD17 AD22 AD20 AD18 AD16 FRAME# 100 AD17
14
6
PCICLK3
AD31 AD29 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 IRDY#
PCIRST#
PCI_PME# AD30 AD28 AD26 AD24
13,20 PGNT#2 14 PCI_PME# 13,14,20
14 PREQ#2
R129 R_AD18 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SMBCLK SMBDATA PAR AD15 AD13 AD11 AD9 C_BE#0 AD6 AD4 AD2 AD0 REQ64#3 100 AD18
14,20 IRDY# 14,20 DEVSEL# 14,20 PLOCK# 14,20 PERR# 14,20 SERR#
FRAME# TRDY# STOP#
14,20 14,20 14,20
TRDY# DEVSEL# STOP# SMBCLK SMBDATA PAR AD15 AD13 AD11 AD9 C_BE#0 AD6 AD4 AD2 AD0 REQ64#2 AD8 AD7 AD5 AD3 AD1 ACK64#3 AD14 AD12 AD10 PLOCK# PERR# SERR# C_BE#1
SMBCLK 6,12,15,18,20,26 SMBDATA 6,12,15,18,20,26 PAR 14,20
C_BE#1 AD14 AD12 AD10
AD8 AD7 AD5 AD3 AD1 ACK64#2
14,20 C_BE#[3:0] 14,20 AD[31:0]
VCC3_3 RN18A 1 RN18B 2 RN18C 3 RN18D 4 8 2.7K 7 2.7K 6 2.7K 5 2.7K ACK64#3 REQ64#2 ACK64#2 REQ64#3 Size A3 Date: Document Number PCI 1 , 2 Monday, August 19, 2002 Sheet 19 of 34 Rev 01
PCI CONNECTORS 3
VCC3_3 -12V +5V +5V +12V VCC3_3 VCC3_3SBY
PCI3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# GND GND RESERVED GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V PCI_CON TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V RESERVED GND GND 3.3V AUX RST# +5V GNT# GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 C/BE0# +3.3V AD6 AD4 GND AD2 AD0 +5V REQ64# +5V +5V A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
13,14 PIRQ#B 14 PIRQ#D
PIRQ#A PIRQ#C
13,14 14
6 14
PCICLK1 PREQ#0
AD31 AD29 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2
PCIRST# PGNT#0
AD30 AD28 AD26 AD24 R131 R_AD16 AD22 AD20 AD18 AD16 100 AD16 C107 47pF(NI)
13,19 14
PCI_PME# 13,14,19
14,19 IRDY# 14,19 DEVSEL# 14,19 PLOCK# 14,19 PERR# 14,19 SERR#
C_BE#1 AD14 AD12 AD10
FRAME# TRDY# STOP#
14,19 14,19 14,19
SMBCLK 6,12,15,18,19,26 SMBDATA 6,12,15,18,19,26
AD15 AD13 AD11 AD9 C_BE#0 AD6 AD4 AD2 AD0 REQ64#1
PAR
14,19
AD8 AD7 AD5 AD3 AD1 ACK64#1
14,19 C_BE#[3:0] 14,19 AD[31:0]
VCC3_3 +5V VCC3_3 R307 1K U13B R180 2.7K 2.7K ACK64#1 REQ64#1
8,14,17,18,21 HPCIRST#
3
4
PCIRST#
PCIRST#
13,19
R179
7407 Size A3 Date: Document Number PCI 3 Monday, August 19, 2002 Sheet 20 of 34 Rev 01
15 PDD[15:0]
R309 IDE1 R_RSTP# PDD7 33 PDD6 PDD5 VCC3_3 PDD4 PDD3 PDD2 PDD1 R320 8.2K R322 4.7K PDD0 17 19 18 20 22 24 26 28 30 32 34 36 38 40 PDD15 5 7 9 11 13 15 6 8 10 12 14 16 PDD9 PDD10 1 3 2 4 PDD8
15 SDD[15:0] IDERST#
R310 IDE2 R_RSTS# SDD7 33 SDD6 SDD5 PDD11 VCC3_3 PDD12 SDD3 PDD13 SDD2 PDD14 SDD1 R285 8.2K R286 SDD0 4.7K 19 20 22 24 26 28 30 32 34 36 38 40 17 18 SDD15 15 16 SDD14 13 14 SDD13 11 12 SDD12 SDD4 9 10 SDD11 5 7 6 8 SDD9 SDD10 1 3 2 4 SDD8
IDERST#
15 15 15 14
PDREQ PDIOR# PIORDY IRQ14 PDA1 PDA0
21 23 25 27 29 31 33 35 37 39
15 PDIOW#
15 15 15 14
SDREQ SDIOR# SIORDY IRQ15 SDA1 SDA0
21 23 25 27 29 31 33 35 37 39
15 SDIOW#
15 PDDACK#
15 SDDACK# P66DETECT 17 PDCS#3 15
S66DETECT 17 SDCS#3 15
15
PDCS#1
33 IDEACTP# PDA2 15 PDA[2:0]
15
SDCS#1
33 IDEACTS# SDA2 15 SDA[2:0]
VCC3_3 +5V R308 1K U13C
8,14,17,18,20 HPCIRST#
5
6
IDERST#
7407
Size A3 Date:
Document Number IDE 1& 2 Monday, August 19, 2002 Sheet 21 of 34
Rev 01
5VSBY
2 F2 FUSE/1.1A 1 R64
15
OC#1
470K R65 + 560K 470uF/16V CE6
FB15
0 C36 0.1uF(NI) 1 2 3 4 USB1-1 VCC MH DATADATA+ MH GND USBX2 USB1-2 5 VCC MH DATADATA+ MH GND USBX2 12 10
9
15 USBP0N 15 USBP0P
FB12 FB11
0 0
11
15 USBP1N 15 USBP1P
FB14 FB13
0 0
6 7 8 C33 47pF(NI) C32 47pF(NI) C35 47pF(NI) C34 47pF(NI)
VCC3_3SBY
5VSBY
VCC3_3SBY
+5V
2
R194 10K(NI) 1 R196
F3 FUSE/1.1A
R250 10K(NI) R248 1
2 F4 FUSE/1.1A
15
OC#2
470K + R190 560K CE35 470uF/16V C190 0.1uF(NI) USB2 1 2 4 6 8 10
15
OC#3
470K + R249 560K CE45 470uF/16V C237 0.1uF(NI) USB3 1 2 4 6 8 10
15 USBP2N 15 USBP2P
3 5 7
15 USBP4N 15 USBP4P
3 5 7
15 USBP3N 15 USBP3P
15 USBP5N 15 USBP5P
Size A3 Date:
Document Number USB Monday, September 02, 2002 Sheet 22 of 34
Rev 01
+5V
1 2
D2 1N4148
RN3D
RN4D
RN4C
RN1D
RN2D
RN2C
RN3C
RN1C
RN3B
RN4A
RN2A
RN1A 4.7K 1 8
RN2B
RN4B
RN3A
RN1B
7
5
7
5
6
7
8
5
5
6
6
8
8
6
2
4
2
4
3
2
1
4
4
3
3
1
1
3
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
2
7
18 STROBE# 18 ALF# 18 PAR_INIT# 18 SLCTIN# 18 PDR[7:0]
PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7
RN5A RN5B RN5C RN5D
1 2 3 4
8 33 7 33 6 33 5 33
4.7K
R33
LPT1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 LPT
RN6A RN6B RN6C RN6D RN8A RN8B RN8C RN8D
1 2 3 4 1 2 3 4
8 33 7 33 6 33 5 33 8 33 7 33 6 33 5 33
28 27 26
18 ERROR# 18 18 18 18 ACK# BUSY PE SLCT#
8
6
6
7
8
8
5
7
7
8
5
5
5
6
6 3 3 2 7
C31 180pF(NI)
1
3
3
2
1
1
2
2
1
4
4
CP1A CP1B CP1C CP4B 180pF(NI) 180pF(NI) 180pF(NI) 180pF(NI)
CP6C CP6A CP6B CP1D 180pF(NI) 180pF(NI) 180pF(NI) 180pF(NI)
CP4A CP5D CP5A CP6D 180pF(NI) 180pF(NI) 180pF(NI) 180pF(NI)
4
CP4D CP4C CP5C CP5B 180pF(NI) 180pF(NI) 180pF(NI) 180pF(NI)
4
Size A3 Date:
Document Number PARALLEL PORT Monday, August 19, 2002 Sheet 23 of 34
Rev 01
+5V +12V-12V
Serial Port/COM Headers
18 18 18 18 18 18 18 18 DCD#0 RXD#0 DSR#0 DTR#0 TXD0 CTS#0 RTS#0 RI#0
C71 1uF(NI) U3
20 19 18 17 16 15 14 13 12 11 VCC3_3SBY 5VSBY
VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND GD75232
VCC12 RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12
1 2 3 4 5 6 7 8 9 10 CP3A CP3B CP3C CP3D CP2A CP2B CP2C CP2D COM 1 6 2 7 3 8 4 9 5 COM1
11 10
1
2
3
4
1
2
3
8
7
6
5
8
7
6
4 R221 8.2K
4
1 2 3
1 2 3
D3 2 1N4148 1 1
Place Close to Header
WOL_CONN(NI)
15
ICH_RI#
2 Q11 R219 1 2N7002 3 R218 47K C228 1uF 47K 2
D16 1N4148(NI) D4 2 1N4148 +5V 1
C74 1uF(NI) U4
+12V-12V
5
WOL
100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI)
4
20
VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND GD75232
VCC12 RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12
1 2 3
COM2 HEADER
COM2
1 6 7 8 9 10
18 18 18 18 18 18 18 18
DCD#1 RXD#1 DSR#1 DTR#1 TXD1 CTS#1 RTS#1 RI#1
19 18 17 16 15 14 13 12 11
4 2 5 3 6 4 7 5 8 9 10 CP8D CP8C CP8B CP8A CP7D CP7B CP7C CP7A
4
3
2
1
4
2
3
100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 100pF(NI) 5 6 7 8 5 7 6 8 Document Number SERIAL PORT Monday, August 19, 2002 Sheet 24 of 34
Place Close to Header
Size A3 Date:
1
Rev 01
5VSBY 0
F1 2 1 FUSE/1.1A
FB21
C50 0.1uF(NI)
8 7 6 5 RN7 4.7K 1 2 3 4
KBMSA 6 4 2 1 3 5 C47 47pF(NI) C46 47pF(NI) NC VCC NC DATA GND CLK KBMS MH 4 2 1 3 6 5 MH MH 13 14 15
18 18
MDAT MCLK
FB18 FB17
0 0
KBMSB 12 10 8 7 9 11 C49 47pF(NI) C48 47pF(NI) NC VCC NC DATA GND CLK KBMS 4 2 1 3
6 5
18 18
KDAT KCLK
FB20 FB19
0 0
MH MH
16 17
Size A4 Date:
Document Number KEYBOARD/MOUSE Monday, August 19, 2002 Sheet 25 of 34
Rev 01
-12V VCC3_3 5VSBY
VCC3_3SBY +12V +5V
CNR
B1 B2 B3 B4 B5 B6 B7
RESERVED/MII_MDIO RESERVED/MII_COL RESERVED/MII_TXEN GND[8] RESERVED/MII_RXERR RESERVED/MII_TXD3 GND[9] LAN_TXD1/MII_TXD1 LAN_RSTSYNC/MII_TXC GND[10] LAN_RXD2/MII_RXD2 LAN_RXD0/MII_RXD0 GND[11] RESERVED[2] +5Vdual USB_OC# GND[12] -12V +3.3VD KEY KEY
RESERVED/MII_MDC RESERVED/MII_CRS GND[1] RESERVED/MII_RXDV RESERVED/MII_RXC GND[2]
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
14 CNR_TXD1 14 CNR_RSTSYNC 14 CNR_RXD2 14 CNR_RXD0
B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
CNR
LAN_TXD2/MII_TXD2 LAN_TXD0/MII_TXD0 GND[3] LAN_CLK/RESERVED LAN_RXD1/MII_RXD3 RESERVED/MII_RXD1 USB+ GND[4] USB+12V GND[5] +3.3VDUAL +5VD KEY KEY GND[6] EE_DIN EE_CS SMB_A1 SMB_A2 SMB_SDA AC97_RESET# RESERVED[1] AC97_SDATA_IN1 AC97_SDATA_IN0 GND[7]
CNR_TXD2 14 CNR_TXD0 14 CNR_CLK 14 CNR_RXD1 14
B20
GND[13] EE_DOUT EE_SHCLK GND[14] SMB_A0 SMB_SCL PRIMARY_DN# GND[15] AC97_SYNC AC97_SDATA_OUT AC97_BITCLK
A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 R146 R147 10K(NI) VCC3_3
15 CNR_EE_DIN 15 CNR_EE_SHCLK
B21 B22 B23 B24
CNR_EE_DOUT 15 CNR_EE_CS 15
6,12,15,18,19,20 SMBCLK
B25 B26 B27
AC_RST#
SMBDATA 6,12,15,18,19,20 AC_RST# 15 AC_SDIN2 15 AC_SDIN1 15 AC_SDIN0 15,29
15,29 AC_SYNC 15,29 AC_SDOUT 15,29 AC_BITCLK
VCC3_3SBY R145 0
B28 B29 B30
VCC3_3SBY 10K
R155 4.7K
R162 4.7K
D13
29 AC97_RST#
1 D14
1 1N4148
2 3 1 JP6 2 Onboard AC97 Codec Setting
1N4148
AC_RST#
2
Ensable Disable
JP6 1-2 2-3
(Default)
Size A3 Date:
Document Number CNR Monday, August 19, 2002 Sheet 26 of 34
Rev 01
+5V +5V
FB10 R48 2.2K R49 2.2K R51 2.2K R52 2.2K GAME 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 0
18 J1BUTTON1 18 J2BUTTON1 18 18 18 18 JOY1X JOY2X JOY2Y JOY1Y
R38 R39 R40 R41 2.2K 2.2K 2.2K 2.2K
17 16
18 J2BUTTON2 18 J1BUTTON2 18 MIDI_IN
R53 R50 2.2K 2.2K
18 MIDI_OUT
GAMEPORT C45 C62 47pF(NI) C63 47pF(NI) C64 47pF(NI) C65 47pF(NI) 470pF(NI) 470pF(NI) C42 C40 1000pF(NI) C41 1000pF(NI) C43 1000pF(NI) C44 1000pF(NI)
Size A4 Date:
Document Number GAME PORT Monday, August 19, 2002 Sheet 27 of 34
Rev 01
+5V
VGA Connectors
FB7
FB16 0
0 R58 37.4/1% C54 3.3pF(NI) R59 75/1% C55 3.3pF(NI) C24 3.3pF(NI) L_RED MONOPU FB6 6 1 11 7 2 12 0 R56 37.4/1% C52 3.3pF(NI) R57 75/1% C53 3.3pF(NI) C23 3.3pF(NI) L_BLUE L_HSYNC FB8 FUSE_5 MON2PU L_VSYNC 0 R60 37.4/1% C56 3.3pF(NI) R61 75/1% C57 3