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( P4 LGA775P Processor with DDR2 SDRAM Mainboard )
Rev:3.0 Page Title of Schematic :
A 945P-A/ 945PL-A
Schematics Version History Table :
Title
Cover Sheet
Page
1
Title
PCI-E 88E8052 GIGA LAN
Page
36
A
Circuit Ver. PCB Ver. Total Page Modified Page(s) Date System Block Diagram 2 PCI-E SERIAL ATA SiI3132_1 37
A A 38 01/20/'05 P4 LGA775P Part A 3 PCI-E SERIAL ATA SiI3132_2 38
P4 LGA775P Part B 4 PCI EXPRESS EX2 39
B B 39 03/24/'05
P4 LGA775P Part C 5
1.0 1.0 39 04/18/'05
P4 LGA775P Part D 6
1.1 1.1 39 05/17/'05
P4 LGA775P Part E 7
1.2 1.2 3 4
39
6 7
ADD R594 02/21/06
Clock Generator(ICS954127) 8
3.0 3.0 15 22 29 Modify for Support Conroe and PWM RT8802A 06/05/06
I-LP(MCH)Part A & E & F 9
B
I-LP(MCH)Part D 10 B
I-LP(MCH)Part B & C 11
I-LP(MCH)Part G 12
DDIMM 1&2 ( DDR SDRAMs ) 13
DDIMM 3&4 ( DDR SDRAMs ) 14
DDR & V_FSB_VTT Power 15
PCI EXPRESS 16-PORT 16
ICH7 Part A & D (SATA-CONNECTOR) 17
ICH7 Part B & C (RTC) 18
ICH7 Part E & F (POWER & GND) 19
IDE1 Connector 20
C
USB/FWH 21 C
LPC_FDD/KB/M 22
I/O Ports 23
H/W Monitor 24
Azalia Codec 25
Audio Interface 26
ATX Power & Front Panel 27
LAN 28
Vcore DC-DC 29
MIS DC-DC(DUAL & VDDQ) 30
D
PCI Slot 1&2 31 D
Back I/O 32
PCI Slot 3 33 Elitegroup Computer Systems
VT6308 (1394) 34 Title
PCIE X1 35 Cover Sheet
Size Document Number Rev
Custom 945P-A/945PL-A 3.0
Date: Tuesday, June 27, 2006 Sheet 1 of 40
1 2 3 4 5 6 7 8
A B C D E
DEVICE IDSEL INT# REQ# GNT# PCB : 305 x 244 mm ; 4 layers
PCI1 17 C/D/E/F PREQ-0 PGNT-0
INTEL
PCI2 18 D/E/F/G PREQ-1 PGNT-1
P4 Processor
PCI3 19 E/F/G/H PREQ-2 PGNT-2
1394 20 G PREQ-3 PGNT-3 PSC, Smithfield -
LAN 21 F PREQ-4 PGNT-4
LGA 775 pin
4 4
BW :4.1GB/s @ FSB : 533MHz & Freq : 133MHz
BW : 6.4GB/s @ FSB : 800MHz & Freq : 200MHz
BW : 10.7GB/s @ DDR2 :533/667MHz
BW : 6.4GB/s @ FSB : 1066MHz & Freq : 266MHz
DDIMM1: DDR2 Socket 240P
INTEL DDIMM2 : DDR2 Socket 240P
PCIEx16 i945P
DDIMM3: DDR2 Socket 240P
1210pin FC-BGA DDIMM4 : DDR2 Socket 240P
BW : 2GB/s (Support Lsoch)
USBLAN SATA5 7Pin
3
USB V2.0 M88E8053 RJ45 Sil3132 3
USB1 USB2 USB3 USB4 SATA6 7pin
2 ports 2 ports 2 ports 2 ports INTEL
Up to Ultra ATA/100 ICH7R PCIEx1 PCIEX2
IDE1 40pin One IDE Channel 652pin EBGA BW : 133MB/s @Freq : 33MHz
Line in
Audio Codec Azalia I/F
Line out
Mic in ALC880
Center/Bass out intel LPC bus
FWH
Surround 32pin PLCC
SATA1 7Pin
Side-Surround
2
SATA2 7pin Super I/O VIA 1394 10/100 PCI1 Slot 120pin @ AD17 2
Lan
SATA3 7Pin BW : 150MB/s W83627THF PCI2 Slot 120pin @ AD18
SATA4 7pin TPM 1.1 128pin PQFP PCI3 Slot 120pin @ AD19
USBLAN
CONN/ RJ45
HEADER
1 1
Elitegroup Computer Systems
Title
System Block Diagram
Size Document Number Rev
Custom 945P-A/945PL-A 3.0
Date: Tuesday, June 27, 2006 Sheet 2 of 40
A B C D E
5 4 3 2 1
STP1 Testing Point
ICT_775_E23 1
STP2 Testing Point
ICT_775_E7 1
STP3 R690 0-O
VTT_OUT_R
ICT_775_F23 1
Testing Point R691 0
V_FSB_VTT
2
4
6
8
2
4
6
8
R664 1K-04-X LG-775-J3 ICT_775_F6 R523 51-1-O
COMP8 RN42 RN1
R665 1K-04-X R1 51-1
680-8P4R 680-8P4R
R666 61-04 H_BPM2_1 R4 51-1
1
3
5
7
1
3
5
7
VTT_OUT_L
COMP6 R5 49.9-1 VTT_OUT_R VID0
4 CPU_GTLREF3 CPUVID0 29
H_VCCPLL
CPU_GTLREF3
MCH_GTLREF_CPU FORCEPH_N
9 MCH_GTLREF_CPU FORCEPH_N 15,29
VID0 VID1
CPUVID1 29
LG-775-J3
VSSSEN VSS_SENSE_AN6 VID1
D 4,29 VSSSEN R7 0 VID2 D
VCCSEN VCC_SENSE_AN5 VID3 VID2
4,29 VCCSEN CPUVID2 29
R9 0 VID4
VTT_OUT_R COMP7 VID5
R11 49.9-1 VID6 VID3
VID7 CPUVID3 29
0.1U/25V
BC1 VID_SELECT
VID_SELECT 29
CPU1A VID4
AM2
AM3
AM5
AM7
AC4
AH2
AN5
AN6
AN7
AE3
AE4
AE6
G10
AK6
AK4
D14
D16
D23
CPUVID4 29
A20
E23
E24
B13
AL5
AL6
AL4
F23
F29
W1
G6
C9
D1
N4
N5
LGA775
E5
E6
E7
P5
V1
Y3
F6
J3
VID5
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED25
RESERVED26
RESERVED27
RESERVED28
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID_SELECT
CPUVID5 29
H_D0 B4 L5 H_A3
9 H_D0 D0 A3 H_A3 9
H_D1 C5 P6 H_A4
9 H_D1 D1 A4 H_A4 9
H_D2 A4 M5 H_A5 VID6
9 H_D2 D2 A5 H_A5 9 CPUVID6 29
H_D3 C6 L4 H_A6
9 H_D3 D3 A6 H_A6 9
H_D4 A5 M4 H_A7
9 H_D4 D4 A7 H_A7 9
H_D5 B6 R4 H_A8 VID7
9 H_D5 D5 A8 H_A8 9 CPUVID7 29
H_D6 B7 T5 H_A9
9 H_D6 D6 A9 H_A9 9
H_D7 A7 U6 H_A10
9 H_D7 D7 A10 H_A10 9
H_D8 A10 T4 H_A11
9 H_D8 D8 A11 H_A11 9
H_D9 A11 U5 H_A12
9 H_D9 D9 A12 H_A12 9
H_D10 B10 U4 H_A13
9 H_D10 D10 A13 H_A13 9
H_D11 C11 V5 H_A14
9 H_D11 D11 A14 H_A14 9
H_D12 D8 V4 H_A15
9 H_D12 D12 A15 H_A15 9
H_D13 B12 W5 H_A16
9 H_D13 D13 A16 H_A16 9
H_D14 C12 AB6 H_A17
9 H_D14 D14 A17 H_A17 9
H_D15 D11 W6 H_A18
9 H_D15 D15 A18 H_A18 9
H_D16 G9 Y6 H_A19
9 H_D16 D16 A19 H_A19 9 VTT_OUT_R
H_D17 F8 Y4 H_A20
9 H_D17 D17 A20 H_A20 9
H_D18 F9 AA4 H_A21
9 H_D18 D18 A21 H_A21 9
H_D19 E9 AD6 H_A22
9 H_D19 D19 A22 H_A22 9
H_D20 D7 AA5 H_A23
9 H_D20 D20 A23 H_A23 9
H_D21 E10 AB5 H_A24
9 H_D21 D21 A24 H_A24 9
H_D22 D10 AC5 H_A25 H_BPM0 ER1 51-04
9 H_D22 D22 A25 H_A25 9
H_D23 F11 AB4 H_A26
9 H_D23 D23 A26 H_A26 9
H_D24 F12 AF5 H_A27 H_BPM1 ER2 51-04
9 H_D24 D24 A27 H_A27 9
H_D25 D13 AF4 H_A28
9 H_D25 D25 A28 H_A28 9
C H_D26 E13 AG6 H_A29 H_BPM2 ER3 51-04 C
9 H_D26 D26 A29 H_A29 9
H_D27 G13 AG4 H_A30
9 H_D27 D27 A30 H_A30 9
H_D28 F14 AG5 H_A31 H_BPM3 ER4 51-04
9 H_D28 D28 A31 H_A31 9
H_D29 G14 AH4
9 H_D29 H_D30 D29 A32 H_BPM4 ER5 51-04
9 H_D30 F15 D30 A33 AH5
H_D31 G15 AJ5
9 H_D31 H_D32 D31 A34 H_BPM5 ER6 51-04
9 H_D32 G16 D32 A35 AJ6
H_D33 E15
9 H_D33 H_D34 D33
9 H_D34 E16 D34
H_D35 G18 AJ2 H_BPM0
9 H_D35 H_D36 D35 BPM0 H_BPM1
9 H_D36 G17 D36 BPM1 AJ1
H_D37 H_BPM2
9 H_D37 H_D38
F17
F18
D37 BPM2 AD2
AG2 H_BPM3
Please BPM TERMINATION NEAR to CPU
9 H_D38 H_D39 D38 BPM3 H_BPM4
9 H_D39 E18 D39 BPM4 AF2
H_D40 E19 AG3 H_BPM5
9 H_D40 H_D41 D40 BPM5
9 H_D41 F20 D41
H_D42 STP5
9 H_D42 E21 D42
H_D43 ICT_775_J16 STP6 TESTHI12 R16 51-1 VTT_OUT_L
9 H_D43 F21 D43 DP0 J16 1 VTT_OUT_L
H_D44 ICT_775_H15 STP7
9 H_D44 G21 D44 DP1 H15 1
H_D45 ICT_775_H16 STP8
9 H_D45 E22 D45 DP2 H16 1
H_D46 D22 J17 ICT_775_J17 1 Testing Point
9 H_D46 H_D47 D46 DP3 Testing Point
9 H_D47 G22 D47
H_D48 D20 Testing Point
9 H_D48 H_D49 D48 H_REQ0 Testing Point
9 H_D49 D17 D49 REQ0 K4 H_REQ0 9
H_D50 A14 J5 H_REQ1
9 H_D50 D50 REQ1 H_REQ1 9
H_D51 C15 M6 H_REQ2 TESTHI0 R17 51-1 V_FSB_VTT
9 H_D51 D51 REQ2 H_REQ2 9
H_D52 C14 K6 H_REQ3
9 H_D52 D52 REQ3 H_REQ3 9
H_D53 B15 J6 H_REQ4 TESTHI2_7 R18 51-1
9 H_D53 D53 REQ4 H_REQ4 9
H_D54 C18
9 H_D54 H_D55 D54 TESTHI1 R19 51-1
9 H_D55 B16 D55 VTT_OUT_L
H_D56 A17 AE8
9 H_D56 H_D57 D56 SKTOCC
9 H_D57 B18 D57
H_D58 C21 TESTHI10 R22 51-1
9 H_D58 H_D59 D58 TESTHI0
9 H_D59 B21 D59 TESTH0 F26
H_D60 B19 W3 TESTHI1 TESTHI11 R23 51-1
9 H_D60 H_D61 D60 TESTH1
9 H_D61 A19 D61 TESTH2 F25