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5 4 3 2 1
D
C51-M940 Page Index
01-COVER PAGE
02-BLOCK DIAGRAM D
03-CPU M2-1 HyperTransport
REV:1.0 PCB:15-K57-011000
BOM:81-685-K57100 04-CPU M2-1 DDR2
05-CPU M2-3 Miscellany
06-CPU M2-4 Power and Ground
07-First Logic DDR2 DIMM
08-DDR2 Termination
09-C51G HT CPU
10-C51G HT MCP51
11-C51G PCI-E
12-C51G DAC/VGA CONN
C 13-C51G P/G C
14-MCP51G HT C51PV
15-MCP51G PCI
16-MCP51G SATA/IDE/CONN
17-MCP51G AUDIO/USB/MISC
18-MCP51G GMII
19-MCP51G P/G
20-PCI-E*16
21-PCI 1&2
22-PCI-E*1&CNR
23-LPC SIO-ITE8716F/FDD
B 24-LPT / COM / PS2 B
25-USB
26-PWR CONN. / FNT PNL
27-CPU VCORE
28-DC-DC
29-ALC883/861/660/655
30-ALC883/861/660/655 CONN.
31-RTL8100C & AC131
Signature Date 32-1394 VT6308
Designer Eli Yang
Layout
A A
Cherry/Huntion Elitegroup Computer Systems
Check Tommy
Title
COVER PAGE
Approval
Size Document Number Rev
B
C51-M940 1.0
Date: Thursday, March 23, 2006 Sheet 1 of 32
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
POWER
D D
SUPPLY VREG
CONNECTOR SOCKET 940
128-BIT 200/266/333/400MHZ
AM2 DDIMM1: DDR2 Socket 240P
DDIMM2: DDR2 Socket 240P
HT 16X16 1GHZ
PCI EXPRESS
PCI-E X16 NFORCE VGA CONN
CRUSH 51
C PCI EXPRESS 468 BGA C
PCI-E X1
HT 4X4 800 MHZ
PCI 33MHZ PCI SLOT 1
AZAILIA / AC97 ALC883 / ALC655
ATA 133
NFORCE 10/100-GIGA Lan PCI SLOT 2
PRIMARY IDE 8100C/8110SC
MCP 51
508 BGA
SECONDARY IDE X8 USB2
INTEGRATED SATA 1/2/3/4
X4 - SATA CONN
B
BACK PANEL CONN B
USB2 PORTS 1-0
DOUBLE STACK
FLOPPY CONN USB2 PORTS 3-2
X2/GBIT LAN
PS2/KBRD CONN
FRONT PANEL HDR
SIO LPC BUS 33MHZ
PARALLEL CONN
IT8716F-L/BX USB2 PORTS 5-4
IEEE1394 / VT6308
TPM CONN
USB2 PORTS 7-6
SERIAL CONN
A 4MB FLASH A
MII / Broadcom AC131
Elitegroup Computer Systems
Title
BLOCK DIAGRAM
Size Document Number Rev
B
COVER PAGE 1.0
Date: Thursday, March 23, 2006 Sheet 2 of 32
5 4 3 2 1
8 7 6 5 4 3 2 1
CPUA
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_H1 9
L0_CLKIN_L1 P6 AD4 L0_CLKOUT_L1
L0_CLKIN_L(1) L0_CLKOUT_L(1) L0_CLKOUT_L1 9
VLDT_B L0_CLKIN_H0 N3 AD1 L0_CLKOUT_H0
L0_CLKIN_H(0) L0_CLKOUT_H(0) L0_CLKOUT_H0 9
L0_CLKIN_L0 N2 AC1 L0_CLKOUT_L0
L0_CLKIN_L(0) L0_CLKOUT_L(0) L0_CLKOUT_L0 9
R151 51 L0_CTLIN_H1 V4 Y6 L0_CTLOUT_H1
L0_CTLIN_H(1) L0_CTLOUT_H(1) STP2 CPUE
R152 51 L0_CTLIN_L1 V5 W6 L0_CTLOUT_L1
L0_CTLIN_L(1) L0_CTLOUT_L(1) STP1
L0_CTLIN_H0 U1 W2 L0_CTLOUT_H0 INTERNAL MISC E
L0_CTLIN_H(0) L0_CTLOUT_H(0) L0_CTLOUT_H0 9
D L0_CTLIN_L0 V1 L0_CTLIN_L(0) L0_CTLOUT_L(0) W3 L0_CTLOUT_L0
L0_CTLOUT_L0 9 L25
L26
RSVD1 RSVD17 E20
B19
D
L0_CADIN_H15 L0_CADOUT_H15 RSVD2 RSVD18
U6 L0_CADIN_H(15) L0_CADOUT_H(15) Y5 L31 RSVD3
L0_CADIN_L15 V6 Y4 L0_CADOUT_L15 L30 AL4
L0_CADIN_H14 L0_CADIN_L(15) L0_CADOUT_L(15) L0_CADOUT_H14 RSVD4 RSVD19
T4 L0_CADIN_H(14) L0_CADOUT_H(14) AB6 RSVD20 AK4
L0_CADIN_L14 T5 AA6 L0_CADOUT_L14 W26 AK3
L0_CADIN_H13 L0_CADIN_L(14) L0_CADOUT_L(14) L0_CADOUT_H13 RSVD5 RSVD21
R6 L0_CADIN_H(13) L0_CADOUT_H(13) AB5 W25 RSVD6
L0_CADIN_L13 T6 AB4 L0_CADOUT_L13 AE27
L0_CADIN_H12 L0_CADIN_L(13) L0_CADOUT_L(13) L0_CADOUT_H12 RSVD7
P4 L0_CADIN_H(12) L0_CADOUT_H(12) AD6 U24 RSVD8 RSVD22 F2
L0_CADIN_L12 P5 AC6 L0_CADOUT_L12 V24 F3
L0_CADIN_H11 L0_CADIN_L(12) L0_CADOUT_L(12) L0_CADOUT_H11 RSVD9 RSVD23
M4 L0_CADIN_H(11) L0_CADOUT_H(11) AF6 AE28 RSVD10
L0_CADIN_L11 M5 AE6 L0_CADOUT_L11 G4
L0_CADIN_H10 L0_CADIN_L(11) L0_CADOUT_L(11) L0_CADOUT_H10 RSVD24
L6 L0_CADIN_H(10) L0_CADOUT_H(10) AF5 Y31 RSVD11 RSVD25 G3
L0_CADIN_L10 M6 AF4 L0_CADOUT_L10 Y30 G5
L0_CADIN_H9 L0_CADIN_L(10) L0_CADOUT_L(10) L0_CADOUT_H9 RSVD12 RSVD26
K4 L0_CADIN_H(9) L0_CADOUT_H(9) AH6 AG31 RSVD13
L0_CADIN_L9 K5 AG6 L0_CADOUT_L9 V31 AD25
L0_CADIN_H8 L0_CADIN_L(9) L0_CADOUT_L(9) L0_CADOUT_H8 RSVD14 RSVD27
J6 L0_CADIN_H(8) L0_CADOUT_H(8) AH5 W31 RSVD15 RSVD28 AE24
L0_CADIN_L8 K6 AH4 L0_CADOUT_L8 AF31 AE25
L0_CADIN_L(8) L0_CADOUT_L(8) RSVD16 RSVD29
RSVD30 AJ18
L0_CADIN_H7 U3 Y1 L0_CADOUT_H7 AD18 AJ20
L0_CADIN_L7 L0_CADIN_H(7) L0_CADOUT_H(7) L0_CADOUT_L7 KEY1 RSVD31
U2 L0_CADIN_L(7) L0_CADOUT_L(7) W1 AD19 KEY2 RSVD32 C18
L0_CADIN_H6 R1 AA2 L0_CADOUT_H6 AE7 C20
L0_CADIN_L6 L0_CADIN_H(6) L0_CADOUT_H(6) L0_CADOUT_L6 KEY3 RSVD33
T1 L0_CADIN_L(6) L0_CADOUT_L(6) AA3 AE8 KEY4 RSVD34 G24
L0_CADIN_H5 R3 AB1 L0_CADOUT_H5 H3 G25
L0_CADIN_L5 L0_CADIN_H(5) L0_CADOUT_H(5) L0_CADOUT_L5 KEY5 RSVD35
R2 L0_CADIN_L(5) L0_CADOUT_L(5) AA1 H4 KEY6 RSVD36 H25
L0_CADIN_H4 N1 AC2 L0_CADOUT_H4 H20 V29
L0_CADIN_L4 L0_CADIN_H(4) L0_CADOUT_H(4) L0_CADOUT_L4 KEY7 RSVD37
P1 L0_CADIN_L(4) L0_CADOUT_L(4) AC3 H21 KEY8 RSVD38 W30
L0_CADIN_H3 L1 AE2 L0_CADOUT_H3
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 L0_CADIN_L(3) L0_CADOUT_L(3) AE3
L0_CADIN_H2 L0_CADOUT_H2 Socket_M2
C L0_CADIN_L2
L3
L2
L0_CADIN_H(2) L0_CADOUT_H(2) AF1
AE1 L0_CADOUT_L2 C
L0_CADIN_H1 L0_CADIN_L(2) L0_CADOUT_L(2) L0_CADOUT_H1
J1 L0_CADIN_H(1) L0_CADOUT_H(1) AG2
L0_CADIN_L1 K1 AG3 L0_CADOUT_L1
L0_CADIN_H0 L0_CADIN_L(1) L0_CADOUT_L(1) L0_CADOUT_H0
J3 L0_CADIN_H(0) L0_CADOUT_H(0) AH1
L0_CADIN_L0 J2 AG1 L0_CADOUT_L0
L0_CADIN_L(0) L0_CADOUT_L(0)
L0_CLKIN_H1
L0_CLKIN_H1 9
L0_CLKIN_L1
L0_CLKIN_L1 9
L0_CLKIN_H0
L0_CLKIN_H0 9
L0_CLKIN_L0
L0_CLKIN_L0 9
L0_CTLIN_H0
B L0_CTLIN_L0
L0_CTLIN_H0
L0_CTLIN_L0
9
9
B
L0_CADIN_L[0..15]
L0_CADIN_L[0..15] 9
L0_CADIN_H[0..15]
L0_CADIN_H[0..15] 9
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] 9
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] 9
A A
Elitegroup Computer Systems
Title
C51-M940
Size Document Number Rev
B
CPU M2-1 HyperTransport 1.0
Date: Thursday, March 23, 2006 Sheet 3 of 32
8 7 6 5 4 3 2 1
CPUB CPUC
MA0_CLK_H[2..0] MEMORY INTERFACE A MEMORY INTERFACE B
MA0_CLK_H2 AG21 AE14 MA_DATA63 MB0_CLK_H2 AJ19 AH13 MB_DATA63
7,8 MA0_CLK_H[2..0] MA0_CLK_L2 MA0_CLK_H(2) MA_DATA(63) MA_DATA62 MB0_CLK_L2 MB0_CLK_H(2) MB_DATA(63) MB_DATA62
AG20 MA0_CLK_L(2) MA_DATA(62) AG14 AK19 MB0_CLK_L(2) MB_DATA(62) AL13
D 7,8 MA0_CLK_L[2..0]
MA0_CLK_L[2..0] MA0_CLK_H1
MA0_CLK_L1
G19
H19
MA0_CLK_H(1) MA_DATA(61) AG16
AD17
MA_DATA61
MA_DATA60
MB0_CLK_H1
MB0_CLK_L1
A18
A19
MB0_CLK_H(1) MB_DATA(61) AL15
AJ15
MB_DATA61
MB_DATA60
D
MA0_CS_L[1..0] MA0_CLK_H0 MA0_CLK_L(1) MA_DATA(60) MA_DATA59 MB0_CLK_H0 MB0_CLK_L(1) MB_DATA(60) MB_DATA59
7,8 MA0_CS_L[1..0] U27 MA0_CLK_H(0) MA_DATA(59) AD13 U31 MB0_CLK_H(0) MB_DATA(59) AF13
MA0_CLK_L0 U26 AE13 MA_DATA58 MB0_CLK_L0 U30 AG13 MB_DATA58
MA0_ODT0 MA0_CLK_L(0) MA_DATA(58) MA_DATA57 MB0_CLK_L(0) MB_DATA(58) MB_DATA57
7,8 MA0_ODT0 MA_DATA(57) AG15 MB_DATA(57) AL14
MA0_CS_L1 AC25 AE16 MA_DATA56 MB0_CS_L1 AE30 AK15 MB_DATA56
MA0_CS_L0 MA0_CS_L(1) MA_DATA(56) MA_DATA55 MB0_CS_L0 MB0_CS_L(1) MB_DATA(56) MB_DATA55
AA24 MA0_CS_L(0) MA_DATA(55) AG17 AC31 MB0_CS_L(0) MB_DATA(55) AL16
AE18 MA_DATA54 AL17 MB_DATA54
MA0_ODT0 MA_DATA(54) MA_DATA53 MB0_ODT0 MB_DATA(54) MB_DATA53
AC28 MA0_ODT(0) MA_DATA(53) AD21 AD29 MB0_ODT(0) MB_DATA(53) AK21
AG22 MA_DATA52 AL21 MB_DATA52
MA_DATA(52) MA_DATA51 MB_DATA(52) MB_DATA51
AE20 MA1_CLK_H(2) MA_DATA(51) AE17 AL19 MB1_CLK_H(2) MB_DATA(51) AH15
AE19 AF17 MA_DATA50 AL18 AJ16 MB_DATA50
MA1_CLK_L(2) MA_DATA(50) MA_DATA49 MB1_CLK_L(2) MB_DATA(50) MB_DATA49
G20 MA1_CLK_H(1) MA_DATA(49) AF21 C19 MB1_CLK_H(1) MB_DATA(49) AH19
G21 AE21 MA_DATA48 D19 AL20 MB_DATA48
MA_CAS_L MA1_CLK_L(1) MA_DATA(48) MA_DATA47 MB1_CLK_L(1) MB_DATA(48) MB_DATA47
7,8 MA_CAS_L V27 MA1_CLK_H(0) MA_DATA(47) AF23 W29 MB1_CLK_H(0) MB_DATA(47) AJ22
MA_WE_L W27 AE23 MA_DATA46 W28 AL22 MB_DATA46
7,8 MA_WE_L MA_RAS_L MA1_CLK_L(0) MA_DATA(46) MA_DATA45 MB1_CLK_L(0) MB_DATA(46) MB_DATA45
7,8 MA_RAS_L MA_DATA(45) AJ26 MB_DATA(45) AL24
AD27 AG26 MA_DATA44 AE29 AK25 MB_DATA44
MA_BANK[2..0] MA1_CS_L(1) MA_DATA(44) MA_DATA43 MB1_CS_L(1) MB_DATA(44) MB_DATA43
7,8 MA_BANK[2..0] AA25 MA1_CS_L(0) MA_DATA(43) AE22 AB31 MB1_CS_L(0) MB_DATA(43) AJ21
AG23 MA_DATA42 AH21 MB_DATA42
MA_DATA(42) MA_DATA41 MB_DATA(42) MB_DATA41
AC27 MA1_ODT(0) MA_DATA(41) AH25 AD31 MB1_ODT(0) MB_DATA(41) AH23
MA_CKE0 AF25 MA_DATA40 AJ24 MB_DATA40
7,8 MA_CKE0 MA_DATA(40) MA_DATA39 MB_DATA(40) MB_DATA39
MA_DATA(39) AJ28 MB_DATA(39) AL27
MA_ADD[15..0] MA_CAS_L AB25 AJ29 MA_DATA38 MB_CAS_L AC29 AK27 MB_DATA38
7,8 MA_ADD[15..0] MA_WE_L MA_CAS_L MA_DATA(38) MA_DATA37 MB_WE_L MB_CAS_L MB_DATA(38) MB_DATA37
AB27 MA_WE_L MA_DATA(37) AF29 AC30 MB_WE_L MB_DATA(37) AH31
MA_DQS_H[8..0] MA_RAS_L AA26 AE26 MA_DATA36 MB_RAS_L AB29 AG30 MB_DATA36
7 MA_DQS_H[8..0] MA_RAS_L MA_DATA(36) MA_DATA35 MB_RAS_L MB_DATA(36) MB_DATA35
MA_DATA(35) AJ27 MB_DATA(35) AL25
MA_DQS_L[8..0] MA_BANK2 N25 AH27 MA_DATA34 MB_BANK2 N31 AL26 MB_DATA34
7 MA_DQS_L[8..0] MA_BANK1 MA_BANK(2) MA_DATA(34) MA_DATA33 MB_BANK1 MB_BANK(2) MB_DATA(34) MB_DATA33
Y27 MA_BANK(1) MA_DATA(33) AG29 AA31 MB_BANK(1) MB_DATA(33) AJ30
MA_DM[8..0] MA_BANK0 MA_DATA32 MB_BANK0 MB_DATA32
C 7 MA_DM[8..0] AA27 MA_BANK(0) MA_DATA(32) AF27
E29 MA_DATA31
AA28 MB_BANK(0) MB_DATA(32) AJ31
E31 MB_DATA31 C
MA_DATA[63..0] MA_DATA(31) MA_DATA30 MB_DATA(31) MB_DATA30
7 MA_DATA[63..0] L27 MA_CKE(1) MA_DATA(30) E28 M31 MB_CKE(1) MB_DATA(30) E30
MA_CKE0 M25 D27 MA_DATA29 MB_CKE0 M29 B27 MB_DATA29
MA_CHECK[7..0] MA_CKE(0) MA_DATA(29) MA_DATA28 MB_CKE(0) MB_DATA(29) MB_DATA28
7 MA_CHECK[7..0] MA_DATA(28) C27 MB_DATA(28) A27
MA_ADD15 M27 G26 MA_DATA27 MB_ADD15 N28 F29 MB_DATA27
MA_ADD14 MA_ADD(15) MA_DATA(27) MA_DATA26 MB_ADD14 MB_ADD(15) MB_DATA(27) MB_DATA26
N24 MA_ADD(14) MA_DATA(26) F27 N29 MB_ADD(14) MB_DATA(26) F31
MB0_CLK_H[2..0] MA_ADD13 AC26 C28 MA_DATA25 MB_ADD13 AE31 A29 MB_DATA25
7,8 MB0_CLK_H[2..0] MA_ADD12 MA_ADD(13) MA_DATA(25) MA_DATA24 MB_ADD12 MB_ADD(13) MB_DATA(25) MB_DATA24
N26 MA_ADD(12) MA_DATA(24) E27 N30 MB_ADD(12) MB_DATA(24) A28
MB0_CLK_L[2..0] MA_ADD11 P25 F25 MA_DATA23 MB_ADD11 P29 A25 MB_DATA23
7,8 MB0_CLK_L[2..0] MA_ADD10 MA_ADD(11) MA_DATA(23) MA_DATA22 MB_ADD10 MB_ADD(11) MB_DATA(23) MB_DATA22
Y25 MA_ADD(10) MA_DATA(22) E25 AA29 MB_ADD(10) MB_DATA(22) A24
MB0_CS_L[1..0] MA_ADD9 N27 E23 MA_DATA21 MB_ADD9 P31 C22 MB_DATA21
7,8 MB0_CS_L[1..0] MA_ADD8 MA_ADD(9) MA_DATA(21) MA_DATA20 MB_ADD8 MB_ADD(9) MB_DATA(21) MB_DATA20
R24 MA_ADD(8) MA_DATA(20) D23 R29 MB_ADD(8) MB_DATA(20) D21
MB0_ODT0 MA_ADD7 P27 E26 MA_DATA19 MB_ADD7 R28 A26 MB_DATA19
7,8 MB0_ODT0 MA_ADD6 MA_ADD(7) MA_DATA(19) MA_DATA18 MB_ADD6 MB_ADD(7) MB_DATA(19) MB_DATA18
R25 MA_ADD(6) MA_DATA(18) C26 R31 MB_ADD(6) MB_DATA(18) B25
MA_ADD5 R26 G23 MA_DATA17 MB_ADD5 R30 B23 MB_DATA17
MA_ADD4 MA_ADD(5) MA_DATA(17) MA_DATA16 MB_ADD4 MB_ADD(5) MB_DATA(17) MB_DATA16
R27 MA_ADD(4) MA_DATA(16) F23 T31 MB_ADD(4) MB_DATA(16) A22
MA_ADD3 T25 E22 MA_DATA15 MB_ADD3 T29 B21 MB_DATA15
MA_ADD2 MA_ADD(3) MA_DATA(15) MA_DATA14 MB_ADD2 MB_ADD(3) MB_DATA(15) MB_DATA14
U25 MA_ADD(2) MA_DATA(14) E21 U29 MB_ADD(2) MB_DATA(14) A20
MA_ADD1 T27 F17 MA_DATA13 MB_ADD1 U28 C16 MB_DATA13
MA_ADD0 MA_ADD(1) MA_DATA(13) MA_DATA12 MB_ADD0 MB_ADD(1) MB_DATA(13) MB_DATA12
W24 MA_ADD(0) MA_DATA(12) G17 AA30 MB_ADD(0) MB_DATA(12) D15
G22 MA_DATA11 C21 MB_DATA11
MA_DQS_H7 MA_DATA(11) MA_DATA10 MB_DQS_H7 MB_DATA(11) MB_DATA10
AD15 MA_DQS_H(7) MA_DATA(10) F21 AK13 MB_DQS_H(7) MB_DATA(10) A21
MB_CAS_L MA_DQS_L7 AE15 G18 MA_DATA9 MB_DQS_L7 AJ13 A17 MB_DATA9
7,8 MB_CAS_L MB_WE_L MA_DQS_H6 MA_DQS_L(7) MA_DATA(9) MA_DATA8 MB_DQS_H6 MB_DQS_L(7) MB_DATA(9) MB_DATA8
7,8 MB_WE_L AG18 MA_DQS_H(6) MA_DATA(8) E17 AK17 MB_DQS_H(6) MB_DATA(8) A16
MB_RAS_L MA_DQS_L6 AG19 G16 MA_DATA7 MB_DQS_L6 AJ17 B15 MB_DATA7
7,8 MB_RAS_L MA_DQS_H5 MA_DQS_L(6) MA_DATA(7) MA_DATA6 MB_DQS_H5 MB_DQS_L(6) MB_DATA(7) MB_DATA6
AG24 MA_DQS_H(5) MA_DATA(6) E15 AK23 MB_DQS_H(5) MB_DATA(6) A14
MB_BANK[2..0] MA_DQS_L5 AG25 G13 MA_DATA5 MB_DQS_L5 AL23 E13 MB_DATA5
7,8 MB_BANK[2..0] MA_DQS_H4 MA_DQS_L(5) MA_DATA(5) MA_DATA4 MB_DQS_H4 MB_DQS_L(5) MB_DATA(5) MB_DATA4
AG27 MA_DQS_H(4) MA_DATA(4) H13 AL28 MB_DQS_H(4) MB_DATA(4) F13
MA_DQS_L4 AG28 H17 MA_DATA3 MB_DQS_L4 AL29 C15 MB_DATA3
B 7,8 MB_CKE0
MB_CKE0 MA_DQS_H3 D29
MA_DQS_L(4)
MA_DQS_H(3)
MA_DATA(3)
MA_DATA(2) E16 MA_DATA2 MB_DQS_H3 D31
MB_DQS_L(4)
MB_DQS_H(3)
MB_DATA(3)
MB_DATA(2) A15 MB_DATA2 B
MA_DQS_L3 C29 E14 MA_DATA1 MB_DQS_L3 C31 A13 MB_DATA1
MB_ADD[15..0] MA_DQS_H2 MA_DQS_L(3) MA_DATA(1) MA_DATA0 MB_DQS_H2 MB_DQS_L(3) MB_DATA(1) MB_DATA0
7,8 MB_ADD[15..0] C25 MA_DQS_H(2) MA_DATA(0) G14 C24 MB_DQS_H(2) MB_DATA(0) D13
MA_DQS_L2 D25 MB_DQS_L2 C23
MB_DQS_H[8..0] MA_DQS_H1 MA_DQS_L(2) MA_DQS_H8 MB_DQS_H1 MB_DQS_L(2) MB_DQS_H8
7 MB_DQS_H[8..0] E19 MA_DQS_H(1) MA_DQS_H(8) J28 D17 MB_DQS_H(1) MB_DQS_H(8) J31
MA_DQS_L1 F19 J27 MA_DQS_L8 MB_DQS_L1 C17 J30 MB_DQS_L8
MB_DQS_L[8..0] MA_DQS_H0 MA_DQS_L(1) MA_DQS_L(8) MB_DQS_H0 MB_DQS_L(1) MB_DQS_L(8)
7 MB_DQS_L[8..0] F15 MA_DQS_H(0) C14 MB_DQS_H(0)
MA_DQS_L0 G15 J25 MA_DM8 MB_DQS_L0 C13 J29 MB_DM8
MB_DM[8..0] MA_DQS_L(0) MA_DM(8) MB_DQS_L(0) MB_DM(8)
7 MB_DM[8..0] MA_DM7 MA_CHECK7 MB_DM7 MB_CHECK7
AF15 MA_DM(7) MA_CHECK(7) K25 AJ14 MB_DM(7) MB_CHECK(7) K29
MB_DATA[63..0] MA_DM6 AF19 J26 MA_CHECK6 MB_DM6 AH17 K31 MB_CHECK6
7 MB_DATA[63..0] MA_DM5 MA_DM(6) MA_CHECK(6) MA_CHECK5 MB_DM5 MB_DM(6) MB_CHECK(6) MB_CHECK5
AJ25 MA_DM(5) MA_CHECK(5) G28 AJ23 MB_DM(5) MB_CHECK(5) G30
MB_CHECK[7..0] MA_DM4 AH29 G27 MA_CHECK4 MB_DM4 AK29 G29 MB_CHECK4
7 MB_CHECK[7..0] MA_DM3 MA_DM(4) MA_CHECK(4) MA_CHECK3 MB_DM3 MB_DM(4) MB_CHECK(4) MB_CHECK3
B29 MA_DM(3) MA_CHECK(3) L24 C30 MB_DM(3) MB_CHECK(3) L29
MA_DM2 E24 K27 MA_CHECK2 MB_DM2 A23 L28 MB_CHECK2
MA_DM1 MA_DM(2) MA_CHECK(2) MA_CHECK1 MB_DM1 MB_DM(2) MB_CHECK(2) MB_CHECK1
E18 MA_DM(1) MA_CHECK(1) H29 B17 MB_DM(1) MB_CHECK(1) H31
MA_DM0 H15 H27 MA_CHECK0 MB_DM0 B13 G31 MB_CHECK0
MA_DM(0) MA_CHECK(0) MB_DM(0) MB_CHECK(0)
Socket_M2 Socket_M2
A A
Elitegroup Computer Systems
Title
C51-M940
Size Document Number Rev
B
CPU M2-2 DDR2 1.0
Date: Thursday, March 23, 2006 Sheet 4 of 32
8 7 6 5 4 3 2 1
D +2.5V_VDDA for CPU PLL CPU_VID[4..0]
CPU_VID[4..0] 27 D
+12V VCC3 +2.5V_VDDA
CPUD
VREF25 R93 Width:50mil and Long:500mil V_DIMM
D
10K 4 U7A L27 MISC V_DIMM
1 2 3 Q21 1 2 CPU_VDDA C10
+ VDDA1
1 G 2N7002-S FB-120-08-L D10
C190 C194 C195 VDDA2
2
S
-
CLKIN_H A8 R131 R182 R184
AZ324M-AS 4.7u-16V-08 3300P .22u-25VY CLKIN_L CLKIN_H
+2.5V_VDDA B8
11
CLKIN_L 300 300 300
CPU_ALL_PWROK C9 D2 CPU_VID5 CPU_VID5 TP2
+2.5V_VDDA@105mA 9 CPU_ALL_PWROK PWROK VID(5)
CPU_LDTSTOP- D8 D1 CPU_VID4
9 CPU_LDTSTOP- LDTSTOP_L VID(4)
CPU_HT_RESET- C7 C1 CPU_VID3
9 CPU_HT_RESET- RESET_L VID(3)
1 VID(2) E3 CPU_VID2
EC24 CPU_PRESENT_L AL3 E2 CPU_VID1
100u-16V-LF CPU_PRESENT_L VID(1) CPU_VID0
E1
2